Ermanno Brusadin / mbed

mbed library sources

Dependents:   FRDM-KL46Z_LCD_Test FRDM-KL46Z_LCD_Test FRDM-KL46Z_Plantilla FRDM-KL46Z_Plantilla ... more

targets/cmsis/TARGET_NXP/TARGET_LPC13XX/LPC13Uxx.h@0:6bc4ac881c8e, 2016-07-28 (annotated)

Committer:
ebrus
Date:
Thu Jul 28 15:56:34 2016 +0000
Revision:
0:6bc4ac881c8e
1;

Who changed what in which revision?

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ebrus 0:6bc4ac881c8e 1
ebrus 0:6bc4ac881c8e 2 /****************************************************************************************************//**
ebrus 0:6bc4ac881c8e 3 * @file LPC13Uxx.h
ebrus 0:6bc4ac881c8e 4 *
ebrus 0:6bc4ac881c8e 5 *
ebrus 0:6bc4ac881c8e 6 *
ebrus 0:6bc4ac881c8e 7 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
ebrus 0:6bc4ac881c8e 8 * default LPC13Uxx Device Series
ebrus 0:6bc4ac881c8e 9 *
ebrus 0:6bc4ac881c8e 10 * @version V0.1
ebrus 0:6bc4ac881c8e 11 * @date 18. Jan 2012
ebrus 0:6bc4ac881c8e 12 *
ebrus 0:6bc4ac881c8e 13 * @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
ebrus 0:6bc4ac881c8e 14 *
ebrus 0:6bc4ac881c8e 15 * from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
ebrus 0:6bc4ac881c8e 16 * created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
ebrus 0:6bc4ac881c8e 17 *
ebrus 0:6bc4ac881c8e 18 *******************************************************************************************************/
ebrus 0:6bc4ac881c8e 19
ebrus 0:6bc4ac881c8e 20 /** @addtogroup NXP
ebrus 0:6bc4ac881c8e 21 * @{
ebrus 0:6bc4ac881c8e 22 */
ebrus 0:6bc4ac881c8e 23
ebrus 0:6bc4ac881c8e 24 /** @addtogroup LPC13Uxx
ebrus 0:6bc4ac881c8e 25 * @{
ebrus 0:6bc4ac881c8e 26 */
ebrus 0:6bc4ac881c8e 27
ebrus 0:6bc4ac881c8e 28 #ifndef __LPC13UXX_H__
ebrus 0:6bc4ac881c8e 29 #define __LPC13UXX_H__
ebrus 0:6bc4ac881c8e 30
ebrus 0:6bc4ac881c8e 31 #ifdef __cplusplus
ebrus 0:6bc4ac881c8e 32 extern "C" {
ebrus 0:6bc4ac881c8e 33 #endif
ebrus 0:6bc4ac881c8e 34
ebrus 0:6bc4ac881c8e 35
ebrus 0:6bc4ac881c8e 36 #if defined ( __CC_ARM )
ebrus 0:6bc4ac881c8e 37 #pragma anon_unions
ebrus 0:6bc4ac881c8e 38 #endif
ebrus 0:6bc4ac881c8e 39
ebrus 0:6bc4ac881c8e 40 /* Interrupt Number Definition */
ebrus 0:6bc4ac881c8e 41
ebrus 0:6bc4ac881c8e 42 typedef enum {
ebrus 0:6bc4ac881c8e 43 // ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
ebrus 0:6bc4ac881c8e 44 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
ebrus 0:6bc4ac881c8e 45 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
ebrus 0:6bc4ac881c8e 46 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
ebrus 0:6bc4ac881c8e 47 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
ebrus 0:6bc4ac881c8e 48 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
ebrus 0:6bc4ac881c8e 49 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
ebrus 0:6bc4ac881c8e 50 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
ebrus 0:6bc4ac881c8e 51 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
ebrus 0:6bc4ac881c8e 52 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
ebrus 0:6bc4ac881c8e 53 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
ebrus 0:6bc4ac881c8e 54 // ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
ebrus 0:6bc4ac881c8e 55 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
ebrus 0:6bc4ac881c8e 56 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
ebrus 0:6bc4ac881c8e 57 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
ebrus 0:6bc4ac881c8e 58 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
ebrus 0:6bc4ac881c8e 59 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
ebrus 0:6bc4ac881c8e 60 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
ebrus 0:6bc4ac881c8e 61 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
ebrus 0:6bc4ac881c8e 62 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
ebrus 0:6bc4ac881c8e 63 GINT0_IRQn = 8, /*!< 8 GINT0 */
ebrus 0:6bc4ac881c8e 64 GINT1_IRQn = 9, /*!< 9 GINT1 */
ebrus 0:6bc4ac881c8e 65 Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
ebrus 0:6bc4ac881c8e 66 Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
ebrus 0:6bc4ac881c8e 67 RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
ebrus 0:6bc4ac881c8e 68 Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
ebrus 0:6bc4ac881c8e 69 SSP1_IRQn = 14, /*!< 14 SSP1 */
ebrus 0:6bc4ac881c8e 70 I2C_IRQn = 15, /*!< 15 I2C */
ebrus 0:6bc4ac881c8e 71 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
ebrus 0:6bc4ac881c8e 72 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
ebrus 0:6bc4ac881c8e 73 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
ebrus 0:6bc4ac881c8e 74 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
ebrus 0:6bc4ac881c8e 75 SSP0_IRQn = 20, /*!< 20 SSP0 */
ebrus 0:6bc4ac881c8e 76 USART_IRQn = 21, /*!< 21 USART */
ebrus 0:6bc4ac881c8e 77 USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
ebrus 0:6bc4ac881c8e 78 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
ebrus 0:6bc4ac881c8e 79 ADC_IRQn = 24, /*!< 24 ADC */
ebrus 0:6bc4ac881c8e 80 WDT_IRQn = 25, /*!< 25 WDT */
ebrus 0:6bc4ac881c8e 81 BOD_IRQn = 26, /*!< 26 BOD */
ebrus 0:6bc4ac881c8e 82 FMC_IRQn = 27, /*!< 27 FMC */
ebrus 0:6bc4ac881c8e 83 Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
ebrus 0:6bc4ac881c8e 84 Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
ebrus 0:6bc4ac881c8e 85 USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
ebrus 0:6bc4ac881c8e 86 Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
ebrus 0:6bc4ac881c8e 87 } IRQn_Type;
ebrus 0:6bc4ac881c8e 88
ebrus 0:6bc4ac881c8e 89
ebrus 0:6bc4ac881c8e 90 /** @addtogroup Configuration_of_CMSIS
ebrus 0:6bc4ac881c8e 91 * @{
ebrus 0:6bc4ac881c8e 92 */
ebrus 0:6bc4ac881c8e 93
ebrus 0:6bc4ac881c8e 94 /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
ebrus 0:6bc4ac881c8e 95
ebrus 0:6bc4ac881c8e 96 #define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
ebrus 0:6bc4ac881c8e 97 #define __MPU_PRESENT 0 /*!< MPU present or not */
ebrus 0:6bc4ac881c8e 98 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
ebrus 0:6bc4ac881c8e 99 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
ebrus 0:6bc4ac881c8e 100 /** @} */ /* End of group Configuration_of_CMSIS */
ebrus 0:6bc4ac881c8e 101
ebrus 0:6bc4ac881c8e 102 #include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
ebrus 0:6bc4ac881c8e 103 #include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
ebrus 0:6bc4ac881c8e 104
ebrus 0:6bc4ac881c8e 105 /** @addtogroup Device_Peripheral_Registers
ebrus 0:6bc4ac881c8e 106 * @{
ebrus 0:6bc4ac881c8e 107 */
ebrus 0:6bc4ac881c8e 108
ebrus 0:6bc4ac881c8e 109
ebrus 0:6bc4ac881c8e 110 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 111 // ----- I2C -----
ebrus 0:6bc4ac881c8e 112 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 113
ebrus 0:6bc4ac881c8e 114
ebrus 0:6bc4ac881c8e 115
ebrus 0:6bc4ac881c8e 116 typedef struct { /*!< (@ 0x40000000) I2C Structure */
ebrus 0:6bc4ac881c8e 117 __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
ebrus 0:6bc4ac881c8e 118 __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
ebrus 0:6bc4ac881c8e 119 __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
ebrus 0:6bc4ac881c8e 120 __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
ebrus 0:6bc4ac881c8e 121 __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
ebrus 0:6bc4ac881c8e 122 __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
ebrus 0:6bc4ac881c8e 123 __O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
ebrus 0:6bc4ac881c8e 124 __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
ebrus 0:6bc4ac881c8e 125 union{
ebrus 0:6bc4ac881c8e 126 __IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
ebrus 0:6bc4ac881c8e 127 struct{
ebrus 0:6bc4ac881c8e 128 __IO uint32_t ADR1;
ebrus 0:6bc4ac881c8e 129 __IO uint32_t ADR2;
ebrus 0:6bc4ac881c8e 130 __IO uint32_t ADR3;
ebrus 0:6bc4ac881c8e 131 };
ebrus 0:6bc4ac881c8e 132 };
ebrus 0:6bc4ac881c8e 133 __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
ebrus 0:6bc4ac881c8e 134 union{
ebrus 0:6bc4ac881c8e 135 __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
ebrus 0:6bc4ac881c8e 136 struct{
ebrus 0:6bc4ac881c8e 137 __IO uint32_t MASK0;
ebrus 0:6bc4ac881c8e 138 __IO uint32_t MASK1;
ebrus 0:6bc4ac881c8e 139 __IO uint32_t MASK2;
ebrus 0:6bc4ac881c8e 140 __IO uint32_t MASK3;
ebrus 0:6bc4ac881c8e 141 };
ebrus 0:6bc4ac881c8e 142 };
ebrus 0:6bc4ac881c8e 143 } LPC_I2C_Type;
ebrus 0:6bc4ac881c8e 144
ebrus 0:6bc4ac881c8e 145
ebrus 0:6bc4ac881c8e 146 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 147 // ----- WWDT -----
ebrus 0:6bc4ac881c8e 148 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 149
ebrus 0:6bc4ac881c8e 150
ebrus 0:6bc4ac881c8e 151 typedef struct { /*!< (@ 0x40004000) WWDT Structure */
ebrus 0:6bc4ac881c8e 152 __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
ebrus 0:6bc4ac881c8e 153 __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
ebrus 0:6bc4ac881c8e 154 __O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
ebrus 0:6bc4ac881c8e 155 __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
ebrus 0:6bc4ac881c8e 156 __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
ebrus 0:6bc4ac881c8e 157 __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
ebrus 0:6bc4ac881c8e 158 __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
ebrus 0:6bc4ac881c8e 159 } LPC_WWDT_Type;
ebrus 0:6bc4ac881c8e 160
ebrus 0:6bc4ac881c8e 161
ebrus 0:6bc4ac881c8e 162 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 163 // ----- USART -----
ebrus 0:6bc4ac881c8e 164 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 165
ebrus 0:6bc4ac881c8e 166
ebrus 0:6bc4ac881c8e 167 typedef struct { /*!< (@ 0x40008000) USART Structure */
ebrus 0:6bc4ac881c8e 168
ebrus 0:6bc4ac881c8e 169 union {
ebrus 0:6bc4ac881c8e 170 __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
ebrus 0:6bc4ac881c8e 171 __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
ebrus 0:6bc4ac881c8e 172 __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
ebrus 0:6bc4ac881c8e 173 };
ebrus 0:6bc4ac881c8e 174
ebrus 0:6bc4ac881c8e 175 union {
ebrus 0:6bc4ac881c8e 176 __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
ebrus 0:6bc4ac881c8e 177 __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
ebrus 0:6bc4ac881c8e 178 };
ebrus 0:6bc4ac881c8e 179
ebrus 0:6bc4ac881c8e 180 union {
ebrus 0:6bc4ac881c8e 181 __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
ebrus 0:6bc4ac881c8e 182 __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
ebrus 0:6bc4ac881c8e 183 };
ebrus 0:6bc4ac881c8e 184 __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
ebrus 0:6bc4ac881c8e 185 __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
ebrus 0:6bc4ac881c8e 186 __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
ebrus 0:6bc4ac881c8e 187 __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
ebrus 0:6bc4ac881c8e 188 __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
ebrus 0:6bc4ac881c8e 189 __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
ebrus 0:6bc4ac881c8e 190 __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
ebrus 0:6bc4ac881c8e 191 __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
ebrus 0:6bc4ac881c8e 192 __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
ebrus 0:6bc4ac881c8e 193 __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
ebrus 0:6bc4ac881c8e 194 __I uint32_t RESERVED0[3];
ebrus 0:6bc4ac881c8e 195 __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
ebrus 0:6bc4ac881c8e 196 __I uint32_t RESERVED1;
ebrus 0:6bc4ac881c8e 197 __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
ebrus 0:6bc4ac881c8e 198 __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
ebrus 0:6bc4ac881c8e 199 __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
ebrus 0:6bc4ac881c8e 200 __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
ebrus 0:6bc4ac881c8e 201 __IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
ebrus 0:6bc4ac881c8e 202 } LPC_USART_Type;
ebrus 0:6bc4ac881c8e 203
ebrus 0:6bc4ac881c8e 204
ebrus 0:6bc4ac881c8e 205 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 206 // ----- CT16B0 -----
ebrus 0:6bc4ac881c8e 207 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 208
ebrus 0:6bc4ac881c8e 209 typedef struct { /*!< (@ 0x4000C000) LPC_CTxxBx_Type Structure */
ebrus 0:6bc4ac881c8e 210 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
ebrus 0:6bc4ac881c8e 211 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
ebrus 0:6bc4ac881c8e 212 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
ebrus 0:6bc4ac881c8e 213 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
ebrus 0:6bc4ac881c8e 214 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
ebrus 0:6bc4ac881c8e 215 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
ebrus 0:6bc4ac881c8e 216 union {
ebrus 0:6bc4ac881c8e 217 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
ebrus 0:6bc4ac881c8e 218 struct{
ebrus 0:6bc4ac881c8e 219 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
ebrus 0:6bc4ac881c8e 220 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
ebrus 0:6bc4ac881c8e 221 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
ebrus 0:6bc4ac881c8e 222 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
ebrus 0:6bc4ac881c8e 223 };
ebrus 0:6bc4ac881c8e 224 };
ebrus 0:6bc4ac881c8e 225 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
ebrus 0:6bc4ac881c8e 226 union{
ebrus 0:6bc4ac881c8e 227 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
ebrus 0:6bc4ac881c8e 228 struct{
ebrus 0:6bc4ac881c8e 229 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
ebrus 0:6bc4ac881c8e 230 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
ebrus 0:6bc4ac881c8e 231 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
ebrus 0:6bc4ac881c8e 232 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
ebrus 0:6bc4ac881c8e 233 };
ebrus 0:6bc4ac881c8e 234 };
ebrus 0:6bc4ac881c8e 235 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
ebrus 0:6bc4ac881c8e 236 __I uint32_t RESERVED0[12];
ebrus 0:6bc4ac881c8e 237 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
ebrus 0:6bc4ac881c8e 238 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
ebrus 0:6bc4ac881c8e 239 } LPC_CTxxBx_Type;
ebrus 0:6bc4ac881c8e 240
ebrus 0:6bc4ac881c8e 241 typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
ebrus 0:6bc4ac881c8e 242 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
ebrus 0:6bc4ac881c8e 243 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
ebrus 0:6bc4ac881c8e 244 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
ebrus 0:6bc4ac881c8e 245 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
ebrus 0:6bc4ac881c8e 246 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
ebrus 0:6bc4ac881c8e 247 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
ebrus 0:6bc4ac881c8e 248 union {
ebrus 0:6bc4ac881c8e 249 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
ebrus 0:6bc4ac881c8e 250 struct{
ebrus 0:6bc4ac881c8e 251 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
ebrus 0:6bc4ac881c8e 252 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
ebrus 0:6bc4ac881c8e 253 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
ebrus 0:6bc4ac881c8e 254 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
ebrus 0:6bc4ac881c8e 255 };
ebrus 0:6bc4ac881c8e 256 };
ebrus 0:6bc4ac881c8e 257 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
ebrus 0:6bc4ac881c8e 258 union{
ebrus 0:6bc4ac881c8e 259 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
ebrus 0:6bc4ac881c8e 260 struct{
ebrus 0:6bc4ac881c8e 261 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
ebrus 0:6bc4ac881c8e 262 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
ebrus 0:6bc4ac881c8e 263 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
ebrus 0:6bc4ac881c8e 264 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
ebrus 0:6bc4ac881c8e 265 };
ebrus 0:6bc4ac881c8e 266 };
ebrus 0:6bc4ac881c8e 267 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
ebrus 0:6bc4ac881c8e 268 __I uint32_t RESERVED0[12];
ebrus 0:6bc4ac881c8e 269 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
ebrus 0:6bc4ac881c8e 270 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
ebrus 0:6bc4ac881c8e 271 } LPC_CT16B0_Type;
ebrus 0:6bc4ac881c8e 272
ebrus 0:6bc4ac881c8e 273
ebrus 0:6bc4ac881c8e 274 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 275 // ----- CT16B1 -----
ebrus 0:6bc4ac881c8e 276 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 277
ebrus 0:6bc4ac881c8e 278 typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
ebrus 0:6bc4ac881c8e 279 __IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
ebrus 0:6bc4ac881c8e 280 __IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
ebrus 0:6bc4ac881c8e 281 __IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
ebrus 0:6bc4ac881c8e 282 __IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
ebrus 0:6bc4ac881c8e 283 __IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
ebrus 0:6bc4ac881c8e 284 __IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
ebrus 0:6bc4ac881c8e 285 union {
ebrus 0:6bc4ac881c8e 286 __IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
ebrus 0:6bc4ac881c8e 287 struct{
ebrus 0:6bc4ac881c8e 288 __IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
ebrus 0:6bc4ac881c8e 289 __IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
ebrus 0:6bc4ac881c8e 290 __IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
ebrus 0:6bc4ac881c8e 291 __IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
ebrus 0:6bc4ac881c8e 292 };
ebrus 0:6bc4ac881c8e 293 };
ebrus 0:6bc4ac881c8e 294 __IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
ebrus 0:6bc4ac881c8e 295 union{
ebrus 0:6bc4ac881c8e 296 __I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
ebrus 0:6bc4ac881c8e 297 struct{
ebrus 0:6bc4ac881c8e 298 __I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
ebrus 0:6bc4ac881c8e 299 __I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
ebrus 0:6bc4ac881c8e 300 __I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
ebrus 0:6bc4ac881c8e 301 __I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
ebrus 0:6bc4ac881c8e 302 };
ebrus 0:6bc4ac881c8e 303 };
ebrus 0:6bc4ac881c8e 304 __IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
ebrus 0:6bc4ac881c8e 305 __I uint32_t RESERVED0[12];
ebrus 0:6bc4ac881c8e 306 __IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
ebrus 0:6bc4ac881c8e 307 __IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
ebrus 0:6bc4ac881c8e 308 } LPC_CT16B1_Type;
ebrus 0:6bc4ac881c8e 309
ebrus 0:6bc4ac881c8e 310
ebrus 0:6bc4ac881c8e 311 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 312 // ----- CT32B0 -----
ebrus 0:6bc4ac881c8e 313 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 314 typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
ebrus 0:6bc4ac881c8e 315 __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
ebrus 0:6bc4ac881c8e 316 __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
ebrus 0:6bc4ac881c8e 317 __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
ebrus 0:6bc4ac881c8e 318 __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
ebrus 0:6bc4ac881c8e 319 __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
ebrus 0:6bc4ac881c8e 320 __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
ebrus 0:6bc4ac881c8e 321 union {
ebrus 0:6bc4ac881c8e 322 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
ebrus 0:6bc4ac881c8e 323 struct{
ebrus 0:6bc4ac881c8e 324 __IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
ebrus 0:6bc4ac881c8e 325 __IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
ebrus 0:6bc4ac881c8e 326 __IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
ebrus 0:6bc4ac881c8e 327 __IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
ebrus 0:6bc4ac881c8e 328 };
ebrus 0:6bc4ac881c8e 329 };
ebrus 0:6bc4ac881c8e 330 __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
ebrus 0:6bc4ac881c8e 331 union{
ebrus 0:6bc4ac881c8e 332 __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
ebrus 0:6bc4ac881c8e 333 struct{
ebrus 0:6bc4ac881c8e 334 __I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
ebrus 0:6bc4ac881c8e 335 __I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
ebrus 0:6bc4ac881c8e 336 __I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
ebrus 0:6bc4ac881c8e 337 __I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
ebrus 0:6bc4ac881c8e 338 };
ebrus 0:6bc4ac881c8e 339 };
ebrus 0:6bc4ac881c8e 340 __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
ebrus 0:6bc4ac881c8e 341 __I uint32_t RESERVED0[12];
ebrus 0:6bc4ac881c8e 342 __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
ebrus 0:6bc4ac881c8e 343 __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
ebrus 0:6bc4ac881c8e 344 } LPC_CT32B0_Type;
ebrus 0:6bc4ac881c8e 345
ebrus 0:6bc4ac881c8e 346
ebrus 0:6bc4ac881c8e 347 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 348 // ----- CT32B1 -----
ebrus 0:6bc4ac881c8e 349 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 350 typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
ebrus 0:6bc4ac881c8e 351 __IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
ebrus 0:6bc4ac881c8e 352 __IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
ebrus 0:6bc4ac881c8e 353 __IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
ebrus 0:6bc4ac881c8e 354 __IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
ebrus 0:6bc4ac881c8e 355 __IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
ebrus 0:6bc4ac881c8e 356 __IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
ebrus 0:6bc4ac881c8e 357 union {
ebrus 0:6bc4ac881c8e 358 __IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
ebrus 0:6bc4ac881c8e 359 struct{
ebrus 0:6bc4ac881c8e 360 __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
ebrus 0:6bc4ac881c8e 361 __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
ebrus 0:6bc4ac881c8e 362 __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
ebrus 0:6bc4ac881c8e 363 __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
ebrus 0:6bc4ac881c8e 364 };
ebrus 0:6bc4ac881c8e 365 };
ebrus 0:6bc4ac881c8e 366 __IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
ebrus 0:6bc4ac881c8e 367 union{
ebrus 0:6bc4ac881c8e 368 __I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
ebrus 0:6bc4ac881c8e 369 struct{
ebrus 0:6bc4ac881c8e 370 __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
ebrus 0:6bc4ac881c8e 371 __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
ebrus 0:6bc4ac881c8e 372 __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
ebrus 0:6bc4ac881c8e 373 __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
ebrus 0:6bc4ac881c8e 374 };
ebrus 0:6bc4ac881c8e 375 };
ebrus 0:6bc4ac881c8e 376 __IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
ebrus 0:6bc4ac881c8e 377 __I uint32_t RESERVED0[12];
ebrus 0:6bc4ac881c8e 378 __IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
ebrus 0:6bc4ac881c8e 379 __IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
ebrus 0:6bc4ac881c8e 380 } LPC_CT32B1_Type;
ebrus 0:6bc4ac881c8e 381
ebrus 0:6bc4ac881c8e 382
ebrus 0:6bc4ac881c8e 383 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 384 // ----- ADC -----
ebrus 0:6bc4ac881c8e 385 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 386 typedef struct { /*!< (@ 0x4001C000) ADC Structure */
ebrus 0:6bc4ac881c8e 387 __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
ebrus 0:6bc4ac881c8e 388 __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
ebrus 0:6bc4ac881c8e 389 __I uint32_t RESERVED0[1];
ebrus 0:6bc4ac881c8e 390 __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
ebrus 0:6bc4ac881c8e 391 union{
ebrus 0:6bc4ac881c8e 392 __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
ebrus 0:6bc4ac881c8e 393 struct{
ebrus 0:6bc4ac881c8e 394 __I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
ebrus 0:6bc4ac881c8e 395 __I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
ebrus 0:6bc4ac881c8e 396 __I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
ebrus 0:6bc4ac881c8e 397 __I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
ebrus 0:6bc4ac881c8e 398 __I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
ebrus 0:6bc4ac881c8e 399 __I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
ebrus 0:6bc4ac881c8e 400 __I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
ebrus 0:6bc4ac881c8e 401 __I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
ebrus 0:6bc4ac881c8e 402 };
ebrus 0:6bc4ac881c8e 403 };
ebrus 0:6bc4ac881c8e 404 __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
ebrus 0:6bc4ac881c8e 405 } LPC_ADC_Type;
ebrus 0:6bc4ac881c8e 406
ebrus 0:6bc4ac881c8e 407
ebrus 0:6bc4ac881c8e 408 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 409 // ----- PMU -----
ebrus 0:6bc4ac881c8e 410 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 411
ebrus 0:6bc4ac881c8e 412 typedef struct { /*!< (@ 0x40038000) PMU Structure */
ebrus 0:6bc4ac881c8e 413 __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
ebrus 0:6bc4ac881c8e 414 union{
ebrus 0:6bc4ac881c8e 415 __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
ebrus 0:6bc4ac881c8e 416 struct{
ebrus 0:6bc4ac881c8e 417 __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
ebrus 0:6bc4ac881c8e 418 __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
ebrus 0:6bc4ac881c8e 419 __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
ebrus 0:6bc4ac881c8e 420 __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
ebrus 0:6bc4ac881c8e 421 };
ebrus 0:6bc4ac881c8e 422 };
ebrus 0:6bc4ac881c8e 423 __IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
ebrus 0:6bc4ac881c8e 424 } LPC_PMU_Type;
ebrus 0:6bc4ac881c8e 425
ebrus 0:6bc4ac881c8e 426
ebrus 0:6bc4ac881c8e 427 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 428 // ----- FLASHCTRL -----
ebrus 0:6bc4ac881c8e 429 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 430
ebrus 0:6bc4ac881c8e 431 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
ebrus 0:6bc4ac881c8e 432 __I uint32_t RESERVED0[4];
ebrus 0:6bc4ac881c8e 433 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
ebrus 0:6bc4ac881c8e 434 __I uint32_t RESERVED1[3];
ebrus 0:6bc4ac881c8e 435 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
ebrus 0:6bc4ac881c8e 436 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
ebrus 0:6bc4ac881c8e 437 __I uint32_t RESERVED2[1];
ebrus 0:6bc4ac881c8e 438 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
ebrus 0:6bc4ac881c8e 439 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
ebrus 0:6bc4ac881c8e 440 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
ebrus 0:6bc4ac881c8e 441 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
ebrus 0:6bc4ac881c8e 442 __I uint32_t RESERVED3[1001];
ebrus 0:6bc4ac881c8e 443 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
ebrus 0:6bc4ac881c8e 444 __I uint32_t RESERVED4[1];
ebrus 0:6bc4ac881c8e 445 __O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
ebrus 0:6bc4ac881c8e 446 } LPC_FLASHCTRL_Type;
ebrus 0:6bc4ac881c8e 447
ebrus 0:6bc4ac881c8e 448
ebrus 0:6bc4ac881c8e 449 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 450 // ----- SSP -----
ebrus 0:6bc4ac881c8e 451 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 452 typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
ebrus 0:6bc4ac881c8e 453 __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
ebrus 0:6bc4ac881c8e 454 __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
ebrus 0:6bc4ac881c8e 455 __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
ebrus 0:6bc4ac881c8e 456 __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
ebrus 0:6bc4ac881c8e 457 __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
ebrus 0:6bc4ac881c8e 458 __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
ebrus 0:6bc4ac881c8e 459 __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
ebrus 0:6bc4ac881c8e 460 __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
ebrus 0:6bc4ac881c8e 461 __O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
ebrus 0:6bc4ac881c8e 462 } LPC_SSPx_Type;
ebrus 0:6bc4ac881c8e 463
ebrus 0:6bc4ac881c8e 464
ebrus 0:6bc4ac881c8e 465 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 466 // ----- IOCON -----
ebrus 0:6bc4ac881c8e 467 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 468 typedef struct { /*!< (@ 0x40044000) IOCON Structure */
ebrus 0:6bc4ac881c8e 469 __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
ebrus 0:6bc4ac881c8e 470 __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
ebrus 0:6bc4ac881c8e 471 __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
ebrus 0:6bc4ac881c8e 472 __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
ebrus 0:6bc4ac881c8e 473 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
ebrus 0:6bc4ac881c8e 474 __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
ebrus 0:6bc4ac881c8e 475 __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
ebrus 0:6bc4ac881c8e 476 __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
ebrus 0:6bc4ac881c8e 477 __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
ebrus 0:6bc4ac881c8e 478 __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
ebrus 0:6bc4ac881c8e 479 __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
ebrus 0:6bc4ac881c8e 480 __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
ebrus 0:6bc4ac881c8e 481 __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
ebrus 0:6bc4ac881c8e 482 __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
ebrus 0:6bc4ac881c8e 483 __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
ebrus 0:6bc4ac881c8e 484 __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
ebrus 0:6bc4ac881c8e 485 __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
ebrus 0:6bc4ac881c8e 486 __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
ebrus 0:6bc4ac881c8e 487 __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
ebrus 0:6bc4ac881c8e 488 __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
ebrus 0:6bc4ac881c8e 489 __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
ebrus 0:6bc4ac881c8e 490 __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
ebrus 0:6bc4ac881c8e 491 __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
ebrus 0:6bc4ac881c8e 492 __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
ebrus 0:6bc4ac881c8e 493 __IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
ebrus 0:6bc4ac881c8e 494 __IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
ebrus 0:6bc4ac881c8e 495 __IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
ebrus 0:6bc4ac881c8e 496 __IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
ebrus 0:6bc4ac881c8e 497 __IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
ebrus 0:6bc4ac881c8e 498 __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
ebrus 0:6bc4ac881c8e 499 __IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
ebrus 0:6bc4ac881c8e 500 __IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
ebrus 0:6bc4ac881c8e 501 __IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
ebrus 0:6bc4ac881c8e 502 __IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
ebrus 0:6bc4ac881c8e 503 __IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
ebrus 0:6bc4ac881c8e 504 __IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
ebrus 0:6bc4ac881c8e 505 __IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
ebrus 0:6bc4ac881c8e 506 __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
ebrus 0:6bc4ac881c8e 507 __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
ebrus 0:6bc4ac881c8e 508 __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
ebrus 0:6bc4ac881c8e 509 __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
ebrus 0:6bc4ac881c8e 510 __IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
ebrus 0:6bc4ac881c8e 511 __IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
ebrus 0:6bc4ac881c8e 512 __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
ebrus 0:6bc4ac881c8e 513 __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
ebrus 0:6bc4ac881c8e 514 __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
ebrus 0:6bc4ac881c8e 515 __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
ebrus 0:6bc4ac881c8e 516 __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
ebrus 0:6bc4ac881c8e 517 __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
ebrus 0:6bc4ac881c8e 518 __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
ebrus 0:6bc4ac881c8e 519 __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
ebrus 0:6bc4ac881c8e 520 __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
ebrus 0:6bc4ac881c8e 521 __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
ebrus 0:6bc4ac881c8e 522 __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
ebrus 0:6bc4ac881c8e 523 __IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
ebrus 0:6bc4ac881c8e 524 __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
ebrus 0:6bc4ac881c8e 525 } LPC_IOCON_Type;
ebrus 0:6bc4ac881c8e 526
ebrus 0:6bc4ac881c8e 527
ebrus 0:6bc4ac881c8e 528 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 529 // ----- SYSCON -----
ebrus 0:6bc4ac881c8e 530 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 531
ebrus 0:6bc4ac881c8e 532 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
ebrus 0:6bc4ac881c8e 533 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
ebrus 0:6bc4ac881c8e 534 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
ebrus 0:6bc4ac881c8e 535 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
ebrus 0:6bc4ac881c8e 536 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
ebrus 0:6bc4ac881c8e 537 __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
ebrus 0:6bc4ac881c8e 538 __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
ebrus 0:6bc4ac881c8e 539 __I uint32_t RESERVED0[2];
ebrus 0:6bc4ac881c8e 540 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
ebrus 0:6bc4ac881c8e 541 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
ebrus 0:6bc4ac881c8e 542 __I uint32_t RESERVED1[2];
ebrus 0:6bc4ac881c8e 543 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
ebrus 0:6bc4ac881c8e 544 __I uint32_t RESERVED2[3];
ebrus 0:6bc4ac881c8e 545 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
ebrus 0:6bc4ac881c8e 546 __I uint32_t RESERVED3;
ebrus 0:6bc4ac881c8e 547 __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
ebrus 0:6bc4ac881c8e 548 __I uint32_t RESERVED4[9];
ebrus 0:6bc4ac881c8e 549 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
ebrus 0:6bc4ac881c8e 550 __I uint32_t RESERVED5;
ebrus 0:6bc4ac881c8e 551 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
ebrus 0:6bc4ac881c8e 552 __I uint32_t RESERVED6;
ebrus 0:6bc4ac881c8e 553 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
ebrus 0:6bc4ac881c8e 554 __I uint32_t RESERVED7[4];
ebrus 0:6bc4ac881c8e 555 __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
ebrus 0:6bc4ac881c8e 556 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
ebrus 0:6bc4ac881c8e 557 __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
ebrus 0:6bc4ac881c8e 558 __I uint32_t RESERVED8[3];
ebrus 0:6bc4ac881c8e 559 __IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
ebrus 0:6bc4ac881c8e 560 __IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
ebrus 0:6bc4ac881c8e 561 __I uint32_t RESERVED9[3];
ebrus 0:6bc4ac881c8e 562 __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
ebrus 0:6bc4ac881c8e 563 __I uint32_t RESERVED10;
ebrus 0:6bc4ac881c8e 564 __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
ebrus 0:6bc4ac881c8e 565 __I uint32_t RESERVED11[5];
ebrus 0:6bc4ac881c8e 566 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
ebrus 0:6bc4ac881c8e 567 __I uint32_t RESERVED12;
ebrus 0:6bc4ac881c8e 568 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
ebrus 0:6bc4ac881c8e 569 __I uint32_t RESERVED13[5];
ebrus 0:6bc4ac881c8e 570 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
ebrus 0:6bc4ac881c8e 571 __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
ebrus 0:6bc4ac881c8e 572 __I uint32_t RESERVED14[18];
ebrus 0:6bc4ac881c8e 573 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
ebrus 0:6bc4ac881c8e 574 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
ebrus 0:6bc4ac881c8e 575 __I uint32_t RESERVED15[6];
ebrus 0:6bc4ac881c8e 576 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
ebrus 0:6bc4ac881c8e 577 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
ebrus 0:6bc4ac881c8e 578 __IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
ebrus 0:6bc4ac881c8e 579 __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
ebrus 0:6bc4ac881c8e 580 __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
ebrus 0:6bc4ac881c8e 581 __I uint32_t RESERVED16[25];
ebrus 0:6bc4ac881c8e 582 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
ebrus 0:6bc4ac881c8e 583 __I uint32_t RESERVED17[3];
ebrus 0:6bc4ac881c8e 584 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
ebrus 0:6bc4ac881c8e 585 __I uint32_t RESERVED18[6];
ebrus 0:6bc4ac881c8e 586 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
ebrus 0:6bc4ac881c8e 587 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
ebrus 0:6bc4ac881c8e 588 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
ebrus 0:6bc4ac881c8e 589 __I uint32_t RESERVED19[111];
ebrus 0:6bc4ac881c8e 590 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
ebrus 0:6bc4ac881c8e 591 } LPC_SYSCON_Type;
ebrus 0:6bc4ac881c8e 592
ebrus 0:6bc4ac881c8e 593
ebrus 0:6bc4ac881c8e 594 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 595 // ----- GPIO_PIN_INT -----
ebrus 0:6bc4ac881c8e 596 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 597 typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
ebrus 0:6bc4ac881c8e 598 __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
ebrus 0:6bc4ac881c8e 599 __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
ebrus 0:6bc4ac881c8e 600 __O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
ebrus 0:6bc4ac881c8e 601 __O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
ebrus 0:6bc4ac881c8e 602 __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
ebrus 0:6bc4ac881c8e 603 __O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
ebrus 0:6bc4ac881c8e 604 __O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
ebrus 0:6bc4ac881c8e 605 __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
ebrus 0:6bc4ac881c8e 606 __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
ebrus 0:6bc4ac881c8e 607 __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
ebrus 0:6bc4ac881c8e 608 } LPC_GPIO_PIN_INT_Type;
ebrus 0:6bc4ac881c8e 609
ebrus 0:6bc4ac881c8e 610
ebrus 0:6bc4ac881c8e 611 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 612 // ----- GPIO_GROUP_INT0 -----
ebrus 0:6bc4ac881c8e 613 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 614 typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
ebrus 0:6bc4ac881c8e 615 __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
ebrus 0:6bc4ac881c8e 616 __I uint32_t RESERVED0[7];
ebrus 0:6bc4ac881c8e 617 __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
ebrus 0:6bc4ac881c8e 618 __I uint32_t RESERVED1[6];
ebrus 0:6bc4ac881c8e 619 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
ebrus 0:6bc4ac881c8e 620 } LPC_GPIO_GROUP_INT0_Type;
ebrus 0:6bc4ac881c8e 621
ebrus 0:6bc4ac881c8e 622
ebrus 0:6bc4ac881c8e 623 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 624 // ----- GPIO_GROUP_INT1 -----
ebrus 0:6bc4ac881c8e 625 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 626
ebrus 0:6bc4ac881c8e 627 typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
ebrus 0:6bc4ac881c8e 628 __IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
ebrus 0:6bc4ac881c8e 629 __I uint32_t RESERVED0[7];
ebrus 0:6bc4ac881c8e 630 __IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
ebrus 0:6bc4ac881c8e 631 __I uint32_t RESERVED1[6];
ebrus 0:6bc4ac881c8e 632 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
ebrus 0:6bc4ac881c8e 633 } LPC_GPIO_GROUP_INT1_Type;
ebrus 0:6bc4ac881c8e 634
ebrus 0:6bc4ac881c8e 635
ebrus 0:6bc4ac881c8e 636 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 637 // ----- Repetitive Interrupt Timer (RIT) -----
ebrus 0:6bc4ac881c8e 638 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 639
ebrus 0:6bc4ac881c8e 640 typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
ebrus 0:6bc4ac881c8e 641 __IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
ebrus 0:6bc4ac881c8e 642 __IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
ebrus 0:6bc4ac881c8e 643 __IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
ebrus 0:6bc4ac881c8e 644 __IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
ebrus 0:6bc4ac881c8e 645 __IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
ebrus 0:6bc4ac881c8e 646 __IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
ebrus 0:6bc4ac881c8e 647 __I uint32_t RESERVED0[1];
ebrus 0:6bc4ac881c8e 648 __IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
ebrus 0:6bc4ac881c8e 649 } LPC_RITIMER_Type;
ebrus 0:6bc4ac881c8e 650
ebrus 0:6bc4ac881c8e 651
ebrus 0:6bc4ac881c8e 652 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 653 // ----- USB -----
ebrus 0:6bc4ac881c8e 654 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 655 typedef struct { /*!< (@ 0x40020000) USB Structure */
ebrus 0:6bc4ac881c8e 656 __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
ebrus 0:6bc4ac881c8e 657 __IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
ebrus 0:6bc4ac881c8e 658 __IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
ebrus 0:6bc4ac881c8e 659 __IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
ebrus 0:6bc4ac881c8e 660 __IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
ebrus 0:6bc4ac881c8e 661 __IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
ebrus 0:6bc4ac881c8e 662 __IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
ebrus 0:6bc4ac881c8e 663 __IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
ebrus 0:6bc4ac881c8e 664 __IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
ebrus 0:6bc4ac881c8e 665 __IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
ebrus 0:6bc4ac881c8e 666 __IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
ebrus 0:6bc4ac881c8e 667 __IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
ebrus 0:6bc4ac881c8e 668 __I uint32_t RESERVED0[1];
ebrus 0:6bc4ac881c8e 669 __I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
ebrus 0:6bc4ac881c8e 670 } LPC_USB_Type;
ebrus 0:6bc4ac881c8e 671
ebrus 0:6bc4ac881c8e 672
ebrus 0:6bc4ac881c8e 673 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 674 // ----- GPIO_PORT -----
ebrus 0:6bc4ac881c8e 675 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 676
ebrus 0:6bc4ac881c8e 677 typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
ebrus 0:6bc4ac881c8e 678 union {
ebrus 0:6bc4ac881c8e 679 struct {
ebrus 0:6bc4ac881c8e 680 __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
ebrus 0:6bc4ac881c8e 681 __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
ebrus 0:6bc4ac881c8e 682 };
ebrus 0:6bc4ac881c8e 683 __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
ebrus 0:6bc4ac881c8e 684 };
ebrus 0:6bc4ac881c8e 685 __I uint32_t RESERVED0[1008];
ebrus 0:6bc4ac881c8e 686 union {
ebrus 0:6bc4ac881c8e 687 struct {
ebrus 0:6bc4ac881c8e 688 __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
ebrus 0:6bc4ac881c8e 689 __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
ebrus 0:6bc4ac881c8e 690 };
ebrus 0:6bc4ac881c8e 691 __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
ebrus 0:6bc4ac881c8e 692 };
ebrus 0:6bc4ac881c8e 693 __I uint32_t RESERVED1[960];
ebrus 0:6bc4ac881c8e 694 __IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
ebrus 0:6bc4ac881c8e 695 __I uint32_t RESERVED2[30];
ebrus 0:6bc4ac881c8e 696 __IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
ebrus 0:6bc4ac881c8e 697 __I uint32_t RESERVED3[30];
ebrus 0:6bc4ac881c8e 698 __IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
ebrus 0:6bc4ac881c8e 699 __I uint32_t RESERVED4[30];
ebrus 0:6bc4ac881c8e 700 __IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
ebrus 0:6bc4ac881c8e 701 __I uint32_t RESERVED5[30];
ebrus 0:6bc4ac881c8e 702 __IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
ebrus 0:6bc4ac881c8e 703 __I uint32_t RESERVED6[30];
ebrus 0:6bc4ac881c8e 704 __O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
ebrus 0:6bc4ac881c8e 705 __I uint32_t RESERVED7[30];
ebrus 0:6bc4ac881c8e 706 __O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
ebrus 0:6bc4ac881c8e 707 } LPC_GPIO_Type;
ebrus 0:6bc4ac881c8e 708
ebrus 0:6bc4ac881c8e 709
ebrus 0:6bc4ac881c8e 710 #if defined ( __CC_ARM )
ebrus 0:6bc4ac881c8e 711 #pragma no_anon_unions
ebrus 0:6bc4ac881c8e 712 #endif
ebrus 0:6bc4ac881c8e 713
ebrus 0:6bc4ac881c8e 714
ebrus 0:6bc4ac881c8e 715 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 716 // ----- Peripheral memory map -----
ebrus 0:6bc4ac881c8e 717 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 718
ebrus 0:6bc4ac881c8e 719 #define LPC_I2C_BASE (0x40000000)
ebrus 0:6bc4ac881c8e 720 #define LPC_WWDT_BASE (0x40004000)
ebrus 0:6bc4ac881c8e 721 #define LPC_USART_BASE (0x40008000)
ebrus 0:6bc4ac881c8e 722 #define LPC_CT16B0_BASE (0x4000C000)
ebrus 0:6bc4ac881c8e 723 #define LPC_CT16B1_BASE (0x40010000)
ebrus 0:6bc4ac881c8e 724 #define LPC_CT32B0_BASE (0x40014000)
ebrus 0:6bc4ac881c8e 725 #define LPC_CT32B1_BASE (0x40018000)
ebrus 0:6bc4ac881c8e 726 #define LPC_ADC_BASE (0x4001C000)
ebrus 0:6bc4ac881c8e 727 #define LPC_PMU_BASE (0x40038000)
ebrus 0:6bc4ac881c8e 728 #define LPC_FLASHCTRL_BASE (0x4003C000)
ebrus 0:6bc4ac881c8e 729 #define LPC_SSP0_BASE (0x40040000)
ebrus 0:6bc4ac881c8e 730 #define LPC_IOCON_BASE (0x40044000)
ebrus 0:6bc4ac881c8e 731 #define LPC_SYSCON_BASE (0x40048000)
ebrus 0:6bc4ac881c8e 732 #define LPC_GPIO_PIN_INT_BASE (0x4004C000)
ebrus 0:6bc4ac881c8e 733 #define LPC_SSP1_BASE (0x40058000)
ebrus 0:6bc4ac881c8e 734 #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
ebrus 0:6bc4ac881c8e 735 #define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
ebrus 0:6bc4ac881c8e 736 #define LPC_RITIMER_BASE (0x40064000)
ebrus 0:6bc4ac881c8e 737 #define LPC_USB_BASE (0x40080000)
ebrus 0:6bc4ac881c8e 738 #define LPC_GPIO_BASE (0x50000000)
ebrus 0:6bc4ac881c8e 739
ebrus 0:6bc4ac881c8e 740
ebrus 0:6bc4ac881c8e 741 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 742 // ----- Peripheral declaration -----
ebrus 0:6bc4ac881c8e 743 // ------------------------------------------------------------------------------------------------
ebrus 0:6bc4ac881c8e 744
ebrus 0:6bc4ac881c8e 745 #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
ebrus 0:6bc4ac881c8e 746 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
ebrus 0:6bc4ac881c8e 747 #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
ebrus 0:6bc4ac881c8e 748 #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
ebrus 0:6bc4ac881c8e 749 #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
ebrus 0:6bc4ac881c8e 750 #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
ebrus 0:6bc4ac881c8e 751 #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
ebrus 0:6bc4ac881c8e 752 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
ebrus 0:6bc4ac881c8e 753 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
ebrus 0:6bc4ac881c8e 754 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
ebrus 0:6bc4ac881c8e 755 #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
ebrus 0:6bc4ac881c8e 756 #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
ebrus 0:6bc4ac881c8e 757 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
ebrus 0:6bc4ac881c8e 758 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
ebrus 0:6bc4ac881c8e 759 #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
ebrus 0:6bc4ac881c8e 760 #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
ebrus 0:6bc4ac881c8e 761 #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
ebrus 0:6bc4ac881c8e 762 #define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
ebrus 0:6bc4ac881c8e 763 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
ebrus 0:6bc4ac881c8e 764 #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
ebrus 0:6bc4ac881c8e 765
ebrus 0:6bc4ac881c8e 766
ebrus 0:6bc4ac881c8e 767 /** @} */ /* End of group Device_Peripheral_Registers */
ebrus 0:6bc4ac881c8e 768 /** @} */ /* End of group (null) */
ebrus 0:6bc4ac881c8e 769 /** @} */ /* End of group h1usf */
ebrus 0:6bc4ac881c8e 770
ebrus 0:6bc4ac881c8e 771 #ifdef __cplusplus
ebrus 0:6bc4ac881c8e 772 }
ebrus 0:6bc4ac881c8e 773 #endif
ebrus 0:6bc4ac881c8e 774
ebrus 0:6bc4ac881c8e 775
ebrus 0:6bc4ac881c8e 776 #endif // __LPC13UXX_H__