Ermanno Brusadin / mbed-src

mbed library sources

targets/hal/TARGET_STM/TARGET_STM32F4XX/PeripheralNames.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

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ebrus 0:0a673c671a56 1 /* mbed Microcontroller Library
ebrus 0:0a673c671a56 2 * Copyright (c) 2006-2013 ARM Limited
ebrus 0:0a673c671a56 3 *
ebrus 0:0a673c671a56 4 * Licensed under the Apache License, Version 2.0 (the "License");
ebrus 0:0a673c671a56 5 * you may not use this file except in compliance with the License.
ebrus 0:0a673c671a56 6 * You may obtain a copy of the License at
ebrus 0:0a673c671a56 7 *
ebrus 0:0a673c671a56 8 * http://www.apache.org/licenses/LICENSE-2.0
ebrus 0:0a673c671a56 9 *
ebrus 0:0a673c671a56 10 * Unless required by applicable law or agreed to in writing, software
ebrus 0:0a673c671a56 11 * distributed under the License is distributed on an "AS IS" BASIS,
ebrus 0:0a673c671a56 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ebrus 0:0a673c671a56 13 * See the License for the specific language governing permissions and
ebrus 0:0a673c671a56 14 * limitations under the License.
ebrus 0:0a673c671a56 15 */
ebrus 0:0a673c671a56 16 #ifndef MBED_PERIPHERALNAMES_H
ebrus 0:0a673c671a56 17 #define MBED_PERIPHERALNAMES_H
ebrus 0:0a673c671a56 18
ebrus 0:0a673c671a56 19 #include "cmsis.h"
ebrus 0:0a673c671a56 20
ebrus 0:0a673c671a56 21 #ifdef __cplusplus
ebrus 0:0a673c671a56 22 extern "C" {
ebrus 0:0a673c671a56 23 #endif
ebrus 0:0a673c671a56 24
ebrus 0:0a673c671a56 25 typedef enum {
ebrus 0:0a673c671a56 26 UART_1 = (int)USART1_BASE,
ebrus 0:0a673c671a56 27 UART_2 = (int)USART2_BASE,
ebrus 0:0a673c671a56 28 UART_3 = (int)USART3_BASE,
ebrus 0:0a673c671a56 29 UART_4 = (int)UART4_BASE,
ebrus 0:0a673c671a56 30 UART_5 = (int)UART5_BASE,
ebrus 0:0a673c671a56 31 UART_6 = (int)USART6_BASE
ebrus 0:0a673c671a56 32 } UARTName;
ebrus 0:0a673c671a56 33
ebrus 0:0a673c671a56 34 typedef enum {
ebrus 0:0a673c671a56 35 ADC0_0 = 0,
ebrus 0:0a673c671a56 36 ADC0_1,
ebrus 0:0a673c671a56 37 ADC0_2,
ebrus 0:0a673c671a56 38 ADC0_3,
ebrus 0:0a673c671a56 39 ADC0_4,
ebrus 0:0a673c671a56 40 ADC0_5,
ebrus 0:0a673c671a56 41 ADC0_6,
ebrus 0:0a673c671a56 42 ADC0_7,
ebrus 0:0a673c671a56 43 ADC0_8,
ebrus 0:0a673c671a56 44 ADC0_9,
ebrus 0:0a673c671a56 45 ADC0_10,
ebrus 0:0a673c671a56 46 ADC0_11,
ebrus 0:0a673c671a56 47 ADC0_12,
ebrus 0:0a673c671a56 48 ADC0_13,
ebrus 0:0a673c671a56 49 ADC0_14,
ebrus 0:0a673c671a56 50 ADC0_15
ebrus 0:0a673c671a56 51 } ADCName;
ebrus 0:0a673c671a56 52
ebrus 0:0a673c671a56 53 typedef enum {
ebrus 0:0a673c671a56 54 DAC_0 = 0,
ebrus 0:0a673c671a56 55 DAC_1
ebrus 0:0a673c671a56 56 } DACName;
ebrus 0:0a673c671a56 57
ebrus 0:0a673c671a56 58 typedef enum {
ebrus 0:0a673c671a56 59 SPI_1 = (int)SPI1_BASE,
ebrus 0:0a673c671a56 60 SPI_2 = (int)SPI2_BASE,
ebrus 0:0a673c671a56 61 SPI_3 = (int)SPI3_BASE,
ebrus 0:0a673c671a56 62 } SPIName;
ebrus 0:0a673c671a56 63
ebrus 0:0a673c671a56 64 typedef enum {
ebrus 0:0a673c671a56 65 I2C_1 = (int)I2C1_BASE,
ebrus 0:0a673c671a56 66 I2C_2 = (int)I2C2_BASE,
ebrus 0:0a673c671a56 67 I2C_3 = (int)I2C3_BASE
ebrus 0:0a673c671a56 68 } I2CName;
ebrus 0:0a673c671a56 69
ebrus 0:0a673c671a56 70 typedef enum {
ebrus 0:0a673c671a56 71 PWM_1 = 1,
ebrus 0:0a673c671a56 72 PWM_2,
ebrus 0:0a673c671a56 73 PWM_3,
ebrus 0:0a673c671a56 74 PWM_4,
ebrus 0:0a673c671a56 75 PWM_5,
ebrus 0:0a673c671a56 76 PWM_6
ebrus 0:0a673c671a56 77 } PWMName;
ebrus 0:0a673c671a56 78
ebrus 0:0a673c671a56 79 typedef enum {
ebrus 0:0a673c671a56 80 CAN_1 = (int)CAN1_BASE,
ebrus 0:0a673c671a56 81 CAN_2 = (int)CAN2_BASE
ebrus 0:0a673c671a56 82 } CANName;
ebrus 0:0a673c671a56 83
ebrus 0:0a673c671a56 84 #ifdef __cplusplus
ebrus 0:0a673c671a56 85 }
ebrus 0:0a673c671a56 86 #endif
ebrus 0:0a673c671a56 87
ebrus 0:0a673c671a56 88 #endif