Ermanno Brusadin / mbed-src

mbed library sources

targets/hal/TARGET_NXP/TARGET_LPC43XX/README.txt@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

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ebrus 0:0a673c671a56 1 mbed port to NXP LPC43xx
ebrus 0:0a673c671a56 2 ========================
ebrus 0:0a673c671a56 3 Updated: 07/11/14
ebrus 0:0a673c671a56 4
ebrus 0:0a673c671a56 5 The NXP LPC43xx microcontrollers includes multiple Cortex-M cores in a single
ebrus 0:0a673c671a56 6 microcontroller package. This port allows mbed developers to take advantage
ebrus 0:0a673c671a56 7 of the LPC43xx in their application using APIs that they are familiar with.
ebrus 0:0a673c671a56 8 Some of the key features of the LPC43xx include:
ebrus 0:0a673c671a56 9
ebrus 0:0a673c671a56 10 * Dual core ARM Cortex-M4/M0 both capable of up to 204 MHz
ebrus 0:0a673c671a56 11 * Up to 264 KB SRAM, 1 MB internal flash
ebrus 0:0a673c671a56 12 * Two High-speed USB 2.0 interfaces
ebrus 0:0a673c671a56 13 * Ethernet MAC
ebrus 0:0a673c671a56 14 * LCD interface
ebrus 0:0a673c671a56 15 * Quad-SPI Flash Interface (SPIFI)
ebrus 0:0a673c671a56 16 * State Configurable Timer (SCT)
ebrus 0:0a673c671a56 17 * Serial GPIO (SGPIO)
ebrus 0:0a673c671a56 18 * Up to 164 GPIO
ebrus 0:0a673c671a56 19
ebrus 0:0a673c671a56 20 The NXP LPC18xx is a single core Cortex-M3 implementation that is compatible
ebrus 0:0a673c671a56 21 with the LPC43XX for cost-sensitive applications not requiring multiple cores.
ebrus 0:0a673c671a56 22
ebrus 0:0a673c671a56 23 mbed port to the LPC43XX - Micromint USA <support@micromint.com>
ebrus 0:0a673c671a56 24
ebrus 0:0a673c671a56 25 Compatibility
ebrus 0:0a673c671a56 26 -------------
ebrus 0:0a673c671a56 27 * This port has been tested with the following boards:
ebrus 0:0a673c671a56 28 Board MCU RAM/Flash
ebrus 0:0a673c671a56 29 Micromint Bambino 200 LPC4330 264K SRAM/4 MB SPIFI flash
ebrus 0:0a673c671a56 30 Micromint Bambino 200E LPC4330 264K SRAM/8 MB SPIFI flash
ebrus 0:0a673c671a56 31 Micromint Bambino 210 LPC4330 264K SRAM/4 MB SPIFI flash
ebrus 0:0a673c671a56 32 Micromint Bambino 210E LPC4330 264K SRAM/8 MB SPIFI flash
ebrus 0:0a673c671a56 33
ebrus 0:0a673c671a56 34 * CMSIS-DAP debugging is implemented with the Micromint Bambino 210/210E.
ebrus 0:0a673c671a56 35 To debug other LPC4330 targets, use a JTAG. The NXP DFU tool can be used
ebrus 0:0a673c671a56 36 for flash programming.
ebrus 0:0a673c671a56 37
ebrus 0:0a673c671a56 38 * This port should support NXP LPC43XX and LPC18XX variants with a single
ebrus 0:0a673c671a56 39 codebase. The core declaration specifies the binaries to be built:
ebrus 0:0a673c671a56 40 mbed define CMSIS define MCU Target
ebrus 0:0a673c671a56 41 __CORTEX_M4 CORE_M4 LPC43xx Cortex-M4
ebrus 0:0a673c671a56 42 __CORTEX_M0 CORE_M0 LPC43xx Cortex-M0
ebrus 0:0a673c671a56 43 __CORTEX_M3 CORE_M3 LPC18xx Cortex-M3
ebrus 0:0a673c671a56 44 These MCUs all share the peripheral IP, common driver code is feasible.
ebrus 0:0a673c671a56 45 Yet each variant can have different memory segments, peripherals, etc.
ebrus 0:0a673c671a56 46 Plus, each board design can integrate different external peripherals
ebrus 0:0a673c671a56 47 or interfaces. A future release of the mbed SDK and its build tools will
ebrus 0:0a673c671a56 48 support specifying the target board when building binaries. At this time
ebrus 0:0a673c671a56 49 building binaries for different targets requires an external project or
ebrus 0:0a673c671a56 50 Makefile.
ebrus 0:0a673c671a56 51
ebrus 0:0a673c671a56 52 * No testing has been done with LPC18xx hardware.
ebrus 0:0a673c671a56 53
ebrus 0:0a673c671a56 54 Notes
ebrus 0:0a673c671a56 55 -----
ebrus 0:0a673c671a56 56 * On the LPC43xx the hardware pin name and the GPIO pin name are not the same,
ebrus 0:0a673c671a56 57 requiring different offsets for the SCU and GPIO registers. To simplify logic
ebrus 0:0a673c671a56 58 the pin identifier encodes the offsets. Macros are used for decoding.
ebrus 0:0a673c671a56 59 For example, P6_11 corresponds to GPIO3[7] and is encoded/decoded as follows:
ebrus 0:0a673c671a56 60
ebrus 0:0a673c671a56 61 P6_11 = MBED_PIN(0x06, 11, 3, 7) = 0x032C0067
ebrus 0:0a673c671a56 62
ebrus 0:0a673c671a56 63 MBED_SCU_REG(P6_11) = 0x4008632C MBED_GPIO_PORT(P6_11) = 3
ebrus 0:0a673c671a56 64 MBED_GPIO_REG(P6_11) = 0x400F4000 MBED_GPIO_PIN(P6_11) = 7
ebrus 0:0a673c671a56 65
ebrus 0:0a673c671a56 66 * Pin names use multiple aliases to support Arduino naming conventions as well
ebrus 0:0a673c671a56 67 as others. For example, to use pin p21 on the Bambino 210 from mbed applications
ebrus 0:0a673c671a56 68 the following aliases are equivalent: p21, D0, UART0_TX, COM1_TX, P6_4.
ebrus 0:0a673c671a56 69 See the board pinout graphic and the PinNames.h for available aliases.
ebrus 0:0a673c671a56 70
ebrus 0:0a673c671a56 71 * The LPC43xx implements GPIO pin and group interrupts. Any pin in the 8 32-bit
ebrus 0:0a673c671a56 72 GPIO ports can interrupt (LPC4350 supports up to 164). On group interrupts a
ebrus 0:0a673c671a56 73 pin can only interrupt on the rising or falling edge, not both as required
ebrus 0:0a673c671a56 74 by the mbed InterruptIn class. Also, group interrupts can't be cleared
ebrus 0:0a673c671a56 75 individually. This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
ebrus 0:0a673c671a56 76 A future implementation may provide group interrupt support.
ebrus 0:0a673c671a56 77
ebrus 0:0a673c671a56 78 * The LPC3xx PWM driver uses the State Configurable Timer (SCT). The default
ebrus 0:0a673c671a56 79 build (PWM_MODE=0) uses the unified 32-bit times. Applications that use PWM
ebrus 0:0a673c671a56 80 and require other SCT uses can use the dual 16-bit mode by changing PWM_MODE
ebrus 0:0a673c671a56 81 when building the library.