Ermanno Brusadin / mbed-src

mbed library sources

targets/hal/TARGET_NXP/TARGET_LPC43XX/PeripheralNames.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /* mbed Microcontroller Library
ebrus 0:0a673c671a56 2 * Copyright (c) 2006-2013 ARM Limited
ebrus 0:0a673c671a56 3 *
ebrus 0:0a673c671a56 4 * Licensed under the Apache License, Version 2.0 (the "License");
ebrus 0:0a673c671a56 5 * you may not use this file except in compliance with the License.
ebrus 0:0a673c671a56 6 * You may obtain a copy of the License at
ebrus 0:0a673c671a56 7 *
ebrus 0:0a673c671a56 8 * http://www.apache.org/licenses/LICENSE-2.0
ebrus 0:0a673c671a56 9 *
ebrus 0:0a673c671a56 10 * Unless required by applicable law or agreed to in writing, software
ebrus 0:0a673c671a56 11 * distributed under the License is distributed on an "AS IS" BASIS,
ebrus 0:0a673c671a56 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ebrus 0:0a673c671a56 13 * See the License for the specific language governing permissions and
ebrus 0:0a673c671a56 14 * limitations under the License.
ebrus 0:0a673c671a56 15 */
ebrus 0:0a673c671a56 16 #ifndef MBED_PERIPHERALNAMES_H
ebrus 0:0a673c671a56 17 #define MBED_PERIPHERALNAMES_H
ebrus 0:0a673c671a56 18
ebrus 0:0a673c671a56 19 #include "cmsis.h"
ebrus 0:0a673c671a56 20
ebrus 0:0a673c671a56 21 #ifdef __cplusplus
ebrus 0:0a673c671a56 22 extern "C" {
ebrus 0:0a673c671a56 23 #endif
ebrus 0:0a673c671a56 24
ebrus 0:0a673c671a56 25 typedef enum {
ebrus 0:0a673c671a56 26 UART_0 = (int)LPC_USART0_BASE,
ebrus 0:0a673c671a56 27 UART_1 = (int)LPC_UART1_BASE,
ebrus 0:0a673c671a56 28 UART_2 = (int)LPC_USART2_BASE,
ebrus 0:0a673c671a56 29 UART_3 = (int)LPC_USART3_BASE
ebrus 0:0a673c671a56 30 } UARTName;
ebrus 0:0a673c671a56 31
ebrus 0:0a673c671a56 32 typedef enum {
ebrus 0:0a673c671a56 33 ADC0_0 = 0,
ebrus 0:0a673c671a56 34 ADC0_1,
ebrus 0:0a673c671a56 35 ADC0_2,
ebrus 0:0a673c671a56 36 ADC0_3,
ebrus 0:0a673c671a56 37 ADC0_4,
ebrus 0:0a673c671a56 38 ADC0_5,
ebrus 0:0a673c671a56 39 ADC0_6,
ebrus 0:0a673c671a56 40 ADC0_7,
ebrus 0:0a673c671a56 41 ADC1_0,
ebrus 0:0a673c671a56 42 ADC1_1,
ebrus 0:0a673c671a56 43 ADC1_2,
ebrus 0:0a673c671a56 44 ADC1_3,
ebrus 0:0a673c671a56 45 ADC1_4,
ebrus 0:0a673c671a56 46 ADC1_5,
ebrus 0:0a673c671a56 47 ADC1_6,
ebrus 0:0a673c671a56 48 ADC1_7
ebrus 0:0a673c671a56 49 } ADCName;
ebrus 0:0a673c671a56 50
ebrus 0:0a673c671a56 51 typedef enum {
ebrus 0:0a673c671a56 52 DAC_0 = 0
ebrus 0:0a673c671a56 53 } DACName;
ebrus 0:0a673c671a56 54
ebrus 0:0a673c671a56 55 typedef enum {
ebrus 0:0a673c671a56 56 SPI_0 = (int)LPC_SSP0_BASE,
ebrus 0:0a673c671a56 57 SPI_1 = (int)LPC_SSP1_BASE
ebrus 0:0a673c671a56 58 } SPIName;
ebrus 0:0a673c671a56 59
ebrus 0:0a673c671a56 60 typedef enum {
ebrus 0:0a673c671a56 61 I2C_0 = (int)LPC_I2C0_BASE,
ebrus 0:0a673c671a56 62 I2C_1 = (int)LPC_I2C1_BASE
ebrus 0:0a673c671a56 63 } I2CName;
ebrus 0:0a673c671a56 64
ebrus 0:0a673c671a56 65 typedef enum {
ebrus 0:0a673c671a56 66 PWM_0,
ebrus 0:0a673c671a56 67 PWM_1,
ebrus 0:0a673c671a56 68 PWM_2,
ebrus 0:0a673c671a56 69 PWM_3,
ebrus 0:0a673c671a56 70 PWM_4,
ebrus 0:0a673c671a56 71 PWM_5,
ebrus 0:0a673c671a56 72 PWM_6,
ebrus 0:0a673c671a56 73 PWM_7,
ebrus 0:0a673c671a56 74 PWM_8,
ebrus 0:0a673c671a56 75 PWM_9,
ebrus 0:0a673c671a56 76 PWM_10,
ebrus 0:0a673c671a56 77 PWM_11,
ebrus 0:0a673c671a56 78 PWM_12,
ebrus 0:0a673c671a56 79 PWM_13,
ebrus 0:0a673c671a56 80 PWM_14,
ebrus 0:0a673c671a56 81 PWM_15
ebrus 0:0a673c671a56 82 } PWMName;
ebrus 0:0a673c671a56 83
ebrus 0:0a673c671a56 84 typedef enum {
ebrus 0:0a673c671a56 85 CAN_0 = (int)LPC_C_CAN0_BASE,
ebrus 0:0a673c671a56 86 CAN_1 = (int)LPC_C_CAN1_BASE
ebrus 0:0a673c671a56 87 } CANName;
ebrus 0:0a673c671a56 88
ebrus 0:0a673c671a56 89 #define STDIO_UART_TX USBTX
ebrus 0:0a673c671a56 90 #define STDIO_UART_RX USBRX
ebrus 0:0a673c671a56 91 #define STDIO_UART UART_2
ebrus 0:0a673c671a56 92
ebrus 0:0a673c671a56 93 // Default peripherals
ebrus 0:0a673c671a56 94 #define MBED_SPI0 SPI0_MOSI, SPI0_MISO, SPI0_SCK, SPI0_SSEL
ebrus 0:0a673c671a56 95 #define MBED_SPI1 SPI1_MOSI, SPI1_MISO, SPI1_SCK, SPI1_SSEL
ebrus 0:0a673c671a56 96
ebrus 0:0a673c671a56 97 #define MBED_UART0 UART0_TX, UART0_RX
ebrus 0:0a673c671a56 98 #define MBED_UART1 UART1_TX, UART1_RX
ebrus 0:0a673c671a56 99 #define MBED_UART2 UART2_TX, UART2_RX
ebrus 0:0a673c671a56 100 #define MBED_UART3 UART3_TX, UART3_RX
ebrus 0:0a673c671a56 101 #define MBED_UARTUSB USBTX, USBRX
ebrus 0:0a673c671a56 102
ebrus 0:0a673c671a56 103 #define COM1 MBED_UART0
ebrus 0:0a673c671a56 104 #define COM2 MBED_UART1
ebrus 0:0a673c671a56 105 #define COM3 MBED_UART2
ebrus 0:0a673c671a56 106 #define COM4 MBED_UART3
ebrus 0:0a673c671a56 107
ebrus 0:0a673c671a56 108 #define MBED_I2C0 I2C0_SDA, I2C0_SCL
ebrus 0:0a673c671a56 109 #define MBED_I2C1 I2C1_SDA, I2C1_SCL
ebrus 0:0a673c671a56 110
ebrus 0:0a673c671a56 111 #define MBED_CAN0 p30, p29
ebrus 0:0a673c671a56 112
ebrus 0:0a673c671a56 113 #define MBED_ANALOGOUT0 DAC0
ebrus 0:0a673c671a56 114
ebrus 0:0a673c671a56 115 #define MBED_ANALOGIN0 ADC0
ebrus 0:0a673c671a56 116 #define MBED_ANALOGIN1 ADC1
ebrus 0:0a673c671a56 117 #define MBED_ANALOGIN2 ADC2
ebrus 0:0a673c671a56 118 #define MBED_ANALOGIN3 ADC3
ebrus 0:0a673c671a56 119 #define MBED_ANALOGIN4 ADC4
ebrus 0:0a673c671a56 120 #define MBED_ANALOGIN5 ADC5
ebrus 0:0a673c671a56 121 #define MBED_ANALOGIN6 ADC6
ebrus 0:0a673c671a56 122 #define MBED_ANALOGIN7 ADC7
ebrus 0:0a673c671a56 123
ebrus 0:0a673c671a56 124 #define MBED_PWMOUT0 p26
ebrus 0:0a673c671a56 125 #define MBED_PWMOUT1 p25
ebrus 0:0a673c671a56 126 #define MBED_PWMOUT2 p24
ebrus 0:0a673c671a56 127 #define MBED_PWMOUT3 p23
ebrus 0:0a673c671a56 128 #define MBED_PWMOUT4 p22
ebrus 0:0a673c671a56 129 #define MBED_PWMOUT5 p21
ebrus 0:0a673c671a56 130
ebrus 0:0a673c671a56 131 #ifdef __cplusplus
ebrus 0:0a673c671a56 132 }
ebrus 0:0a673c671a56 133 #endif
ebrus 0:0a673c671a56 134
ebrus 0:0a673c671a56 135 #endif