Ermanno Brusadin / mbed-src

mbed library sources

targets/hal/TARGET_NXP/TARGET_LPC408X/PeripheralNames.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

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ebrus 0:0a673c671a56 1 /* mbed Microcontroller Library
ebrus 0:0a673c671a56 2 * Copyright (c) 2006-2013 ARM Limited
ebrus 0:0a673c671a56 3 *
ebrus 0:0a673c671a56 4 * Licensed under the Apache License, Version 2.0 (the "License");
ebrus 0:0a673c671a56 5 * you may not use this file except in compliance with the License.
ebrus 0:0a673c671a56 6 * You may obtain a copy of the License at
ebrus 0:0a673c671a56 7 *
ebrus 0:0a673c671a56 8 * http://www.apache.org/licenses/LICENSE-2.0
ebrus 0:0a673c671a56 9 *
ebrus 0:0a673c671a56 10 * Unless required by applicable law or agreed to in writing, software
ebrus 0:0a673c671a56 11 * distributed under the License is distributed on an "AS IS" BASIS,
ebrus 0:0a673c671a56 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ebrus 0:0a673c671a56 13 * See the License for the specific language governing permissions and
ebrus 0:0a673c671a56 14 * limitations under the License.
ebrus 0:0a673c671a56 15 */
ebrus 0:0a673c671a56 16 #ifndef MBED_PERIPHERALNAMES_H
ebrus 0:0a673c671a56 17 #define MBED_PERIPHERALNAMES_H
ebrus 0:0a673c671a56 18
ebrus 0:0a673c671a56 19 #include "cmsis.h"
ebrus 0:0a673c671a56 20
ebrus 0:0a673c671a56 21 #ifdef __cplusplus
ebrus 0:0a673c671a56 22 extern "C" {
ebrus 0:0a673c671a56 23 #endif
ebrus 0:0a673c671a56 24
ebrus 0:0a673c671a56 25 typedef enum {
ebrus 0:0a673c671a56 26 UART_0 = (int)LPC_UART0_BASE,
ebrus 0:0a673c671a56 27 UART_1 = (int)LPC_UART1_BASE,
ebrus 0:0a673c671a56 28 UART_2 = (int)LPC_UART2_BASE,
ebrus 0:0a673c671a56 29 UART_3 = (int)LPC_UART3_BASE,
ebrus 0:0a673c671a56 30 UART_4 = (int)LPC_UART4_BASE
ebrus 0:0a673c671a56 31 } UARTName;
ebrus 0:0a673c671a56 32
ebrus 0:0a673c671a56 33 typedef enum {
ebrus 0:0a673c671a56 34 ADC0_0 = 0,
ebrus 0:0a673c671a56 35 ADC0_1,
ebrus 0:0a673c671a56 36 ADC0_2,
ebrus 0:0a673c671a56 37 ADC0_3,
ebrus 0:0a673c671a56 38 ADC0_4,
ebrus 0:0a673c671a56 39 ADC0_5,
ebrus 0:0a673c671a56 40 ADC0_6,
ebrus 0:0a673c671a56 41 ADC0_7
ebrus 0:0a673c671a56 42 } ADCName;
ebrus 0:0a673c671a56 43
ebrus 0:0a673c671a56 44 typedef enum {
ebrus 0:0a673c671a56 45 DAC_0 = 0
ebrus 0:0a673c671a56 46 } DACName;
ebrus 0:0a673c671a56 47
ebrus 0:0a673c671a56 48 typedef enum {
ebrus 0:0a673c671a56 49 SPI_0 = (int)LPC_SSP0_BASE,
ebrus 0:0a673c671a56 50 SPI_1 = (int)LPC_SSP1_BASE,
ebrus 0:0a673c671a56 51 SPI_2 = (int)LPC_SSP2_BASE
ebrus 0:0a673c671a56 52 } SPIName;
ebrus 0:0a673c671a56 53
ebrus 0:0a673c671a56 54 typedef enum {
ebrus 0:0a673c671a56 55 I2C_0 = (int)LPC_I2C0_BASE,
ebrus 0:0a673c671a56 56 I2C_1 = (int)LPC_I2C1_BASE,
ebrus 0:0a673c671a56 57 I2C_2 = (int)LPC_I2C2_BASE
ebrus 0:0a673c671a56 58 } I2CName;
ebrus 0:0a673c671a56 59
ebrus 0:0a673c671a56 60 typedef enum {
ebrus 0:0a673c671a56 61 PWM0_1 = 1,
ebrus 0:0a673c671a56 62 PWM0_2,
ebrus 0:0a673c671a56 63 PWM0_3,
ebrus 0:0a673c671a56 64 PWM0_4,
ebrus 0:0a673c671a56 65 PWM0_5,
ebrus 0:0a673c671a56 66 PWM0_6,
ebrus 0:0a673c671a56 67 PWM1_1,
ebrus 0:0a673c671a56 68 PWM1_2,
ebrus 0:0a673c671a56 69 PWM1_3,
ebrus 0:0a673c671a56 70 PWM1_4,
ebrus 0:0a673c671a56 71 PWM1_5,
ebrus 0:0a673c671a56 72 PWM1_6
ebrus 0:0a673c671a56 73 } PWMName;
ebrus 0:0a673c671a56 74
ebrus 0:0a673c671a56 75 typedef enum {
ebrus 0:0a673c671a56 76 CAN_1 = (int)LPC_CAN1_BASE,
ebrus 0:0a673c671a56 77 CAN_2 = (int)LPC_CAN2_BASE
ebrus 0:0a673c671a56 78 } CANName;
ebrus 0:0a673c671a56 79
ebrus 0:0a673c671a56 80 #define STDIO_UART_TX USBTX
ebrus 0:0a673c671a56 81 #define STDIO_UART_RX USBRX
ebrus 0:0a673c671a56 82 #define STDIO_UART UART_0
ebrus 0:0a673c671a56 83
ebrus 0:0a673c671a56 84 // Default peripherals
ebrus 0:0a673c671a56 85 #define MBED_SPI0 p5, p6, p7
ebrus 0:0a673c671a56 86 #define MBED_SPI1 p11, p12, p13, p14
ebrus 0:0a673c671a56 87 #define MBED_SPI2 p39, p38, p32, p31
ebrus 0:0a673c671a56 88
ebrus 0:0a673c671a56 89 #define MBED_UART3 p9, p10
ebrus 0:0a673c671a56 90 #define MBED_UART4 p37, p31
ebrus 0:0a673c671a56 91 #define MBED_UARTUSB USBTX, USBRX
ebrus 0:0a673c671a56 92
ebrus 0:0a673c671a56 93 #define MBED_I2C0 p32, p31
ebrus 0:0a673c671a56 94 #define MBED_I2C1 p9, p10
ebrus 0:0a673c671a56 95
ebrus 0:0a673c671a56 96 #define MBED_CAN1 p9, p10
ebrus 0:0a673c671a56 97 #define MBED_CAN2 p34, p33
ebrus 0:0a673c671a56 98
ebrus 0:0a673c671a56 99 #define MBED_ANALOGOUT0 p18
ebrus 0:0a673c671a56 100
ebrus 0:0a673c671a56 101 #define MBED_ANALOGIN0 p15
ebrus 0:0a673c671a56 102 #define MBED_ANALOGIN1 p16
ebrus 0:0a673c671a56 103 #define MBED_ANALOGIN2 p17
ebrus 0:0a673c671a56 104 #define MBED_ANALOGIN3 p18
ebrus 0:0a673c671a56 105 #define MBED_ANALOGIN4 p19
ebrus 0:0a673c671a56 106 #define MBED_ANALOGIN5 p20
ebrus 0:0a673c671a56 107
ebrus 0:0a673c671a56 108 #define MBED_PWMOUT0 p30
ebrus 0:0a673c671a56 109 #define MBED_PWMOUT1 p29
ebrus 0:0a673c671a56 110 #define MBED_PWMOUT2 p28
ebrus 0:0a673c671a56 111 #define MBED_PWMOUT3 p27
ebrus 0:0a673c671a56 112 #define MBED_PWMOUT4 p26
ebrus 0:0a673c671a56 113 #define MBED_PWMOUT5 p25
ebrus 0:0a673c671a56 114
ebrus 0:0a673c671a56 115 #ifdef __cplusplus
ebrus 0:0a673c671a56 116 }
ebrus 0:0a673c671a56 117 #endif
ebrus 0:0a673c671a56 118
ebrus 0:0a673c671a56 119 #endif