Ermanno Brusadin / mbed-src

mbed library sources

targets/hal/TARGET_Freescale/TARGET_K20D50M/PeripheralNames.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

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ebrus 0:0a673c671a56 1 /* mbed Microcontroller Library
ebrus 0:0a673c671a56 2 * Copyright (c) 2006-2013 ARM Limited
ebrus 0:0a673c671a56 3 *
ebrus 0:0a673c671a56 4 * Licensed under the Apache License, Version 2.0 (the "License");
ebrus 0:0a673c671a56 5 * you may not use this file except in compliance with the License.
ebrus 0:0a673c671a56 6 * You may obtain a copy of the License at
ebrus 0:0a673c671a56 7 *
ebrus 0:0a673c671a56 8 * http://www.apache.org/licenses/LICENSE-2.0
ebrus 0:0a673c671a56 9 *
ebrus 0:0a673c671a56 10 * Unless required by applicable law or agreed to in writing, software
ebrus 0:0a673c671a56 11 * distributed under the License is distributed on an "AS IS" BASIS,
ebrus 0:0a673c671a56 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ebrus 0:0a673c671a56 13 * See the License for the specific language governing permissions and
ebrus 0:0a673c671a56 14 * limitations under the License.
ebrus 0:0a673c671a56 15 */
ebrus 0:0a673c671a56 16 #ifndef MBED_PERIPHERALNAMES_H
ebrus 0:0a673c671a56 17 #define MBED_PERIPHERALNAMES_H
ebrus 0:0a673c671a56 18
ebrus 0:0a673c671a56 19 #include "cmsis.h"
ebrus 0:0a673c671a56 20
ebrus 0:0a673c671a56 21 #ifdef __cplusplus
ebrus 0:0a673c671a56 22 extern "C" {
ebrus 0:0a673c671a56 23 #endif
ebrus 0:0a673c671a56 24
ebrus 0:0a673c671a56 25 typedef enum {
ebrus 0:0a673c671a56 26 UART_0 = (int)UART0_BASE,
ebrus 0:0a673c671a56 27 UART_1 = (int)UART1_BASE,
ebrus 0:0a673c671a56 28 UART_2 = (int)UART2_BASE
ebrus 0:0a673c671a56 29 } UARTName;
ebrus 0:0a673c671a56 30 #define STDIO_UART_TX USBTX
ebrus 0:0a673c671a56 31 #define STDIO_UART_RX USBRX
ebrus 0:0a673c671a56 32 #define STDIO_UART UART_0
ebrus 0:0a673c671a56 33
ebrus 0:0a673c671a56 34 typedef enum {
ebrus 0:0a673c671a56 35 I2C_0 = (int)I2C0_BASE,
ebrus 0:0a673c671a56 36 } I2CName;
ebrus 0:0a673c671a56 37
ebrus 0:0a673c671a56 38 #define TPM_SHIFT 8
ebrus 0:0a673c671a56 39 typedef enum {
ebrus 0:0a673c671a56 40 PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
ebrus 0:0a673c671a56 41 PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
ebrus 0:0a673c671a56 42 PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
ebrus 0:0a673c671a56 43 PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
ebrus 0:0a673c671a56 44 PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
ebrus 0:0a673c671a56 45 PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
ebrus 0:0a673c671a56 46 PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
ebrus 0:0a673c671a56 47 PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
ebrus 0:0a673c671a56 48 PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
ebrus 0:0a673c671a56 49 PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
ebrus 0:0a673c671a56 50 } PWMName;
ebrus 0:0a673c671a56 51
ebrus 0:0a673c671a56 52 typedef enum {
ebrus 0:0a673c671a56 53 ADC0_SE4b = 4,
ebrus 0:0a673c671a56 54 ADC0_SE5b = 5,
ebrus 0:0a673c671a56 55 ADC0_SE6b = 6,
ebrus 0:0a673c671a56 56 ADC0_SE7b = 7,
ebrus 0:0a673c671a56 57 ADC0_SE8 = 8,
ebrus 0:0a673c671a56 58 ADC0_SE9 = 9,
ebrus 0:0a673c671a56 59 ADC0_SE12 = 12,
ebrus 0:0a673c671a56 60 ADC0_SE13 = 13,
ebrus 0:0a673c671a56 61 ADC0_SE14 = 14,
ebrus 0:0a673c671a56 62 ADC0_SE15 = 15
ebrus 0:0a673c671a56 63 } ADCName;
ebrus 0:0a673c671a56 64
ebrus 0:0a673c671a56 65 typedef enum {
ebrus 0:0a673c671a56 66 DAC_0 = 0
ebrus 0:0a673c671a56 67 } DACName;
ebrus 0:0a673c671a56 68
ebrus 0:0a673c671a56 69
ebrus 0:0a673c671a56 70 typedef enum {
ebrus 0:0a673c671a56 71 SPI_0 = (int)SPI0_BASE,
ebrus 0:0a673c671a56 72 } SPIName;
ebrus 0:0a673c671a56 73
ebrus 0:0a673c671a56 74 #ifdef __cplusplus
ebrus 0:0a673c671a56 75 }
ebrus 0:0a673c671a56 76 #endif
ebrus 0:0a673c671a56 77
ebrus 0:0a673c671a56 78 #endif