Ermanno Brusadin / mbed-src

mbed library sources

targets/cmsis/core_cmInstr.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

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ebrus 0:0a673c671a56 1 /**************************************************************************//**
ebrus 0:0a673c671a56 2 * @file core_cmInstr.h
ebrus 0:0a673c671a56 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
ebrus 0:0a673c671a56 4 * @version V3.20
ebrus 0:0a673c671a56 5 * @date 05. March 2013
ebrus 0:0a673c671a56 6 *
ebrus 0:0a673c671a56 7 * @note
ebrus 0:0a673c671a56 8 *
ebrus 0:0a673c671a56 9 ******************************************************************************/
ebrus 0:0a673c671a56 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
ebrus 0:0a673c671a56 11
ebrus 0:0a673c671a56 12 All rights reserved.
ebrus 0:0a673c671a56 13 Redistribution and use in source and binary forms, with or without
ebrus 0:0a673c671a56 14 modification, are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 15 - Redistributions of source code must retain the above copyright
ebrus 0:0a673c671a56 16 notice, this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 17 - Redistributions in binary form must reproduce the above copyright
ebrus 0:0a673c671a56 18 notice, this list of conditions and the following disclaimer in the
ebrus 0:0a673c671a56 19 documentation and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 20 - Neither the name of ARM nor the names of its contributors may be used
ebrus 0:0a673c671a56 21 to endorse or promote products derived from this software without
ebrus 0:0a673c671a56 22 specific prior written permission.
ebrus 0:0a673c671a56 23 *
ebrus 0:0a673c671a56 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ebrus 0:0a673c671a56 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
ebrus 0:0a673c671a56 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
ebrus 0:0a673c671a56 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
ebrus 0:0a673c671a56 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
ebrus 0:0a673c671a56 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
ebrus 0:0a673c671a56 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ebrus 0:0a673c671a56 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
ebrus 0:0a673c671a56 34 POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 35 ---------------------------------------------------------------------------*/
ebrus 0:0a673c671a56 36
ebrus 0:0a673c671a56 37
ebrus 0:0a673c671a56 38 #ifndef __CORE_CMINSTR_H
ebrus 0:0a673c671a56 39 #define __CORE_CMINSTR_H
ebrus 0:0a673c671a56 40
ebrus 0:0a673c671a56 41
ebrus 0:0a673c671a56 42 /* ########################## Core Instruction Access ######################### */
ebrus 0:0a673c671a56 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
ebrus 0:0a673c671a56 44 Access to dedicated instructions
ebrus 0:0a673c671a56 45 @{
ebrus 0:0a673c671a56 46 */
ebrus 0:0a673c671a56 47
ebrus 0:0a673c671a56 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
ebrus 0:0a673c671a56 49 /* ARM armcc specific functions */
ebrus 0:0a673c671a56 50
ebrus 0:0a673c671a56 51 #if (__ARMCC_VERSION < 400677)
ebrus 0:0a673c671a56 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
ebrus 0:0a673c671a56 53 #endif
ebrus 0:0a673c671a56 54
ebrus 0:0a673c671a56 55
ebrus 0:0a673c671a56 56 /** \brief No Operation
ebrus 0:0a673c671a56 57
ebrus 0:0a673c671a56 58 No Operation does nothing. This instruction can be used for code alignment purposes.
ebrus 0:0a673c671a56 59 */
ebrus 0:0a673c671a56 60 #define __NOP __nop
ebrus 0:0a673c671a56 61
ebrus 0:0a673c671a56 62
ebrus 0:0a673c671a56 63 /** \brief Wait For Interrupt
ebrus 0:0a673c671a56 64
ebrus 0:0a673c671a56 65 Wait For Interrupt is a hint instruction that suspends execution
ebrus 0:0a673c671a56 66 until one of a number of events occurs.
ebrus 0:0a673c671a56 67 */
ebrus 0:0a673c671a56 68 #define __WFI __wfi
ebrus 0:0a673c671a56 69
ebrus 0:0a673c671a56 70
ebrus 0:0a673c671a56 71 /** \brief Wait For Event
ebrus 0:0a673c671a56 72
ebrus 0:0a673c671a56 73 Wait For Event is a hint instruction that permits the processor to enter
ebrus 0:0a673c671a56 74 a low-power state until one of a number of events occurs.
ebrus 0:0a673c671a56 75 */
ebrus 0:0a673c671a56 76 #define __WFE __wfe
ebrus 0:0a673c671a56 77
ebrus 0:0a673c671a56 78
ebrus 0:0a673c671a56 79 /** \brief Send Event
ebrus 0:0a673c671a56 80
ebrus 0:0a673c671a56 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
ebrus 0:0a673c671a56 82 */
ebrus 0:0a673c671a56 83 #define __SEV __sev
ebrus 0:0a673c671a56 84
ebrus 0:0a673c671a56 85
ebrus 0:0a673c671a56 86 /** \brief Instruction Synchronization Barrier
ebrus 0:0a673c671a56 87
ebrus 0:0a673c671a56 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
ebrus 0:0a673c671a56 89 so that all instructions following the ISB are fetched from cache or
ebrus 0:0a673c671a56 90 memory, after the instruction has been completed.
ebrus 0:0a673c671a56 91 */
ebrus 0:0a673c671a56 92 #define __ISB() __isb(0xF)
ebrus 0:0a673c671a56 93
ebrus 0:0a673c671a56 94
ebrus 0:0a673c671a56 95 /** \brief Data Synchronization Barrier
ebrus 0:0a673c671a56 96
ebrus 0:0a673c671a56 97 This function acts as a special kind of Data Memory Barrier.
ebrus 0:0a673c671a56 98 It completes when all explicit memory accesses before this instruction complete.
ebrus 0:0a673c671a56 99 */
ebrus 0:0a673c671a56 100 #define __DSB() __dsb(0xF)
ebrus 0:0a673c671a56 101
ebrus 0:0a673c671a56 102
ebrus 0:0a673c671a56 103 /** \brief Data Memory Barrier
ebrus 0:0a673c671a56 104
ebrus 0:0a673c671a56 105 This function ensures the apparent order of the explicit memory operations before
ebrus 0:0a673c671a56 106 and after the instruction, without ensuring their completion.
ebrus 0:0a673c671a56 107 */
ebrus 0:0a673c671a56 108 #define __DMB() __dmb(0xF)
ebrus 0:0a673c671a56 109
ebrus 0:0a673c671a56 110
ebrus 0:0a673c671a56 111 /** \brief Reverse byte order (32 bit)
ebrus 0:0a673c671a56 112
ebrus 0:0a673c671a56 113 This function reverses the byte order in integer value.
ebrus 0:0a673c671a56 114
ebrus 0:0a673c671a56 115 \param [in] value Value to reverse
ebrus 0:0a673c671a56 116 \return Reversed value
ebrus 0:0a673c671a56 117 */
ebrus 0:0a673c671a56 118 #define __REV __rev
ebrus 0:0a673c671a56 119
ebrus 0:0a673c671a56 120
ebrus 0:0a673c671a56 121 /** \brief Reverse byte order (16 bit)
ebrus 0:0a673c671a56 122
ebrus 0:0a673c671a56 123 This function reverses the byte order in two unsigned short values.
ebrus 0:0a673c671a56 124
ebrus 0:0a673c671a56 125 \param [in] value Value to reverse
ebrus 0:0a673c671a56 126 \return Reversed value
ebrus 0:0a673c671a56 127 */
ebrus 0:0a673c671a56 128 #ifndef __NO_EMBEDDED_ASM
ebrus 0:0a673c671a56 129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
ebrus 0:0a673c671a56 130 {
ebrus 0:0a673c671a56 131 rev16 r0, r0
ebrus 0:0a673c671a56 132 bx lr
ebrus 0:0a673c671a56 133 }
ebrus 0:0a673c671a56 134 #endif
ebrus 0:0a673c671a56 135
ebrus 0:0a673c671a56 136 /** \brief Reverse byte order in signed short value
ebrus 0:0a673c671a56 137
ebrus 0:0a673c671a56 138 This function reverses the byte order in a signed short value with sign extension to integer.
ebrus 0:0a673c671a56 139
ebrus 0:0a673c671a56 140 \param [in] value Value to reverse
ebrus 0:0a673c671a56 141 \return Reversed value
ebrus 0:0a673c671a56 142 */
ebrus 0:0a673c671a56 143 #ifndef __NO_EMBEDDED_ASM
ebrus 0:0a673c671a56 144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
ebrus 0:0a673c671a56 145 {
ebrus 0:0a673c671a56 146 revsh r0, r0
ebrus 0:0a673c671a56 147 bx lr
ebrus 0:0a673c671a56 148 }
ebrus 0:0a673c671a56 149 #endif
ebrus 0:0a673c671a56 150
ebrus 0:0a673c671a56 151
ebrus 0:0a673c671a56 152 /** \brief Rotate Right in unsigned value (32 bit)
ebrus 0:0a673c671a56 153
ebrus 0:0a673c671a56 154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
ebrus 0:0a673c671a56 155
ebrus 0:0a673c671a56 156 \param [in] value Value to rotate
ebrus 0:0a673c671a56 157 \param [in] value Number of Bits to rotate
ebrus 0:0a673c671a56 158 \return Rotated value
ebrus 0:0a673c671a56 159 */
ebrus 0:0a673c671a56 160 #define __ROR __ror
ebrus 0:0a673c671a56 161
ebrus 0:0a673c671a56 162
ebrus 0:0a673c671a56 163 /** \brief Breakpoint
ebrus 0:0a673c671a56 164
ebrus 0:0a673c671a56 165 This function causes the processor to enter Debug state.
ebrus 0:0a673c671a56 166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
ebrus 0:0a673c671a56 167
ebrus 0:0a673c671a56 168 \param [in] value is ignored by the processor.
ebrus 0:0a673c671a56 169 If required, a debugger can use it to store additional information about the breakpoint.
ebrus 0:0a673c671a56 170 */
ebrus 0:0a673c671a56 171 #define __BKPT(value) __breakpoint(value)
ebrus 0:0a673c671a56 172
ebrus 0:0a673c671a56 173
ebrus 0:0a673c671a56 174 #if (__CORTEX_M >= 0x03)
ebrus 0:0a673c671a56 175
ebrus 0:0a673c671a56 176 /** \brief Reverse bit order of value
ebrus 0:0a673c671a56 177
ebrus 0:0a673c671a56 178 This function reverses the bit order of the given value.
ebrus 0:0a673c671a56 179
ebrus 0:0a673c671a56 180 \param [in] value Value to reverse
ebrus 0:0a673c671a56 181 \return Reversed value
ebrus 0:0a673c671a56 182 */
ebrus 0:0a673c671a56 183 #define __RBIT __rbit
ebrus 0:0a673c671a56 184
ebrus 0:0a673c671a56 185
ebrus 0:0a673c671a56 186 /** \brief LDR Exclusive (8 bit)
ebrus 0:0a673c671a56 187
ebrus 0:0a673c671a56 188 This function performs a exclusive LDR command for 8 bit value.
ebrus 0:0a673c671a56 189
ebrus 0:0a673c671a56 190 \param [in] ptr Pointer to data
ebrus 0:0a673c671a56 191 \return value of type uint8_t at (*ptr)
ebrus 0:0a673c671a56 192 */
ebrus 0:0a673c671a56 193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
ebrus 0:0a673c671a56 194
ebrus 0:0a673c671a56 195
ebrus 0:0a673c671a56 196 /** \brief LDR Exclusive (16 bit)
ebrus 0:0a673c671a56 197
ebrus 0:0a673c671a56 198 This function performs a exclusive LDR command for 16 bit values.
ebrus 0:0a673c671a56 199
ebrus 0:0a673c671a56 200 \param [in] ptr Pointer to data
ebrus 0:0a673c671a56 201 \return value of type uint16_t at (*ptr)
ebrus 0:0a673c671a56 202 */
ebrus 0:0a673c671a56 203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
ebrus 0:0a673c671a56 204
ebrus 0:0a673c671a56 205
ebrus 0:0a673c671a56 206 /** \brief LDR Exclusive (32 bit)
ebrus 0:0a673c671a56 207
ebrus 0:0a673c671a56 208 This function performs a exclusive LDR command for 32 bit values.
ebrus 0:0a673c671a56 209
ebrus 0:0a673c671a56 210 \param [in] ptr Pointer to data
ebrus 0:0a673c671a56 211 \return value of type uint32_t at (*ptr)
ebrus 0:0a673c671a56 212 */
ebrus 0:0a673c671a56 213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
ebrus 0:0a673c671a56 214
ebrus 0:0a673c671a56 215
ebrus 0:0a673c671a56 216 /** \brief STR Exclusive (8 bit)
ebrus 0:0a673c671a56 217
ebrus 0:0a673c671a56 218 This function performs a exclusive STR command for 8 bit values.
ebrus 0:0a673c671a56 219
ebrus 0:0a673c671a56 220 \param [in] value Value to store
ebrus 0:0a673c671a56 221 \param [in] ptr Pointer to location
ebrus 0:0a673c671a56 222 \return 0 Function succeeded
ebrus 0:0a673c671a56 223 \return 1 Function failed
ebrus 0:0a673c671a56 224 */
ebrus 0:0a673c671a56 225 #define __STREXB(value, ptr) __strex(value, ptr)
ebrus 0:0a673c671a56 226
ebrus 0:0a673c671a56 227
ebrus 0:0a673c671a56 228 /** \brief STR Exclusive (16 bit)
ebrus 0:0a673c671a56 229
ebrus 0:0a673c671a56 230 This function performs a exclusive STR command for 16 bit values.
ebrus 0:0a673c671a56 231
ebrus 0:0a673c671a56 232 \param [in] value Value to store
ebrus 0:0a673c671a56 233 \param [in] ptr Pointer to location
ebrus 0:0a673c671a56 234 \return 0 Function succeeded
ebrus 0:0a673c671a56 235 \return 1 Function failed
ebrus 0:0a673c671a56 236 */
ebrus 0:0a673c671a56 237 #define __STREXH(value, ptr) __strex(value, ptr)
ebrus 0:0a673c671a56 238
ebrus 0:0a673c671a56 239
ebrus 0:0a673c671a56 240 /** \brief STR Exclusive (32 bit)
ebrus 0:0a673c671a56 241
ebrus 0:0a673c671a56 242 This function performs a exclusive STR command for 32 bit values.
ebrus 0:0a673c671a56 243
ebrus 0:0a673c671a56 244 \param [in] value Value to store
ebrus 0:0a673c671a56 245 \param [in] ptr Pointer to location
ebrus 0:0a673c671a56 246 \return 0 Function succeeded
ebrus 0:0a673c671a56 247 \return 1 Function failed
ebrus 0:0a673c671a56 248 */
ebrus 0:0a673c671a56 249 #define __STREXW(value, ptr) __strex(value, ptr)
ebrus 0:0a673c671a56 250
ebrus 0:0a673c671a56 251
ebrus 0:0a673c671a56 252 /** \brief Remove the exclusive lock
ebrus 0:0a673c671a56 253
ebrus 0:0a673c671a56 254 This function removes the exclusive lock which is created by LDREX.
ebrus 0:0a673c671a56 255
ebrus 0:0a673c671a56 256 */
ebrus 0:0a673c671a56 257 #define __CLREX __clrex
ebrus 0:0a673c671a56 258
ebrus 0:0a673c671a56 259
ebrus 0:0a673c671a56 260 /** \brief Signed Saturate
ebrus 0:0a673c671a56 261
ebrus 0:0a673c671a56 262 This function saturates a signed value.
ebrus 0:0a673c671a56 263
ebrus 0:0a673c671a56 264 \param [in] value Value to be saturated
ebrus 0:0a673c671a56 265 \param [in] sat Bit position to saturate to (1..32)
ebrus 0:0a673c671a56 266 \return Saturated value
ebrus 0:0a673c671a56 267 */
ebrus 0:0a673c671a56 268 #define __SSAT __ssat
ebrus 0:0a673c671a56 269
ebrus 0:0a673c671a56 270
ebrus 0:0a673c671a56 271 /** \brief Unsigned Saturate
ebrus 0:0a673c671a56 272
ebrus 0:0a673c671a56 273 This function saturates an unsigned value.
ebrus 0:0a673c671a56 274
ebrus 0:0a673c671a56 275 \param [in] value Value to be saturated
ebrus 0:0a673c671a56 276 \param [in] sat Bit position to saturate to (0..31)
ebrus 0:0a673c671a56 277 \return Saturated value
ebrus 0:0a673c671a56 278 */
ebrus 0:0a673c671a56 279 #define __USAT __usat
ebrus 0:0a673c671a56 280
ebrus 0:0a673c671a56 281
ebrus 0:0a673c671a56 282 /** \brief Count leading zeros
ebrus 0:0a673c671a56 283
ebrus 0:0a673c671a56 284 This function counts the number of leading zeros of a data value.
ebrus 0:0a673c671a56 285
ebrus 0:0a673c671a56 286 \param [in] value Value to count the leading zeros
ebrus 0:0a673c671a56 287 \return number of leading zeros in value
ebrus 0:0a673c671a56 288 */
ebrus 0:0a673c671a56 289 #define __CLZ __clz
ebrus 0:0a673c671a56 290
ebrus 0:0a673c671a56 291 #endif /* (__CORTEX_M >= 0x03) */
ebrus 0:0a673c671a56 292
ebrus 0:0a673c671a56 293
ebrus 0:0a673c671a56 294
ebrus 0:0a673c671a56 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
ebrus 0:0a673c671a56 296 /* IAR iccarm specific functions */
ebrus 0:0a673c671a56 297
ebrus 0:0a673c671a56 298 #include <cmsis_iar.h>
ebrus 0:0a673c671a56 299
ebrus 0:0a673c671a56 300
ebrus 0:0a673c671a56 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
ebrus 0:0a673c671a56 302 /* TI CCS specific functions */
ebrus 0:0a673c671a56 303
ebrus 0:0a673c671a56 304 #include <cmsis_ccs.h>
ebrus 0:0a673c671a56 305
ebrus 0:0a673c671a56 306
ebrus 0:0a673c671a56 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
ebrus 0:0a673c671a56 308 /* GNU gcc specific functions */
ebrus 0:0a673c671a56 309
ebrus 0:0a673c671a56 310 /* Define macros for porting to both thumb1 and thumb2.
ebrus 0:0a673c671a56 311 * For thumb1, use low register (r0-r7), specified by constrant "l"
ebrus 0:0a673c671a56 312 * Otherwise, use general registers, specified by constrant "r" */
ebrus 0:0a673c671a56 313 #if defined (__thumb__) && !defined (__thumb2__)
ebrus 0:0a673c671a56 314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
ebrus 0:0a673c671a56 315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
ebrus 0:0a673c671a56 316 #else
ebrus 0:0a673c671a56 317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
ebrus 0:0a673c671a56 318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
ebrus 0:0a673c671a56 319 #endif
ebrus 0:0a673c671a56 320
ebrus 0:0a673c671a56 321 /** \brief No Operation
ebrus 0:0a673c671a56 322
ebrus 0:0a673c671a56 323 No Operation does nothing. This instruction can be used for code alignment purposes.
ebrus 0:0a673c671a56 324 */
ebrus 0:0a673c671a56 325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
ebrus 0:0a673c671a56 326 {
ebrus 0:0a673c671a56 327 __ASM volatile ("nop");
ebrus 0:0a673c671a56 328 }
ebrus 0:0a673c671a56 329
ebrus 0:0a673c671a56 330
ebrus 0:0a673c671a56 331 /** \brief Wait For Interrupt
ebrus 0:0a673c671a56 332
ebrus 0:0a673c671a56 333 Wait For Interrupt is a hint instruction that suspends execution
ebrus 0:0a673c671a56 334 until one of a number of events occurs.
ebrus 0:0a673c671a56 335 */
ebrus 0:0a673c671a56 336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
ebrus 0:0a673c671a56 337 {
ebrus 0:0a673c671a56 338 __ASM volatile ("wfi");
ebrus 0:0a673c671a56 339 }
ebrus 0:0a673c671a56 340
ebrus 0:0a673c671a56 341
ebrus 0:0a673c671a56 342 /** \brief Wait For Event
ebrus 0:0a673c671a56 343
ebrus 0:0a673c671a56 344 Wait For Event is a hint instruction that permits the processor to enter
ebrus 0:0a673c671a56 345 a low-power state until one of a number of events occurs.
ebrus 0:0a673c671a56 346 */
ebrus 0:0a673c671a56 347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
ebrus 0:0a673c671a56 348 {
ebrus 0:0a673c671a56 349 __ASM volatile ("wfe");
ebrus 0:0a673c671a56 350 }
ebrus 0:0a673c671a56 351
ebrus 0:0a673c671a56 352
ebrus 0:0a673c671a56 353 /** \brief Send Event
ebrus 0:0a673c671a56 354
ebrus 0:0a673c671a56 355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
ebrus 0:0a673c671a56 356 */
ebrus 0:0a673c671a56 357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
ebrus 0:0a673c671a56 358 {
ebrus 0:0a673c671a56 359 __ASM volatile ("sev");
ebrus 0:0a673c671a56 360 }
ebrus 0:0a673c671a56 361
ebrus 0:0a673c671a56 362
ebrus 0:0a673c671a56 363 /** \brief Instruction Synchronization Barrier
ebrus 0:0a673c671a56 364
ebrus 0:0a673c671a56 365 Instruction Synchronization Barrier flushes the pipeline in the processor,
ebrus 0:0a673c671a56 366 so that all instructions following the ISB are fetched from cache or
ebrus 0:0a673c671a56 367 memory, after the instruction has been completed.
ebrus 0:0a673c671a56 368 */
ebrus 0:0a673c671a56 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
ebrus 0:0a673c671a56 370 {
ebrus 0:0a673c671a56 371 __ASM volatile ("isb");
ebrus 0:0a673c671a56 372 }
ebrus 0:0a673c671a56 373
ebrus 0:0a673c671a56 374
ebrus 0:0a673c671a56 375 /** \brief Data Synchronization Barrier
ebrus 0:0a673c671a56 376
ebrus 0:0a673c671a56 377 This function acts as a special kind of Data Memory Barrier.
ebrus 0:0a673c671a56 378 It completes when all explicit memory accesses before this instruction complete.
ebrus 0:0a673c671a56 379 */
ebrus 0:0a673c671a56 380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
ebrus 0:0a673c671a56 381 {
ebrus 0:0a673c671a56 382 __ASM volatile ("dsb");
ebrus 0:0a673c671a56 383 }
ebrus 0:0a673c671a56 384
ebrus 0:0a673c671a56 385
ebrus 0:0a673c671a56 386 /** \brief Data Memory Barrier
ebrus 0:0a673c671a56 387
ebrus 0:0a673c671a56 388 This function ensures the apparent order of the explicit memory operations before
ebrus 0:0a673c671a56 389 and after the instruction, without ensuring their completion.
ebrus 0:0a673c671a56 390 */
ebrus 0:0a673c671a56 391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
ebrus 0:0a673c671a56 392 {
ebrus 0:0a673c671a56 393 __ASM volatile ("dmb");
ebrus 0:0a673c671a56 394 }
ebrus 0:0a673c671a56 395
ebrus 0:0a673c671a56 396
ebrus 0:0a673c671a56 397 /** \brief Reverse byte order (32 bit)
ebrus 0:0a673c671a56 398
ebrus 0:0a673c671a56 399 This function reverses the byte order in integer value.
ebrus 0:0a673c671a56 400
ebrus 0:0a673c671a56 401 \param [in] value Value to reverse
ebrus 0:0a673c671a56 402 \return Reversed value
ebrus 0:0a673c671a56 403 */
ebrus 0:0a673c671a56 404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
ebrus 0:0a673c671a56 405 {
ebrus 0:0a673c671a56 406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
ebrus 0:0a673c671a56 407 return __builtin_bswap32(value);
ebrus 0:0a673c671a56 408 #else
ebrus 0:0a673c671a56 409 uint32_t result;
ebrus 0:0a673c671a56 410
ebrus 0:0a673c671a56 411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
ebrus 0:0a673c671a56 412 return(result);
ebrus 0:0a673c671a56 413 #endif
ebrus 0:0a673c671a56 414 }
ebrus 0:0a673c671a56 415
ebrus 0:0a673c671a56 416
ebrus 0:0a673c671a56 417 /** \brief Reverse byte order (16 bit)
ebrus 0:0a673c671a56 418
ebrus 0:0a673c671a56 419 This function reverses the byte order in two unsigned short values.
ebrus 0:0a673c671a56 420
ebrus 0:0a673c671a56 421 \param [in] value Value to reverse
ebrus 0:0a673c671a56 422 \return Reversed value
ebrus 0:0a673c671a56 423 */
ebrus 0:0a673c671a56 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
ebrus 0:0a673c671a56 425 {
ebrus 0:0a673c671a56 426 uint32_t result;
ebrus 0:0a673c671a56 427
ebrus 0:0a673c671a56 428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
ebrus 0:0a673c671a56 429 return(result);
ebrus 0:0a673c671a56 430 }
ebrus 0:0a673c671a56 431
ebrus 0:0a673c671a56 432
ebrus 0:0a673c671a56 433 /** \brief Reverse byte order in signed short value
ebrus 0:0a673c671a56 434
ebrus 0:0a673c671a56 435 This function reverses the byte order in a signed short value with sign extension to integer.
ebrus 0:0a673c671a56 436
ebrus 0:0a673c671a56 437 \param [in] value Value to reverse
ebrus 0:0a673c671a56 438 \return Reversed value
ebrus 0:0a673c671a56 439 */
ebrus 0:0a673c671a56 440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
ebrus 0:0a673c671a56 441 {
ebrus 0:0a673c671a56 442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
ebrus 0:0a673c671a56 443 return (short)__builtin_bswap16(value);
ebrus 0:0a673c671a56 444 #else
ebrus 0:0a673c671a56 445 uint32_t result;
ebrus 0:0a673c671a56 446
ebrus 0:0a673c671a56 447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
ebrus 0:0a673c671a56 448 return(result);
ebrus 0:0a673c671a56 449 #endif
ebrus 0:0a673c671a56 450 }
ebrus 0:0a673c671a56 451
ebrus 0:0a673c671a56 452
ebrus 0:0a673c671a56 453 /** \brief Rotate Right in unsigned value (32 bit)
ebrus 0:0a673c671a56 454
ebrus 0:0a673c671a56 455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
ebrus 0:0a673c671a56 456
ebrus 0:0a673c671a56 457 \param [in] value Value to rotate
ebrus 0:0a673c671a56 458 \param [in] value Number of Bits to rotate
ebrus 0:0a673c671a56 459 \return Rotated value
ebrus 0:0a673c671a56 460 */
ebrus 0:0a673c671a56 461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
ebrus 0:0a673c671a56 462 {
ebrus 0:0a673c671a56 463 return (op1 >> op2) | (op1 << (32 - op2));
ebrus 0:0a673c671a56 464 }
ebrus 0:0a673c671a56 465
ebrus 0:0a673c671a56 466
ebrus 0:0a673c671a56 467 /** \brief Breakpoint
ebrus 0:0a673c671a56 468
ebrus 0:0a673c671a56 469 This function causes the processor to enter Debug state.
ebrus 0:0a673c671a56 470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
ebrus 0:0a673c671a56 471
ebrus 0:0a673c671a56 472 \param [in] value is ignored by the processor.
ebrus 0:0a673c671a56 473 If required, a debugger can use it to store additional information about the breakpoint.
ebrus 0:0a673c671a56 474 */
ebrus 0:0a673c671a56 475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
ebrus 0:0a673c671a56 476
ebrus 0:0a673c671a56 477
ebrus 0:0a673c671a56 478 #if (__CORTEX_M >= 0x03)
ebrus 0:0a673c671a56 479
ebrus 0:0a673c671a56 480 /** \brief Reverse bit order of value
ebrus 0:0a673c671a56 481
ebrus 0:0a673c671a56 482 This function reverses the bit order of the given value.
ebrus 0:0a673c671a56 483
ebrus 0:0a673c671a56 484 \param [in] value Value to reverse
ebrus 0:0a673c671a56 485 \return Reversed value
ebrus 0:0a673c671a56 486 */
ebrus 0:0a673c671a56 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
ebrus 0:0a673c671a56 488 {
ebrus 0:0a673c671a56 489 uint32_t result;
ebrus 0:0a673c671a56 490
ebrus 0:0a673c671a56 491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
ebrus 0:0a673c671a56 492 return(result);
ebrus 0:0a673c671a56 493 }
ebrus 0:0a673c671a56 494
ebrus 0:0a673c671a56 495
ebrus 0:0a673c671a56 496 /** \brief LDR Exclusive (8 bit)
ebrus 0:0a673c671a56 497
ebrus 0:0a673c671a56 498 This function performs a exclusive LDR command for 8 bit value.
ebrus 0:0a673c671a56 499
ebrus 0:0a673c671a56 500 \param [in] ptr Pointer to data
ebrus 0:0a673c671a56 501 \return value of type uint8_t at (*ptr)
ebrus 0:0a673c671a56 502 */
ebrus 0:0a673c671a56 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
ebrus 0:0a673c671a56 504 {
ebrus 0:0a673c671a56 505 uint32_t result;
ebrus 0:0a673c671a56 506
ebrus 0:0a673c671a56 507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
ebrus 0:0a673c671a56 508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
ebrus 0:0a673c671a56 509 #else
ebrus 0:0a673c671a56 510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
ebrus 0:0a673c671a56 511 accepted by assembler. So has to use following less efficient pattern.
ebrus 0:0a673c671a56 512 */
ebrus 0:0a673c671a56 513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
ebrus 0:0a673c671a56 514 #endif
ebrus 0:0a673c671a56 515 return(result);
ebrus 0:0a673c671a56 516 }
ebrus 0:0a673c671a56 517
ebrus 0:0a673c671a56 518
ebrus 0:0a673c671a56 519 /** \brief LDR Exclusive (16 bit)
ebrus 0:0a673c671a56 520
ebrus 0:0a673c671a56 521 This function performs a exclusive LDR command for 16 bit values.
ebrus 0:0a673c671a56 522
ebrus 0:0a673c671a56 523 \param [in] ptr Pointer to data
ebrus 0:0a673c671a56 524 \return value of type uint16_t at (*ptr)
ebrus 0:0a673c671a56 525 */
ebrus 0:0a673c671a56 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
ebrus 0:0a673c671a56 527 {
ebrus 0:0a673c671a56 528 uint32_t result;
ebrus 0:0a673c671a56 529
ebrus 0:0a673c671a56 530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
ebrus 0:0a673c671a56 531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
ebrus 0:0a673c671a56 532 #else
ebrus 0:0a673c671a56 533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
ebrus 0:0a673c671a56 534 accepted by assembler. So has to use following less efficient pattern.
ebrus 0:0a673c671a56 535 */
ebrus 0:0a673c671a56 536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
ebrus 0:0a673c671a56 537 #endif
ebrus 0:0a673c671a56 538 return(result);
ebrus 0:0a673c671a56 539 }
ebrus 0:0a673c671a56 540
ebrus 0:0a673c671a56 541
ebrus 0:0a673c671a56 542 /** \brief LDR Exclusive (32 bit)
ebrus 0:0a673c671a56 543
ebrus 0:0a673c671a56 544 This function performs a exclusive LDR command for 32 bit values.
ebrus 0:0a673c671a56 545
ebrus 0:0a673c671a56 546 \param [in] ptr Pointer to data
ebrus 0:0a673c671a56 547 \return value of type uint32_t at (*ptr)
ebrus 0:0a673c671a56 548 */
ebrus 0:0a673c671a56 549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
ebrus 0:0a673c671a56 550 {
ebrus 0:0a673c671a56 551 uint32_t result;
ebrus 0:0a673c671a56 552
ebrus 0:0a673c671a56 553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
ebrus 0:0a673c671a56 554 return(result);
ebrus 0:0a673c671a56 555 }
ebrus 0:0a673c671a56 556
ebrus 0:0a673c671a56 557
ebrus 0:0a673c671a56 558 /** \brief STR Exclusive (8 bit)
ebrus 0:0a673c671a56 559
ebrus 0:0a673c671a56 560 This function performs a exclusive STR command for 8 bit values.
ebrus 0:0a673c671a56 561
ebrus 0:0a673c671a56 562 \param [in] value Value to store
ebrus 0:0a673c671a56 563 \param [in] ptr Pointer to location
ebrus 0:0a673c671a56 564 \return 0 Function succeeded
ebrus 0:0a673c671a56 565 \return 1 Function failed
ebrus 0:0a673c671a56 566 */
ebrus 0:0a673c671a56 567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
ebrus 0:0a673c671a56 568 {
ebrus 0:0a673c671a56 569 uint32_t result;
ebrus 0:0a673c671a56 570
ebrus 0:0a673c671a56 571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
ebrus 0:0a673c671a56 572 return(result);
ebrus 0:0a673c671a56 573 }
ebrus 0:0a673c671a56 574
ebrus 0:0a673c671a56 575
ebrus 0:0a673c671a56 576 /** \brief STR Exclusive (16 bit)
ebrus 0:0a673c671a56 577
ebrus 0:0a673c671a56 578 This function performs a exclusive STR command for 16 bit values.
ebrus 0:0a673c671a56 579
ebrus 0:0a673c671a56 580 \param [in] value Value to store
ebrus 0:0a673c671a56 581 \param [in] ptr Pointer to location
ebrus 0:0a673c671a56 582 \return 0 Function succeeded
ebrus 0:0a673c671a56 583 \return 1 Function failed
ebrus 0:0a673c671a56 584 */
ebrus 0:0a673c671a56 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
ebrus 0:0a673c671a56 586 {
ebrus 0:0a673c671a56 587 uint32_t result;
ebrus 0:0a673c671a56 588
ebrus 0:0a673c671a56 589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
ebrus 0:0a673c671a56 590 return(result);
ebrus 0:0a673c671a56 591 }
ebrus 0:0a673c671a56 592
ebrus 0:0a673c671a56 593
ebrus 0:0a673c671a56 594 /** \brief STR Exclusive (32 bit)
ebrus 0:0a673c671a56 595
ebrus 0:0a673c671a56 596 This function performs a exclusive STR command for 32 bit values.
ebrus 0:0a673c671a56 597
ebrus 0:0a673c671a56 598 \param [in] value Value to store
ebrus 0:0a673c671a56 599 \param [in] ptr Pointer to location
ebrus 0:0a673c671a56 600 \return 0 Function succeeded
ebrus 0:0a673c671a56 601 \return 1 Function failed
ebrus 0:0a673c671a56 602 */
ebrus 0:0a673c671a56 603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
ebrus 0:0a673c671a56 604 {
ebrus 0:0a673c671a56 605 uint32_t result;
ebrus 0:0a673c671a56 606
ebrus 0:0a673c671a56 607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
ebrus 0:0a673c671a56 608 return(result);
ebrus 0:0a673c671a56 609 }
ebrus 0:0a673c671a56 610
ebrus 0:0a673c671a56 611
ebrus 0:0a673c671a56 612 /** \brief Remove the exclusive lock
ebrus 0:0a673c671a56 613
ebrus 0:0a673c671a56 614 This function removes the exclusive lock which is created by LDREX.
ebrus 0:0a673c671a56 615
ebrus 0:0a673c671a56 616 */
ebrus 0:0a673c671a56 617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
ebrus 0:0a673c671a56 618 {
ebrus 0:0a673c671a56 619 __ASM volatile ("clrex" ::: "memory");
ebrus 0:0a673c671a56 620 }
ebrus 0:0a673c671a56 621
ebrus 0:0a673c671a56 622
ebrus 0:0a673c671a56 623 /** \brief Signed Saturate
ebrus 0:0a673c671a56 624
ebrus 0:0a673c671a56 625 This function saturates a signed value.
ebrus 0:0a673c671a56 626
ebrus 0:0a673c671a56 627 \param [in] value Value to be saturated
ebrus 0:0a673c671a56 628 \param [in] sat Bit position to saturate to (1..32)
ebrus 0:0a673c671a56 629 \return Saturated value
ebrus 0:0a673c671a56 630 */
ebrus 0:0a673c671a56 631 #define __SSAT(ARG1,ARG2) \
ebrus 0:0a673c671a56 632 ({ \
ebrus 0:0a673c671a56 633 uint32_t __RES, __ARG1 = (ARG1); \
ebrus 0:0a673c671a56 634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
ebrus 0:0a673c671a56 635 __RES; \
ebrus 0:0a673c671a56 636 })
ebrus 0:0a673c671a56 637
ebrus 0:0a673c671a56 638
ebrus 0:0a673c671a56 639 /** \brief Unsigned Saturate
ebrus 0:0a673c671a56 640
ebrus 0:0a673c671a56 641 This function saturates an unsigned value.
ebrus 0:0a673c671a56 642
ebrus 0:0a673c671a56 643 \param [in] value Value to be saturated
ebrus 0:0a673c671a56 644 \param [in] sat Bit position to saturate to (0..31)
ebrus 0:0a673c671a56 645 \return Saturated value
ebrus 0:0a673c671a56 646 */
ebrus 0:0a673c671a56 647 #define __USAT(ARG1,ARG2) \
ebrus 0:0a673c671a56 648 ({ \
ebrus 0:0a673c671a56 649 uint32_t __RES, __ARG1 = (ARG1); \
ebrus 0:0a673c671a56 650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
ebrus 0:0a673c671a56 651 __RES; \
ebrus 0:0a673c671a56 652 })
ebrus 0:0a673c671a56 653
ebrus 0:0a673c671a56 654
ebrus 0:0a673c671a56 655 /** \brief Count leading zeros
ebrus 0:0a673c671a56 656
ebrus 0:0a673c671a56 657 This function counts the number of leading zeros of a data value.
ebrus 0:0a673c671a56 658
ebrus 0:0a673c671a56 659 \param [in] value Value to count the leading zeros
ebrus 0:0a673c671a56 660 \return number of leading zeros in value
ebrus 0:0a673c671a56 661 */
ebrus 0:0a673c671a56 662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
ebrus 0:0a673c671a56 663 {
ebrus 0:0a673c671a56 664 uint32_t result;
ebrus 0:0a673c671a56 665
ebrus 0:0a673c671a56 666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
ebrus 0:0a673c671a56 667 return(result);
ebrus 0:0a673c671a56 668 }
ebrus 0:0a673c671a56 669
ebrus 0:0a673c671a56 670 #endif /* (__CORTEX_M >= 0x03) */
ebrus 0:0a673c671a56 671
ebrus 0:0a673c671a56 672
ebrus 0:0a673c671a56 673
ebrus 0:0a673c671a56 674
ebrus 0:0a673c671a56 675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
ebrus 0:0a673c671a56 676 /* TASKING carm specific functions */
ebrus 0:0a673c671a56 677
ebrus 0:0a673c671a56 678 /*
ebrus 0:0a673c671a56 679 * The CMSIS functions have been implemented as intrinsics in the compiler.
ebrus 0:0a673c671a56 680 * Please use "carm -?i" to get an up to date list of all intrinsics,
ebrus 0:0a673c671a56 681 * Including the CMSIS ones.
ebrus 0:0a673c671a56 682 */
ebrus 0:0a673c671a56 683
ebrus 0:0a673c671a56 684 #endif
ebrus 0:0a673c671a56 685
ebrus 0:0a673c671a56 686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
ebrus 0:0a673c671a56 687
ebrus 0:0a673c671a56 688 #endif /* __CORE_CMINSTR_H */