Ermanno Brusadin / mbed-src

mbed library sources

targets/cmsis/core_cmFunc.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

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ebrus 0:0a673c671a56 1 /**************************************************************************//**
ebrus 0:0a673c671a56 2 * @file core_cmFunc.h
ebrus 0:0a673c671a56 3 * @brief CMSIS Cortex-M Core Function Access Header File
ebrus 0:0a673c671a56 4 * @version V3.20
ebrus 0:0a673c671a56 5 * @date 25. February 2013
ebrus 0:0a673c671a56 6 *
ebrus 0:0a673c671a56 7 * @note
ebrus 0:0a673c671a56 8 *
ebrus 0:0a673c671a56 9 ******************************************************************************/
ebrus 0:0a673c671a56 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
ebrus 0:0a673c671a56 11
ebrus 0:0a673c671a56 12 All rights reserved.
ebrus 0:0a673c671a56 13 Redistribution and use in source and binary forms, with or without
ebrus 0:0a673c671a56 14 modification, are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 15 - Redistributions of source code must retain the above copyright
ebrus 0:0a673c671a56 16 notice, this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 17 - Redistributions in binary form must reproduce the above copyright
ebrus 0:0a673c671a56 18 notice, this list of conditions and the following disclaimer in the
ebrus 0:0a673c671a56 19 documentation and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 20 - Neither the name of ARM nor the names of its contributors may be used
ebrus 0:0a673c671a56 21 to endorse or promote products derived from this software without
ebrus 0:0a673c671a56 22 specific prior written permission.
ebrus 0:0a673c671a56 23 *
ebrus 0:0a673c671a56 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ebrus 0:0a673c671a56 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
ebrus 0:0a673c671a56 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
ebrus 0:0a673c671a56 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
ebrus 0:0a673c671a56 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
ebrus 0:0a673c671a56 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
ebrus 0:0a673c671a56 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ebrus 0:0a673c671a56 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
ebrus 0:0a673c671a56 34 POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 35 ---------------------------------------------------------------------------*/
ebrus 0:0a673c671a56 36
ebrus 0:0a673c671a56 37
ebrus 0:0a673c671a56 38 #ifndef __CORE_CMFUNC_H
ebrus 0:0a673c671a56 39 #define __CORE_CMFUNC_H
ebrus 0:0a673c671a56 40
ebrus 0:0a673c671a56 41
ebrus 0:0a673c671a56 42 /* ########################### Core Function Access ########################### */
ebrus 0:0a673c671a56 43 /** \ingroup CMSIS_Core_FunctionInterface
ebrus 0:0a673c671a56 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
ebrus 0:0a673c671a56 45 @{
ebrus 0:0a673c671a56 46 */
ebrus 0:0a673c671a56 47
ebrus 0:0a673c671a56 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
ebrus 0:0a673c671a56 49 /* ARM armcc specific functions */
ebrus 0:0a673c671a56 50
ebrus 0:0a673c671a56 51 #if (__ARMCC_VERSION < 400677)
ebrus 0:0a673c671a56 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
ebrus 0:0a673c671a56 53 #endif
ebrus 0:0a673c671a56 54
ebrus 0:0a673c671a56 55 /* intrinsic void __enable_irq(); */
ebrus 0:0a673c671a56 56 /* intrinsic void __disable_irq(); */
ebrus 0:0a673c671a56 57
ebrus 0:0a673c671a56 58 /** \brief Get Control Register
ebrus 0:0a673c671a56 59
ebrus 0:0a673c671a56 60 This function returns the content of the Control Register.
ebrus 0:0a673c671a56 61
ebrus 0:0a673c671a56 62 \return Control Register value
ebrus 0:0a673c671a56 63 */
ebrus 0:0a673c671a56 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
ebrus 0:0a673c671a56 65 {
ebrus 0:0a673c671a56 66 register uint32_t __regControl __ASM("control");
ebrus 0:0a673c671a56 67 return(__regControl);
ebrus 0:0a673c671a56 68 }
ebrus 0:0a673c671a56 69
ebrus 0:0a673c671a56 70
ebrus 0:0a673c671a56 71 /** \brief Set Control Register
ebrus 0:0a673c671a56 72
ebrus 0:0a673c671a56 73 This function writes the given value to the Control Register.
ebrus 0:0a673c671a56 74
ebrus 0:0a673c671a56 75 \param [in] control Control Register value to set
ebrus 0:0a673c671a56 76 */
ebrus 0:0a673c671a56 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
ebrus 0:0a673c671a56 78 {
ebrus 0:0a673c671a56 79 register uint32_t __regControl __ASM("control");
ebrus 0:0a673c671a56 80 __regControl = control;
ebrus 0:0a673c671a56 81 }
ebrus 0:0a673c671a56 82
ebrus 0:0a673c671a56 83
ebrus 0:0a673c671a56 84 /** \brief Get IPSR Register
ebrus 0:0a673c671a56 85
ebrus 0:0a673c671a56 86 This function returns the content of the IPSR Register.
ebrus 0:0a673c671a56 87
ebrus 0:0a673c671a56 88 \return IPSR Register value
ebrus 0:0a673c671a56 89 */
ebrus 0:0a673c671a56 90 __STATIC_INLINE uint32_t __get_IPSR(void)
ebrus 0:0a673c671a56 91 {
ebrus 0:0a673c671a56 92 register uint32_t __regIPSR __ASM("ipsr");
ebrus 0:0a673c671a56 93 return(__regIPSR);
ebrus 0:0a673c671a56 94 }
ebrus 0:0a673c671a56 95
ebrus 0:0a673c671a56 96
ebrus 0:0a673c671a56 97 /** \brief Get APSR Register
ebrus 0:0a673c671a56 98
ebrus 0:0a673c671a56 99 This function returns the content of the APSR Register.
ebrus 0:0a673c671a56 100
ebrus 0:0a673c671a56 101 \return APSR Register value
ebrus 0:0a673c671a56 102 */
ebrus 0:0a673c671a56 103 __STATIC_INLINE uint32_t __get_APSR(void)
ebrus 0:0a673c671a56 104 {
ebrus 0:0a673c671a56 105 register uint32_t __regAPSR __ASM("apsr");
ebrus 0:0a673c671a56 106 return(__regAPSR);
ebrus 0:0a673c671a56 107 }
ebrus 0:0a673c671a56 108
ebrus 0:0a673c671a56 109
ebrus 0:0a673c671a56 110 /** \brief Get xPSR Register
ebrus 0:0a673c671a56 111
ebrus 0:0a673c671a56 112 This function returns the content of the xPSR Register.
ebrus 0:0a673c671a56 113
ebrus 0:0a673c671a56 114 \return xPSR Register value
ebrus 0:0a673c671a56 115 */
ebrus 0:0a673c671a56 116 __STATIC_INLINE uint32_t __get_xPSR(void)
ebrus 0:0a673c671a56 117 {
ebrus 0:0a673c671a56 118 register uint32_t __regXPSR __ASM("xpsr");
ebrus 0:0a673c671a56 119 return(__regXPSR);
ebrus 0:0a673c671a56 120 }
ebrus 0:0a673c671a56 121
ebrus 0:0a673c671a56 122
ebrus 0:0a673c671a56 123 /** \brief Get Process Stack Pointer
ebrus 0:0a673c671a56 124
ebrus 0:0a673c671a56 125 This function returns the current value of the Process Stack Pointer (PSP).
ebrus 0:0a673c671a56 126
ebrus 0:0a673c671a56 127 \return PSP Register value
ebrus 0:0a673c671a56 128 */
ebrus 0:0a673c671a56 129 __STATIC_INLINE uint32_t __get_PSP(void)
ebrus 0:0a673c671a56 130 {
ebrus 0:0a673c671a56 131 register uint32_t __regProcessStackPointer __ASM("psp");
ebrus 0:0a673c671a56 132 return(__regProcessStackPointer);
ebrus 0:0a673c671a56 133 }
ebrus 0:0a673c671a56 134
ebrus 0:0a673c671a56 135
ebrus 0:0a673c671a56 136 /** \brief Set Process Stack Pointer
ebrus 0:0a673c671a56 137
ebrus 0:0a673c671a56 138 This function assigns the given value to the Process Stack Pointer (PSP).
ebrus 0:0a673c671a56 139
ebrus 0:0a673c671a56 140 \param [in] topOfProcStack Process Stack Pointer value to set
ebrus 0:0a673c671a56 141 */
ebrus 0:0a673c671a56 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
ebrus 0:0a673c671a56 143 {
ebrus 0:0a673c671a56 144 register uint32_t __regProcessStackPointer __ASM("psp");
ebrus 0:0a673c671a56 145 __regProcessStackPointer = topOfProcStack;
ebrus 0:0a673c671a56 146 }
ebrus 0:0a673c671a56 147
ebrus 0:0a673c671a56 148
ebrus 0:0a673c671a56 149 /** \brief Get Main Stack Pointer
ebrus 0:0a673c671a56 150
ebrus 0:0a673c671a56 151 This function returns the current value of the Main Stack Pointer (MSP).
ebrus 0:0a673c671a56 152
ebrus 0:0a673c671a56 153 \return MSP Register value
ebrus 0:0a673c671a56 154 */
ebrus 0:0a673c671a56 155 __STATIC_INLINE uint32_t __get_MSP(void)
ebrus 0:0a673c671a56 156 {
ebrus 0:0a673c671a56 157 register uint32_t __regMainStackPointer __ASM("msp");
ebrus 0:0a673c671a56 158 return(__regMainStackPointer);
ebrus 0:0a673c671a56 159 }
ebrus 0:0a673c671a56 160
ebrus 0:0a673c671a56 161
ebrus 0:0a673c671a56 162 /** \brief Set Main Stack Pointer
ebrus 0:0a673c671a56 163
ebrus 0:0a673c671a56 164 This function assigns the given value to the Main Stack Pointer (MSP).
ebrus 0:0a673c671a56 165
ebrus 0:0a673c671a56 166 \param [in] topOfMainStack Main Stack Pointer value to set
ebrus 0:0a673c671a56 167 */
ebrus 0:0a673c671a56 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
ebrus 0:0a673c671a56 169 {
ebrus 0:0a673c671a56 170 register uint32_t __regMainStackPointer __ASM("msp");
ebrus 0:0a673c671a56 171 __regMainStackPointer = topOfMainStack;
ebrus 0:0a673c671a56 172 }
ebrus 0:0a673c671a56 173
ebrus 0:0a673c671a56 174
ebrus 0:0a673c671a56 175 /** \brief Get Priority Mask
ebrus 0:0a673c671a56 176
ebrus 0:0a673c671a56 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
ebrus 0:0a673c671a56 178
ebrus 0:0a673c671a56 179 \return Priority Mask value
ebrus 0:0a673c671a56 180 */
ebrus 0:0a673c671a56 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
ebrus 0:0a673c671a56 182 {
ebrus 0:0a673c671a56 183 register uint32_t __regPriMask __ASM("primask");
ebrus 0:0a673c671a56 184 return(__regPriMask);
ebrus 0:0a673c671a56 185 }
ebrus 0:0a673c671a56 186
ebrus 0:0a673c671a56 187
ebrus 0:0a673c671a56 188 /** \brief Set Priority Mask
ebrus 0:0a673c671a56 189
ebrus 0:0a673c671a56 190 This function assigns the given value to the Priority Mask Register.
ebrus 0:0a673c671a56 191
ebrus 0:0a673c671a56 192 \param [in] priMask Priority Mask
ebrus 0:0a673c671a56 193 */
ebrus 0:0a673c671a56 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
ebrus 0:0a673c671a56 195 {
ebrus 0:0a673c671a56 196 register uint32_t __regPriMask __ASM("primask");
ebrus 0:0a673c671a56 197 __regPriMask = (priMask);
ebrus 0:0a673c671a56 198 }
ebrus 0:0a673c671a56 199
ebrus 0:0a673c671a56 200
ebrus 0:0a673c671a56 201 #if (__CORTEX_M >= 0x03)
ebrus 0:0a673c671a56 202
ebrus 0:0a673c671a56 203 /** \brief Enable FIQ
ebrus 0:0a673c671a56 204
ebrus 0:0a673c671a56 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
ebrus 0:0a673c671a56 206 Can only be executed in Privileged modes.
ebrus 0:0a673c671a56 207 */
ebrus 0:0a673c671a56 208 #define __enable_fault_irq __enable_fiq
ebrus 0:0a673c671a56 209
ebrus 0:0a673c671a56 210
ebrus 0:0a673c671a56 211 /** \brief Disable FIQ
ebrus 0:0a673c671a56 212
ebrus 0:0a673c671a56 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
ebrus 0:0a673c671a56 214 Can only be executed in Privileged modes.
ebrus 0:0a673c671a56 215 */
ebrus 0:0a673c671a56 216 #define __disable_fault_irq __disable_fiq
ebrus 0:0a673c671a56 217
ebrus 0:0a673c671a56 218
ebrus 0:0a673c671a56 219 /** \brief Get Base Priority
ebrus 0:0a673c671a56 220
ebrus 0:0a673c671a56 221 This function returns the current value of the Base Priority register.
ebrus 0:0a673c671a56 222
ebrus 0:0a673c671a56 223 \return Base Priority register value
ebrus 0:0a673c671a56 224 */
ebrus 0:0a673c671a56 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
ebrus 0:0a673c671a56 226 {
ebrus 0:0a673c671a56 227 register uint32_t __regBasePri __ASM("basepri");
ebrus 0:0a673c671a56 228 return(__regBasePri);
ebrus 0:0a673c671a56 229 }
ebrus 0:0a673c671a56 230
ebrus 0:0a673c671a56 231
ebrus 0:0a673c671a56 232 /** \brief Set Base Priority
ebrus 0:0a673c671a56 233
ebrus 0:0a673c671a56 234 This function assigns the given value to the Base Priority register.
ebrus 0:0a673c671a56 235
ebrus 0:0a673c671a56 236 \param [in] basePri Base Priority value to set
ebrus 0:0a673c671a56 237 */
ebrus 0:0a673c671a56 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
ebrus 0:0a673c671a56 239 {
ebrus 0:0a673c671a56 240 register uint32_t __regBasePri __ASM("basepri");
ebrus 0:0a673c671a56 241 __regBasePri = (basePri & 0xff);
ebrus 0:0a673c671a56 242 }
ebrus 0:0a673c671a56 243
ebrus 0:0a673c671a56 244
ebrus 0:0a673c671a56 245 /** \brief Get Fault Mask
ebrus 0:0a673c671a56 246
ebrus 0:0a673c671a56 247 This function returns the current value of the Fault Mask register.
ebrus 0:0a673c671a56 248
ebrus 0:0a673c671a56 249 \return Fault Mask register value
ebrus 0:0a673c671a56 250 */
ebrus 0:0a673c671a56 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
ebrus 0:0a673c671a56 252 {
ebrus 0:0a673c671a56 253 register uint32_t __regFaultMask __ASM("faultmask");
ebrus 0:0a673c671a56 254 return(__regFaultMask);
ebrus 0:0a673c671a56 255 }
ebrus 0:0a673c671a56 256
ebrus 0:0a673c671a56 257
ebrus 0:0a673c671a56 258 /** \brief Set Fault Mask
ebrus 0:0a673c671a56 259
ebrus 0:0a673c671a56 260 This function assigns the given value to the Fault Mask register.
ebrus 0:0a673c671a56 261
ebrus 0:0a673c671a56 262 \param [in] faultMask Fault Mask value to set
ebrus 0:0a673c671a56 263 */
ebrus 0:0a673c671a56 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
ebrus 0:0a673c671a56 265 {
ebrus 0:0a673c671a56 266 register uint32_t __regFaultMask __ASM("faultmask");
ebrus 0:0a673c671a56 267 __regFaultMask = (faultMask & (uint32_t)1);
ebrus 0:0a673c671a56 268 }
ebrus 0:0a673c671a56 269
ebrus 0:0a673c671a56 270 #endif /* (__CORTEX_M >= 0x03) */
ebrus 0:0a673c671a56 271
ebrus 0:0a673c671a56 272
ebrus 0:0a673c671a56 273 #if (__CORTEX_M == 0x04)
ebrus 0:0a673c671a56 274
ebrus 0:0a673c671a56 275 /** \brief Get FPSCR
ebrus 0:0a673c671a56 276
ebrus 0:0a673c671a56 277 This function returns the current value of the Floating Point Status/Control register.
ebrus 0:0a673c671a56 278
ebrus 0:0a673c671a56 279 \return Floating Point Status/Control register value
ebrus 0:0a673c671a56 280 */
ebrus 0:0a673c671a56 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
ebrus 0:0a673c671a56 282 {
ebrus 0:0a673c671a56 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
ebrus 0:0a673c671a56 284 register uint32_t __regfpscr __ASM("fpscr");
ebrus 0:0a673c671a56 285 return(__regfpscr);
ebrus 0:0a673c671a56 286 #else
ebrus 0:0a673c671a56 287 return(0);
ebrus 0:0a673c671a56 288 #endif
ebrus 0:0a673c671a56 289 }
ebrus 0:0a673c671a56 290
ebrus 0:0a673c671a56 291
ebrus 0:0a673c671a56 292 /** \brief Set FPSCR
ebrus 0:0a673c671a56 293
ebrus 0:0a673c671a56 294 This function assigns the given value to the Floating Point Status/Control register.
ebrus 0:0a673c671a56 295
ebrus 0:0a673c671a56 296 \param [in] fpscr Floating Point Status/Control value to set
ebrus 0:0a673c671a56 297 */
ebrus 0:0a673c671a56 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
ebrus 0:0a673c671a56 299 {
ebrus 0:0a673c671a56 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
ebrus 0:0a673c671a56 301 register uint32_t __regfpscr __ASM("fpscr");
ebrus 0:0a673c671a56 302 __regfpscr = (fpscr);
ebrus 0:0a673c671a56 303 #endif
ebrus 0:0a673c671a56 304 }
ebrus 0:0a673c671a56 305
ebrus 0:0a673c671a56 306 #endif /* (__CORTEX_M == 0x04) */
ebrus 0:0a673c671a56 307
ebrus 0:0a673c671a56 308
ebrus 0:0a673c671a56 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
ebrus 0:0a673c671a56 310 /* IAR iccarm specific functions */
ebrus 0:0a673c671a56 311
ebrus 0:0a673c671a56 312 #include <cmsis_iar.h>
ebrus 0:0a673c671a56 313
ebrus 0:0a673c671a56 314
ebrus 0:0a673c671a56 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
ebrus 0:0a673c671a56 316 /* TI CCS specific functions */
ebrus 0:0a673c671a56 317
ebrus 0:0a673c671a56 318 #include <cmsis_ccs.h>
ebrus 0:0a673c671a56 319
ebrus 0:0a673c671a56 320
ebrus 0:0a673c671a56 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
ebrus 0:0a673c671a56 322 /* GNU gcc specific functions */
ebrus 0:0a673c671a56 323
ebrus 0:0a673c671a56 324 /** \brief Enable IRQ Interrupts
ebrus 0:0a673c671a56 325
ebrus 0:0a673c671a56 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
ebrus 0:0a673c671a56 327 Can only be executed in Privileged modes.
ebrus 0:0a673c671a56 328 */
ebrus 0:0a673c671a56 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
ebrus 0:0a673c671a56 330 {
ebrus 0:0a673c671a56 331 __ASM volatile ("cpsie i" : : : "memory");
ebrus 0:0a673c671a56 332 }
ebrus 0:0a673c671a56 333
ebrus 0:0a673c671a56 334
ebrus 0:0a673c671a56 335 /** \brief Disable IRQ Interrupts
ebrus 0:0a673c671a56 336
ebrus 0:0a673c671a56 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
ebrus 0:0a673c671a56 338 Can only be executed in Privileged modes.
ebrus 0:0a673c671a56 339 */
ebrus 0:0a673c671a56 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
ebrus 0:0a673c671a56 341 {
ebrus 0:0a673c671a56 342 __ASM volatile ("cpsid i" : : : "memory");
ebrus 0:0a673c671a56 343 }
ebrus 0:0a673c671a56 344
ebrus 0:0a673c671a56 345
ebrus 0:0a673c671a56 346 /** \brief Get Control Register
ebrus 0:0a673c671a56 347
ebrus 0:0a673c671a56 348 This function returns the content of the Control Register.
ebrus 0:0a673c671a56 349
ebrus 0:0a673c671a56 350 \return Control Register value
ebrus 0:0a673c671a56 351 */
ebrus 0:0a673c671a56 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
ebrus 0:0a673c671a56 353 {
ebrus 0:0a673c671a56 354 uint32_t result;
ebrus 0:0a673c671a56 355
ebrus 0:0a673c671a56 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
ebrus 0:0a673c671a56 357 return(result);
ebrus 0:0a673c671a56 358 }
ebrus 0:0a673c671a56 359
ebrus 0:0a673c671a56 360
ebrus 0:0a673c671a56 361 /** \brief Set Control Register
ebrus 0:0a673c671a56 362
ebrus 0:0a673c671a56 363 This function writes the given value to the Control Register.
ebrus 0:0a673c671a56 364
ebrus 0:0a673c671a56 365 \param [in] control Control Register value to set
ebrus 0:0a673c671a56 366 */
ebrus 0:0a673c671a56 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
ebrus 0:0a673c671a56 368 {
ebrus 0:0a673c671a56 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
ebrus 0:0a673c671a56 370 }
ebrus 0:0a673c671a56 371
ebrus 0:0a673c671a56 372
ebrus 0:0a673c671a56 373 /** \brief Get IPSR Register
ebrus 0:0a673c671a56 374
ebrus 0:0a673c671a56 375 This function returns the content of the IPSR Register.
ebrus 0:0a673c671a56 376
ebrus 0:0a673c671a56 377 \return IPSR Register value
ebrus 0:0a673c671a56 378 */
ebrus 0:0a673c671a56 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
ebrus 0:0a673c671a56 380 {
ebrus 0:0a673c671a56 381 uint32_t result;
ebrus 0:0a673c671a56 382
ebrus 0:0a673c671a56 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
ebrus 0:0a673c671a56 384 return(result);
ebrus 0:0a673c671a56 385 }
ebrus 0:0a673c671a56 386
ebrus 0:0a673c671a56 387
ebrus 0:0a673c671a56 388 /** \brief Get APSR Register
ebrus 0:0a673c671a56 389
ebrus 0:0a673c671a56 390 This function returns the content of the APSR Register.
ebrus 0:0a673c671a56 391
ebrus 0:0a673c671a56 392 \return APSR Register value
ebrus 0:0a673c671a56 393 */
ebrus 0:0a673c671a56 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
ebrus 0:0a673c671a56 395 {
ebrus 0:0a673c671a56 396 uint32_t result;
ebrus 0:0a673c671a56 397
ebrus 0:0a673c671a56 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
ebrus 0:0a673c671a56 399 return(result);
ebrus 0:0a673c671a56 400 }
ebrus 0:0a673c671a56 401
ebrus 0:0a673c671a56 402
ebrus 0:0a673c671a56 403 /** \brief Get xPSR Register
ebrus 0:0a673c671a56 404
ebrus 0:0a673c671a56 405 This function returns the content of the xPSR Register.
ebrus 0:0a673c671a56 406
ebrus 0:0a673c671a56 407 \return xPSR Register value
ebrus 0:0a673c671a56 408 */
ebrus 0:0a673c671a56 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
ebrus 0:0a673c671a56 410 {
ebrus 0:0a673c671a56 411 uint32_t result;
ebrus 0:0a673c671a56 412
ebrus 0:0a673c671a56 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
ebrus 0:0a673c671a56 414 return(result);
ebrus 0:0a673c671a56 415 }
ebrus 0:0a673c671a56 416
ebrus 0:0a673c671a56 417
ebrus 0:0a673c671a56 418 /** \brief Get Process Stack Pointer
ebrus 0:0a673c671a56 419
ebrus 0:0a673c671a56 420 This function returns the current value of the Process Stack Pointer (PSP).
ebrus 0:0a673c671a56 421
ebrus 0:0a673c671a56 422 \return PSP Register value
ebrus 0:0a673c671a56 423 */
ebrus 0:0a673c671a56 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
ebrus 0:0a673c671a56 425 {
ebrus 0:0a673c671a56 426 register uint32_t result;
ebrus 0:0a673c671a56 427
ebrus 0:0a673c671a56 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
ebrus 0:0a673c671a56 429 return(result);
ebrus 0:0a673c671a56 430 }
ebrus 0:0a673c671a56 431
ebrus 0:0a673c671a56 432
ebrus 0:0a673c671a56 433 /** \brief Set Process Stack Pointer
ebrus 0:0a673c671a56 434
ebrus 0:0a673c671a56 435 This function assigns the given value to the Process Stack Pointer (PSP).
ebrus 0:0a673c671a56 436
ebrus 0:0a673c671a56 437 \param [in] topOfProcStack Process Stack Pointer value to set
ebrus 0:0a673c671a56 438 */
ebrus 0:0a673c671a56 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
ebrus 0:0a673c671a56 440 {
ebrus 0:0a673c671a56 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
ebrus 0:0a673c671a56 442 }
ebrus 0:0a673c671a56 443
ebrus 0:0a673c671a56 444
ebrus 0:0a673c671a56 445 /** \brief Get Main Stack Pointer
ebrus 0:0a673c671a56 446
ebrus 0:0a673c671a56 447 This function returns the current value of the Main Stack Pointer (MSP).
ebrus 0:0a673c671a56 448
ebrus 0:0a673c671a56 449 \return MSP Register value
ebrus 0:0a673c671a56 450 */
ebrus 0:0a673c671a56 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
ebrus 0:0a673c671a56 452 {
ebrus 0:0a673c671a56 453 register uint32_t result;
ebrus 0:0a673c671a56 454
ebrus 0:0a673c671a56 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
ebrus 0:0a673c671a56 456 return(result);
ebrus 0:0a673c671a56 457 }
ebrus 0:0a673c671a56 458
ebrus 0:0a673c671a56 459
ebrus 0:0a673c671a56 460 /** \brief Set Main Stack Pointer
ebrus 0:0a673c671a56 461
ebrus 0:0a673c671a56 462 This function assigns the given value to the Main Stack Pointer (MSP).
ebrus 0:0a673c671a56 463
ebrus 0:0a673c671a56 464 \param [in] topOfMainStack Main Stack Pointer value to set
ebrus 0:0a673c671a56 465 */
ebrus 0:0a673c671a56 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
ebrus 0:0a673c671a56 467 {
ebrus 0:0a673c671a56 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
ebrus 0:0a673c671a56 469 }
ebrus 0:0a673c671a56 470
ebrus 0:0a673c671a56 471
ebrus 0:0a673c671a56 472 /** \brief Get Priority Mask
ebrus 0:0a673c671a56 473
ebrus 0:0a673c671a56 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
ebrus 0:0a673c671a56 475
ebrus 0:0a673c671a56 476 \return Priority Mask value
ebrus 0:0a673c671a56 477 */
ebrus 0:0a673c671a56 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
ebrus 0:0a673c671a56 479 {
ebrus 0:0a673c671a56 480 uint32_t result;
ebrus 0:0a673c671a56 481
ebrus 0:0a673c671a56 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
ebrus 0:0a673c671a56 483 return(result);
ebrus 0:0a673c671a56 484 }
ebrus 0:0a673c671a56 485
ebrus 0:0a673c671a56 486
ebrus 0:0a673c671a56 487 /** \brief Set Priority Mask
ebrus 0:0a673c671a56 488
ebrus 0:0a673c671a56 489 This function assigns the given value to the Priority Mask Register.
ebrus 0:0a673c671a56 490
ebrus 0:0a673c671a56 491 \param [in] priMask Priority Mask
ebrus 0:0a673c671a56 492 */
ebrus 0:0a673c671a56 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
ebrus 0:0a673c671a56 494 {
ebrus 0:0a673c671a56 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
ebrus 0:0a673c671a56 496 }
ebrus 0:0a673c671a56 497
ebrus 0:0a673c671a56 498
ebrus 0:0a673c671a56 499 #if (__CORTEX_M >= 0x03)
ebrus 0:0a673c671a56 500
ebrus 0:0a673c671a56 501 /** \brief Enable FIQ
ebrus 0:0a673c671a56 502
ebrus 0:0a673c671a56 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
ebrus 0:0a673c671a56 504 Can only be executed in Privileged modes.
ebrus 0:0a673c671a56 505 */
ebrus 0:0a673c671a56 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
ebrus 0:0a673c671a56 507 {
ebrus 0:0a673c671a56 508 __ASM volatile ("cpsie f" : : : "memory");
ebrus 0:0a673c671a56 509 }
ebrus 0:0a673c671a56 510
ebrus 0:0a673c671a56 511
ebrus 0:0a673c671a56 512 /** \brief Disable FIQ
ebrus 0:0a673c671a56 513
ebrus 0:0a673c671a56 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
ebrus 0:0a673c671a56 515 Can only be executed in Privileged modes.
ebrus 0:0a673c671a56 516 */
ebrus 0:0a673c671a56 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
ebrus 0:0a673c671a56 518 {
ebrus 0:0a673c671a56 519 __ASM volatile ("cpsid f" : : : "memory");
ebrus 0:0a673c671a56 520 }
ebrus 0:0a673c671a56 521
ebrus 0:0a673c671a56 522
ebrus 0:0a673c671a56 523 /** \brief Get Base Priority
ebrus 0:0a673c671a56 524
ebrus 0:0a673c671a56 525 This function returns the current value of the Base Priority register.
ebrus 0:0a673c671a56 526
ebrus 0:0a673c671a56 527 \return Base Priority register value
ebrus 0:0a673c671a56 528 */
ebrus 0:0a673c671a56 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
ebrus 0:0a673c671a56 530 {
ebrus 0:0a673c671a56 531 uint32_t result;
ebrus 0:0a673c671a56 532
ebrus 0:0a673c671a56 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
ebrus 0:0a673c671a56 534 return(result);
ebrus 0:0a673c671a56 535 }
ebrus 0:0a673c671a56 536
ebrus 0:0a673c671a56 537
ebrus 0:0a673c671a56 538 /** \brief Set Base Priority
ebrus 0:0a673c671a56 539
ebrus 0:0a673c671a56 540 This function assigns the given value to the Base Priority register.
ebrus 0:0a673c671a56 541
ebrus 0:0a673c671a56 542 \param [in] basePri Base Priority value to set
ebrus 0:0a673c671a56 543 */
ebrus 0:0a673c671a56 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
ebrus 0:0a673c671a56 545 {
ebrus 0:0a673c671a56 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
ebrus 0:0a673c671a56 547 }
ebrus 0:0a673c671a56 548
ebrus 0:0a673c671a56 549
ebrus 0:0a673c671a56 550 /** \brief Get Fault Mask
ebrus 0:0a673c671a56 551
ebrus 0:0a673c671a56 552 This function returns the current value of the Fault Mask register.
ebrus 0:0a673c671a56 553
ebrus 0:0a673c671a56 554 \return Fault Mask register value
ebrus 0:0a673c671a56 555 */
ebrus 0:0a673c671a56 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
ebrus 0:0a673c671a56 557 {
ebrus 0:0a673c671a56 558 uint32_t result;
ebrus 0:0a673c671a56 559
ebrus 0:0a673c671a56 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
ebrus 0:0a673c671a56 561 return(result);
ebrus 0:0a673c671a56 562 }
ebrus 0:0a673c671a56 563
ebrus 0:0a673c671a56 564
ebrus 0:0a673c671a56 565 /** \brief Set Fault Mask
ebrus 0:0a673c671a56 566
ebrus 0:0a673c671a56 567 This function assigns the given value to the Fault Mask register.
ebrus 0:0a673c671a56 568
ebrus 0:0a673c671a56 569 \param [in] faultMask Fault Mask value to set
ebrus 0:0a673c671a56 570 */
ebrus 0:0a673c671a56 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
ebrus 0:0a673c671a56 572 {
ebrus 0:0a673c671a56 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
ebrus 0:0a673c671a56 574 }
ebrus 0:0a673c671a56 575
ebrus 0:0a673c671a56 576 #endif /* (__CORTEX_M >= 0x03) */
ebrus 0:0a673c671a56 577
ebrus 0:0a673c671a56 578
ebrus 0:0a673c671a56 579 #if (__CORTEX_M == 0x04)
ebrus 0:0a673c671a56 580
ebrus 0:0a673c671a56 581 /** \brief Get FPSCR
ebrus 0:0a673c671a56 582
ebrus 0:0a673c671a56 583 This function returns the current value of the Floating Point Status/Control register.
ebrus 0:0a673c671a56 584
ebrus 0:0a673c671a56 585 \return Floating Point Status/Control register value
ebrus 0:0a673c671a56 586 */
ebrus 0:0a673c671a56 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
ebrus 0:0a673c671a56 588 {
ebrus 0:0a673c671a56 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
ebrus 0:0a673c671a56 590 uint32_t result;
ebrus 0:0a673c671a56 591
ebrus 0:0a673c671a56 592 /* Empty asm statement works as a scheduling barrier */
ebrus 0:0a673c671a56 593 __ASM volatile ("");
ebrus 0:0a673c671a56 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
ebrus 0:0a673c671a56 595 __ASM volatile ("");
ebrus 0:0a673c671a56 596 return(result);
ebrus 0:0a673c671a56 597 #else
ebrus 0:0a673c671a56 598 return(0);
ebrus 0:0a673c671a56 599 #endif
ebrus 0:0a673c671a56 600 }
ebrus 0:0a673c671a56 601
ebrus 0:0a673c671a56 602
ebrus 0:0a673c671a56 603 /** \brief Set FPSCR
ebrus 0:0a673c671a56 604
ebrus 0:0a673c671a56 605 This function assigns the given value to the Floating Point Status/Control register.
ebrus 0:0a673c671a56 606
ebrus 0:0a673c671a56 607 \param [in] fpscr Floating Point Status/Control value to set
ebrus 0:0a673c671a56 608 */
ebrus 0:0a673c671a56 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
ebrus 0:0a673c671a56 610 {
ebrus 0:0a673c671a56 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
ebrus 0:0a673c671a56 612 /* Empty asm statement works as a scheduling barrier */
ebrus 0:0a673c671a56 613 __ASM volatile ("");
ebrus 0:0a673c671a56 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
ebrus 0:0a673c671a56 615 __ASM volatile ("");
ebrus 0:0a673c671a56 616 #endif
ebrus 0:0a673c671a56 617 }
ebrus 0:0a673c671a56 618
ebrus 0:0a673c671a56 619 #endif /* (__CORTEX_M == 0x04) */
ebrus 0:0a673c671a56 620
ebrus 0:0a673c671a56 621
ebrus 0:0a673c671a56 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
ebrus 0:0a673c671a56 623 /* TASKING carm specific functions */
ebrus 0:0a673c671a56 624
ebrus 0:0a673c671a56 625 /*
ebrus 0:0a673c671a56 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
ebrus 0:0a673c671a56 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
ebrus 0:0a673c671a56 628 * Including the CMSIS ones.
ebrus 0:0a673c671a56 629 */
ebrus 0:0a673c671a56 630
ebrus 0:0a673c671a56 631 #endif
ebrus 0:0a673c671a56 632
ebrus 0:0a673c671a56 633 /*@} end of CMSIS_Core_RegAccFunctions */
ebrus 0:0a673c671a56 634
ebrus 0:0a673c671a56 635
ebrus 0:0a673c671a56 636 #endif /* __CORE_CMFUNC_H */