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targets/cmsis/core_cm3.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:: ebrus
Date:: Wed Jul 27 18:35:32 2016 +0000
Revision:: 0:0a673c671a56

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User	Revision	Line number	New contents of line
ebrus	0:0a673c671a56	1	/************************************************************************//
ebrus	0:0a673c671a56	2	* @file core_cm3.h
ebrus	0:0a673c671a56	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
ebrus	0:0a673c671a56	4	* @version V3.20
ebrus	0:0a673c671a56	5	* @date 25. February 2013
ebrus	0:0a673c671a56	6	*
ebrus	0:0a673c671a56	7	* @note
ebrus	0:0a673c671a56	8	*
ebrus	0:0a673c671a56	9	******************************************************************************/
ebrus	0:0a673c671a56	10	/* Copyright (c) 2009 - 2013 ARM LIMITED
ebrus	0:0a673c671a56	11
ebrus	0:0a673c671a56	12	All rights reserved.
ebrus	0:0a673c671a56	13	Redistribution and use in source and binary forms, with or without
ebrus	0:0a673c671a56	14	modification, are permitted provided that the following conditions are met:
ebrus	0:0a673c671a56	15	- Redistributions of source code must retain the above copyright
ebrus	0:0a673c671a56	16	notice, this list of conditions and the following disclaimer.
ebrus	0:0a673c671a56	17	- Redistributions in binary form must reproduce the above copyright
ebrus	0:0a673c671a56	18	notice, this list of conditions and the following disclaimer in the
ebrus	0:0a673c671a56	19	documentation and/or other materials provided with the distribution.
ebrus	0:0a673c671a56	20	- Neither the name of ARM nor the names of its contributors may be used
ebrus	0:0a673c671a56	21	to endorse or promote products derived from this software without
ebrus	0:0a673c671a56	22	specific prior written permission.
ebrus	0:0a673c671a56	23	*
ebrus	0:0a673c671a56	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus	0:0a673c671a56	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus	0:0a673c671a56	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ebrus	0:0a673c671a56	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
ebrus	0:0a673c671a56	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
ebrus	0:0a673c671a56	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
ebrus	0:0a673c671a56	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
ebrus	0:0a673c671a56	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
ebrus	0:0a673c671a56	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ebrus	0:0a673c671a56	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
ebrus	0:0a673c671a56	34	POSSIBILITY OF SUCH DAMAGE.
ebrus	0:0a673c671a56	35	---------------------------------------------------------------------------*/
ebrus	0:0a673c671a56	36
ebrus	0:0a673c671a56	37
ebrus	0:0a673c671a56	38	#if defined ( __ICCARM__ )
ebrus	0:0a673c671a56	39	#pragma system_include /* treat file as system include file for MISRA check */
ebrus	0:0a673c671a56	40	#endif
ebrus	0:0a673c671a56	41
ebrus	0:0a673c671a56	42	#ifdef __cplusplus
ebrus	0:0a673c671a56	43	extern "C" {
ebrus	0:0a673c671a56	44	#endif
ebrus	0:0a673c671a56	45
ebrus	0:0a673c671a56	46	#ifndef __CORE_CM3_H_GENERIC
ebrus	0:0a673c671a56	47	#define __CORE_CM3_H_GENERIC
ebrus	0:0a673c671a56	48
ebrus	0:0a673c671a56	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
ebrus	0:0a673c671a56	50	CMSIS violates the following MISRA-C:2004 rules:
ebrus	0:0a673c671a56	51
ebrus	0:0a673c671a56	52	\li Required Rule 8.5, object/function definition in header file.<br>
ebrus	0:0a673c671a56	53	Function definitions in header files are used to allow 'inlining'.
ebrus	0:0a673c671a56	54
ebrus	0:0a673c671a56	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
ebrus	0:0a673c671a56	56	Unions are used for effective representation of core registers.
ebrus	0:0a673c671a56	57
ebrus	0:0a673c671a56	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
ebrus	0:0a673c671a56	59	Function-like macros are used to allow more efficient code.
ebrus	0:0a673c671a56	60	*/
ebrus	0:0a673c671a56	61
ebrus	0:0a673c671a56	62
ebrus	0:0a673c671a56	63	/*******************************************************************************
ebrus	0:0a673c671a56	64	* CMSIS definitions
ebrus	0:0a673c671a56	65	******************************************************************************/
ebrus	0:0a673c671a56	66	/** \ingroup Cortex_M3
ebrus	0:0a673c671a56	67	@{
ebrus	0:0a673c671a56	68	*/
ebrus	0:0a673c671a56	69
ebrus	0:0a673c671a56	70	/* CMSIS CM3 definitions */
ebrus	0:0a673c671a56	71	#define __CM3_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
ebrus	0:0a673c671a56	72	#define __CM3_CMSIS_VERSION_SUB (0x20) /!< [15:0] CMSIS HAL sub version /
ebrus	0:0a673c671a56	73	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
ebrus	0:0a673c671a56	74	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
ebrus	0:0a673c671a56	75
ebrus	0:0a673c671a56	76	#define __CORTEX_M (0x03) /!< Cortex-M Core /
ebrus	0:0a673c671a56	77
ebrus	0:0a673c671a56	78
ebrus	0:0a673c671a56	79	#if defined ( __CC_ARM )
ebrus	0:0a673c671a56	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
ebrus	0:0a673c671a56	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
ebrus	0:0a673c671a56	82	#define __STATIC_INLINE static __inline
ebrus	0:0a673c671a56	83
ebrus	0:0a673c671a56	84	#elif defined ( __ICCARM__ )
ebrus	0:0a673c671a56	85	#define __ASM __asm /!< asm keyword for IAR Compiler /
ebrus	0:0a673c671a56	86	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
ebrus	0:0a673c671a56	87	#define __STATIC_INLINE static inline
ebrus	0:0a673c671a56	88
ebrus	0:0a673c671a56	89	#elif defined ( __TMS470__ )
ebrus	0:0a673c671a56	90	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
ebrus	0:0a673c671a56	91	#define __STATIC_INLINE static inline
ebrus	0:0a673c671a56	92
ebrus	0:0a673c671a56	93	#elif defined ( __GNUC__ )
ebrus	0:0a673c671a56	94	#define __ASM __asm /!< asm keyword for GNU Compiler /
ebrus	0:0a673c671a56	95	#define __INLINE inline /!< inline keyword for GNU Compiler /
ebrus	0:0a673c671a56	96	#define __STATIC_INLINE static inline
ebrus	0:0a673c671a56	97
ebrus	0:0a673c671a56	98	#elif defined ( __TASKING__ )
ebrus	0:0a673c671a56	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
ebrus	0:0a673c671a56	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
ebrus	0:0a673c671a56	101	#define __STATIC_INLINE static inline
ebrus	0:0a673c671a56	102
ebrus	0:0a673c671a56	103	#endif
ebrus	0:0a673c671a56	104
ebrus	0:0a673c671a56	105	/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
ebrus	0:0a673c671a56	106	*/
ebrus	0:0a673c671a56	107	#define __FPU_USED 0
ebrus	0:0a673c671a56	108
ebrus	0:0a673c671a56	109	#if defined ( __CC_ARM )
ebrus	0:0a673c671a56	110	#if defined __TARGET_FPU_VFP
ebrus	0:0a673c671a56	111	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ebrus	0:0a673c671a56	112	#endif
ebrus	0:0a673c671a56	113
ebrus	0:0a673c671a56	114	#elif defined ( __ICCARM__ )
ebrus	0:0a673c671a56	115	#if defined __ARMVFP__
ebrus	0:0a673c671a56	116	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ebrus	0:0a673c671a56	117	#endif
ebrus	0:0a673c671a56	118
ebrus	0:0a673c671a56	119	#elif defined ( __TMS470__ )
ebrus	0:0a673c671a56	120	#if defined __TI__VFP_SUPPORT____
ebrus	0:0a673c671a56	121	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ebrus	0:0a673c671a56	122	#endif
ebrus	0:0a673c671a56	123
ebrus	0:0a673c671a56	124	#elif defined ( __GNUC__ )
ebrus	0:0a673c671a56	125	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
ebrus	0:0a673c671a56	126	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ebrus	0:0a673c671a56	127	#endif
ebrus	0:0a673c671a56	128
ebrus	0:0a673c671a56	129	#elif defined ( __TASKING__ )
ebrus	0:0a673c671a56	130	#if defined __FPU_VFP__
ebrus	0:0a673c671a56	131	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ebrus	0:0a673c671a56	132	#endif
ebrus	0:0a673c671a56	133	#endif
ebrus	0:0a673c671a56	134
ebrus	0:0a673c671a56	135	#include <stdint.h> /* standard types definitions */
ebrus	0:0a673c671a56	136	#include <core_cmInstr.h> /* Core Instruction Access */
ebrus	0:0a673c671a56	137	#include <core_cmFunc.h> /* Core Function Access */
ebrus	0:0a673c671a56	138
ebrus	0:0a673c671a56	139	#endif /* __CORE_CM3_H_GENERIC */
ebrus	0:0a673c671a56	140
ebrus	0:0a673c671a56	141	#ifndef __CMSIS_GENERIC
ebrus	0:0a673c671a56	142
ebrus	0:0a673c671a56	143	#ifndef __CORE_CM3_H_DEPENDANT
ebrus	0:0a673c671a56	144	#define __CORE_CM3_H_DEPENDANT
ebrus	0:0a673c671a56	145
ebrus	0:0a673c671a56	146	/* check device defines and use defaults */
ebrus	0:0a673c671a56	147	#if defined __CHECK_DEVICE_DEFINES
ebrus	0:0a673c671a56	148	#ifndef __CM3_REV
ebrus	0:0a673c671a56	149	#define __CM3_REV 0x0200
ebrus	0:0a673c671a56	150	#warning "__CM3_REV not defined in device header file; using default!"
ebrus	0:0a673c671a56	151	#endif
ebrus	0:0a673c671a56	152
ebrus	0:0a673c671a56	153	#ifndef __MPU_PRESENT
ebrus	0:0a673c671a56	154	#define __MPU_PRESENT 0
ebrus	0:0a673c671a56	155	#warning "__MPU_PRESENT not defined in device header file; using default!"
ebrus	0:0a673c671a56	156	#endif
ebrus	0:0a673c671a56	157
ebrus	0:0a673c671a56	158	#ifndef __NVIC_PRIO_BITS
ebrus	0:0a673c671a56	159	#define __NVIC_PRIO_BITS 4
ebrus	0:0a673c671a56	160	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
ebrus	0:0a673c671a56	161	#endif
ebrus	0:0a673c671a56	162
ebrus	0:0a673c671a56	163	#ifndef __Vendor_SysTickConfig
ebrus	0:0a673c671a56	164	#define __Vendor_SysTickConfig 0
ebrus	0:0a673c671a56	165	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
ebrus	0:0a673c671a56	166	#endif
ebrus	0:0a673c671a56	167	#endif
ebrus	0:0a673c671a56	168
ebrus	0:0a673c671a56	169	/* IO definitions (access restrictions to peripheral registers) */
ebrus	0:0a673c671a56	170	/**
ebrus	0:0a673c671a56	171	\defgroup CMSIS_glob_defs CMSIS Global Defines
ebrus	0:0a673c671a56	172
ebrus	0:0a673c671a56	173	<strong>IO Type Qualifiers</strong> are used
ebrus	0:0a673c671a56	174	\li to specify the access to peripheral variables.
ebrus	0:0a673c671a56	175	\li for automatic generation of peripheral register debug information.
ebrus	0:0a673c671a56	176	*/
ebrus	0:0a673c671a56	177	#ifdef __cplusplus
ebrus	0:0a673c671a56	178	#define __I volatile /!< Defines 'read only' permissions /
ebrus	0:0a673c671a56	179	#else
ebrus	0:0a673c671a56	180	#define __I volatile const /!< Defines 'read only' permissions /
ebrus	0:0a673c671a56	181	#endif
ebrus	0:0a673c671a56	182	#define __O volatile /!< Defines 'write only' permissions /
ebrus	0:0a673c671a56	183	#define __IO volatile /!< Defines 'read / write' permissions /
ebrus	0:0a673c671a56	184
ebrus	0:0a673c671a56	185	/@} end of group Cortex_M3 /
ebrus	0:0a673c671a56	186
ebrus	0:0a673c671a56	187
ebrus	0:0a673c671a56	188
ebrus	0:0a673c671a56	189	/*******************************************************************************
ebrus	0:0a673c671a56	190	* Register Abstraction
ebrus	0:0a673c671a56	191	Core Register contain:
ebrus	0:0a673c671a56	192	- Core Register
ebrus	0:0a673c671a56	193	- Core NVIC Register
ebrus	0:0a673c671a56	194	- Core SCB Register
ebrus	0:0a673c671a56	195	- Core SysTick Register
ebrus	0:0a673c671a56	196	- Core Debug Register
ebrus	0:0a673c671a56	197	- Core MPU Register
ebrus	0:0a673c671a56	198	******************************************************************************/
ebrus	0:0a673c671a56	199	/** \defgroup CMSIS_core_register Defines and Type Definitions
ebrus	0:0a673c671a56	200	\brief Type definitions and defines for Cortex-M processor based devices.
ebrus	0:0a673c671a56	201	*/
ebrus	0:0a673c671a56	202
ebrus	0:0a673c671a56	203	/** \ingroup CMSIS_core_register
ebrus	0:0a673c671a56	204	\defgroup CMSIS_CORE Status and Control Registers
ebrus	0:0a673c671a56	205	\brief Core Register type definitions.
ebrus	0:0a673c671a56	206	@{
ebrus	0:0a673c671a56	207	*/
ebrus	0:0a673c671a56	208
ebrus	0:0a673c671a56	209	/** \brief Union type to access the Application Program Status Register (APSR).
ebrus	0:0a673c671a56	210	*/
ebrus	0:0a673c671a56	211	typedef union
ebrus	0:0a673c671a56	212	{
ebrus	0:0a673c671a56	213	struct
ebrus	0:0a673c671a56	214	{
ebrus	0:0a673c671a56	215	#if (__CORTEX_M != 0x04)
ebrus	0:0a673c671a56	216	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
ebrus	0:0a673c671a56	217	#else
ebrus	0:0a673c671a56	218	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
ebrus	0:0a673c671a56	219	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
ebrus	0:0a673c671a56	220	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
ebrus	0:0a673c671a56	221	#endif
ebrus	0:0a673c671a56	222	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
ebrus	0:0a673c671a56	223	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
ebrus	0:0a673c671a56	224	uint32_t C:1; /!< bit: 29 Carry condition code flag /
ebrus	0:0a673c671a56	225	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
ebrus	0:0a673c671a56	226	uint32_t N:1; /!< bit: 31 Negative condition code flag /
ebrus	0:0a673c671a56	227	} b; /!< Structure used for bit access /
ebrus	0:0a673c671a56	228	uint32_t w; /!< Type used for word access /
ebrus	0:0a673c671a56	229	} APSR_Type;
ebrus	0:0a673c671a56	230
ebrus	0:0a673c671a56	231
ebrus	0:0a673c671a56	232	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
ebrus	0:0a673c671a56	233	*/
ebrus	0:0a673c671a56	234	typedef union
ebrus	0:0a673c671a56	235	{
ebrus	0:0a673c671a56	236	struct
ebrus	0:0a673c671a56	237	{
ebrus	0:0a673c671a56	238	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
ebrus	0:0a673c671a56	239	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
ebrus	0:0a673c671a56	240	} b; /!< Structure used for bit access /
ebrus	0:0a673c671a56	241	uint32_t w; /!< Type used for word access /
ebrus	0:0a673c671a56	242	} IPSR_Type;
ebrus	0:0a673c671a56	243
ebrus	0:0a673c671a56	244
ebrus	0:0a673c671a56	245	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
ebrus	0:0a673c671a56	246	*/
ebrus	0:0a673c671a56	247	typedef union
ebrus	0:0a673c671a56	248	{
ebrus	0:0a673c671a56	249	struct
ebrus	0:0a673c671a56	250	{
ebrus	0:0a673c671a56	251	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
ebrus	0:0a673c671a56	252	#if (__CORTEX_M != 0x04)
ebrus	0:0a673c671a56	253	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
ebrus	0:0a673c671a56	254	#else
ebrus	0:0a673c671a56	255	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
ebrus	0:0a673c671a56	256	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
ebrus	0:0a673c671a56	257	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
ebrus	0:0a673c671a56	258	#endif
ebrus	0:0a673c671a56	259	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
ebrus	0:0a673c671a56	260	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
ebrus	0:0a673c671a56	261	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
ebrus	0:0a673c671a56	262	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
ebrus	0:0a673c671a56	263	uint32_t C:1; /!< bit: 29 Carry condition code flag /
ebrus	0:0a673c671a56	264	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
ebrus	0:0a673c671a56	265	uint32_t N:1; /!< bit: 31 Negative condition code flag /
ebrus	0:0a673c671a56	266	} b; /!< Structure used for bit access /
ebrus	0:0a673c671a56	267	uint32_t w; /!< Type used for word access /
ebrus	0:0a673c671a56	268	} xPSR_Type;
ebrus	0:0a673c671a56	269
ebrus	0:0a673c671a56	270
ebrus	0:0a673c671a56	271	/** \brief Union type to access the Control Registers (CONTROL).
ebrus	0:0a673c671a56	272	*/
ebrus	0:0a673c671a56	273	typedef union
ebrus	0:0a673c671a56	274	{
ebrus	0:0a673c671a56	275	struct
ebrus	0:0a673c671a56	276	{
ebrus	0:0a673c671a56	277	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
ebrus	0:0a673c671a56	278	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
ebrus	0:0a673c671a56	279	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
ebrus	0:0a673c671a56	280	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
ebrus	0:0a673c671a56	281	} b; /!< Structure used for bit access /
ebrus	0:0a673c671a56	282	uint32_t w; /!< Type used for word access /
ebrus	0:0a673c671a56	283	} CONTROL_Type;
ebrus	0:0a673c671a56	284
ebrus	0:0a673c671a56	285	/@} end of group CMSIS_CORE /
ebrus	0:0a673c671a56	286
ebrus	0:0a673c671a56	287
ebrus	0:0a673c671a56	288	/** \ingroup CMSIS_core_register
ebrus	0:0a673c671a56	289	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
ebrus	0:0a673c671a56	290	\brief Type definitions for the NVIC Registers
ebrus	0:0a673c671a56	291	@{
ebrus	0:0a673c671a56	292	*/
ebrus	0:0a673c671a56	293
ebrus	0:0a673c671a56	294	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
ebrus	0:0a673c671a56	295	*/
ebrus	0:0a673c671a56	296	typedef struct
ebrus	0:0a673c671a56	297	{
ebrus	0:0a673c671a56	298	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
ebrus	0:0a673c671a56	299	uint32_t RESERVED0[24];
ebrus	0:0a673c671a56	300	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
ebrus	0:0a673c671a56	301	uint32_t RSERVED1[24];
ebrus	0:0a673c671a56	302	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
ebrus	0:0a673c671a56	303	uint32_t RESERVED2[24];
ebrus	0:0a673c671a56	304	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
ebrus	0:0a673c671a56	305	uint32_t RESERVED3[24];
ebrus	0:0a673c671a56	306	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
ebrus	0:0a673c671a56	307	uint32_t RESERVED4[56];
ebrus	0:0a673c671a56	308	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
ebrus	0:0a673c671a56	309	uint32_t RESERVED5[644];
ebrus	0:0a673c671a56	310	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
ebrus	0:0a673c671a56	311	} NVIC_Type;
ebrus	0:0a673c671a56	312
ebrus	0:0a673c671a56	313	/* Software Triggered Interrupt Register Definitions */
ebrus	0:0a673c671a56	314	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
ebrus	0:0a673c671a56	315	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
ebrus	0:0a673c671a56	316
ebrus	0:0a673c671a56	317	/@} end of group CMSIS_NVIC /
ebrus	0:0a673c671a56	318
ebrus	0:0a673c671a56	319
ebrus	0:0a673c671a56	320	/** \ingroup CMSIS_core_register
ebrus	0:0a673c671a56	321	\defgroup CMSIS_SCB System Control Block (SCB)
ebrus	0:0a673c671a56	322	\brief Type definitions for the System Control Block Registers
ebrus	0:0a673c671a56	323	@{
ebrus	0:0a673c671a56	324	*/
ebrus	0:0a673c671a56	325
ebrus	0:0a673c671a56	326	/** \brief Structure type to access the System Control Block (SCB).
ebrus	0:0a673c671a56	327	*/
ebrus	0:0a673c671a56	328	typedef struct
ebrus	0:0a673c671a56	329	{
ebrus	0:0a673c671a56	330	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
ebrus	0:0a673c671a56	331	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
ebrus	0:0a673c671a56	332	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
ebrus	0:0a673c671a56	333	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
ebrus	0:0a673c671a56	334	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
ebrus	0:0a673c671a56	335	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
ebrus	0:0a673c671a56	336	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
ebrus	0:0a673c671a56	337	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
ebrus	0:0a673c671a56	338	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
ebrus	0:0a673c671a56	339	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
ebrus	0:0a673c671a56	340	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
ebrus	0:0a673c671a56	341	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
ebrus	0:0a673c671a56	342	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
ebrus	0:0a673c671a56	343	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
ebrus	0:0a673c671a56	344	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
ebrus	0:0a673c671a56	345	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
ebrus	0:0a673c671a56	346	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
ebrus	0:0a673c671a56	347	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
ebrus	0:0a673c671a56	348	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
ebrus	0:0a673c671a56	349	uint32_t RESERVED0[5];
ebrus	0:0a673c671a56	350	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
ebrus	0:0a673c671a56	351	} SCB_Type;
ebrus	0:0a673c671a56	352
ebrus	0:0a673c671a56	353	/* SCB CPUID Register Definitions */
ebrus	0:0a673c671a56	354	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
ebrus	0:0a673c671a56	355	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
ebrus	0:0a673c671a56	356
ebrus	0:0a673c671a56	357	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
ebrus	0:0a673c671a56	358	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
ebrus	0:0a673c671a56	359
ebrus	0:0a673c671a56	360	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
ebrus	0:0a673c671a56	361	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
ebrus	0:0a673c671a56	362
ebrus	0:0a673c671a56	363	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
ebrus	0:0a673c671a56	364	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
ebrus	0:0a673c671a56	365
ebrus	0:0a673c671a56	366	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
ebrus	0:0a673c671a56	367	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
ebrus	0:0a673c671a56	368
ebrus	0:0a673c671a56	369	/* SCB Interrupt Control State Register Definitions */
ebrus	0:0a673c671a56	370	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
ebrus	0:0a673c671a56	371	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
ebrus	0:0a673c671a56	372
ebrus	0:0a673c671a56	373	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
ebrus	0:0a673c671a56	374	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
ebrus	0:0a673c671a56	375
ebrus	0:0a673c671a56	376	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
ebrus	0:0a673c671a56	377	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
ebrus	0:0a673c671a56	378
ebrus	0:0a673c671a56	379	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
ebrus	0:0a673c671a56	380	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
ebrus	0:0a673c671a56	381
ebrus	0:0a673c671a56	382	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
ebrus	0:0a673c671a56	383	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
ebrus	0:0a673c671a56	384
ebrus	0:0a673c671a56	385	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
ebrus	0:0a673c671a56	386	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
ebrus	0:0a673c671a56	387
ebrus	0:0a673c671a56	388	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
ebrus	0:0a673c671a56	389	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
ebrus	0:0a673c671a56	390
ebrus	0:0a673c671a56	391	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
ebrus	0:0a673c671a56	392	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
ebrus	0:0a673c671a56	393
ebrus	0:0a673c671a56	394	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
ebrus	0:0a673c671a56	395	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
ebrus	0:0a673c671a56	396
ebrus	0:0a673c671a56	397	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
ebrus	0:0a673c671a56	398	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
ebrus	0:0a673c671a56	399
ebrus	0:0a673c671a56	400	/* SCB Vector Table Offset Register Definitions */
ebrus	0:0a673c671a56	401	#if (__CM3_REV < 0x0201) /* core r2p1 */
ebrus	0:0a673c671a56	402	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
ebrus	0:0a673c671a56	403	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
ebrus	0:0a673c671a56	404
ebrus	0:0a673c671a56	405	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
ebrus	0:0a673c671a56	406	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
ebrus	0:0a673c671a56	407	#else
ebrus	0:0a673c671a56	408	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
ebrus	0:0a673c671a56	409	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
ebrus	0:0a673c671a56	410	#endif
ebrus	0:0a673c671a56	411
ebrus	0:0a673c671a56	412	/* SCB Application Interrupt and Reset Control Register Definitions */
ebrus	0:0a673c671a56	413	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
ebrus	0:0a673c671a56	414	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
ebrus	0:0a673c671a56	415
ebrus	0:0a673c671a56	416	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
ebrus	0:0a673c671a56	417	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
ebrus	0:0a673c671a56	418
ebrus	0:0a673c671a56	419	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
ebrus	0:0a673c671a56	420	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
ebrus	0:0a673c671a56	421
ebrus	0:0a673c671a56	422	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
ebrus	0:0a673c671a56	423	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
ebrus	0:0a673c671a56	424
ebrus	0:0a673c671a56	425	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
ebrus	0:0a673c671a56	426	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
ebrus	0:0a673c671a56	427
ebrus	0:0a673c671a56	428	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
ebrus	0:0a673c671a56	429	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
ebrus	0:0a673c671a56	430
ebrus	0:0a673c671a56	431	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
ebrus	0:0a673c671a56	432	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
ebrus	0:0a673c671a56	433
ebrus	0:0a673c671a56	434	/* SCB System Control Register Definitions */
ebrus	0:0a673c671a56	435	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
ebrus	0:0a673c671a56	436	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
ebrus	0:0a673c671a56	437
ebrus	0:0a673c671a56	438	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
ebrus	0:0a673c671a56	439	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
ebrus	0:0a673c671a56	440
ebrus	0:0a673c671a56	441	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
ebrus	0:0a673c671a56	442	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
ebrus	0:0a673c671a56	443
ebrus	0:0a673c671a56	444	/* SCB Configuration Control Register Definitions */
ebrus	0:0a673c671a56	445	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
ebrus	0:0a673c671a56	446	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
ebrus	0:0a673c671a56	447
ebrus	0:0a673c671a56	448	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
ebrus	0:0a673c671a56	449	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
ebrus	0:0a673c671a56	450
ebrus	0:0a673c671a56	451	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
ebrus	0:0a673c671a56	452	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
ebrus	0:0a673c671a56	453
ebrus	0:0a673c671a56	454	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
ebrus	0:0a673c671a56	455	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
ebrus	0:0a673c671a56	456
ebrus	0:0a673c671a56	457	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
ebrus	0:0a673c671a56	458	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
ebrus	0:0a673c671a56	459
ebrus	0:0a673c671a56	460	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
ebrus	0:0a673c671a56	461	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
ebrus	0:0a673c671a56	462
ebrus	0:0a673c671a56	463	/* SCB System Handler Control and State Register Definitions */
ebrus	0:0a673c671a56	464	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
ebrus	0:0a673c671a56	465	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
ebrus	0:0a673c671a56	466
ebrus	0:0a673c671a56	467	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
ebrus	0:0a673c671a56	468	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
ebrus	0:0a673c671a56	469
ebrus	0:0a673c671a56	470	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
ebrus	0:0a673c671a56	471	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
ebrus	0:0a673c671a56	472
ebrus	0:0a673c671a56	473	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
ebrus	0:0a673c671a56	474	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
ebrus	0:0a673c671a56	475
ebrus	0:0a673c671a56	476	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
ebrus	0:0a673c671a56	477	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
ebrus	0:0a673c671a56	478
ebrus	0:0a673c671a56	479	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
ebrus	0:0a673c671a56	480	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
ebrus	0:0a673c671a56	481
ebrus	0:0a673c671a56	482	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
ebrus	0:0a673c671a56	483	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
ebrus	0:0a673c671a56	484
ebrus	0:0a673c671a56	485	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
ebrus	0:0a673c671a56	486	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
ebrus	0:0a673c671a56	487
ebrus	0:0a673c671a56	488	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
ebrus	0:0a673c671a56	489	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
ebrus	0:0a673c671a56	490
ebrus	0:0a673c671a56	491	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
ebrus	0:0a673c671a56	492	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
ebrus	0:0a673c671a56	493
ebrus	0:0a673c671a56	494	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
ebrus	0:0a673c671a56	495	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
ebrus	0:0a673c671a56	496
ebrus	0:0a673c671a56	497	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
ebrus	0:0a673c671a56	498	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
ebrus	0:0a673c671a56	499
ebrus	0:0a673c671a56	500	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
ebrus	0:0a673c671a56	501	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
ebrus	0:0a673c671a56	502
ebrus	0:0a673c671a56	503	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
ebrus	0:0a673c671a56	504	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
ebrus	0:0a673c671a56	505
ebrus	0:0a673c671a56	506	/* SCB Configurable Fault Status Registers Definitions */
ebrus	0:0a673c671a56	507	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
ebrus	0:0a673c671a56	508	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
ebrus	0:0a673c671a56	509
ebrus	0:0a673c671a56	510	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
ebrus	0:0a673c671a56	511	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
ebrus	0:0a673c671a56	512
ebrus	0:0a673c671a56	513	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
ebrus	0:0a673c671a56	514	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
ebrus	0:0a673c671a56	515
ebrus	0:0a673c671a56	516	/* SCB Hard Fault Status Registers Definitions */
ebrus	0:0a673c671a56	517	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
ebrus	0:0a673c671a56	518	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
ebrus	0:0a673c671a56	519
ebrus	0:0a673c671a56	520	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
ebrus	0:0a673c671a56	521	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
ebrus	0:0a673c671a56	522
ebrus	0:0a673c671a56	523	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
ebrus	0:0a673c671a56	524	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
ebrus	0:0a673c671a56	525
ebrus	0:0a673c671a56	526	/* SCB Debug Fault Status Register Definitions */
ebrus	0:0a673c671a56	527	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
ebrus	0:0a673c671a56	528	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
ebrus	0:0a673c671a56	529
ebrus	0:0a673c671a56	530	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
ebrus	0:0a673c671a56	531	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
ebrus	0:0a673c671a56	532
ebrus	0:0a673c671a56	533	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
ebrus	0:0a673c671a56	534	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
ebrus	0:0a673c671a56	535
ebrus	0:0a673c671a56	536	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
ebrus	0:0a673c671a56	537	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
ebrus	0:0a673c671a56	538
ebrus	0:0a673c671a56	539	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
ebrus	0:0a673c671a56	540	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
ebrus	0:0a673c671a56	541
ebrus	0:0a673c671a56	542	/@} end of group CMSIS_SCB /
ebrus	0:0a673c671a56	543
ebrus	0:0a673c671a56	544
ebrus	0:0a673c671a56	545	/** \ingroup CMSIS_core_register
ebrus	0:0a673c671a56	546	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
ebrus	0:0a673c671a56	547	\brief Type definitions for the System Control and ID Register not in the SCB
ebrus	0:0a673c671a56	548	@{
ebrus	0:0a673c671a56	549	*/
ebrus	0:0a673c671a56	550
ebrus	0:0a673c671a56	551	/** \brief Structure type to access the System Control and ID Register not in the SCB.
ebrus	0:0a673c671a56	552	*/
ebrus	0:0a673c671a56	553	typedef struct
ebrus	0:0a673c671a56	554	{
ebrus	0:0a673c671a56	555	uint32_t RESERVED0[1];
ebrus	0:0a673c671a56	556	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
ebrus	0:0a673c671a56	557	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
ebrus	0:0a673c671a56	558	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
ebrus	0:0a673c671a56	559	#else
ebrus	0:0a673c671a56	560	uint32_t RESERVED1[1];
ebrus	0:0a673c671a56	561	#endif
ebrus	0:0a673c671a56	562	} SCnSCB_Type;
ebrus	0:0a673c671a56	563
ebrus	0:0a673c671a56	564	/* Interrupt Controller Type Register Definitions */
ebrus	0:0a673c671a56	565	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
ebrus	0:0a673c671a56	566	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
ebrus	0:0a673c671a56	567
ebrus	0:0a673c671a56	568	/* Auxiliary Control Register Definitions */
ebrus	0:0a673c671a56	569
ebrus	0:0a673c671a56	570	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
ebrus	0:0a673c671a56	571	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
ebrus	0:0a673c671a56	572
ebrus	0:0a673c671a56	573	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
ebrus	0:0a673c671a56	574	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
ebrus	0:0a673c671a56	575
ebrus	0:0a673c671a56	576	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
ebrus	0:0a673c671a56	577	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
ebrus	0:0a673c671a56	578
ebrus	0:0a673c671a56	579	/@} end of group CMSIS_SCnotSCB /
ebrus	0:0a673c671a56	580
ebrus	0:0a673c671a56	581
ebrus	0:0a673c671a56	582	/** \ingroup CMSIS_core_register
ebrus	0:0a673c671a56	583	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
ebrus	0:0a673c671a56	584	\brief Type definitions for the System Timer Registers.
ebrus	0:0a673c671a56	585	@{
ebrus	0:0a673c671a56	586	*/
ebrus	0:0a673c671a56	587
ebrus	0:0a673c671a56	588	/** \brief Structure type to access the System Timer (SysTick).
ebrus	0:0a673c671a56	589	*/
ebrus	0:0a673c671a56	590	typedef struct
ebrus	0:0a673c671a56	591	{
ebrus	0:0a673c671a56	592	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
ebrus	0:0a673c671a56	593	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
ebrus	0:0a673c671a56	594	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
ebrus	0:0a673c671a56	595	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
ebrus	0:0a673c671a56	596	} SysTick_Type;
ebrus	0:0a673c671a56	597
ebrus	0:0a673c671a56	598	/* SysTick Control / Status Register Definitions */
ebrus	0:0a673c671a56	599	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
ebrus	0:0a673c671a56	600	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
ebrus	0:0a673c671a56	601
ebrus	0:0a673c671a56	602	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
ebrus	0:0a673c671a56	603	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
ebrus	0:0a673c671a56	604
ebrus	0:0a673c671a56	605	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
ebrus	0:0a673c671a56	606	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
ebrus	0:0a673c671a56	607
ebrus	0:0a673c671a56	608	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
ebrus	0:0a673c671a56	609	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
ebrus	0:0a673c671a56	610
ebrus	0:0a673c671a56	611	/* SysTick Reload Register Definitions */
ebrus	0:0a673c671a56	612	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
ebrus	0:0a673c671a56	613	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
ebrus	0:0a673c671a56	614
ebrus	0:0a673c671a56	615	/* SysTick Current Register Definitions */
ebrus	0:0a673c671a56	616	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
ebrus	0:0a673c671a56	617	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
ebrus	0:0a673c671a56	618
ebrus	0:0a673c671a56	619	/* SysTick Calibration Register Definitions */
ebrus	0:0a673c671a56	620	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
ebrus	0:0a673c671a56	621	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
ebrus	0:0a673c671a56	622
ebrus	0:0a673c671a56	623	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
ebrus	0:0a673c671a56	624	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
ebrus	0:0a673c671a56	625
ebrus	0:0a673c671a56	626	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
ebrus	0:0a673c671a56	627	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
ebrus	0:0a673c671a56	628
ebrus	0:0a673c671a56	629	/@} end of group CMSIS_SysTick /
ebrus	0:0a673c671a56	630
ebrus	0:0a673c671a56	631
ebrus	0:0a673c671a56	632	/** \ingroup CMSIS_core_register
ebrus	0:0a673c671a56	633	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
ebrus	0:0a673c671a56	634	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
ebrus	0:0a673c671a56	635	@{
ebrus	0:0a673c671a56	636	*/
ebrus	0:0a673c671a56	637
ebrus	0:0a673c671a56	638	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
ebrus	0:0a673c671a56	639	*/
ebrus	0:0a673c671a56	640	typedef struct
ebrus	0:0a673c671a56	641	{
ebrus	0:0a673c671a56	642	__O union
ebrus	0:0a673c671a56	643	{
ebrus	0:0a673c671a56	644	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
ebrus	0:0a673c671a56	645	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
ebrus	0:0a673c671a56	646	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
ebrus	0:0a673c671a56	647	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
ebrus	0:0a673c671a56	648	uint32_t RESERVED0[864];
ebrus	0:0a673c671a56	649	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
ebrus	0:0a673c671a56	650	uint32_t RESERVED1[15];
ebrus	0:0a673c671a56	651	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
ebrus	0:0a673c671a56	652	uint32_t RESERVED2[15];
ebrus	0:0a673c671a56	653	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
ebrus	0:0a673c671a56	654	uint32_t RESERVED3[29];
ebrus	0:0a673c671a56	655	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
ebrus	0:0a673c671a56	656	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
ebrus	0:0a673c671a56	657	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
ebrus	0:0a673c671a56	658	uint32_t RESERVED4[43];
ebrus	0:0a673c671a56	659	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
ebrus	0:0a673c671a56	660	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
ebrus	0:0a673c671a56	661	uint32_t RESERVED5[6];
ebrus	0:0a673c671a56	662	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
ebrus	0:0a673c671a56	663	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
ebrus	0:0a673c671a56	664	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
ebrus	0:0a673c671a56	665	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
ebrus	0:0a673c671a56	666	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
ebrus	0:0a673c671a56	667	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
ebrus	0:0a673c671a56	668	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
ebrus	0:0a673c671a56	669	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
ebrus	0:0a673c671a56	670	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
ebrus	0:0a673c671a56	671	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
ebrus	0:0a673c671a56	672	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
ebrus	0:0a673c671a56	673	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
ebrus	0:0a673c671a56	674	} ITM_Type;
ebrus	0:0a673c671a56	675
ebrus	0:0a673c671a56	676	/* ITM Trace Privilege Register Definitions */
ebrus	0:0a673c671a56	677	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
ebrus	0:0a673c671a56	678	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
ebrus	0:0a673c671a56	679
ebrus	0:0a673c671a56	680	/* ITM Trace Control Register Definitions */
ebrus	0:0a673c671a56	681	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
ebrus	0:0a673c671a56	682	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
ebrus	0:0a673c671a56	683
ebrus	0:0a673c671a56	684	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
ebrus	0:0a673c671a56	685	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
ebrus	0:0a673c671a56	686
ebrus	0:0a673c671a56	687	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
ebrus	0:0a673c671a56	688	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
ebrus	0:0a673c671a56	689
ebrus	0:0a673c671a56	690	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
ebrus	0:0a673c671a56	691	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
ebrus	0:0a673c671a56	692
ebrus	0:0a673c671a56	693	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
ebrus	0:0a673c671a56	694	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
ebrus	0:0a673c671a56	695
ebrus	0:0a673c671a56	696	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
ebrus	0:0a673c671a56	697	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
ebrus	0:0a673c671a56	698
ebrus	0:0a673c671a56	699	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
ebrus	0:0a673c671a56	700	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
ebrus	0:0a673c671a56	701
ebrus	0:0a673c671a56	702	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
ebrus	0:0a673c671a56	703	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
ebrus	0:0a673c671a56	704
ebrus	0:0a673c671a56	705	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
ebrus	0:0a673c671a56	706	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
ebrus	0:0a673c671a56	707
ebrus	0:0a673c671a56	708	/* ITM Integration Write Register Definitions */
ebrus	0:0a673c671a56	709	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
ebrus	0:0a673c671a56	710	#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
ebrus	0:0a673c671a56	711
ebrus	0:0a673c671a56	712	/* ITM Integration Read Register Definitions */
ebrus	0:0a673c671a56	713	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
ebrus	0:0a673c671a56	714	#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
ebrus	0:0a673c671a56	715
ebrus	0:0a673c671a56	716	/* ITM Integration Mode Control Register Definitions */
ebrus	0:0a673c671a56	717	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
ebrus	0:0a673c671a56	718	#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
ebrus	0:0a673c671a56	719
ebrus	0:0a673c671a56	720	/* ITM Lock Status Register Definitions */
ebrus	0:0a673c671a56	721	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
ebrus	0:0a673c671a56	722	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
ebrus	0:0a673c671a56	723
ebrus	0:0a673c671a56	724	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
ebrus	0:0a673c671a56	725	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
ebrus	0:0a673c671a56	726
ebrus	0:0a673c671a56	727	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
ebrus	0:0a673c671a56	728	#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
ebrus	0:0a673c671a56	729
ebrus	0:0a673c671a56	730	/@}/ /* end of group CMSIS_ITM */
ebrus	0:0a673c671a56	731
ebrus	0:0a673c671a56	732
ebrus	0:0a673c671a56	733	/** \ingroup CMSIS_core_register
ebrus	0:0a673c671a56	734	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
ebrus	0:0a673c671a56	735	\brief Type definitions for the Data Watchpoint and Trace (DWT)
ebrus	0:0a673c671a56	736	@{
ebrus	0:0a673c671a56	737	*/
ebrus	0:0a673c671a56	738
ebrus	0:0a673c671a56	739	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
ebrus	0:0a673c671a56	740	*/
ebrus	0:0a673c671a56	741	typedef struct
ebrus	0:0a673c671a56	742	{
ebrus	0:0a673c671a56	743	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
ebrus	0:0a673c671a56	744	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
ebrus	0:0a673c671a56	745	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
ebrus	0:0a673c671a56	746	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
ebrus	0:0a673c671a56	747	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
ebrus	0:0a673c671a56	748	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
ebrus	0:0a673c671a56	749	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
ebrus	0:0a673c671a56	750	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
ebrus	0:0a673c671a56	751	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
ebrus	0:0a673c671a56	752	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
ebrus	0:0a673c671a56	753	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
ebrus	0:0a673c671a56	754	uint32_t RESERVED0[1];
ebrus	0:0a673c671a56	755	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
ebrus	0:0a673c671a56	756	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
ebrus	0:0a673c671a56	757	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
ebrus	0:0a673c671a56	758	uint32_t RESERVED1[1];
ebrus	0:0a673c671a56	759	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
ebrus	0:0a673c671a56	760	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
ebrus	0:0a673c671a56	761	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
ebrus	0:0a673c671a56	762	uint32_t RESERVED2[1];
ebrus	0:0a673c671a56	763	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
ebrus	0:0a673c671a56	764	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
ebrus	0:0a673c671a56	765	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
ebrus	0:0a673c671a56	766	} DWT_Type;
ebrus	0:0a673c671a56	767
ebrus	0:0a673c671a56	768	/* DWT Control Register Definitions */
ebrus	0:0a673c671a56	769	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
ebrus	0:0a673c671a56	770	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
ebrus	0:0a673c671a56	771
ebrus	0:0a673c671a56	772	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
ebrus	0:0a673c671a56	773	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
ebrus	0:0a673c671a56	774
ebrus	0:0a673c671a56	775	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
ebrus	0:0a673c671a56	776	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
ebrus	0:0a673c671a56	777
ebrus	0:0a673c671a56	778	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
ebrus	0:0a673c671a56	779	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
ebrus	0:0a673c671a56	780
ebrus	0:0a673c671a56	781	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
ebrus	0:0a673c671a56	782	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
ebrus	0:0a673c671a56	783
ebrus	0:0a673c671a56	784	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
ebrus	0:0a673c671a56	785	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
ebrus	0:0a673c671a56	786
ebrus	0:0a673c671a56	787	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
ebrus	0:0a673c671a56	788	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
ebrus	0:0a673c671a56	789
ebrus	0:0a673c671a56	790	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
ebrus	0:0a673c671a56	791	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
ebrus	0:0a673c671a56	792
ebrus	0:0a673c671a56	793	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
ebrus	0:0a673c671a56	794	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
ebrus	0:0a673c671a56	795
ebrus	0:0a673c671a56	796	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
ebrus	0:0a673c671a56	797	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
ebrus	0:0a673c671a56	798
ebrus	0:0a673c671a56	799	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
ebrus	0:0a673c671a56	800	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
ebrus	0:0a673c671a56	801
ebrus	0:0a673c671a56	802	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
ebrus	0:0a673c671a56	803	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
ebrus	0:0a673c671a56	804
ebrus	0:0a673c671a56	805	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
ebrus	0:0a673c671a56	806	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
ebrus	0:0a673c671a56	807
ebrus	0:0a673c671a56	808	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
ebrus	0:0a673c671a56	809	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
ebrus	0:0a673c671a56	810
ebrus	0:0a673c671a56	811	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
ebrus	0:0a673c671a56	812	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
ebrus	0:0a673c671a56	813
ebrus	0:0a673c671a56	814	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
ebrus	0:0a673c671a56	815	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
ebrus	0:0a673c671a56	816
ebrus	0:0a673c671a56	817	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
ebrus	0:0a673c671a56	818	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
ebrus	0:0a673c671a56	819
ebrus	0:0a673c671a56	820	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
ebrus	0:0a673c671a56	821	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /!< DWT CTRL: CYCCNTENA Mask /
ebrus	0:0a673c671a56	822
ebrus	0:0a673c671a56	823	/* DWT CPI Count Register Definitions */
ebrus	0:0a673c671a56	824	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
ebrus	0:0a673c671a56	825	#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /!< DWT CPICNT: CPICNT Mask /
ebrus	0:0a673c671a56	826
ebrus	0:0a673c671a56	827	/* DWT Exception Overhead Count Register Definitions */
ebrus	0:0a673c671a56	828	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
ebrus	0:0a673c671a56	829	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /!< DWT EXCCNT: EXCCNT Mask /
ebrus	0:0a673c671a56	830
ebrus	0:0a673c671a56	831	/* DWT Sleep Count Register Definitions */
ebrus	0:0a673c671a56	832	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
ebrus	0:0a673c671a56	833	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /!< DWT SLEEPCNT: SLEEPCNT Mask /
ebrus	0:0a673c671a56	834
ebrus	0:0a673c671a56	835	/* DWT LSU Count Register Definitions */
ebrus	0:0a673c671a56	836	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
ebrus	0:0a673c671a56	837	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /!< DWT LSUCNT: LSUCNT Mask /
ebrus	0:0a673c671a56	838
ebrus	0:0a673c671a56	839	/* DWT Folded-instruction Count Register Definitions */
ebrus	0:0a673c671a56	840	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
ebrus	0:0a673c671a56	841	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /!< DWT FOLDCNT: FOLDCNT Mask /
ebrus	0:0a673c671a56	842
ebrus	0:0a673c671a56	843	/* DWT Comparator Mask Register Definitions */
ebrus	0:0a673c671a56	844	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
ebrus	0:0a673c671a56	845	#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /!< DWT MASK: MASK Mask /
ebrus	0:0a673c671a56	846
ebrus	0:0a673c671a56	847	/* DWT Comparator Function Register Definitions */
ebrus	0:0a673c671a56	848	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
ebrus	0:0a673c671a56	849	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
ebrus	0:0a673c671a56	850
ebrus	0:0a673c671a56	851	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
ebrus	0:0a673c671a56	852	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
ebrus	0:0a673c671a56	853
ebrus	0:0a673c671a56	854	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
ebrus	0:0a673c671a56	855	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
ebrus	0:0a673c671a56	856
ebrus	0:0a673c671a56	857	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
ebrus	0:0a673c671a56	858	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
ebrus	0:0a673c671a56	859
ebrus	0:0a673c671a56	860	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
ebrus	0:0a673c671a56	861	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
ebrus	0:0a673c671a56	862
ebrus	0:0a673c671a56	863	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
ebrus	0:0a673c671a56	864	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
ebrus	0:0a673c671a56	865
ebrus	0:0a673c671a56	866	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
ebrus	0:0a673c671a56	867	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
ebrus	0:0a673c671a56	868
ebrus	0:0a673c671a56	869	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
ebrus	0:0a673c671a56	870	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
ebrus	0:0a673c671a56	871
ebrus	0:0a673c671a56	872	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
ebrus	0:0a673c671a56	873	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /!< DWT FUNCTION: FUNCTION Mask /
ebrus	0:0a673c671a56	874
ebrus	0:0a673c671a56	875	/@}/ /* end of group CMSIS_DWT */
ebrus	0:0a673c671a56	876
ebrus	0:0a673c671a56	877
ebrus	0:0a673c671a56	878	/** \ingroup CMSIS_core_register
ebrus	0:0a673c671a56	879	\defgroup CMSIS_TPI Trace Port Interface (TPI)
ebrus	0:0a673c671a56	880	\brief Type definitions for the Trace Port Interface (TPI)
ebrus	0:0a673c671a56	881	@{
ebrus	0:0a673c671a56	882	*/
ebrus	0:0a673c671a56	883
ebrus	0:0a673c671a56	884	/** \brief Structure type to access the Trace Port Interface Register (TPI).
ebrus	0:0a673c671a56	885	*/
ebrus	0:0a673c671a56	886	typedef struct
ebrus	0:0a673c671a56	887	{
ebrus	0:0a673c671a56	888	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
ebrus	0:0a673c671a56	889	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
ebrus	0:0a673c671a56	890	uint32_t RESERVED0[2];
ebrus	0:0a673c671a56	891	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
ebrus	0:0a673c671a56	892	uint32_t RESERVED1[55];
ebrus	0:0a673c671a56	893	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
ebrus	0:0a673c671a56	894	uint32_t RESERVED2[131];
ebrus	0:0a673c671a56	895	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
ebrus	0:0a673c671a56	896	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
ebrus	0:0a673c671a56	897	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
ebrus	0:0a673c671a56	898	uint32_t RESERVED3[759];
ebrus	0:0a673c671a56	899	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
ebrus	0:0a673c671a56	900	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
ebrus	0:0a673c671a56	901	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
ebrus	0:0a673c671a56	902	uint32_t RESERVED4[1];
ebrus	0:0a673c671a56	903	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
ebrus	0:0a673c671a56	904	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
ebrus	0:0a673c671a56	905	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
ebrus	0:0a673c671a56	906	uint32_t RESERVED5[39];
ebrus	0:0a673c671a56	907	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
ebrus	0:0a673c671a56	908	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
ebrus	0:0a673c671a56	909	uint32_t RESERVED7[8];
ebrus	0:0a673c671a56	910	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
ebrus	0:0a673c671a56	911	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
ebrus	0:0a673c671a56	912	} TPI_Type;
ebrus	0:0a673c671a56	913
ebrus	0:0a673c671a56	914	/* TPI Asynchronous Clock Prescaler Register Definitions */
ebrus	0:0a673c671a56	915	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
ebrus	0:0a673c671a56	916	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /!< TPI ACPR: PRESCALER Mask /
ebrus	0:0a673c671a56	917
ebrus	0:0a673c671a56	918	/* TPI Selected Pin Protocol Register Definitions */
ebrus	0:0a673c671a56	919	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
ebrus	0:0a673c671a56	920	#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /!< TPI SPPR: TXMODE Mask /
ebrus	0:0a673c671a56	921
ebrus	0:0a673c671a56	922	/* TPI Formatter and Flush Status Register Definitions */
ebrus	0:0a673c671a56	923	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
ebrus	0:0a673c671a56	924	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
ebrus	0:0a673c671a56	925
ebrus	0:0a673c671a56	926	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
ebrus	0:0a673c671a56	927	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
ebrus	0:0a673c671a56	928
ebrus	0:0a673c671a56	929	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
ebrus	0:0a673c671a56	930	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
ebrus	0:0a673c671a56	931
ebrus	0:0a673c671a56	932	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
ebrus	0:0a673c671a56	933	#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /!< TPI FFSR: FlInProg Mask /
ebrus	0:0a673c671a56	934
ebrus	0:0a673c671a56	935	/* TPI Formatter and Flush Control Register Definitions */
ebrus	0:0a673c671a56	936	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
ebrus	0:0a673c671a56	937	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
ebrus	0:0a673c671a56	938
ebrus	0:0a673c671a56	939	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
ebrus	0:0a673c671a56	940	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
ebrus	0:0a673c671a56	941
ebrus	0:0a673c671a56	942	/* TPI TRIGGER Register Definitions */
ebrus	0:0a673c671a56	943	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
ebrus	0:0a673c671a56	944	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /!< TPI TRIGGER: TRIGGER Mask /
ebrus	0:0a673c671a56	945
ebrus	0:0a673c671a56	946	/* TPI Integration ETM Data Register Definitions (FIFO0) */
ebrus	0:0a673c671a56	947	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
ebrus	0:0a673c671a56	948	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
ebrus	0:0a673c671a56	949
ebrus	0:0a673c671a56	950	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
ebrus	0:0a673c671a56	951	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
ebrus	0:0a673c671a56	952
ebrus	0:0a673c671a56	953	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
ebrus	0:0a673c671a56	954	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
ebrus	0:0a673c671a56	955
ebrus	0:0a673c671a56	956	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
ebrus	0:0a673c671a56	957	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
ebrus	0:0a673c671a56	958
ebrus	0:0a673c671a56	959	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
ebrus	0:0a673c671a56	960	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
ebrus	0:0a673c671a56	961
ebrus	0:0a673c671a56	962	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
ebrus	0:0a673c671a56	963	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
ebrus	0:0a673c671a56	964
ebrus	0:0a673c671a56	965	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
ebrus	0:0a673c671a56	966	#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /!< TPI FIFO0: ETM0 Mask /
ebrus	0:0a673c671a56	967
ebrus	0:0a673c671a56	968	/* TPI ITATBCTR2 Register Definitions */
ebrus	0:0a673c671a56	969	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
ebrus	0:0a673c671a56	970	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /!< TPI ITATBCTR2: ATREADY Mask /
ebrus	0:0a673c671a56	971
ebrus	0:0a673c671a56	972	/* TPI Integration ITM Data Register Definitions (FIFO1) */
ebrus	0:0a673c671a56	973	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
ebrus	0:0a673c671a56	974	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
ebrus	0:0a673c671a56	975
ebrus	0:0a673c671a56	976	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
ebrus	0:0a673c671a56	977	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
ebrus	0:0a673c671a56	978
ebrus	0:0a673c671a56	979	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
ebrus	0:0a673c671a56	980	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
ebrus	0:0a673c671a56	981
ebrus	0:0a673c671a56	982	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
ebrus	0:0a673c671a56	983	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
ebrus	0:0a673c671a56	984
ebrus	0:0a673c671a56	985	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
ebrus	0:0a673c671a56	986	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
ebrus	0:0a673c671a56	987
ebrus	0:0a673c671a56	988	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
ebrus	0:0a673c671a56	989	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
ebrus	0:0a673c671a56	990
ebrus	0:0a673c671a56	991	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
ebrus	0:0a673c671a56	992	#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /!< TPI FIFO1: ITM0 Mask /
ebrus	0:0a673c671a56	993
ebrus	0:0a673c671a56	994	/* TPI ITATBCTR0 Register Definitions */
ebrus	0:0a673c671a56	995	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
ebrus	0:0a673c671a56	996	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /!< TPI ITATBCTR0: ATREADY Mask /
ebrus	0:0a673c671a56	997
ebrus	0:0a673c671a56	998	/* TPI Integration Mode Control Register Definitions */
ebrus	0:0a673c671a56	999	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
ebrus	0:0a673c671a56	1000	#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /!< TPI ITCTRL: Mode Mask /
ebrus	0:0a673c671a56	1001
ebrus	0:0a673c671a56	1002	/* TPI DEVID Register Definitions */
ebrus	0:0a673c671a56	1003	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
ebrus	0:0a673c671a56	1004	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
ebrus	0:0a673c671a56	1005
ebrus	0:0a673c671a56	1006	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
ebrus	0:0a673c671a56	1007	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
ebrus	0:0a673c671a56	1008
ebrus	0:0a673c671a56	1009	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
ebrus	0:0a673c671a56	1010	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
ebrus	0:0a673c671a56	1011
ebrus	0:0a673c671a56	1012	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
ebrus	0:0a673c671a56	1013	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
ebrus	0:0a673c671a56	1014
ebrus	0:0a673c671a56	1015	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
ebrus	0:0a673c671a56	1016	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
ebrus	0:0a673c671a56	1017
ebrus	0:0a673c671a56	1018	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
ebrus	0:0a673c671a56	1019	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /!< TPI DEVID: NrTraceInput Mask /
ebrus	0:0a673c671a56	1020
ebrus	0:0a673c671a56	1021	/* TPI DEVTYPE Register Definitions */
ebrus	0:0a673c671a56	1022	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
ebrus	0:0a673c671a56	1023	#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /!< TPI DEVTYPE: SubType Mask /
ebrus	0:0a673c671a56	1024
ebrus	0:0a673c671a56	1025	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
ebrus	0:0a673c671a56	1026	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
ebrus	0:0a673c671a56	1027
ebrus	0:0a673c671a56	1028	/@}/ /* end of group CMSIS_TPI */
ebrus	0:0a673c671a56	1029
ebrus	0:0a673c671a56	1030
ebrus	0:0a673c671a56	1031	#if (__MPU_PRESENT == 1)
ebrus	0:0a673c671a56	1032	/** \ingroup CMSIS_core_register
ebrus	0:0a673c671a56	1033	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
ebrus	0:0a673c671a56	1034	\brief Type definitions for the Memory Protection Unit (MPU)
ebrus	0:0a673c671a56	1035	@{
ebrus	0:0a673c671a56	1036	*/
ebrus	0:0a673c671a56	1037
ebrus	0:0a673c671a56	1038	/** \brief Structure type to access the Memory Protection Unit (MPU).
ebrus	0:0a673c671a56	1039	*/
ebrus	0:0a673c671a56	1040	typedef struct
ebrus	0:0a673c671a56	1041	{
ebrus	0:0a673c671a56	1042	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
ebrus	0:0a673c671a56	1043	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
ebrus	0:0a673c671a56	1044	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
ebrus	0:0a673c671a56	1045	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
ebrus	0:0a673c671a56	1046	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
ebrus	0:0a673c671a56	1047	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
ebrus	0:0a673c671a56	1048	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
ebrus	0:0a673c671a56	1049	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
ebrus	0:0a673c671a56	1050	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
ebrus	0:0a673c671a56	1051	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
ebrus	0:0a673c671a56	1052	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
ebrus	0:0a673c671a56	1053	} MPU_Type;
ebrus	0:0a673c671a56	1054
ebrus	0:0a673c671a56	1055	/* MPU Type Register */
ebrus	0:0a673c671a56	1056	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
ebrus	0:0a673c671a56	1057	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
ebrus	0:0a673c671a56	1058
ebrus	0:0a673c671a56	1059	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
ebrus	0:0a673c671a56	1060	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
ebrus	0:0a673c671a56	1061
ebrus	0:0a673c671a56	1062	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
ebrus	0:0a673c671a56	1063	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
ebrus	0:0a673c671a56	1064
ebrus	0:0a673c671a56	1065	/* MPU Control Register */
ebrus	0:0a673c671a56	1066	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
ebrus	0:0a673c671a56	1067	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
ebrus	0:0a673c671a56	1068
ebrus	0:0a673c671a56	1069	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
ebrus	0:0a673c671a56	1070	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
ebrus	0:0a673c671a56	1071
ebrus	0:0a673c671a56	1072	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
ebrus	0:0a673c671a56	1073	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
ebrus	0:0a673c671a56	1074
ebrus	0:0a673c671a56	1075	/* MPU Region Number Register */
ebrus	0:0a673c671a56	1076	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
ebrus	0:0a673c671a56	1077	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
ebrus	0:0a673c671a56	1078
ebrus	0:0a673c671a56	1079	/* MPU Region Base Address Register */
ebrus	0:0a673c671a56	1080	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
ebrus	0:0a673c671a56	1081	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
ebrus	0:0a673c671a56	1082
ebrus	0:0a673c671a56	1083	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
ebrus	0:0a673c671a56	1084	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
ebrus	0:0a673c671a56	1085
ebrus	0:0a673c671a56	1086	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
ebrus	0:0a673c671a56	1087	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
ebrus	0:0a673c671a56	1088
ebrus	0:0a673c671a56	1089	/* MPU Region Attribute and Size Register */
ebrus	0:0a673c671a56	1090	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
ebrus	0:0a673c671a56	1091	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
ebrus	0:0a673c671a56	1092
ebrus	0:0a673c671a56	1093	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
ebrus	0:0a673c671a56	1094	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
ebrus	0:0a673c671a56	1095
ebrus	0:0a673c671a56	1096	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
ebrus	0:0a673c671a56	1097	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
ebrus	0:0a673c671a56	1098
ebrus	0:0a673c671a56	1099	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
ebrus	0:0a673c671a56	1100	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
ebrus	0:0a673c671a56	1101
ebrus	0:0a673c671a56	1102	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
ebrus	0:0a673c671a56	1103	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
ebrus	0:0a673c671a56	1104
ebrus	0:0a673c671a56	1105	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
ebrus	0:0a673c671a56	1106	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
ebrus	0:0a673c671a56	1107
ebrus	0:0a673c671a56	1108	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
ebrus	0:0a673c671a56	1109	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
ebrus	0:0a673c671a56	1110
ebrus	0:0a673c671a56	1111	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
ebrus	0:0a673c671a56	1112	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
ebrus	0:0a673c671a56	1113
ebrus	0:0a673c671a56	1114	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
ebrus	0:0a673c671a56	1115	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
ebrus	0:0a673c671a56	1116
ebrus	0:0a673c671a56	1117	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
ebrus	0:0a673c671a56	1118	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
ebrus	0:0a673c671a56	1119
ebrus	0:0a673c671a56	1120	/@} end of group CMSIS_MPU /
ebrus	0:0a673c671a56	1121	#endif
ebrus	0:0a673c671a56	1122
ebrus	0:0a673c671a56	1123
ebrus	0:0a673c671a56	1124	/** \ingroup CMSIS_core_register
ebrus	0:0a673c671a56	1125	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
ebrus	0:0a673c671a56	1126	\brief Type definitions for the Core Debug Registers
ebrus	0:0a673c671a56	1127	@{
ebrus	0:0a673c671a56	1128	*/
ebrus	0:0a673c671a56	1129
ebrus	0:0a673c671a56	1130	/** \brief Structure type to access the Core Debug Register (CoreDebug).
ebrus	0:0a673c671a56	1131	*/
ebrus	0:0a673c671a56	1132	typedef struct
ebrus	0:0a673c671a56	1133	{
ebrus	0:0a673c671a56	1134	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
ebrus	0:0a673c671a56	1135	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
ebrus	0:0a673c671a56	1136	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
ebrus	0:0a673c671a56	1137	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
ebrus	0:0a673c671a56	1138	} CoreDebug_Type;
ebrus	0:0a673c671a56	1139
ebrus	0:0a673c671a56	1140	/* Debug Halting Control and Status Register */
ebrus	0:0a673c671a56	1141	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
ebrus	0:0a673c671a56	1142	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
ebrus	0:0a673c671a56	1143
ebrus	0:0a673c671a56	1144	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
ebrus	0:0a673c671a56	1145	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
ebrus	0:0a673c671a56	1146
ebrus	0:0a673c671a56	1147	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
ebrus	0:0a673c671a56	1148	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
ebrus	0:0a673c671a56	1149
ebrus	0:0a673c671a56	1150	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
ebrus	0:0a673c671a56	1151	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
ebrus	0:0a673c671a56	1152
ebrus	0:0a673c671a56	1153	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
ebrus	0:0a673c671a56	1154	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
ebrus	0:0a673c671a56	1155
ebrus	0:0a673c671a56	1156	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
ebrus	0:0a673c671a56	1157	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
ebrus	0:0a673c671a56	1158
ebrus	0:0a673c671a56	1159	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
ebrus	0:0a673c671a56	1160	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
ebrus	0:0a673c671a56	1161
ebrus	0:0a673c671a56	1162	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
ebrus	0:0a673c671a56	1163	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
ebrus	0:0a673c671a56	1164
ebrus	0:0a673c671a56	1165	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
ebrus	0:0a673c671a56	1166	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
ebrus	0:0a673c671a56	1167
ebrus	0:0a673c671a56	1168	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
ebrus	0:0a673c671a56	1169	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
ebrus	0:0a673c671a56	1170
ebrus	0:0a673c671a56	1171	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
ebrus	0:0a673c671a56	1172	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
ebrus	0:0a673c671a56	1173
ebrus	0:0a673c671a56	1174	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
ebrus	0:0a673c671a56	1175	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
ebrus	0:0a673c671a56	1176
ebrus	0:0a673c671a56	1177	/* Debug Core Register Selector Register */
ebrus	0:0a673c671a56	1178	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
ebrus	0:0a673c671a56	1179	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
ebrus	0:0a673c671a56	1180
ebrus	0:0a673c671a56	1181	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
ebrus	0:0a673c671a56	1182	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
ebrus	0:0a673c671a56	1183
ebrus	0:0a673c671a56	1184	/* Debug Exception and Monitor Control Register */
ebrus	0:0a673c671a56	1185	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
ebrus	0:0a673c671a56	1186	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
ebrus	0:0a673c671a56	1187
ebrus	0:0a673c671a56	1188	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
ebrus	0:0a673c671a56	1189	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
ebrus	0:0a673c671a56	1190
ebrus	0:0a673c671a56	1191	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
ebrus	0:0a673c671a56	1192	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
ebrus	0:0a673c671a56	1193
ebrus	0:0a673c671a56	1194	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
ebrus	0:0a673c671a56	1195	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
ebrus	0:0a673c671a56	1196
ebrus	0:0a673c671a56	1197	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
ebrus	0:0a673c671a56	1198	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
ebrus	0:0a673c671a56	1199
ebrus	0:0a673c671a56	1200	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
ebrus	0:0a673c671a56	1201	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
ebrus	0:0a673c671a56	1202
ebrus	0:0a673c671a56	1203	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
ebrus	0:0a673c671a56	1204	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
ebrus	0:0a673c671a56	1205
ebrus	0:0a673c671a56	1206	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
ebrus	0:0a673c671a56	1207	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
ebrus	0:0a673c671a56	1208
ebrus	0:0a673c671a56	1209	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
ebrus	0:0a673c671a56	1210	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
ebrus	0:0a673c671a56	1211
ebrus	0:0a673c671a56	1212	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
ebrus	0:0a673c671a56	1213	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
ebrus	0:0a673c671a56	1214
ebrus	0:0a673c671a56	1215	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
ebrus	0:0a673c671a56	1216	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
ebrus	0:0a673c671a56	1217
ebrus	0:0a673c671a56	1218	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
ebrus	0:0a673c671a56	1219	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
ebrus	0:0a673c671a56	1220
ebrus	0:0a673c671a56	1221	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
ebrus	0:0a673c671a56	1222	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
ebrus	0:0a673c671a56	1223
ebrus	0:0a673c671a56	1224	/@} end of group CMSIS_CoreDebug /
ebrus	0:0a673c671a56	1225
ebrus	0:0a673c671a56	1226
ebrus	0:0a673c671a56	1227	/** \ingroup CMSIS_core_register
ebrus	0:0a673c671a56	1228	\defgroup CMSIS_core_base Core Definitions
ebrus	0:0a673c671a56	1229	\brief Definitions for base addresses, unions, and structures.
ebrus	0:0a673c671a56	1230	@{
ebrus	0:0a673c671a56	1231	*/
ebrus	0:0a673c671a56	1232
ebrus	0:0a673c671a56	1233	/* Memory mapping of Cortex-M3 Hardware */
ebrus	0:0a673c671a56	1234	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
ebrus	0:0a673c671a56	1235	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
ebrus	0:0a673c671a56	1236	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
ebrus	0:0a673c671a56	1237	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
ebrus	0:0a673c671a56	1238	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
ebrus	0:0a673c671a56	1239	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
ebrus	0:0a673c671a56	1240	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
ebrus	0:0a673c671a56	1241	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
ebrus	0:0a673c671a56	1242
ebrus	0:0a673c671a56	1243	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
ebrus	0:0a673c671a56	1244	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
ebrus	0:0a673c671a56	1245	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
ebrus	0:0a673c671a56	1246	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
ebrus	0:0a673c671a56	1247	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
ebrus	0:0a673c671a56	1248	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
ebrus	0:0a673c671a56	1249	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
ebrus	0:0a673c671a56	1250	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
ebrus	0:0a673c671a56	1251
ebrus	0:0a673c671a56	1252	#if (__MPU_PRESENT == 1)
ebrus	0:0a673c671a56	1253	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
ebrus	0:0a673c671a56	1254	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
ebrus	0:0a673c671a56	1255	#endif
ebrus	0:0a673c671a56	1256
ebrus	0:0a673c671a56	1257	/@} /
ebrus	0:0a673c671a56	1258
ebrus	0:0a673c671a56	1259
ebrus	0:0a673c671a56	1260
ebrus	0:0a673c671a56	1261	/*******************************************************************************
ebrus	0:0a673c671a56	1262	* Hardware Abstraction Layer
ebrus	0:0a673c671a56	1263	Core Function Interface contains:
ebrus	0:0a673c671a56	1264	- Core NVIC Functions
ebrus	0:0a673c671a56	1265	- Core SysTick Functions
ebrus	0:0a673c671a56	1266	- Core Debug Functions
ebrus	0:0a673c671a56	1267	- Core Register Access Functions
ebrus	0:0a673c671a56	1268	******************************************************************************/
ebrus	0:0a673c671a56	1269	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
ebrus	0:0a673c671a56	1270	*/
ebrus	0:0a673c671a56	1271
ebrus	0:0a673c671a56	1272
ebrus	0:0a673c671a56	1273
ebrus	0:0a673c671a56	1274	/* ########################## NVIC functions #################################### */
ebrus	0:0a673c671a56	1275	/** \ingroup CMSIS_Core_FunctionInterface
ebrus	0:0a673c671a56	1276	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
ebrus	0:0a673c671a56	1277	\brief Functions that manage interrupts and exceptions via the NVIC.
ebrus	0:0a673c671a56	1278	@{
ebrus	0:0a673c671a56	1279	*/
ebrus	0:0a673c671a56	1280
ebrus	0:0a673c671a56	1281	/** \brief Set Priority Grouping
ebrus	0:0a673c671a56	1282
ebrus	0:0a673c671a56	1283	The function sets the priority grouping field using the required unlock sequence.
ebrus	0:0a673c671a56	1284	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
ebrus	0:0a673c671a56	1285	Only values from 0..7 are used.
ebrus	0:0a673c671a56	1286	In case of a conflict between priority grouping and available
ebrus	0:0a673c671a56	1287	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
ebrus	0:0a673c671a56	1288
ebrus	0:0a673c671a56	1289	\param [in] PriorityGroup Priority grouping field.
ebrus	0:0a673c671a56	1290	*/
ebrus	0:0a673c671a56	1291	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
ebrus	0:0a673c671a56	1292	{
ebrus	0:0a673c671a56	1293	uint32_t reg_value;
ebrus	0:0a673c671a56	1294	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
ebrus	0:0a673c671a56	1295
ebrus	0:0a673c671a56	1296	reg_value = SCB->AIRCR; /* read old register configuration */
ebrus	0:0a673c671a56	1297	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
ebrus	0:0a673c671a56	1298	reg_value = (reg_value \|
ebrus	0:0a673c671a56	1299	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
ebrus	0:0a673c671a56	1300	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
ebrus	0:0a673c671a56	1301	SCB->AIRCR = reg_value;
ebrus	0:0a673c671a56	1302	}
ebrus	0:0a673c671a56	1303
ebrus	0:0a673c671a56	1304
ebrus	0:0a673c671a56	1305	/** \brief Get Priority Grouping
ebrus	0:0a673c671a56	1306
ebrus	0:0a673c671a56	1307	The function reads the priority grouping field from the NVIC Interrupt Controller.
ebrus	0:0a673c671a56	1308
ebrus	0:0a673c671a56	1309	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
ebrus	0:0a673c671a56	1310	*/
ebrus	0:0a673c671a56	1311	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
ebrus	0:0a673c671a56	1312	{
ebrus	0:0a673c671a56	1313	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
ebrus	0:0a673c671a56	1314	}
ebrus	0:0a673c671a56	1315
ebrus	0:0a673c671a56	1316
ebrus	0:0a673c671a56	1317	/** \brief Enable External Interrupt
ebrus	0:0a673c671a56	1318
ebrus	0:0a673c671a56	1319	The function enables a device-specific interrupt in the NVIC interrupt controller.
ebrus	0:0a673c671a56	1320
ebrus	0:0a673c671a56	1321	\param [in] IRQn External interrupt number. Value cannot be negative.
ebrus	0:0a673c671a56	1322	*/
ebrus	0:0a673c671a56	1323	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
ebrus	0:0a673c671a56	1324	{
ebrus	0:0a673c671a56	1325	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
ebrus	0:0a673c671a56	1326	}
ebrus	0:0a673c671a56	1327
ebrus	0:0a673c671a56	1328
ebrus	0:0a673c671a56	1329	/** \brief Disable External Interrupt
ebrus	0:0a673c671a56	1330
ebrus	0:0a673c671a56	1331	The function disables a device-specific interrupt in the NVIC interrupt controller.
ebrus	0:0a673c671a56	1332
ebrus	0:0a673c671a56	1333	\param [in] IRQn External interrupt number. Value cannot be negative.
ebrus	0:0a673c671a56	1334	*/
ebrus	0:0a673c671a56	1335	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
ebrus	0:0a673c671a56	1336	{
ebrus	0:0a673c671a56	1337	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
ebrus	0:0a673c671a56	1338	}
ebrus	0:0a673c671a56	1339
ebrus	0:0a673c671a56	1340
ebrus	0:0a673c671a56	1341	/** \brief Get Pending Interrupt
ebrus	0:0a673c671a56	1342
ebrus	0:0a673c671a56	1343	The function reads the pending register in the NVIC and returns the pending bit
ebrus	0:0a673c671a56	1344	for the specified interrupt.
ebrus	0:0a673c671a56	1345
ebrus	0:0a673c671a56	1346	\param [in] IRQn Interrupt number.
ebrus	0:0a673c671a56	1347
ebrus	0:0a673c671a56	1348	\return 0 Interrupt status is not pending.
ebrus	0:0a673c671a56	1349	\return 1 Interrupt status is pending.
ebrus	0:0a673c671a56	1350	*/
ebrus	0:0a673c671a56	1351	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
ebrus	0:0a673c671a56	1352	{
ebrus	0:0a673c671a56	1353	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
ebrus	0:0a673c671a56	1354	}
ebrus	0:0a673c671a56	1355
ebrus	0:0a673c671a56	1356
ebrus	0:0a673c671a56	1357	/** \brief Set Pending Interrupt
ebrus	0:0a673c671a56	1358
ebrus	0:0a673c671a56	1359	The function sets the pending bit of an external interrupt.
ebrus	0:0a673c671a56	1360
ebrus	0:0a673c671a56	1361	\param [in] IRQn Interrupt number. Value cannot be negative.
ebrus	0:0a673c671a56	1362	*/
ebrus	0:0a673c671a56	1363	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
ebrus	0:0a673c671a56	1364	{
ebrus	0:0a673c671a56	1365	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
ebrus	0:0a673c671a56	1366	}
ebrus	0:0a673c671a56	1367
ebrus	0:0a673c671a56	1368
ebrus	0:0a673c671a56	1369	/** \brief Clear Pending Interrupt
ebrus	0:0a673c671a56	1370
ebrus	0:0a673c671a56	1371	The function clears the pending bit of an external interrupt.
ebrus	0:0a673c671a56	1372
ebrus	0:0a673c671a56	1373	\param [in] IRQn External interrupt number. Value cannot be negative.
ebrus	0:0a673c671a56	1374	*/
ebrus	0:0a673c671a56	1375	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
ebrus	0:0a673c671a56	1376	{
ebrus	0:0a673c671a56	1377	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
ebrus	0:0a673c671a56	1378	}
ebrus	0:0a673c671a56	1379
ebrus	0:0a673c671a56	1380
ebrus	0:0a673c671a56	1381	/** \brief Get Active Interrupt
ebrus	0:0a673c671a56	1382
ebrus	0:0a673c671a56	1383	The function reads the active register in NVIC and returns the active bit.
ebrus	0:0a673c671a56	1384
ebrus	0:0a673c671a56	1385	\param [in] IRQn Interrupt number.
ebrus	0:0a673c671a56	1386
ebrus	0:0a673c671a56	1387	\return 0 Interrupt status is not active.
ebrus	0:0a673c671a56	1388	\return 1 Interrupt status is active.
ebrus	0:0a673c671a56	1389	*/
ebrus	0:0a673c671a56	1390	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
ebrus	0:0a673c671a56	1391	{
ebrus	0:0a673c671a56	1392	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
ebrus	0:0a673c671a56	1393	}
ebrus	0:0a673c671a56	1394
ebrus	0:0a673c671a56	1395
ebrus	0:0a673c671a56	1396	/** \brief Set Interrupt Priority
ebrus	0:0a673c671a56	1397
ebrus	0:0a673c671a56	1398	The function sets the priority of an interrupt.
ebrus	0:0a673c671a56	1399
ebrus	0:0a673c671a56	1400	\note The priority cannot be set for every core interrupt.
ebrus	0:0a673c671a56	1401
ebrus	0:0a673c671a56	1402	\param [in] IRQn Interrupt number.
ebrus	0:0a673c671a56	1403	\param [in] priority Priority to set.
ebrus	0:0a673c671a56	1404	*/
ebrus	0:0a673c671a56	1405	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
ebrus	0:0a673c671a56	1406	{
ebrus	0:0a673c671a56	1407	if(IRQn < 0) {
ebrus	0:0a673c671a56	1408	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
ebrus	0:0a673c671a56	1409	else {
ebrus	0:0a673c671a56	1410	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
ebrus	0:0a673c671a56	1411	}
ebrus	0:0a673c671a56	1412
ebrus	0:0a673c671a56	1413
ebrus	0:0a673c671a56	1414	/** \brief Get Interrupt Priority
ebrus	0:0a673c671a56	1415
ebrus	0:0a673c671a56	1416	The function reads the priority of an interrupt. The interrupt
ebrus	0:0a673c671a56	1417	number can be positive to specify an external (device specific)
ebrus	0:0a673c671a56	1418	interrupt, or negative to specify an internal (core) interrupt.
ebrus	0:0a673c671a56	1419
ebrus	0:0a673c671a56	1420
ebrus	0:0a673c671a56	1421	\param [in] IRQn Interrupt number.
ebrus	0:0a673c671a56	1422	\return Interrupt Priority. Value is aligned automatically to the implemented
ebrus	0:0a673c671a56	1423	priority bits of the microcontroller.
ebrus	0:0a673c671a56	1424	*/
ebrus	0:0a673c671a56	1425	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
ebrus	0:0a673c671a56	1426	{
ebrus	0:0a673c671a56	1427
ebrus	0:0a673c671a56	1428	if(IRQn < 0) {
ebrus	0:0a673c671a56	1429	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
ebrus	0:0a673c671a56	1430	else {
ebrus	0:0a673c671a56	1431	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
ebrus	0:0a673c671a56	1432	}
ebrus	0:0a673c671a56	1433
ebrus	0:0a673c671a56	1434
ebrus	0:0a673c671a56	1435	/** \brief Encode Priority
ebrus	0:0a673c671a56	1436
ebrus	0:0a673c671a56	1437	The function encodes the priority for an interrupt with the given priority group,
ebrus	0:0a673c671a56	1438	preemptive priority value, and subpriority value.
ebrus	0:0a673c671a56	1439	In case of a conflict between priority grouping and available
ebrus	0:0a673c671a56	1440	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
ebrus	0:0a673c671a56	1441
ebrus	0:0a673c671a56	1442	\param [in] PriorityGroup Used priority group.
ebrus	0:0a673c671a56	1443	\param [in] PreemptPriority Preemptive priority value (starting from 0).
ebrus	0:0a673c671a56	1444	\param [in] SubPriority Subpriority value (starting from 0).
ebrus	0:0a673c671a56	1445	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
ebrus	0:0a673c671a56	1446	*/
ebrus	0:0a673c671a56	1447	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
ebrus	0:0a673c671a56	1448	{
ebrus	0:0a673c671a56	1449	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
ebrus	0:0a673c671a56	1450	uint32_t PreemptPriorityBits;
ebrus	0:0a673c671a56	1451	uint32_t SubPriorityBits;
ebrus	0:0a673c671a56	1452
ebrus	0:0a673c671a56	1453	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
ebrus	0:0a673c671a56	1454	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
ebrus	0:0a673c671a56	1455
ebrus	0:0a673c671a56	1456	return (
ebrus	0:0a673c671a56	1457	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
ebrus	0:0a673c671a56	1458	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
ebrus	0:0a673c671a56	1459	);
ebrus	0:0a673c671a56	1460	}
ebrus	0:0a673c671a56	1461
ebrus	0:0a673c671a56	1462
ebrus	0:0a673c671a56	1463	/** \brief Decode Priority
ebrus	0:0a673c671a56	1464
ebrus	0:0a673c671a56	1465	The function decodes an interrupt priority value with a given priority group to
ebrus	0:0a673c671a56	1466	preemptive priority value and subpriority value.
ebrus	0:0a673c671a56	1467	In case of a conflict between priority grouping and available
ebrus	0:0a673c671a56	1468	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
ebrus	0:0a673c671a56	1469
ebrus	0:0a673c671a56	1470	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
ebrus	0:0a673c671a56	1471	\param [in] PriorityGroup Used priority group.
ebrus	0:0a673c671a56	1472	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
ebrus	0:0a673c671a56	1473	\param [out] pSubPriority Subpriority value (starting from 0).
ebrus	0:0a673c671a56	1474	*/
ebrus	0:0a673c671a56	1475	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
ebrus	0:0a673c671a56	1476	{
ebrus	0:0a673c671a56	1477	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
ebrus	0:0a673c671a56	1478	uint32_t PreemptPriorityBits;
ebrus	0:0a673c671a56	1479	uint32_t SubPriorityBits;
ebrus	0:0a673c671a56	1480
ebrus	0:0a673c671a56	1481	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
ebrus	0:0a673c671a56	1482	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
ebrus	0:0a673c671a56	1483
ebrus	0:0a673c671a56	1484	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
ebrus	0:0a673c671a56	1485	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
ebrus	0:0a673c671a56	1486	}
ebrus	0:0a673c671a56	1487
ebrus	0:0a673c671a56	1488
ebrus	0:0a673c671a56	1489	/** \brief System Reset
ebrus	0:0a673c671a56	1490
ebrus	0:0a673c671a56	1491	The function initiates a system reset request to reset the MCU.
ebrus	0:0a673c671a56	1492	*/
ebrus	0:0a673c671a56	1493	__STATIC_INLINE void NVIC_SystemReset(void)
ebrus	0:0a673c671a56	1494	{
ebrus	0:0a673c671a56	1495	__DSB(); /* Ensure all outstanding memory accesses included
ebrus	0:0a673c671a56	1496	buffered write are completed before reset */
ebrus	0:0a673c671a56	1497	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
ebrus	0:0a673c671a56	1498	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
ebrus	0:0a673c671a56	1499	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
ebrus	0:0a673c671a56	1500	__DSB(); /* Ensure completion of memory access */
ebrus	0:0a673c671a56	1501	while(1); /* wait until reset */
ebrus	0:0a673c671a56	1502	}
ebrus	0:0a673c671a56	1503
ebrus	0:0a673c671a56	1504	/@} end of CMSIS_Core_NVICFunctions /
ebrus	0:0a673c671a56	1505
ebrus	0:0a673c671a56	1506
ebrus	0:0a673c671a56	1507
ebrus	0:0a673c671a56	1508	/* ################################## SysTick function ############################################ */
ebrus	0:0a673c671a56	1509	/** \ingroup CMSIS_Core_FunctionInterface
ebrus	0:0a673c671a56	1510	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
ebrus	0:0a673c671a56	1511	\brief Functions that configure the System.
ebrus	0:0a673c671a56	1512	@{
ebrus	0:0a673c671a56	1513	*/
ebrus	0:0a673c671a56	1514
ebrus	0:0a673c671a56	1515	#if (__Vendor_SysTickConfig == 0)
ebrus	0:0a673c671a56	1516
ebrus	0:0a673c671a56	1517	/** \brief System Tick Configuration
ebrus	0:0a673c671a56	1518
ebrus	0:0a673c671a56	1519	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
ebrus	0:0a673c671a56	1520	Counter is in free running mode to generate periodic interrupts.
ebrus	0:0a673c671a56	1521
ebrus	0:0a673c671a56	1522	\param [in] ticks Number of ticks between two interrupts.
ebrus	0:0a673c671a56	1523
ebrus	0:0a673c671a56	1524	\return 0 Function succeeded.
ebrus	0:0a673c671a56	1525	\return 1 Function failed.
ebrus	0:0a673c671a56	1526
ebrus	0:0a673c671a56	1527	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
ebrus	0:0a673c671a56	1528	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
ebrus	0:0a673c671a56	1529	must contain a vendor-specific implementation of this function.
ebrus	0:0a673c671a56	1530
ebrus	0:0a673c671a56	1531	*/
ebrus	0:0a673c671a56	1532	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
ebrus	0:0a673c671a56	1533	{
ebrus	0:0a673c671a56	1534	if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
ebrus	0:0a673c671a56	1535
ebrus	0:0a673c671a56	1536	SysTick->LOAD = ticks - 1; /* set reload register */
ebrus	0:0a673c671a56	1537	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
ebrus	0:0a673c671a56	1538	SysTick->VAL = 0; /* Load the SysTick Counter Value */
ebrus	0:0a673c671a56	1539	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
ebrus	0:0a673c671a56	1540	SysTick_CTRL_TICKINT_Msk \|
ebrus	0:0a673c671a56	1541	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
ebrus	0:0a673c671a56	1542	return (0); /* Function successful */
ebrus	0:0a673c671a56	1543	}
ebrus	0:0a673c671a56	1544
ebrus	0:0a673c671a56	1545	#endif
ebrus	0:0a673c671a56	1546
ebrus	0:0a673c671a56	1547	/@} end of CMSIS_Core_SysTickFunctions /
ebrus	0:0a673c671a56	1548
ebrus	0:0a673c671a56	1549
ebrus	0:0a673c671a56	1550
ebrus	0:0a673c671a56	1551	/* ##################################### Debug In/Output function ########################################### */
ebrus	0:0a673c671a56	1552	/** \ingroup CMSIS_Core_FunctionInterface
ebrus	0:0a673c671a56	1553	\defgroup CMSIS_core_DebugFunctions ITM Functions
ebrus	0:0a673c671a56	1554	\brief Functions that access the ITM debug interface.
ebrus	0:0a673c671a56	1555	@{
ebrus	0:0a673c671a56	1556	*/
ebrus	0:0a673c671a56	1557
ebrus	0:0a673c671a56	1558	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
ebrus	0:0a673c671a56	1559	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
ebrus	0:0a673c671a56	1560
ebrus	0:0a673c671a56	1561
ebrus	0:0a673c671a56	1562	/** \brief ITM Send Character
ebrus	0:0a673c671a56	1563
ebrus	0:0a673c671a56	1564	The function transmits a character via the ITM channel 0, and
ebrus	0:0a673c671a56	1565	\li Just returns when no debugger is connected that has booked the output.
ebrus	0:0a673c671a56	1566	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
ebrus	0:0a673c671a56	1567
ebrus	0:0a673c671a56	1568	\param [in] ch Character to transmit.
ebrus	0:0a673c671a56	1569
ebrus	0:0a673c671a56	1570	\returns Character to transmit.
ebrus	0:0a673c671a56	1571	*/
ebrus	0:0a673c671a56	1572	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
ebrus	0:0a673c671a56	1573	{
ebrus	0:0a673c671a56	1574	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
ebrus	0:0a673c671a56	1575	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
ebrus	0:0a673c671a56	1576	{
ebrus	0:0a673c671a56	1577	while (ITM->PORT[0].u32 == 0);
ebrus	0:0a673c671a56	1578	ITM->PORT[0].u8 = (uint8_t) ch;
ebrus	0:0a673c671a56	1579	}
ebrus	0:0a673c671a56	1580	return (ch);
ebrus	0:0a673c671a56	1581	}
ebrus	0:0a673c671a56	1582
ebrus	0:0a673c671a56	1583
ebrus	0:0a673c671a56	1584	/** \brief ITM Receive Character
ebrus	0:0a673c671a56	1585
ebrus	0:0a673c671a56	1586	The function inputs a character via the external variable \ref ITM_RxBuffer.
ebrus	0:0a673c671a56	1587
ebrus	0:0a673c671a56	1588	\return Received character.
ebrus	0:0a673c671a56	1589	\return -1 No character pending.
ebrus	0:0a673c671a56	1590	*/
ebrus	0:0a673c671a56	1591	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
ebrus	0:0a673c671a56	1592	int32_t ch = -1; /* no character available */
ebrus	0:0a673c671a56	1593
ebrus	0:0a673c671a56	1594	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ebrus	0:0a673c671a56	1595	ch = ITM_RxBuffer;
ebrus	0:0a673c671a56	1596	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
ebrus	0:0a673c671a56	1597	}
ebrus	0:0a673c671a56	1598
ebrus	0:0a673c671a56	1599	return (ch);
ebrus	0:0a673c671a56	1600	}
ebrus	0:0a673c671a56	1601
ebrus	0:0a673c671a56	1602
ebrus	0:0a673c671a56	1603	/** \brief ITM Check Character
ebrus	0:0a673c671a56	1604
ebrus	0:0a673c671a56	1605	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
ebrus	0:0a673c671a56	1606
ebrus	0:0a673c671a56	1607	\return 0 No character available.
ebrus	0:0a673c671a56	1608	\return 1 Character available.
ebrus	0:0a673c671a56	1609	*/
ebrus	0:0a673c671a56	1610	__STATIC_INLINE int32_t ITM_CheckChar (void) {
ebrus	0:0a673c671a56	1611
ebrus	0:0a673c671a56	1612	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
ebrus	0:0a673c671a56	1613	return (0); /* no character available */
ebrus	0:0a673c671a56	1614	} else {
ebrus	0:0a673c671a56	1615	return (1); /* character available */
ebrus	0:0a673c671a56	1616	}
ebrus	0:0a673c671a56	1617	}
ebrus	0:0a673c671a56	1618
ebrus	0:0a673c671a56	1619	/@} end of CMSIS_core_DebugFunctions /
ebrus	0:0a673c671a56	1620
ebrus	0:0a673c671a56	1621	#endif /* __CORE_CM3_H_DEPENDANT */
ebrus	0:0a673c671a56	1622
ebrus	0:0a673c671a56	1623	#endif /* __CMSIS_GENERIC */
ebrus	0:0a673c671a56	1624
ebrus	0:0a673c671a56	1625	#ifdef __cplusplus
ebrus	0:0a673c671a56	1626	}
ebrus	0:0a673c671a56	1627	#endif

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Type:	Library
Created:	27 Jul 2016
Imports:	961
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targets/cmsis/core_cm3.h@0:0a673c671a56, 2016-07-27 (annotated)

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