Ermanno Brusadin / mbed-src

mbed library sources

targets/cmsis/core_cm0plus.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

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ebrus 0:0a673c671a56 1 /**************************************************************************//**
ebrus 0:0a673c671a56 2 * @file core_cm0plus.h
ebrus 0:0a673c671a56 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
ebrus 0:0a673c671a56 4 * @version V3.20
ebrus 0:0a673c671a56 5 * @date 25. February 2013
ebrus 0:0a673c671a56 6 *
ebrus 0:0a673c671a56 7 * @note
ebrus 0:0a673c671a56 8 *
ebrus 0:0a673c671a56 9 ******************************************************************************/
ebrus 0:0a673c671a56 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
ebrus 0:0a673c671a56 11
ebrus 0:0a673c671a56 12 All rights reserved.
ebrus 0:0a673c671a56 13 Redistribution and use in source and binary forms, with or without
ebrus 0:0a673c671a56 14 modification, are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 15 - Redistributions of source code must retain the above copyright
ebrus 0:0a673c671a56 16 notice, this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 17 - Redistributions in binary form must reproduce the above copyright
ebrus 0:0a673c671a56 18 notice, this list of conditions and the following disclaimer in the
ebrus 0:0a673c671a56 19 documentation and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 20 - Neither the name of ARM nor the names of its contributors may be used
ebrus 0:0a673c671a56 21 to endorse or promote products derived from this software without
ebrus 0:0a673c671a56 22 specific prior written permission.
ebrus 0:0a673c671a56 23 *
ebrus 0:0a673c671a56 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ebrus 0:0a673c671a56 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
ebrus 0:0a673c671a56 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
ebrus 0:0a673c671a56 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
ebrus 0:0a673c671a56 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
ebrus 0:0a673c671a56 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
ebrus 0:0a673c671a56 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ebrus 0:0a673c671a56 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
ebrus 0:0a673c671a56 34 POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 35 ---------------------------------------------------------------------------*/
ebrus 0:0a673c671a56 36
ebrus 0:0a673c671a56 37
ebrus 0:0a673c671a56 38 #if defined ( __ICCARM__ )
ebrus 0:0a673c671a56 39 #pragma system_include /* treat file as system include file for MISRA check */
ebrus 0:0a673c671a56 40 #endif
ebrus 0:0a673c671a56 41
ebrus 0:0a673c671a56 42 #ifdef __cplusplus
ebrus 0:0a673c671a56 43 extern "C" {
ebrus 0:0a673c671a56 44 #endif
ebrus 0:0a673c671a56 45
ebrus 0:0a673c671a56 46 #ifndef __CORE_CM0PLUS_H_GENERIC
ebrus 0:0a673c671a56 47 #define __CORE_CM0PLUS_H_GENERIC
ebrus 0:0a673c671a56 48
ebrus 0:0a673c671a56 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
ebrus 0:0a673c671a56 50 CMSIS violates the following MISRA-C:2004 rules:
ebrus 0:0a673c671a56 51
ebrus 0:0a673c671a56 52 \li Required Rule 8.5, object/function definition in header file.<br>
ebrus 0:0a673c671a56 53 Function definitions in header files are used to allow 'inlining'.
ebrus 0:0a673c671a56 54
ebrus 0:0a673c671a56 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
ebrus 0:0a673c671a56 56 Unions are used for effective representation of core registers.
ebrus 0:0a673c671a56 57
ebrus 0:0a673c671a56 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
ebrus 0:0a673c671a56 59 Function-like macros are used to allow more efficient code.
ebrus 0:0a673c671a56 60 */
ebrus 0:0a673c671a56 61
ebrus 0:0a673c671a56 62
ebrus 0:0a673c671a56 63 /*******************************************************************************
ebrus 0:0a673c671a56 64 * CMSIS definitions
ebrus 0:0a673c671a56 65 ******************************************************************************/
ebrus 0:0a673c671a56 66 /** \ingroup Cortex-M0+
ebrus 0:0a673c671a56 67 @{
ebrus 0:0a673c671a56 68 */
ebrus 0:0a673c671a56 69
ebrus 0:0a673c671a56 70 /* CMSIS CM0P definitions */
ebrus 0:0a673c671a56 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
ebrus 0:0a673c671a56 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
ebrus 0:0a673c671a56 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
ebrus 0:0a673c671a56 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
ebrus 0:0a673c671a56 75
ebrus 0:0a673c671a56 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
ebrus 0:0a673c671a56 77
ebrus 0:0a673c671a56 78
ebrus 0:0a673c671a56 79 #if defined ( __CC_ARM )
ebrus 0:0a673c671a56 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
ebrus 0:0a673c671a56 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
ebrus 0:0a673c671a56 82 #define __STATIC_INLINE static __inline
ebrus 0:0a673c671a56 83
ebrus 0:0a673c671a56 84 #elif defined ( __ICCARM__ )
ebrus 0:0a673c671a56 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
ebrus 0:0a673c671a56 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
ebrus 0:0a673c671a56 87 #define __STATIC_INLINE static inline
ebrus 0:0a673c671a56 88
ebrus 0:0a673c671a56 89 #elif defined ( __GNUC__ )
ebrus 0:0a673c671a56 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
ebrus 0:0a673c671a56 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
ebrus 0:0a673c671a56 92 #define __STATIC_INLINE static inline
ebrus 0:0a673c671a56 93
ebrus 0:0a673c671a56 94 #elif defined ( __TASKING__ )
ebrus 0:0a673c671a56 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
ebrus 0:0a673c671a56 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
ebrus 0:0a673c671a56 97 #define __STATIC_INLINE static inline
ebrus 0:0a673c671a56 98
ebrus 0:0a673c671a56 99 #endif
ebrus 0:0a673c671a56 100
ebrus 0:0a673c671a56 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
ebrus 0:0a673c671a56 102 */
ebrus 0:0a673c671a56 103 #define __FPU_USED 0
ebrus 0:0a673c671a56 104
ebrus 0:0a673c671a56 105 #if defined ( __CC_ARM )
ebrus 0:0a673c671a56 106 #if defined __TARGET_FPU_VFP
ebrus 0:0a673c671a56 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ebrus 0:0a673c671a56 108 #endif
ebrus 0:0a673c671a56 109
ebrus 0:0a673c671a56 110 #elif defined ( __ICCARM__ )
ebrus 0:0a673c671a56 111 #if defined __ARMVFP__
ebrus 0:0a673c671a56 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ebrus 0:0a673c671a56 113 #endif
ebrus 0:0a673c671a56 114
ebrus 0:0a673c671a56 115 #elif defined ( __GNUC__ )
ebrus 0:0a673c671a56 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
ebrus 0:0a673c671a56 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ebrus 0:0a673c671a56 118 #endif
ebrus 0:0a673c671a56 119
ebrus 0:0a673c671a56 120 #elif defined ( __TASKING__ )
ebrus 0:0a673c671a56 121 #if defined __FPU_VFP__
ebrus 0:0a673c671a56 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
ebrus 0:0a673c671a56 123 #endif
ebrus 0:0a673c671a56 124 #endif
ebrus 0:0a673c671a56 125
ebrus 0:0a673c671a56 126 #include <stdint.h> /* standard types definitions */
ebrus 0:0a673c671a56 127 #include <core_cmInstr.h> /* Core Instruction Access */
ebrus 0:0a673c671a56 128 #include <core_cmFunc.h> /* Core Function Access */
ebrus 0:0a673c671a56 129
ebrus 0:0a673c671a56 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
ebrus 0:0a673c671a56 131
ebrus 0:0a673c671a56 132 #ifndef __CMSIS_GENERIC
ebrus 0:0a673c671a56 133
ebrus 0:0a673c671a56 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
ebrus 0:0a673c671a56 135 #define __CORE_CM0PLUS_H_DEPENDANT
ebrus 0:0a673c671a56 136
ebrus 0:0a673c671a56 137 /* check device defines and use defaults */
ebrus 0:0a673c671a56 138 #if defined __CHECK_DEVICE_DEFINES
ebrus 0:0a673c671a56 139 #ifndef __CM0PLUS_REV
ebrus 0:0a673c671a56 140 #define __CM0PLUS_REV 0x0000
ebrus 0:0a673c671a56 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
ebrus 0:0a673c671a56 142 #endif
ebrus 0:0a673c671a56 143
ebrus 0:0a673c671a56 144 #ifndef __MPU_PRESENT
ebrus 0:0a673c671a56 145 #define __MPU_PRESENT 0
ebrus 0:0a673c671a56 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
ebrus 0:0a673c671a56 147 #endif
ebrus 0:0a673c671a56 148
ebrus 0:0a673c671a56 149 #ifndef __VTOR_PRESENT
ebrus 0:0a673c671a56 150 #define __VTOR_PRESENT 0
ebrus 0:0a673c671a56 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
ebrus 0:0a673c671a56 152 #endif
ebrus 0:0a673c671a56 153
ebrus 0:0a673c671a56 154 #ifndef __NVIC_PRIO_BITS
ebrus 0:0a673c671a56 155 #define __NVIC_PRIO_BITS 2
ebrus 0:0a673c671a56 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
ebrus 0:0a673c671a56 157 #endif
ebrus 0:0a673c671a56 158
ebrus 0:0a673c671a56 159 #ifndef __Vendor_SysTickConfig
ebrus 0:0a673c671a56 160 #define __Vendor_SysTickConfig 0
ebrus 0:0a673c671a56 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
ebrus 0:0a673c671a56 162 #endif
ebrus 0:0a673c671a56 163 #endif
ebrus 0:0a673c671a56 164
ebrus 0:0a673c671a56 165 /* IO definitions (access restrictions to peripheral registers) */
ebrus 0:0a673c671a56 166 /**
ebrus 0:0a673c671a56 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
ebrus 0:0a673c671a56 168
ebrus 0:0a673c671a56 169 <strong>IO Type Qualifiers</strong> are used
ebrus 0:0a673c671a56 170 \li to specify the access to peripheral variables.
ebrus 0:0a673c671a56 171 \li for automatic generation of peripheral register debug information.
ebrus 0:0a673c671a56 172 */
ebrus 0:0a673c671a56 173 #ifdef __cplusplus
ebrus 0:0a673c671a56 174 #define __I volatile /*!< Defines 'read only' permissions */
ebrus 0:0a673c671a56 175 #else
ebrus 0:0a673c671a56 176 #define __I volatile const /*!< Defines 'read only' permissions */
ebrus 0:0a673c671a56 177 #endif
ebrus 0:0a673c671a56 178 #define __O volatile /*!< Defines 'write only' permissions */
ebrus 0:0a673c671a56 179 #define __IO volatile /*!< Defines 'read / write' permissions */
ebrus 0:0a673c671a56 180
ebrus 0:0a673c671a56 181 /*@} end of group Cortex-M0+ */
ebrus 0:0a673c671a56 182
ebrus 0:0a673c671a56 183
ebrus 0:0a673c671a56 184
ebrus 0:0a673c671a56 185 /*******************************************************************************
ebrus 0:0a673c671a56 186 * Register Abstraction
ebrus 0:0a673c671a56 187 Core Register contain:
ebrus 0:0a673c671a56 188 - Core Register
ebrus 0:0a673c671a56 189 - Core NVIC Register
ebrus 0:0a673c671a56 190 - Core SCB Register
ebrus 0:0a673c671a56 191 - Core SysTick Register
ebrus 0:0a673c671a56 192 - Core MPU Register
ebrus 0:0a673c671a56 193 ******************************************************************************/
ebrus 0:0a673c671a56 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
ebrus 0:0a673c671a56 195 \brief Type definitions and defines for Cortex-M processor based devices.
ebrus 0:0a673c671a56 196 */
ebrus 0:0a673c671a56 197
ebrus 0:0a673c671a56 198 /** \ingroup CMSIS_core_register
ebrus 0:0a673c671a56 199 \defgroup CMSIS_CORE Status and Control Registers
ebrus 0:0a673c671a56 200 \brief Core Register type definitions.
ebrus 0:0a673c671a56 201 @{
ebrus 0:0a673c671a56 202 */
ebrus 0:0a673c671a56 203
ebrus 0:0a673c671a56 204 /** \brief Union type to access the Application Program Status Register (APSR).
ebrus 0:0a673c671a56 205 */
ebrus 0:0a673c671a56 206 typedef union
ebrus 0:0a673c671a56 207 {
ebrus 0:0a673c671a56 208 struct
ebrus 0:0a673c671a56 209 {
ebrus 0:0a673c671a56 210 #if (__CORTEX_M != 0x04)
ebrus 0:0a673c671a56 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
ebrus 0:0a673c671a56 212 #else
ebrus 0:0a673c671a56 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
ebrus 0:0a673c671a56 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
ebrus 0:0a673c671a56 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
ebrus 0:0a673c671a56 216 #endif
ebrus 0:0a673c671a56 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
ebrus 0:0a673c671a56 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
ebrus 0:0a673c671a56 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
ebrus 0:0a673c671a56 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
ebrus 0:0a673c671a56 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
ebrus 0:0a673c671a56 222 } b; /*!< Structure used for bit access */
ebrus 0:0a673c671a56 223 uint32_t w; /*!< Type used for word access */
ebrus 0:0a673c671a56 224 } APSR_Type;
ebrus 0:0a673c671a56 225
ebrus 0:0a673c671a56 226
ebrus 0:0a673c671a56 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
ebrus 0:0a673c671a56 228 */
ebrus 0:0a673c671a56 229 typedef union
ebrus 0:0a673c671a56 230 {
ebrus 0:0a673c671a56 231 struct
ebrus 0:0a673c671a56 232 {
ebrus 0:0a673c671a56 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
ebrus 0:0a673c671a56 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
ebrus 0:0a673c671a56 235 } b; /*!< Structure used for bit access */
ebrus 0:0a673c671a56 236 uint32_t w; /*!< Type used for word access */
ebrus 0:0a673c671a56 237 } IPSR_Type;
ebrus 0:0a673c671a56 238
ebrus 0:0a673c671a56 239
ebrus 0:0a673c671a56 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
ebrus 0:0a673c671a56 241 */
ebrus 0:0a673c671a56 242 typedef union
ebrus 0:0a673c671a56 243 {
ebrus 0:0a673c671a56 244 struct
ebrus 0:0a673c671a56 245 {
ebrus 0:0a673c671a56 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
ebrus 0:0a673c671a56 247 #if (__CORTEX_M != 0x04)
ebrus 0:0a673c671a56 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
ebrus 0:0a673c671a56 249 #else
ebrus 0:0a673c671a56 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
ebrus 0:0a673c671a56 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
ebrus 0:0a673c671a56 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
ebrus 0:0a673c671a56 253 #endif
ebrus 0:0a673c671a56 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
ebrus 0:0a673c671a56 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
ebrus 0:0a673c671a56 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
ebrus 0:0a673c671a56 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
ebrus 0:0a673c671a56 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
ebrus 0:0a673c671a56 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
ebrus 0:0a673c671a56 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
ebrus 0:0a673c671a56 261 } b; /*!< Structure used for bit access */
ebrus 0:0a673c671a56 262 uint32_t w; /*!< Type used for word access */
ebrus 0:0a673c671a56 263 } xPSR_Type;
ebrus 0:0a673c671a56 264
ebrus 0:0a673c671a56 265
ebrus 0:0a673c671a56 266 /** \brief Union type to access the Control Registers (CONTROL).
ebrus 0:0a673c671a56 267 */
ebrus 0:0a673c671a56 268 typedef union
ebrus 0:0a673c671a56 269 {
ebrus 0:0a673c671a56 270 struct
ebrus 0:0a673c671a56 271 {
ebrus 0:0a673c671a56 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
ebrus 0:0a673c671a56 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
ebrus 0:0a673c671a56 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
ebrus 0:0a673c671a56 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
ebrus 0:0a673c671a56 276 } b; /*!< Structure used for bit access */
ebrus 0:0a673c671a56 277 uint32_t w; /*!< Type used for word access */
ebrus 0:0a673c671a56 278 } CONTROL_Type;
ebrus 0:0a673c671a56 279
ebrus 0:0a673c671a56 280 /*@} end of group CMSIS_CORE */
ebrus 0:0a673c671a56 281
ebrus 0:0a673c671a56 282
ebrus 0:0a673c671a56 283 /** \ingroup CMSIS_core_register
ebrus 0:0a673c671a56 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
ebrus 0:0a673c671a56 285 \brief Type definitions for the NVIC Registers
ebrus 0:0a673c671a56 286 @{
ebrus 0:0a673c671a56 287 */
ebrus 0:0a673c671a56 288
ebrus 0:0a673c671a56 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
ebrus 0:0a673c671a56 290 */
ebrus 0:0a673c671a56 291 typedef struct
ebrus 0:0a673c671a56 292 {
ebrus 0:0a673c671a56 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
ebrus 0:0a673c671a56 294 uint32_t RESERVED0[31];
ebrus 0:0a673c671a56 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
ebrus 0:0a673c671a56 296 uint32_t RSERVED1[31];
ebrus 0:0a673c671a56 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
ebrus 0:0a673c671a56 298 uint32_t RESERVED2[31];
ebrus 0:0a673c671a56 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
ebrus 0:0a673c671a56 300 uint32_t RESERVED3[31];
ebrus 0:0a673c671a56 301 uint32_t RESERVED4[64];
ebrus 0:0a673c671a56 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
ebrus 0:0a673c671a56 303 } NVIC_Type;
ebrus 0:0a673c671a56 304
ebrus 0:0a673c671a56 305 /*@} end of group CMSIS_NVIC */
ebrus 0:0a673c671a56 306
ebrus 0:0a673c671a56 307
ebrus 0:0a673c671a56 308 /** \ingroup CMSIS_core_register
ebrus 0:0a673c671a56 309 \defgroup CMSIS_SCB System Control Block (SCB)
ebrus 0:0a673c671a56 310 \brief Type definitions for the System Control Block Registers
ebrus 0:0a673c671a56 311 @{
ebrus 0:0a673c671a56 312 */
ebrus 0:0a673c671a56 313
ebrus 0:0a673c671a56 314 /** \brief Structure type to access the System Control Block (SCB).
ebrus 0:0a673c671a56 315 */
ebrus 0:0a673c671a56 316 typedef struct
ebrus 0:0a673c671a56 317 {
ebrus 0:0a673c671a56 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
ebrus 0:0a673c671a56 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
ebrus 0:0a673c671a56 320 #if (__VTOR_PRESENT == 1)
ebrus 0:0a673c671a56 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
ebrus 0:0a673c671a56 322 #else
ebrus 0:0a673c671a56 323 uint32_t RESERVED0;
ebrus 0:0a673c671a56 324 #endif
ebrus 0:0a673c671a56 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
ebrus 0:0a673c671a56 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
ebrus 0:0a673c671a56 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
ebrus 0:0a673c671a56 328 uint32_t RESERVED1;
ebrus 0:0a673c671a56 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
ebrus 0:0a673c671a56 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
ebrus 0:0a673c671a56 331 } SCB_Type;
ebrus 0:0a673c671a56 332
ebrus 0:0a673c671a56 333 /* SCB CPUID Register Definitions */
ebrus 0:0a673c671a56 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
ebrus 0:0a673c671a56 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
ebrus 0:0a673c671a56 336
ebrus 0:0a673c671a56 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
ebrus 0:0a673c671a56 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
ebrus 0:0a673c671a56 339
ebrus 0:0a673c671a56 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
ebrus 0:0a673c671a56 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
ebrus 0:0a673c671a56 342
ebrus 0:0a673c671a56 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
ebrus 0:0a673c671a56 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
ebrus 0:0a673c671a56 345
ebrus 0:0a673c671a56 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
ebrus 0:0a673c671a56 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
ebrus 0:0a673c671a56 348
ebrus 0:0a673c671a56 349 /* SCB Interrupt Control State Register Definitions */
ebrus 0:0a673c671a56 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
ebrus 0:0a673c671a56 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
ebrus 0:0a673c671a56 352
ebrus 0:0a673c671a56 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
ebrus 0:0a673c671a56 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
ebrus 0:0a673c671a56 355
ebrus 0:0a673c671a56 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
ebrus 0:0a673c671a56 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
ebrus 0:0a673c671a56 358
ebrus 0:0a673c671a56 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
ebrus 0:0a673c671a56 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
ebrus 0:0a673c671a56 361
ebrus 0:0a673c671a56 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
ebrus 0:0a673c671a56 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
ebrus 0:0a673c671a56 364
ebrus 0:0a673c671a56 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
ebrus 0:0a673c671a56 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
ebrus 0:0a673c671a56 367
ebrus 0:0a673c671a56 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
ebrus 0:0a673c671a56 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
ebrus 0:0a673c671a56 370
ebrus 0:0a673c671a56 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
ebrus 0:0a673c671a56 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
ebrus 0:0a673c671a56 373
ebrus 0:0a673c671a56 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
ebrus 0:0a673c671a56 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
ebrus 0:0a673c671a56 376
ebrus 0:0a673c671a56 377 #if (__VTOR_PRESENT == 1)
ebrus 0:0a673c671a56 378 /* SCB Interrupt Control State Register Definitions */
ebrus 0:0a673c671a56 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
ebrus 0:0a673c671a56 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
ebrus 0:0a673c671a56 381 #endif
ebrus 0:0a673c671a56 382
ebrus 0:0a673c671a56 383 /* SCB Application Interrupt and Reset Control Register Definitions */
ebrus 0:0a673c671a56 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
ebrus 0:0a673c671a56 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
ebrus 0:0a673c671a56 386
ebrus 0:0a673c671a56 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
ebrus 0:0a673c671a56 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
ebrus 0:0a673c671a56 389
ebrus 0:0a673c671a56 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
ebrus 0:0a673c671a56 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
ebrus 0:0a673c671a56 392
ebrus 0:0a673c671a56 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
ebrus 0:0a673c671a56 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
ebrus 0:0a673c671a56 395
ebrus 0:0a673c671a56 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
ebrus 0:0a673c671a56 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
ebrus 0:0a673c671a56 398
ebrus 0:0a673c671a56 399 /* SCB System Control Register Definitions */
ebrus 0:0a673c671a56 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
ebrus 0:0a673c671a56 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
ebrus 0:0a673c671a56 402
ebrus 0:0a673c671a56 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
ebrus 0:0a673c671a56 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
ebrus 0:0a673c671a56 405
ebrus 0:0a673c671a56 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
ebrus 0:0a673c671a56 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
ebrus 0:0a673c671a56 408
ebrus 0:0a673c671a56 409 /* SCB Configuration Control Register Definitions */
ebrus 0:0a673c671a56 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
ebrus 0:0a673c671a56 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
ebrus 0:0a673c671a56 412
ebrus 0:0a673c671a56 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
ebrus 0:0a673c671a56 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
ebrus 0:0a673c671a56 415
ebrus 0:0a673c671a56 416 /* SCB System Handler Control and State Register Definitions */
ebrus 0:0a673c671a56 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
ebrus 0:0a673c671a56 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
ebrus 0:0a673c671a56 419
ebrus 0:0a673c671a56 420 /*@} end of group CMSIS_SCB */
ebrus 0:0a673c671a56 421
ebrus 0:0a673c671a56 422
ebrus 0:0a673c671a56 423 /** \ingroup CMSIS_core_register
ebrus 0:0a673c671a56 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
ebrus 0:0a673c671a56 425 \brief Type definitions for the System Timer Registers.
ebrus 0:0a673c671a56 426 @{
ebrus 0:0a673c671a56 427 */
ebrus 0:0a673c671a56 428
ebrus 0:0a673c671a56 429 /** \brief Structure type to access the System Timer (SysTick).
ebrus 0:0a673c671a56 430 */
ebrus 0:0a673c671a56 431 typedef struct
ebrus 0:0a673c671a56 432 {
ebrus 0:0a673c671a56 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
ebrus 0:0a673c671a56 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
ebrus 0:0a673c671a56 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
ebrus 0:0a673c671a56 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
ebrus 0:0a673c671a56 437 } SysTick_Type;
ebrus 0:0a673c671a56 438
ebrus 0:0a673c671a56 439 /* SysTick Control / Status Register Definitions */
ebrus 0:0a673c671a56 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
ebrus 0:0a673c671a56 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
ebrus 0:0a673c671a56 442
ebrus 0:0a673c671a56 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
ebrus 0:0a673c671a56 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
ebrus 0:0a673c671a56 445
ebrus 0:0a673c671a56 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
ebrus 0:0a673c671a56 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
ebrus 0:0a673c671a56 448
ebrus 0:0a673c671a56 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
ebrus 0:0a673c671a56 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
ebrus 0:0a673c671a56 451
ebrus 0:0a673c671a56 452 /* SysTick Reload Register Definitions */
ebrus 0:0a673c671a56 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
ebrus 0:0a673c671a56 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
ebrus 0:0a673c671a56 455
ebrus 0:0a673c671a56 456 /* SysTick Current Register Definitions */
ebrus 0:0a673c671a56 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
ebrus 0:0a673c671a56 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
ebrus 0:0a673c671a56 459
ebrus 0:0a673c671a56 460 /* SysTick Calibration Register Definitions */
ebrus 0:0a673c671a56 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
ebrus 0:0a673c671a56 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
ebrus 0:0a673c671a56 463
ebrus 0:0a673c671a56 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
ebrus 0:0a673c671a56 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
ebrus 0:0a673c671a56 466
ebrus 0:0a673c671a56 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
ebrus 0:0a673c671a56 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
ebrus 0:0a673c671a56 469
ebrus 0:0a673c671a56 470 /*@} end of group CMSIS_SysTick */
ebrus 0:0a673c671a56 471
ebrus 0:0a673c671a56 472 #if (__MPU_PRESENT == 1)
ebrus 0:0a673c671a56 473 /** \ingroup CMSIS_core_register
ebrus 0:0a673c671a56 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
ebrus 0:0a673c671a56 475 \brief Type definitions for the Memory Protection Unit (MPU)
ebrus 0:0a673c671a56 476 @{
ebrus 0:0a673c671a56 477 */
ebrus 0:0a673c671a56 478
ebrus 0:0a673c671a56 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
ebrus 0:0a673c671a56 480 */
ebrus 0:0a673c671a56 481 typedef struct
ebrus 0:0a673c671a56 482 {
ebrus 0:0a673c671a56 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
ebrus 0:0a673c671a56 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
ebrus 0:0a673c671a56 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
ebrus 0:0a673c671a56 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
ebrus 0:0a673c671a56 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
ebrus 0:0a673c671a56 488 } MPU_Type;
ebrus 0:0a673c671a56 489
ebrus 0:0a673c671a56 490 /* MPU Type Register */
ebrus 0:0a673c671a56 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
ebrus 0:0a673c671a56 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
ebrus 0:0a673c671a56 493
ebrus 0:0a673c671a56 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
ebrus 0:0a673c671a56 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
ebrus 0:0a673c671a56 496
ebrus 0:0a673c671a56 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
ebrus 0:0a673c671a56 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
ebrus 0:0a673c671a56 499
ebrus 0:0a673c671a56 500 /* MPU Control Register */
ebrus 0:0a673c671a56 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
ebrus 0:0a673c671a56 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
ebrus 0:0a673c671a56 503
ebrus 0:0a673c671a56 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
ebrus 0:0a673c671a56 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
ebrus 0:0a673c671a56 506
ebrus 0:0a673c671a56 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
ebrus 0:0a673c671a56 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
ebrus 0:0a673c671a56 509
ebrus 0:0a673c671a56 510 /* MPU Region Number Register */
ebrus 0:0a673c671a56 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
ebrus 0:0a673c671a56 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
ebrus 0:0a673c671a56 513
ebrus 0:0a673c671a56 514 /* MPU Region Base Address Register */
ebrus 0:0a673c671a56 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
ebrus 0:0a673c671a56 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
ebrus 0:0a673c671a56 517
ebrus 0:0a673c671a56 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
ebrus 0:0a673c671a56 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
ebrus 0:0a673c671a56 520
ebrus 0:0a673c671a56 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
ebrus 0:0a673c671a56 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
ebrus 0:0a673c671a56 523
ebrus 0:0a673c671a56 524 /* MPU Region Attribute and Size Register */
ebrus 0:0a673c671a56 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
ebrus 0:0a673c671a56 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
ebrus 0:0a673c671a56 527
ebrus 0:0a673c671a56 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
ebrus 0:0a673c671a56 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
ebrus 0:0a673c671a56 530
ebrus 0:0a673c671a56 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
ebrus 0:0a673c671a56 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
ebrus 0:0a673c671a56 533
ebrus 0:0a673c671a56 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
ebrus 0:0a673c671a56 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
ebrus 0:0a673c671a56 536
ebrus 0:0a673c671a56 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
ebrus 0:0a673c671a56 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
ebrus 0:0a673c671a56 539
ebrus 0:0a673c671a56 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
ebrus 0:0a673c671a56 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
ebrus 0:0a673c671a56 542
ebrus 0:0a673c671a56 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
ebrus 0:0a673c671a56 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
ebrus 0:0a673c671a56 545
ebrus 0:0a673c671a56 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
ebrus 0:0a673c671a56 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
ebrus 0:0a673c671a56 548
ebrus 0:0a673c671a56 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
ebrus 0:0a673c671a56 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
ebrus 0:0a673c671a56 551
ebrus 0:0a673c671a56 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
ebrus 0:0a673c671a56 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
ebrus 0:0a673c671a56 554
ebrus 0:0a673c671a56 555 /*@} end of group CMSIS_MPU */
ebrus 0:0a673c671a56 556 #endif
ebrus 0:0a673c671a56 557
ebrus 0:0a673c671a56 558
ebrus 0:0a673c671a56 559 /** \ingroup CMSIS_core_register
ebrus 0:0a673c671a56 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
ebrus 0:0a673c671a56 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
ebrus 0:0a673c671a56 562 are only accessible over DAP and not via processor. Therefore
ebrus 0:0a673c671a56 563 they are not covered by the Cortex-M0 header file.
ebrus 0:0a673c671a56 564 @{
ebrus 0:0a673c671a56 565 */
ebrus 0:0a673c671a56 566 /*@} end of group CMSIS_CoreDebug */
ebrus 0:0a673c671a56 567
ebrus 0:0a673c671a56 568
ebrus 0:0a673c671a56 569 /** \ingroup CMSIS_core_register
ebrus 0:0a673c671a56 570 \defgroup CMSIS_core_base Core Definitions
ebrus 0:0a673c671a56 571 \brief Definitions for base addresses, unions, and structures.
ebrus 0:0a673c671a56 572 @{
ebrus 0:0a673c671a56 573 */
ebrus 0:0a673c671a56 574
ebrus 0:0a673c671a56 575 /* Memory mapping of Cortex-M0+ Hardware */
ebrus 0:0a673c671a56 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
ebrus 0:0a673c671a56 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
ebrus 0:0a673c671a56 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
ebrus 0:0a673c671a56 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
ebrus 0:0a673c671a56 580
ebrus 0:0a673c671a56 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
ebrus 0:0a673c671a56 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
ebrus 0:0a673c671a56 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
ebrus 0:0a673c671a56 584
ebrus 0:0a673c671a56 585 #if (__MPU_PRESENT == 1)
ebrus 0:0a673c671a56 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
ebrus 0:0a673c671a56 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
ebrus 0:0a673c671a56 588 #endif
ebrus 0:0a673c671a56 589
ebrus 0:0a673c671a56 590 /*@} */
ebrus 0:0a673c671a56 591
ebrus 0:0a673c671a56 592
ebrus 0:0a673c671a56 593
ebrus 0:0a673c671a56 594 /*******************************************************************************
ebrus 0:0a673c671a56 595 * Hardware Abstraction Layer
ebrus 0:0a673c671a56 596 Core Function Interface contains:
ebrus 0:0a673c671a56 597 - Core NVIC Functions
ebrus 0:0a673c671a56 598 - Core SysTick Functions
ebrus 0:0a673c671a56 599 - Core Register Access Functions
ebrus 0:0a673c671a56 600 ******************************************************************************/
ebrus 0:0a673c671a56 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
ebrus 0:0a673c671a56 602 */
ebrus 0:0a673c671a56 603
ebrus 0:0a673c671a56 604
ebrus 0:0a673c671a56 605
ebrus 0:0a673c671a56 606 /* ########################## NVIC functions #################################### */
ebrus 0:0a673c671a56 607 /** \ingroup CMSIS_Core_FunctionInterface
ebrus 0:0a673c671a56 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
ebrus 0:0a673c671a56 609 \brief Functions that manage interrupts and exceptions via the NVIC.
ebrus 0:0a673c671a56 610 @{
ebrus 0:0a673c671a56 611 */
ebrus 0:0a673c671a56 612
ebrus 0:0a673c671a56 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
ebrus 0:0a673c671a56 614 /* The following MACROS handle generation of the register offset and byte masks */
ebrus 0:0a673c671a56 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
ebrus 0:0a673c671a56 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
ebrus 0:0a673c671a56 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
ebrus 0:0a673c671a56 618
ebrus 0:0a673c671a56 619
ebrus 0:0a673c671a56 620 /** \brief Enable External Interrupt
ebrus 0:0a673c671a56 621
ebrus 0:0a673c671a56 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
ebrus 0:0a673c671a56 623
ebrus 0:0a673c671a56 624 \param [in] IRQn External interrupt number. Value cannot be negative.
ebrus 0:0a673c671a56 625 */
ebrus 0:0a673c671a56 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
ebrus 0:0a673c671a56 627 {
ebrus 0:0a673c671a56 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
ebrus 0:0a673c671a56 629 }
ebrus 0:0a673c671a56 630
ebrus 0:0a673c671a56 631
ebrus 0:0a673c671a56 632 /** \brief Disable External Interrupt
ebrus 0:0a673c671a56 633
ebrus 0:0a673c671a56 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
ebrus 0:0a673c671a56 635
ebrus 0:0a673c671a56 636 \param [in] IRQn External interrupt number. Value cannot be negative.
ebrus 0:0a673c671a56 637 */
ebrus 0:0a673c671a56 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
ebrus 0:0a673c671a56 639 {
ebrus 0:0a673c671a56 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
ebrus 0:0a673c671a56 641 }
ebrus 0:0a673c671a56 642
ebrus 0:0a673c671a56 643
ebrus 0:0a673c671a56 644 /** \brief Get Pending Interrupt
ebrus 0:0a673c671a56 645
ebrus 0:0a673c671a56 646 The function reads the pending register in the NVIC and returns the pending bit
ebrus 0:0a673c671a56 647 for the specified interrupt.
ebrus 0:0a673c671a56 648
ebrus 0:0a673c671a56 649 \param [in] IRQn Interrupt number.
ebrus 0:0a673c671a56 650
ebrus 0:0a673c671a56 651 \return 0 Interrupt status is not pending.
ebrus 0:0a673c671a56 652 \return 1 Interrupt status is pending.
ebrus 0:0a673c671a56 653 */
ebrus 0:0a673c671a56 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
ebrus 0:0a673c671a56 655 {
ebrus 0:0a673c671a56 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
ebrus 0:0a673c671a56 657 }
ebrus 0:0a673c671a56 658
ebrus 0:0a673c671a56 659
ebrus 0:0a673c671a56 660 /** \brief Set Pending Interrupt
ebrus 0:0a673c671a56 661
ebrus 0:0a673c671a56 662 The function sets the pending bit of an external interrupt.
ebrus 0:0a673c671a56 663
ebrus 0:0a673c671a56 664 \param [in] IRQn Interrupt number. Value cannot be negative.
ebrus 0:0a673c671a56 665 */
ebrus 0:0a673c671a56 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
ebrus 0:0a673c671a56 667 {
ebrus 0:0a673c671a56 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
ebrus 0:0a673c671a56 669 }
ebrus 0:0a673c671a56 670
ebrus 0:0a673c671a56 671
ebrus 0:0a673c671a56 672 /** \brief Clear Pending Interrupt
ebrus 0:0a673c671a56 673
ebrus 0:0a673c671a56 674 The function clears the pending bit of an external interrupt.
ebrus 0:0a673c671a56 675
ebrus 0:0a673c671a56 676 \param [in] IRQn External interrupt number. Value cannot be negative.
ebrus 0:0a673c671a56 677 */
ebrus 0:0a673c671a56 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
ebrus 0:0a673c671a56 679 {
ebrus 0:0a673c671a56 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
ebrus 0:0a673c671a56 681 }
ebrus 0:0a673c671a56 682
ebrus 0:0a673c671a56 683
ebrus 0:0a673c671a56 684 /** \brief Set Interrupt Priority
ebrus 0:0a673c671a56 685
ebrus 0:0a673c671a56 686 The function sets the priority of an interrupt.
ebrus 0:0a673c671a56 687
ebrus 0:0a673c671a56 688 \note The priority cannot be set for every core interrupt.
ebrus 0:0a673c671a56 689
ebrus 0:0a673c671a56 690 \param [in] IRQn Interrupt number.
ebrus 0:0a673c671a56 691 \param [in] priority Priority to set.
ebrus 0:0a673c671a56 692 */
ebrus 0:0a673c671a56 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
ebrus 0:0a673c671a56 694 {
ebrus 0:0a673c671a56 695 if(IRQn < 0) {
ebrus 0:0a673c671a56 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
ebrus 0:0a673c671a56 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
ebrus 0:0a673c671a56 698 else {
ebrus 0:0a673c671a56 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
ebrus 0:0a673c671a56 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
ebrus 0:0a673c671a56 701 }
ebrus 0:0a673c671a56 702
ebrus 0:0a673c671a56 703
ebrus 0:0a673c671a56 704 /** \brief Get Interrupt Priority
ebrus 0:0a673c671a56 705
ebrus 0:0a673c671a56 706 The function reads the priority of an interrupt. The interrupt
ebrus 0:0a673c671a56 707 number can be positive to specify an external (device specific)
ebrus 0:0a673c671a56 708 interrupt, or negative to specify an internal (core) interrupt.
ebrus 0:0a673c671a56 709
ebrus 0:0a673c671a56 710
ebrus 0:0a673c671a56 711 \param [in] IRQn Interrupt number.
ebrus 0:0a673c671a56 712 \return Interrupt Priority. Value is aligned automatically to the implemented
ebrus 0:0a673c671a56 713 priority bits of the microcontroller.
ebrus 0:0a673c671a56 714 */
ebrus 0:0a673c671a56 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
ebrus 0:0a673c671a56 716 {
ebrus 0:0a673c671a56 717
ebrus 0:0a673c671a56 718 if(IRQn < 0) {
ebrus 0:0a673c671a56 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
ebrus 0:0a673c671a56 720 else {
ebrus 0:0a673c671a56 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
ebrus 0:0a673c671a56 722 }
ebrus 0:0a673c671a56 723
ebrus 0:0a673c671a56 724
ebrus 0:0a673c671a56 725 /** \brief System Reset
ebrus 0:0a673c671a56 726
ebrus 0:0a673c671a56 727 The function initiates a system reset request to reset the MCU.
ebrus 0:0a673c671a56 728 */
ebrus 0:0a673c671a56 729 __STATIC_INLINE void NVIC_SystemReset(void)
ebrus 0:0a673c671a56 730 {
ebrus 0:0a673c671a56 731 __DSB(); /* Ensure all outstanding memory accesses included
ebrus 0:0a673c671a56 732 buffered write are completed before reset */
ebrus 0:0a673c671a56 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
ebrus 0:0a673c671a56 734 SCB_AIRCR_SYSRESETREQ_Msk);
ebrus 0:0a673c671a56 735 __DSB(); /* Ensure completion of memory access */
ebrus 0:0a673c671a56 736 while(1); /* wait until reset */
ebrus 0:0a673c671a56 737 }
ebrus 0:0a673c671a56 738
ebrus 0:0a673c671a56 739 /*@} end of CMSIS_Core_NVICFunctions */
ebrus 0:0a673c671a56 740
ebrus 0:0a673c671a56 741
ebrus 0:0a673c671a56 742
ebrus 0:0a673c671a56 743 /* ################################## SysTick function ############################################ */
ebrus 0:0a673c671a56 744 /** \ingroup CMSIS_Core_FunctionInterface
ebrus 0:0a673c671a56 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
ebrus 0:0a673c671a56 746 \brief Functions that configure the System.
ebrus 0:0a673c671a56 747 @{
ebrus 0:0a673c671a56 748 */
ebrus 0:0a673c671a56 749
ebrus 0:0a673c671a56 750 #if (__Vendor_SysTickConfig == 0)
ebrus 0:0a673c671a56 751
ebrus 0:0a673c671a56 752 /** \brief System Tick Configuration
ebrus 0:0a673c671a56 753
ebrus 0:0a673c671a56 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
ebrus 0:0a673c671a56 755 Counter is in free running mode to generate periodic interrupts.
ebrus 0:0a673c671a56 756
ebrus 0:0a673c671a56 757 \param [in] ticks Number of ticks between two interrupts.
ebrus 0:0a673c671a56 758
ebrus 0:0a673c671a56 759 \return 0 Function succeeded.
ebrus 0:0a673c671a56 760 \return 1 Function failed.
ebrus 0:0a673c671a56 761
ebrus 0:0a673c671a56 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
ebrus 0:0a673c671a56 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
ebrus 0:0a673c671a56 764 must contain a vendor-specific implementation of this function.
ebrus 0:0a673c671a56 765
ebrus 0:0a673c671a56 766 */
ebrus 0:0a673c671a56 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
ebrus 0:0a673c671a56 768 {
ebrus 0:0a673c671a56 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
ebrus 0:0a673c671a56 770
ebrus 0:0a673c671a56 771 SysTick->LOAD = ticks - 1; /* set reload register */
ebrus 0:0a673c671a56 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
ebrus 0:0a673c671a56 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
ebrus 0:0a673c671a56 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
ebrus 0:0a673c671a56 775 SysTick_CTRL_TICKINT_Msk |
ebrus 0:0a673c671a56 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
ebrus 0:0a673c671a56 777 return (0); /* Function successful */
ebrus 0:0a673c671a56 778 }
ebrus 0:0a673c671a56 779
ebrus 0:0a673c671a56 780 #endif
ebrus 0:0a673c671a56 781
ebrus 0:0a673c671a56 782 /*@} end of CMSIS_Core_SysTickFunctions */
ebrus 0:0a673c671a56 783
ebrus 0:0a673c671a56 784
ebrus 0:0a673c671a56 785
ebrus 0:0a673c671a56 786
ebrus 0:0a673c671a56 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
ebrus 0:0a673c671a56 788
ebrus 0:0a673c671a56 789 #endif /* __CMSIS_GENERIC */
ebrus 0:0a673c671a56 790
ebrus 0:0a673c671a56 791 #ifdef __cplusplus
ebrus 0:0a673c671a56 792 }
ebrus 0:0a673c671a56 793 #endif