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targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_gpio.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32f10x_gpio.h
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V3.6.1
ebrus 0:0a673c671a56 6 * @date 05-March-2012
ebrus 0:0a673c671a56 7 * @brief This file contains all the functions prototypes for the GPIO
ebrus 0:0a673c671a56 8 * firmware library.
ebrus 0:0a673c671a56 9 *******************************************************************************
ebrus 0:0a673c671a56 10 * Copyright (c) 2014, STMicroelectronics
ebrus 0:0a673c671a56 11 * All rights reserved.
ebrus 0:0a673c671a56 12 *
ebrus 0:0a673c671a56 13 * Redistribution and use in source and binary forms, with or without
ebrus 0:0a673c671a56 14 * modification, are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 15 *
ebrus 0:0a673c671a56 16 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 17 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 19 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 20 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 22 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 23 * without specific prior written permission.
ebrus 0:0a673c671a56 24 *
ebrus 0:0a673c671a56 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 35 *******************************************************************************
ebrus 0:0a673c671a56 36 */
ebrus 0:0a673c671a56 37
ebrus 0:0a673c671a56 38 /* Define to prevent recursive inclusion -------------------------------------*/
ebrus 0:0a673c671a56 39 #ifndef __STM32F10x_GPIO_H
ebrus 0:0a673c671a56 40 #define __STM32F10x_GPIO_H
ebrus 0:0a673c671a56 41
ebrus 0:0a673c671a56 42 #ifdef __cplusplus
ebrus 0:0a673c671a56 43 extern "C" {
ebrus 0:0a673c671a56 44 #endif
ebrus 0:0a673c671a56 45
ebrus 0:0a673c671a56 46 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 47 #include "stm32f10x.h"
ebrus 0:0a673c671a56 48
ebrus 0:0a673c671a56 49 /** @addtogroup STM32F10x_StdPeriph_Driver
ebrus 0:0a673c671a56 50 * @{
ebrus 0:0a673c671a56 51 */
ebrus 0:0a673c671a56 52
ebrus 0:0a673c671a56 53 /** @addtogroup GPIO
ebrus 0:0a673c671a56 54 * @{
ebrus 0:0a673c671a56 55 */
ebrus 0:0a673c671a56 56
ebrus 0:0a673c671a56 57 /** @defgroup GPIO_Exported_Types
ebrus 0:0a673c671a56 58 * @{
ebrus 0:0a673c671a56 59 */
ebrus 0:0a673c671a56 60
ebrus 0:0a673c671a56 61 #define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
ebrus 0:0a673c671a56 62 ((PERIPH) == GPIOB) || \
ebrus 0:0a673c671a56 63 ((PERIPH) == GPIOC) || \
ebrus 0:0a673c671a56 64 ((PERIPH) == GPIOD) || \
ebrus 0:0a673c671a56 65 ((PERIPH) == GPIOE) || \
ebrus 0:0a673c671a56 66 ((PERIPH) == GPIOF) || \
ebrus 0:0a673c671a56 67 ((PERIPH) == GPIOG))
ebrus 0:0a673c671a56 68
ebrus 0:0a673c671a56 69 /**
ebrus 0:0a673c671a56 70 * @brief Output Maximum frequency selection
ebrus 0:0a673c671a56 71 */
ebrus 0:0a673c671a56 72
ebrus 0:0a673c671a56 73 typedef enum
ebrus 0:0a673c671a56 74 {
ebrus 0:0a673c671a56 75 GPIO_Speed_10MHz = 1,
ebrus 0:0a673c671a56 76 GPIO_Speed_2MHz,
ebrus 0:0a673c671a56 77 GPIO_Speed_50MHz
ebrus 0:0a673c671a56 78 }GPIOSpeed_TypeDef;
ebrus 0:0a673c671a56 79 #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
ebrus 0:0a673c671a56 80 ((SPEED) == GPIO_Speed_50MHz))
ebrus 0:0a673c671a56 81
ebrus 0:0a673c671a56 82 /**
ebrus 0:0a673c671a56 83 * @brief Configuration Mode enumeration
ebrus 0:0a673c671a56 84 */
ebrus 0:0a673c671a56 85
ebrus 0:0a673c671a56 86 typedef enum
ebrus 0:0a673c671a56 87 { GPIO_Mode_AIN = 0x0,
ebrus 0:0a673c671a56 88 GPIO_Mode_IN_FLOATING = 0x04,
ebrus 0:0a673c671a56 89 GPIO_Mode_IPD = 0x28,
ebrus 0:0a673c671a56 90 GPIO_Mode_IPU = 0x48,
ebrus 0:0a673c671a56 91 GPIO_Mode_Out_OD = 0x14,
ebrus 0:0a673c671a56 92 GPIO_Mode_Out_PP = 0x10,
ebrus 0:0a673c671a56 93 GPIO_Mode_AF_OD = 0x1C,
ebrus 0:0a673c671a56 94 GPIO_Mode_AF_PP = 0x18
ebrus 0:0a673c671a56 95 }GPIOMode_TypeDef;
ebrus 0:0a673c671a56 96
ebrus 0:0a673c671a56 97 #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
ebrus 0:0a673c671a56 98 ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
ebrus 0:0a673c671a56 99 ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
ebrus 0:0a673c671a56 100 ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
ebrus 0:0a673c671a56 101
ebrus 0:0a673c671a56 102 /**
ebrus 0:0a673c671a56 103 * @brief GPIO Init structure definition
ebrus 0:0a673c671a56 104 */
ebrus 0:0a673c671a56 105
ebrus 0:0a673c671a56 106 typedef struct
ebrus 0:0a673c671a56 107 {
ebrus 0:0a673c671a56 108 uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
ebrus 0:0a673c671a56 109 This parameter can be any value of @ref GPIO_pins_define */
ebrus 0:0a673c671a56 110
ebrus 0:0a673c671a56 111 GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
ebrus 0:0a673c671a56 112 This parameter can be a value of @ref GPIOSpeed_TypeDef */
ebrus 0:0a673c671a56 113
ebrus 0:0a673c671a56 114 GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
ebrus 0:0a673c671a56 115 This parameter can be a value of @ref GPIOMode_TypeDef */
ebrus 0:0a673c671a56 116 }GPIO_InitTypeDef;
ebrus 0:0a673c671a56 117
ebrus 0:0a673c671a56 118
ebrus 0:0a673c671a56 119 /**
ebrus 0:0a673c671a56 120 * @brief Bit_SET and Bit_RESET enumeration
ebrus 0:0a673c671a56 121 */
ebrus 0:0a673c671a56 122
ebrus 0:0a673c671a56 123 typedef enum
ebrus 0:0a673c671a56 124 { Bit_RESET = 0,
ebrus 0:0a673c671a56 125 Bit_SET
ebrus 0:0a673c671a56 126 }BitAction;
ebrus 0:0a673c671a56 127
ebrus 0:0a673c671a56 128 #define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
ebrus 0:0a673c671a56 129
ebrus 0:0a673c671a56 130 /**
ebrus 0:0a673c671a56 131 * @}
ebrus 0:0a673c671a56 132 */
ebrus 0:0a673c671a56 133
ebrus 0:0a673c671a56 134 /** @defgroup GPIO_Exported_Constants
ebrus 0:0a673c671a56 135 * @{
ebrus 0:0a673c671a56 136 */
ebrus 0:0a673c671a56 137
ebrus 0:0a673c671a56 138 /** @defgroup GPIO_pins_define
ebrus 0:0a673c671a56 139 * @{
ebrus 0:0a673c671a56 140 */
ebrus 0:0a673c671a56 141
ebrus 0:0a673c671a56 142 #define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
ebrus 0:0a673c671a56 143 #define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
ebrus 0:0a673c671a56 144 #define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
ebrus 0:0a673c671a56 145 #define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
ebrus 0:0a673c671a56 146 #define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
ebrus 0:0a673c671a56 147 #define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
ebrus 0:0a673c671a56 148 #define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
ebrus 0:0a673c671a56 149 #define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
ebrus 0:0a673c671a56 150 #define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
ebrus 0:0a673c671a56 151 #define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
ebrus 0:0a673c671a56 152 #define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
ebrus 0:0a673c671a56 153 #define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
ebrus 0:0a673c671a56 154 #define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
ebrus 0:0a673c671a56 155 #define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
ebrus 0:0a673c671a56 156 #define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
ebrus 0:0a673c671a56 157 #define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
ebrus 0:0a673c671a56 158 #define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
ebrus 0:0a673c671a56 159
ebrus 0:0a673c671a56 160 #define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
ebrus 0:0a673c671a56 161
ebrus 0:0a673c671a56 162 #define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
ebrus 0:0a673c671a56 163 ((PIN) == GPIO_Pin_1) || \
ebrus 0:0a673c671a56 164 ((PIN) == GPIO_Pin_2) || \
ebrus 0:0a673c671a56 165 ((PIN) == GPIO_Pin_3) || \
ebrus 0:0a673c671a56 166 ((PIN) == GPIO_Pin_4) || \
ebrus 0:0a673c671a56 167 ((PIN) == GPIO_Pin_5) || \
ebrus 0:0a673c671a56 168 ((PIN) == GPIO_Pin_6) || \
ebrus 0:0a673c671a56 169 ((PIN) == GPIO_Pin_7) || \
ebrus 0:0a673c671a56 170 ((PIN) == GPIO_Pin_8) || \
ebrus 0:0a673c671a56 171 ((PIN) == GPIO_Pin_9) || \
ebrus 0:0a673c671a56 172 ((PIN) == GPIO_Pin_10) || \
ebrus 0:0a673c671a56 173 ((PIN) == GPIO_Pin_11) || \
ebrus 0:0a673c671a56 174 ((PIN) == GPIO_Pin_12) || \
ebrus 0:0a673c671a56 175 ((PIN) == GPIO_Pin_13) || \
ebrus 0:0a673c671a56 176 ((PIN) == GPIO_Pin_14) || \
ebrus 0:0a673c671a56 177 ((PIN) == GPIO_Pin_15))
ebrus 0:0a673c671a56 178
ebrus 0:0a673c671a56 179 /**
ebrus 0:0a673c671a56 180 * @}
ebrus 0:0a673c671a56 181 */
ebrus 0:0a673c671a56 182
ebrus 0:0a673c671a56 183 /** @defgroup GPIO_Remap_define
ebrus 0:0a673c671a56 184 * @{
ebrus 0:0a673c671a56 185 */
ebrus 0:0a673c671a56 186
ebrus 0:0a673c671a56 187 #define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
ebrus 0:0a673c671a56 188 #define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
ebrus 0:0a673c671a56 189 #define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
ebrus 0:0a673c671a56 190 #define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
ebrus 0:0a673c671a56 191 #define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
ebrus 0:0a673c671a56 192 #define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
ebrus 0:0a673c671a56 193 #define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
ebrus 0:0a673c671a56 194 #define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
ebrus 0:0a673c671a56 195 #define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
ebrus 0:0a673c671a56 196 #define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
ebrus 0:0a673c671a56 197 #define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
ebrus 0:0a673c671a56 198 #define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
ebrus 0:0a673c671a56 199 #define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
ebrus 0:0a673c671a56 200 #define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
ebrus 0:0a673c671a56 201 #define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
ebrus 0:0a673c671a56 202 #define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
ebrus 0:0a673c671a56 203 #define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
ebrus 0:0a673c671a56 204 #define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
ebrus 0:0a673c671a56 205 #define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
ebrus 0:0a673c671a56 206 #define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
ebrus 0:0a673c671a56 207 #define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
ebrus 0:0a673c671a56 208 #define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
ebrus 0:0a673c671a56 209 #define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */
ebrus 0:0a673c671a56 210 #define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */
ebrus 0:0a673c671a56 211 #define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
ebrus 0:0a673c671a56 212 #define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
ebrus 0:0a673c671a56 213 #define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
ebrus 0:0a673c671a56 214 #define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
ebrus 0:0a673c671a56 215 #define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
ebrus 0:0a673c671a56 216 to TIM2 Internal Trigger 1 for calibration
ebrus 0:0a673c671a56 217 (only for Connectivity line devices) */
ebrus 0:0a673c671a56 218 #define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
ebrus 0:0a673c671a56 219
ebrus 0:0a673c671a56 220 #define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */
ebrus 0:0a673c671a56 221 #define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */
ebrus 0:0a673c671a56 222 #define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */
ebrus 0:0a673c671a56 223 #define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */
ebrus 0:0a673c671a56 224 #define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */
ebrus 0:0a673c671a56 225
ebrus 0:0a673c671a56 226 #define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
ebrus 0:0a673c671a56 227 #define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
ebrus 0:0a673c671a56 228 #define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
ebrus 0:0a673c671a56 229 #define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */
ebrus 0:0a673c671a56 230 #define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */
ebrus 0:0a673c671a56 231 #define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */
ebrus 0:0a673c671a56 232
ebrus 0:0a673c671a56 233 #define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
ebrus 0:0a673c671a56 234 #define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */
ebrus 0:0a673c671a56 235 #define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
ebrus 0:0a673c671a56 236 only for High density Value line devices) */
ebrus 0:0a673c671a56 237
ebrus 0:0a673c671a56 238 #define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
ebrus 0:0a673c671a56 239 ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
ebrus 0:0a673c671a56 240 ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
ebrus 0:0a673c671a56 241 ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
ebrus 0:0a673c671a56 242 ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
ebrus 0:0a673c671a56 243 ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
ebrus 0:0a673c671a56 244 ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
ebrus 0:0a673c671a56 245 ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
ebrus 0:0a673c671a56 246 ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
ebrus 0:0a673c671a56 247 ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
ebrus 0:0a673c671a56 248 ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
ebrus 0:0a673c671a56 249 ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
ebrus 0:0a673c671a56 250 ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
ebrus 0:0a673c671a56 251 ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
ebrus 0:0a673c671a56 252 ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
ebrus 0:0a673c671a56 253 ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
ebrus 0:0a673c671a56 254 ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
ebrus 0:0a673c671a56 255 ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
ebrus 0:0a673c671a56 256 ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
ebrus 0:0a673c671a56 257 ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
ebrus 0:0a673c671a56 258 ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
ebrus 0:0a673c671a56 259 ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))
ebrus 0:0a673c671a56 260
ebrus 0:0a673c671a56 261 /**
ebrus 0:0a673c671a56 262 * @}
ebrus 0:0a673c671a56 263 */
ebrus 0:0a673c671a56 264
ebrus 0:0a673c671a56 265 /** @defgroup GPIO_Port_Sources
ebrus 0:0a673c671a56 266 * @{
ebrus 0:0a673c671a56 267 */
ebrus 0:0a673c671a56 268
ebrus 0:0a673c671a56 269 #define GPIO_PortSourceGPIOA ((uint8_t)0x00)
ebrus 0:0a673c671a56 270 #define GPIO_PortSourceGPIOB ((uint8_t)0x01)
ebrus 0:0a673c671a56 271 #define GPIO_PortSourceGPIOC ((uint8_t)0x02)
ebrus 0:0a673c671a56 272 #define GPIO_PortSourceGPIOD ((uint8_t)0x03)
ebrus 0:0a673c671a56 273 #define GPIO_PortSourceGPIOE ((uint8_t)0x04)
ebrus 0:0a673c671a56 274 #define GPIO_PortSourceGPIOF ((uint8_t)0x05)
ebrus 0:0a673c671a56 275 #define GPIO_PortSourceGPIOG ((uint8_t)0x06)
ebrus 0:0a673c671a56 276 #define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
ebrus 0:0a673c671a56 277 ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
ebrus 0:0a673c671a56 278 ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
ebrus 0:0a673c671a56 279 ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
ebrus 0:0a673c671a56 280 ((PORTSOURCE) == GPIO_PortSourceGPIOE))
ebrus 0:0a673c671a56 281
ebrus 0:0a673c671a56 282 #define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
ebrus 0:0a673c671a56 283 ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
ebrus 0:0a673c671a56 284 ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
ebrus 0:0a673c671a56 285 ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
ebrus 0:0a673c671a56 286 ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
ebrus 0:0a673c671a56 287 ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
ebrus 0:0a673c671a56 288 ((PORTSOURCE) == GPIO_PortSourceGPIOG))
ebrus 0:0a673c671a56 289
ebrus 0:0a673c671a56 290 /**
ebrus 0:0a673c671a56 291 * @}
ebrus 0:0a673c671a56 292 */
ebrus 0:0a673c671a56 293
ebrus 0:0a673c671a56 294 /** @defgroup GPIO_Pin_sources
ebrus 0:0a673c671a56 295 * @{
ebrus 0:0a673c671a56 296 */
ebrus 0:0a673c671a56 297
ebrus 0:0a673c671a56 298 #define GPIO_PinSource0 ((uint8_t)0x00)
ebrus 0:0a673c671a56 299 #define GPIO_PinSource1 ((uint8_t)0x01)
ebrus 0:0a673c671a56 300 #define GPIO_PinSource2 ((uint8_t)0x02)
ebrus 0:0a673c671a56 301 #define GPIO_PinSource3 ((uint8_t)0x03)
ebrus 0:0a673c671a56 302 #define GPIO_PinSource4 ((uint8_t)0x04)
ebrus 0:0a673c671a56 303 #define GPIO_PinSource5 ((uint8_t)0x05)
ebrus 0:0a673c671a56 304 #define GPIO_PinSource6 ((uint8_t)0x06)
ebrus 0:0a673c671a56 305 #define GPIO_PinSource7 ((uint8_t)0x07)
ebrus 0:0a673c671a56 306 #define GPIO_PinSource8 ((uint8_t)0x08)
ebrus 0:0a673c671a56 307 #define GPIO_PinSource9 ((uint8_t)0x09)
ebrus 0:0a673c671a56 308 #define GPIO_PinSource10 ((uint8_t)0x0A)
ebrus 0:0a673c671a56 309 #define GPIO_PinSource11 ((uint8_t)0x0B)
ebrus 0:0a673c671a56 310 #define GPIO_PinSource12 ((uint8_t)0x0C)
ebrus 0:0a673c671a56 311 #define GPIO_PinSource13 ((uint8_t)0x0D)
ebrus 0:0a673c671a56 312 #define GPIO_PinSource14 ((uint8_t)0x0E)
ebrus 0:0a673c671a56 313 #define GPIO_PinSource15 ((uint8_t)0x0F)
ebrus 0:0a673c671a56 314
ebrus 0:0a673c671a56 315 #define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
ebrus 0:0a673c671a56 316 ((PINSOURCE) == GPIO_PinSource1) || \
ebrus 0:0a673c671a56 317 ((PINSOURCE) == GPIO_PinSource2) || \
ebrus 0:0a673c671a56 318 ((PINSOURCE) == GPIO_PinSource3) || \
ebrus 0:0a673c671a56 319 ((PINSOURCE) == GPIO_PinSource4) || \
ebrus 0:0a673c671a56 320 ((PINSOURCE) == GPIO_PinSource5) || \
ebrus 0:0a673c671a56 321 ((PINSOURCE) == GPIO_PinSource6) || \
ebrus 0:0a673c671a56 322 ((PINSOURCE) == GPIO_PinSource7) || \
ebrus 0:0a673c671a56 323 ((PINSOURCE) == GPIO_PinSource8) || \
ebrus 0:0a673c671a56 324 ((PINSOURCE) == GPIO_PinSource9) || \
ebrus 0:0a673c671a56 325 ((PINSOURCE) == GPIO_PinSource10) || \
ebrus 0:0a673c671a56 326 ((PINSOURCE) == GPIO_PinSource11) || \
ebrus 0:0a673c671a56 327 ((PINSOURCE) == GPIO_PinSource12) || \
ebrus 0:0a673c671a56 328 ((PINSOURCE) == GPIO_PinSource13) || \
ebrus 0:0a673c671a56 329 ((PINSOURCE) == GPIO_PinSource14) || \
ebrus 0:0a673c671a56 330 ((PINSOURCE) == GPIO_PinSource15))
ebrus 0:0a673c671a56 331
ebrus 0:0a673c671a56 332 /**
ebrus 0:0a673c671a56 333 * @}
ebrus 0:0a673c671a56 334 */
ebrus 0:0a673c671a56 335
ebrus 0:0a673c671a56 336 /** @defgroup Ethernet_Media_Interface
ebrus 0:0a673c671a56 337 * @{
ebrus 0:0a673c671a56 338 */
ebrus 0:0a673c671a56 339 #define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
ebrus 0:0a673c671a56 340 #define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
ebrus 0:0a673c671a56 341
ebrus 0:0a673c671a56 342 #define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
ebrus 0:0a673c671a56 343 ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
ebrus 0:0a673c671a56 344
ebrus 0:0a673c671a56 345 /**
ebrus 0:0a673c671a56 346 * @}
ebrus 0:0a673c671a56 347 */
ebrus 0:0a673c671a56 348 /**
ebrus 0:0a673c671a56 349 * @}
ebrus 0:0a673c671a56 350 */
ebrus 0:0a673c671a56 351
ebrus 0:0a673c671a56 352 /** @defgroup GPIO_Exported_Macros
ebrus 0:0a673c671a56 353 * @{
ebrus 0:0a673c671a56 354 */
ebrus 0:0a673c671a56 355
ebrus 0:0a673c671a56 356 /**
ebrus 0:0a673c671a56 357 * @}
ebrus 0:0a673c671a56 358 */
ebrus 0:0a673c671a56 359
ebrus 0:0a673c671a56 360 /** @defgroup GPIO_Exported_Functions
ebrus 0:0a673c671a56 361 * @{
ebrus 0:0a673c671a56 362 */
ebrus 0:0a673c671a56 363
ebrus 0:0a673c671a56 364 void GPIO_DeInit(GPIO_TypeDef* GPIOx);
ebrus 0:0a673c671a56 365 void GPIO_AFIODeInit(void);
ebrus 0:0a673c671a56 366 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
ebrus 0:0a673c671a56 367 void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
ebrus 0:0a673c671a56 368 uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
ebrus 0:0a673c671a56 369 uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
ebrus 0:0a673c671a56 370 uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
ebrus 0:0a673c671a56 371 uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
ebrus 0:0a673c671a56 372 void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
ebrus 0:0a673c671a56 373 void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
ebrus 0:0a673c671a56 374 void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
ebrus 0:0a673c671a56 375 void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
ebrus 0:0a673c671a56 376 void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
ebrus 0:0a673c671a56 377 void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
ebrus 0:0a673c671a56 378 void GPIO_EventOutputCmd(FunctionalState NewState);
ebrus 0:0a673c671a56 379 void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
ebrus 0:0a673c671a56 380 void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
ebrus 0:0a673c671a56 381 void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
ebrus 0:0a673c671a56 382
ebrus 0:0a673c671a56 383 #ifdef __cplusplus
ebrus 0:0a673c671a56 384 }
ebrus 0:0a673c671a56 385 #endif
ebrus 0:0a673c671a56 386
ebrus 0:0a673c671a56 387 #endif /* __STM32F10x_GPIO_H */
ebrus 0:0a673c671a56 388 /**
ebrus 0:0a673c671a56 389 * @}
ebrus 0:0a673c671a56 390 */
ebrus 0:0a673c671a56 391
ebrus 0:0a673c671a56 392 /**
ebrus 0:0a673c671a56 393 * @}
ebrus 0:0a673c671a56 394 */
ebrus 0:0a673c671a56 395
ebrus 0:0a673c671a56 396 /**
ebrus 0:0a673c671a56 397 * @}
ebrus 0:0a673c671a56 398 */
ebrus 0:0a673c671a56 399
ebrus 0:0a673c671a56 400 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/