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targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/stm32f10x_flash.c@0:0a673c671a56, 2016-07-27 (annotated)

Committer:: ebrus
Date:: Wed Jul 27 18:35:32 2016 +0000
Revision:: 0:0a673c671a56

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User	Revision	Line number	New contents of line
ebrus	0:0a673c671a56	1	/**
ebrus	0:0a673c671a56	2	******************************************************************************
ebrus	0:0a673c671a56	3	* @file stm32f10x_flash.c
ebrus	0:0a673c671a56	4	* @author MCD Application Team
ebrus	0:0a673c671a56	5	* @version V3.6.1
ebrus	0:0a673c671a56	6	* @date 05-March-2012
ebrus	0:0a673c671a56	7	* @brief This file provides all the FLASH firmware functions.
ebrus	0:0a673c671a56	8	*******************************************************************************
ebrus	0:0a673c671a56	9	* Copyright (c) 2014, STMicroelectronics
ebrus	0:0a673c671a56	10	* All rights reserved.
ebrus	0:0a673c671a56	11	*
ebrus	0:0a673c671a56	12	* Redistribution and use in source and binary forms, with or without
ebrus	0:0a673c671a56	13	* modification, are permitted provided that the following conditions are met:
ebrus	0:0a673c671a56	14	*
ebrus	0:0a673c671a56	15	* 1. Redistributions of source code must retain the above copyright notice,
ebrus	0:0a673c671a56	16	* this list of conditions and the following disclaimer.
ebrus	0:0a673c671a56	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus	0:0a673c671a56	18	* this list of conditions and the following disclaimer in the documentation
ebrus	0:0a673c671a56	19	* and/or other materials provided with the distribution.
ebrus	0:0a673c671a56	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus	0:0a673c671a56	21	* may be used to endorse or promote products derived from this software
ebrus	0:0a673c671a56	22	* without specific prior written permission.
ebrus	0:0a673c671a56	23	*
ebrus	0:0a673c671a56	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus	0:0a673c671a56	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus	0:0a673c671a56	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus	0:0a673c671a56	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus	0:0a673c671a56	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus	0:0a673c671a56	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus	0:0a673c671a56	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus	0:0a673c671a56	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus	0:0a673c671a56	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus	0:0a673c671a56	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus	0:0a673c671a56	34	*******************************************************************************
ebrus	0:0a673c671a56	35	*/
ebrus	0:0a673c671a56	36
ebrus	0:0a673c671a56	37	/* Includes ------------------------------------------------------------------*/
ebrus	0:0a673c671a56	38	#include "stm32f10x_flash.h"
ebrus	0:0a673c671a56	39
ebrus	0:0a673c671a56	40	/** @addtogroup STM32F10x_StdPeriph_Driver
ebrus	0:0a673c671a56	41	* @{
ebrus	0:0a673c671a56	42	*/
ebrus	0:0a673c671a56	43
ebrus	0:0a673c671a56	44	/** @defgroup FLASH
ebrus	0:0a673c671a56	45	* @brief FLASH driver modules
ebrus	0:0a673c671a56	46	* @{
ebrus	0:0a673c671a56	47	*/
ebrus	0:0a673c671a56	48
ebrus	0:0a673c671a56	49	/** @defgroup FLASH_Private_TypesDefinitions
ebrus	0:0a673c671a56	50	* @{
ebrus	0:0a673c671a56	51	*/
ebrus	0:0a673c671a56	52
ebrus	0:0a673c671a56	53	/**
ebrus	0:0a673c671a56	54	* @}
ebrus	0:0a673c671a56	55	*/
ebrus	0:0a673c671a56	56
ebrus	0:0a673c671a56	57	/** @defgroup FLASH_Private_Defines
ebrus	0:0a673c671a56	58	* @{
ebrus	0:0a673c671a56	59	*/
ebrus	0:0a673c671a56	60
ebrus	0:0a673c671a56	61	/* Flash Access Control Register bits */
ebrus	0:0a673c671a56	62	#define ACR_LATENCY_Mask ((uint32_t)0x00000038)
ebrus	0:0a673c671a56	63	#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
ebrus	0:0a673c671a56	64	#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
ebrus	0:0a673c671a56	65
ebrus	0:0a673c671a56	66	/* Flash Access Control Register bits */
ebrus	0:0a673c671a56	67	#define ACR_PRFTBS_Mask ((uint32_t)0x00000020)
ebrus	0:0a673c671a56	68
ebrus	0:0a673c671a56	69	/* Flash Control Register bits */
ebrus	0:0a673c671a56	70	#define CR_PG_Set ((uint32_t)0x00000001)
ebrus	0:0a673c671a56	71	#define CR_PG_Reset ((uint32_t)0x00001FFE)
ebrus	0:0a673c671a56	72	#define CR_PER_Set ((uint32_t)0x00000002)
ebrus	0:0a673c671a56	73	#define CR_PER_Reset ((uint32_t)0x00001FFD)
ebrus	0:0a673c671a56	74	#define CR_MER_Set ((uint32_t)0x00000004)
ebrus	0:0a673c671a56	75	#define CR_MER_Reset ((uint32_t)0x00001FFB)
ebrus	0:0a673c671a56	76	#define CR_OPTPG_Set ((uint32_t)0x00000010)
ebrus	0:0a673c671a56	77	#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)
ebrus	0:0a673c671a56	78	#define CR_OPTER_Set ((uint32_t)0x00000020)
ebrus	0:0a673c671a56	79	#define CR_OPTER_Reset ((uint32_t)0x00001FDF)
ebrus	0:0a673c671a56	80	#define CR_STRT_Set ((uint32_t)0x00000040)
ebrus	0:0a673c671a56	81	#define CR_LOCK_Set ((uint32_t)0x00000080)
ebrus	0:0a673c671a56	82
ebrus	0:0a673c671a56	83	/* FLASH Mask */
ebrus	0:0a673c671a56	84	#define RDPRT_Mask ((uint32_t)0x00000002)
ebrus	0:0a673c671a56	85	#define WRP0_Mask ((uint32_t)0x000000FF)
ebrus	0:0a673c671a56	86	#define WRP1_Mask ((uint32_t)0x0000FF00)
ebrus	0:0a673c671a56	87	#define WRP2_Mask ((uint32_t)0x00FF0000)
ebrus	0:0a673c671a56	88	#define WRP3_Mask ((uint32_t)0xFF000000)
ebrus	0:0a673c671a56	89	#define OB_USER_BFB2 ((uint16_t)0x0008)
ebrus	0:0a673c671a56	90
ebrus	0:0a673c671a56	91	/* FLASH BANK address */
ebrus	0:0a673c671a56	92	#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
ebrus	0:0a673c671a56	93
ebrus	0:0a673c671a56	94	/* Delay definition */
ebrus	0:0a673c671a56	95	#define EraseTimeout ((uint32_t)0x000B0000)
ebrus	0:0a673c671a56	96	#define ProgramTimeout ((uint32_t)0x00002000)
ebrus	0:0a673c671a56	97	/**
ebrus	0:0a673c671a56	98	* @}
ebrus	0:0a673c671a56	99	*/
ebrus	0:0a673c671a56	100
ebrus	0:0a673c671a56	101	/** @defgroup FLASH_Private_Macros
ebrus	0:0a673c671a56	102	* @{
ebrus	0:0a673c671a56	103	*/
ebrus	0:0a673c671a56	104
ebrus	0:0a673c671a56	105	/**
ebrus	0:0a673c671a56	106	* @}
ebrus	0:0a673c671a56	107	*/
ebrus	0:0a673c671a56	108
ebrus	0:0a673c671a56	109	/** @defgroup FLASH_Private_Variables
ebrus	0:0a673c671a56	110	* @{
ebrus	0:0a673c671a56	111	*/
ebrus	0:0a673c671a56	112
ebrus	0:0a673c671a56	113	/**
ebrus	0:0a673c671a56	114	* @}
ebrus	0:0a673c671a56	115	*/
ebrus	0:0a673c671a56	116
ebrus	0:0a673c671a56	117	/** @defgroup FLASH_Private_FunctionPrototypes
ebrus	0:0a673c671a56	118	* @{
ebrus	0:0a673c671a56	119	*/
ebrus	0:0a673c671a56	120
ebrus	0:0a673c671a56	121	/**
ebrus	0:0a673c671a56	122	* @}
ebrus	0:0a673c671a56	123	*/
ebrus	0:0a673c671a56	124
ebrus	0:0a673c671a56	125	/** @defgroup FLASH_Private_Functions
ebrus	0:0a673c671a56	126	* @{
ebrus	0:0a673c671a56	127	*/
ebrus	0:0a673c671a56	128
ebrus	0:0a673c671a56	129	/**
ebrus	0:0a673c671a56	130	@code
ebrus	0:0a673c671a56	131
ebrus	0:0a673c671a56	132	This driver provides functions to configure and program the Flash memory of all STM32F10x devices,
ebrus	0:0a673c671a56	133	including the latest STM32F10x_XL density devices.
ebrus	0:0a673c671a56	134
ebrus	0:0a673c671a56	135	STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:
ebrus	0:0a673c671a56	136	- bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)
ebrus	0:0a673c671a56	137	- bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)
ebrus	0:0a673c671a56	138	While other STM32F10x devices features only one bank with memory up to 512 Kbytes.
ebrus	0:0a673c671a56	139
ebrus	0:0a673c671a56	140	In version V3.3.0, some functions were updated and new ones were added to support
ebrus	0:0a673c671a56	141	STM32F10x_XL devices. Thus some functions manages all devices, while other are
ebrus	0:0a673c671a56	142	dedicated for XL devices only.
ebrus	0:0a673c671a56	143
ebrus	0:0a673c671a56	144	The table below presents the list of available functions depending on the used STM32F10x devices.
ebrus	0:0a673c671a56	145
ebrus	0:0a673c671a56	146	***************************************************
ebrus	0:0a673c671a56	147	* Legacy functions used for all STM32F10x devices *
ebrus	0:0a673c671a56	148	***************************************************
ebrus	0:0a673c671a56	149	+----------------------------------------------------------------------------------------------------------------------------------+
ebrus	0:0a673c671a56	150	\| Functions prototypes \|STM32F10x_XL\|Other STM32F10x\| Comments \|
ebrus	0:0a673c671a56	151	\| \| devices \| devices \| \|
ebrus	0:0a673c671a56	152	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	153	\|FLASH_SetLatency \| Yes \| Yes \| No change \|
ebrus	0:0a673c671a56	154	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	155	\|FLASH_HalfCycleAccessCmd \| Yes \| Yes \| No change \|
ebrus	0:0a673c671a56	156	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	157	\|FLASH_PrefetchBufferCmd \| Yes \| Yes \| No change \|
ebrus	0:0a673c671a56	158	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	159	\|FLASH_Unlock \| Yes \| Yes \| - For STM32F10X_XL devices: unlock Bank1 and Bank2. \|
ebrus	0:0a673c671a56	160	\| \| \| \| - For other devices: unlock Bank1 and it is equivalent \|
ebrus	0:0a673c671a56	161	\| \| \| \| to FLASH_UnlockBank1 function. \|
ebrus	0:0a673c671a56	162	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	163	\|FLASH_Lock \| Yes \| Yes \| - For STM32F10X_XL devices: lock Bank1 and Bank2. \|
ebrus	0:0a673c671a56	164	\| \| \| \| - For other devices: lock Bank1 and it is equivalent \|
ebrus	0:0a673c671a56	165	\| \| \| \| to FLASH_LockBank1 function. \|
ebrus	0:0a673c671a56	166	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	167	\|FLASH_ErasePage \| Yes \| Yes \| - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 \|
ebrus	0:0a673c671a56	168	\| \| \| \| - For other devices: erase a page in Bank1 \|
ebrus	0:0a673c671a56	169	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	170	\|FLASH_EraseAllPages \| Yes \| Yes \| - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 \|
ebrus	0:0a673c671a56	171	\| \| \| \| - For other devices: erase all pages in Bank1 \|
ebrus	0:0a673c671a56	172	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	173	\|FLASH_EraseOptionBytes \| Yes \| Yes \| No change \|
ebrus	0:0a673c671a56	174	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	175	\|FLASH_ProgramWord \| Yes \| Yes \| Updated to program up to 1MByte (depending on the used device) \|
ebrus	0:0a673c671a56	176	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	177	\|FLASH_ProgramHalfWord \| Yes \| Yes \| Updated to program up to 1MByte (depending on the used device) \|
ebrus	0:0a673c671a56	178	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	179	\|FLASH_ProgramOptionByteData \| Yes \| Yes \| No change \|
ebrus	0:0a673c671a56	180	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	181	\|FLASH_EnableWriteProtection \| Yes \| Yes \| No change \|
ebrus	0:0a673c671a56	182	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	183	\|FLASH_ReadOutProtection \| Yes \| Yes \| No change \|
ebrus	0:0a673c671a56	184	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	185	\|FLASH_UserOptionByteConfig \| Yes \| Yes \| No change \|
ebrus	0:0a673c671a56	186	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	187	\|FLASH_GetUserOptionByte \| Yes \| Yes \| No change \|
ebrus	0:0a673c671a56	188	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	189	\|FLASH_GetWriteProtectionOptionByte \| Yes \| Yes \| No change \|
ebrus	0:0a673c671a56	190	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	191	\|FLASH_GetReadOutProtectionStatus \| Yes \| Yes \| No change \|
ebrus	0:0a673c671a56	192	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	193	\|FLASH_GetPrefetchBufferStatus \| Yes \| Yes \| No change \|
ebrus	0:0a673c671a56	194	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	195	\|FLASH_ITConfig \| Yes \| Yes \| - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts\|
ebrus	0:0a673c671a56	196	\| \| \| \| - For other devices: enable Bank1's interrupts \|
ebrus	0:0a673c671a56	197	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	198	\|FLASH_GetFlagStatus \| Yes \| Yes \| - For STM32F10x_XL devices: return Bank1 and Bank2's flag status\|
ebrus	0:0a673c671a56	199	\| \| \| \| - For other devices: return Bank1's flag status \|
ebrus	0:0a673c671a56	200	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	201	\|FLASH_ClearFlag \| Yes \| Yes \| - For STM32F10x_XL devices: clear Bank1 and Bank2's flag \|
ebrus	0:0a673c671a56	202	\| \| \| \| - For other devices: clear Bank1's flag \|
ebrus	0:0a673c671a56	203	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	204	\|FLASH_GetStatus \| Yes \| Yes \| - Return the status of Bank1 (for all devices) \|
ebrus	0:0a673c671a56	205	\| \| \| \| equivalent to FLASH_GetBank1Status function \|
ebrus	0:0a673c671a56	206	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	207	\|FLASH_WaitForLastOperation \| Yes \| Yes \| - Wait for Bank1 last operation (for all devices) \|
ebrus	0:0a673c671a56	208	\| \| \| \| equivalent to: FLASH_WaitForLastBank1Operation function \|
ebrus	0:0a673c671a56	209	+----------------------------------------------------------------------------------------------------------------------------------+
ebrus	0:0a673c671a56	210
ebrus	0:0a673c671a56	211	************************************************************************************************************************
ebrus	0:0a673c671a56	212	* New functions used for all STM32F10x devices to manage Bank1: *
ebrus	0:0a673c671a56	213	* - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *
ebrus	0:0a673c671a56	214	* - For other devices, these functions are optional (covered by functions listed above) *
ebrus	0:0a673c671a56	215	************************************************************************************************************************
ebrus	0:0a673c671a56	216	+----------------------------------------------------------------------------------------------------------------------------------+
ebrus	0:0a673c671a56	217	\| Functions prototypes \|STM32F10x_XL\|Other STM32F10x\| Comments \|
ebrus	0:0a673c671a56	218	\| \| devices \| devices \| \|
ebrus	0:0a673c671a56	219	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	220	\| FLASH_UnlockBank1 \| Yes \| Yes \| - Unlock Bank1 \|
ebrus	0:0a673c671a56	221	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	222	\|FLASH_LockBank1 \| Yes \| Yes \| - Lock Bank1 \|
ebrus	0:0a673c671a56	223	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	224	\| FLASH_EraseAllBank1Pages \| Yes \| Yes \| - Erase all pages in Bank1 \|
ebrus	0:0a673c671a56	225	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	226	\| FLASH_GetBank1Status \| Yes \| Yes \| - Return the status of Bank1 \|
ebrus	0:0a673c671a56	227	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	228	\| FLASH_WaitForLastBank1Operation \| Yes \| Yes \| - Wait for Bank1 last operation \|
ebrus	0:0a673c671a56	229	+----------------------------------------------------------------------------------------------------------------------------------+
ebrus	0:0a673c671a56	230
ebrus	0:0a673c671a56	231	*****************************************************************************
ebrus	0:0a673c671a56	232	* New Functions used only with STM32F10x_XL density devices to manage Bank2 *
ebrus	0:0a673c671a56	233	*****************************************************************************
ebrus	0:0a673c671a56	234	+----------------------------------------------------------------------------------------------------------------------------------+
ebrus	0:0a673c671a56	235	\| Functions prototypes \|STM32F10x_XL\|Other STM32F10x\| Comments \|
ebrus	0:0a673c671a56	236	\| \| devices \| devices \| \|
ebrus	0:0a673c671a56	237	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	238	\| FLASH_UnlockBank2 \| Yes \| No \| - Unlock Bank2 \|
ebrus	0:0a673c671a56	239	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	240	\|FLASH_LockBank2 \| Yes \| No \| - Lock Bank2 \|
ebrus	0:0a673c671a56	241	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	242	\| FLASH_EraseAllBank2Pages \| Yes \| No \| - Erase all pages in Bank2 \|
ebrus	0:0a673c671a56	243	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	244	\| FLASH_GetBank2Status \| Yes \| No \| - Return the status of Bank2 \|
ebrus	0:0a673c671a56	245	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	246	\| FLASH_WaitForLastBank2Operation \| Yes \| No \| - Wait for Bank2 last operation \|
ebrus	0:0a673c671a56	247	\|----------------------------------------------------------------------------------------------------------------------------------\|
ebrus	0:0a673c671a56	248	\| FLASH_BootConfig \| Yes \| No \| - Configure to boot from Bank1 or Bank2 \|
ebrus	0:0a673c671a56	249	+----------------------------------------------------------------------------------------------------------------------------------+
ebrus	0:0a673c671a56	250	@endcode
ebrus	0:0a673c671a56	251	*/
ebrus	0:0a673c671a56	252
ebrus	0:0a673c671a56	253
ebrus	0:0a673c671a56	254	/**
ebrus	0:0a673c671a56	255	* @brief Sets the code latency value.
ebrus	0:0a673c671a56	256	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	257	* @param FLASH_Latency: specifies the FLASH Latency value.
ebrus	0:0a673c671a56	258	* This parameter can be one of the following values:
ebrus	0:0a673c671a56	259	* @arg FLASH_Latency_0: FLASH Zero Latency cycle
ebrus	0:0a673c671a56	260	* @arg FLASH_Latency_1: FLASH One Latency cycle
ebrus	0:0a673c671a56	261	* @arg FLASH_Latency_2: FLASH Two Latency cycles
ebrus	0:0a673c671a56	262	* @retval None
ebrus	0:0a673c671a56	263	*/
ebrus	0:0a673c671a56	264	void FLASH_SetLatency(uint32_t FLASH_Latency)
ebrus	0:0a673c671a56	265	{
ebrus	0:0a673c671a56	266	uint32_t tmpreg = 0;
ebrus	0:0a673c671a56	267
ebrus	0:0a673c671a56	268	/* Check the parameters */
ebrus	0:0a673c671a56	269	assert_param(IS_FLASH_LATENCY(FLASH_Latency));
ebrus	0:0a673c671a56	270
ebrus	0:0a673c671a56	271	/* Read the ACR register */
ebrus	0:0a673c671a56	272	tmpreg = FLASH->ACR;
ebrus	0:0a673c671a56	273
ebrus	0:0a673c671a56	274	/* Sets the Latency value */
ebrus	0:0a673c671a56	275	tmpreg &= ACR_LATENCY_Mask;
ebrus	0:0a673c671a56	276	tmpreg \|= FLASH_Latency;
ebrus	0:0a673c671a56	277
ebrus	0:0a673c671a56	278	/* Write the ACR register */
ebrus	0:0a673c671a56	279	FLASH->ACR = tmpreg;
ebrus	0:0a673c671a56	280	}
ebrus	0:0a673c671a56	281
ebrus	0:0a673c671a56	282	/**
ebrus	0:0a673c671a56	283	* @brief Enables or disables the Half cycle flash access.
ebrus	0:0a673c671a56	284	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	285	* @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
ebrus	0:0a673c671a56	286	* This parameter can be one of the following values:
ebrus	0:0a673c671a56	287	* @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
ebrus	0:0a673c671a56	288	* @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
ebrus	0:0a673c671a56	289	* @retval None
ebrus	0:0a673c671a56	290	*/
ebrus	0:0a673c671a56	291	void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
ebrus	0:0a673c671a56	292	{
ebrus	0:0a673c671a56	293	/* Check the parameters */
ebrus	0:0a673c671a56	294	assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
ebrus	0:0a673c671a56	295
ebrus	0:0a673c671a56	296	/* Enable or disable the Half cycle access */
ebrus	0:0a673c671a56	297	FLASH->ACR &= ACR_HLFCYA_Mask;
ebrus	0:0a673c671a56	298	FLASH->ACR \|= FLASH_HalfCycleAccess;
ebrus	0:0a673c671a56	299	}
ebrus	0:0a673c671a56	300
ebrus	0:0a673c671a56	301	/**
ebrus	0:0a673c671a56	302	* @brief Enables or disables the Prefetch Buffer.
ebrus	0:0a673c671a56	303	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	304	* @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
ebrus	0:0a673c671a56	305	* This parameter can be one of the following values:
ebrus	0:0a673c671a56	306	* @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
ebrus	0:0a673c671a56	307	* @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
ebrus	0:0a673c671a56	308	* @retval None
ebrus	0:0a673c671a56	309	*/
ebrus	0:0a673c671a56	310	void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
ebrus	0:0a673c671a56	311	{
ebrus	0:0a673c671a56	312	/* Check the parameters */
ebrus	0:0a673c671a56	313	assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
ebrus	0:0a673c671a56	314
ebrus	0:0a673c671a56	315	/* Enable or disable the Prefetch Buffer */
ebrus	0:0a673c671a56	316	FLASH->ACR &= ACR_PRFTBE_Mask;
ebrus	0:0a673c671a56	317	FLASH->ACR \|= FLASH_PrefetchBuffer;
ebrus	0:0a673c671a56	318	}
ebrus	0:0a673c671a56	319
ebrus	0:0a673c671a56	320	/**
ebrus	0:0a673c671a56	321	* @brief Unlocks the FLASH Program Erase Controller.
ebrus	0:0a673c671a56	322	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	323	* - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.
ebrus	0:0a673c671a56	324	* - For all other devices it unlocks Bank1 and it is equivalent
ebrus	0:0a673c671a56	325	* to FLASH_UnlockBank1 function..
ebrus	0:0a673c671a56	326	* @param None
ebrus	0:0a673c671a56	327	* @retval None
ebrus	0:0a673c671a56	328	*/
ebrus	0:0a673c671a56	329	void FLASH_Unlock(void)
ebrus	0:0a673c671a56	330	{
ebrus	0:0a673c671a56	331	/* Authorize the FPEC of Bank1 Access */
ebrus	0:0a673c671a56	332	FLASH->KEYR = FLASH_KEY1;
ebrus	0:0a673c671a56	333	FLASH->KEYR = FLASH_KEY2;
ebrus	0:0a673c671a56	334
ebrus	0:0a673c671a56	335	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	336	/* Authorize the FPEC of Bank2 Access */
ebrus	0:0a673c671a56	337	FLASH->KEYR2 = FLASH_KEY1;
ebrus	0:0a673c671a56	338	FLASH->KEYR2 = FLASH_KEY2;
ebrus	0:0a673c671a56	339	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	340	}
ebrus	0:0a673c671a56	341	/**
ebrus	0:0a673c671a56	342	* @brief Unlocks the FLASH Bank1 Program Erase Controller.
ebrus	0:0a673c671a56	343	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	344	* - For STM32F10X_XL devices this function unlocks Bank1.
ebrus	0:0a673c671a56	345	* - For all other devices it unlocks Bank1 and it is
ebrus	0:0a673c671a56	346	* equivalent to FLASH_Unlock function.
ebrus	0:0a673c671a56	347	* @param None
ebrus	0:0a673c671a56	348	* @retval None
ebrus	0:0a673c671a56	349	*/
ebrus	0:0a673c671a56	350	void FLASH_UnlockBank1(void)
ebrus	0:0a673c671a56	351	{
ebrus	0:0a673c671a56	352	/* Authorize the FPEC of Bank1 Access */
ebrus	0:0a673c671a56	353	FLASH->KEYR = FLASH_KEY1;
ebrus	0:0a673c671a56	354	FLASH->KEYR = FLASH_KEY2;
ebrus	0:0a673c671a56	355	}
ebrus	0:0a673c671a56	356
ebrus	0:0a673c671a56	357	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	358	/**
ebrus	0:0a673c671a56	359	* @brief Unlocks the FLASH Bank2 Program Erase Controller.
ebrus	0:0a673c671a56	360	* @note This function can be used only for STM32F10X_XL density devices.
ebrus	0:0a673c671a56	361	* @param None
ebrus	0:0a673c671a56	362	* @retval None
ebrus	0:0a673c671a56	363	*/
ebrus	0:0a673c671a56	364	void FLASH_UnlockBank2(void)
ebrus	0:0a673c671a56	365	{
ebrus	0:0a673c671a56	366	/* Authorize the FPEC of Bank2 Access */
ebrus	0:0a673c671a56	367	FLASH->KEYR2 = FLASH_KEY1;
ebrus	0:0a673c671a56	368	FLASH->KEYR2 = FLASH_KEY2;
ebrus	0:0a673c671a56	369
ebrus	0:0a673c671a56	370	}
ebrus	0:0a673c671a56	371	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	372
ebrus	0:0a673c671a56	373	/**
ebrus	0:0a673c671a56	374	* @brief Locks the FLASH Program Erase Controller.
ebrus	0:0a673c671a56	375	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	376	* - For STM32F10X_XL devices this function Locks Bank1 and Bank2.
ebrus	0:0a673c671a56	377	* - For all other devices it Locks Bank1 and it is equivalent
ebrus	0:0a673c671a56	378	* to FLASH_LockBank1 function.
ebrus	0:0a673c671a56	379	* @param None
ebrus	0:0a673c671a56	380	* @retval None
ebrus	0:0a673c671a56	381	*/
ebrus	0:0a673c671a56	382	void FLASH_Lock(void)
ebrus	0:0a673c671a56	383	{
ebrus	0:0a673c671a56	384	/* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
ebrus	0:0a673c671a56	385	FLASH->CR \|= CR_LOCK_Set;
ebrus	0:0a673c671a56	386
ebrus	0:0a673c671a56	387	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	388	/* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
ebrus	0:0a673c671a56	389	FLASH->CR2 \|= CR_LOCK_Set;
ebrus	0:0a673c671a56	390	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	391	}
ebrus	0:0a673c671a56	392
ebrus	0:0a673c671a56	393	/**
ebrus	0:0a673c671a56	394	* @brief Locks the FLASH Bank1 Program Erase Controller.
ebrus	0:0a673c671a56	395	* @note this function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	396	* - For STM32F10X_XL devices this function Locks Bank1.
ebrus	0:0a673c671a56	397	* - For all other devices it Locks Bank1 and it is equivalent
ebrus	0:0a673c671a56	398	* to FLASH_Lock function.
ebrus	0:0a673c671a56	399	* @param None
ebrus	0:0a673c671a56	400	* @retval None
ebrus	0:0a673c671a56	401	*/
ebrus	0:0a673c671a56	402	void FLASH_LockBank1(void)
ebrus	0:0a673c671a56	403	{
ebrus	0:0a673c671a56	404	/* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
ebrus	0:0a673c671a56	405	FLASH->CR \|= CR_LOCK_Set;
ebrus	0:0a673c671a56	406	}
ebrus	0:0a673c671a56	407
ebrus	0:0a673c671a56	408	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	409	/**
ebrus	0:0a673c671a56	410	* @brief Locks the FLASH Bank2 Program Erase Controller.
ebrus	0:0a673c671a56	411	* @note This function can be used only for STM32F10X_XL density devices.
ebrus	0:0a673c671a56	412	* @param None
ebrus	0:0a673c671a56	413	* @retval None
ebrus	0:0a673c671a56	414	*/
ebrus	0:0a673c671a56	415	void FLASH_LockBank2(void)
ebrus	0:0a673c671a56	416	{
ebrus	0:0a673c671a56	417	/* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
ebrus	0:0a673c671a56	418	FLASH->CR2 \|= CR_LOCK_Set;
ebrus	0:0a673c671a56	419	}
ebrus	0:0a673c671a56	420	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	421
ebrus	0:0a673c671a56	422	/**
ebrus	0:0a673c671a56	423	* @brief Erases a specified FLASH page.
ebrus	0:0a673c671a56	424	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	425	* @param Page_Address: The page address to be erased.
ebrus	0:0a673c671a56	426	* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
ebrus	0:0a673c671a56	427	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	428	*/
ebrus	0:0a673c671a56	429	FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
ebrus	0:0a673c671a56	430	{
ebrus	0:0a673c671a56	431	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	432	/* Check the parameters */
ebrus	0:0a673c671a56	433	assert_param(IS_FLASH_ADDRESS(Page_Address));
ebrus	0:0a673c671a56	434
ebrus	0:0a673c671a56	435	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	436	if(Page_Address < FLASH_BANK1_END_ADDRESS)
ebrus	0:0a673c671a56	437	{
ebrus	0:0a673c671a56	438	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	439	status = FLASH_WaitForLastBank1Operation(EraseTimeout);
ebrus	0:0a673c671a56	440	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	441	{
ebrus	0:0a673c671a56	442	/* if the previous operation is completed, proceed to erase the page */
ebrus	0:0a673c671a56	443	FLASH->CR\|= CR_PER_Set;
ebrus	0:0a673c671a56	444	FLASH->AR = Page_Address;
ebrus	0:0a673c671a56	445	FLASH->CR\|= CR_STRT_Set;
ebrus	0:0a673c671a56	446
ebrus	0:0a673c671a56	447	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	448	status = FLASH_WaitForLastBank1Operation(EraseTimeout);
ebrus	0:0a673c671a56	449
ebrus	0:0a673c671a56	450	/* Disable the PER Bit */
ebrus	0:0a673c671a56	451	FLASH->CR &= CR_PER_Reset;
ebrus	0:0a673c671a56	452	}
ebrus	0:0a673c671a56	453	}
ebrus	0:0a673c671a56	454	else
ebrus	0:0a673c671a56	455	{
ebrus	0:0a673c671a56	456	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	457	status = FLASH_WaitForLastBank2Operation(EraseTimeout);
ebrus	0:0a673c671a56	458	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	459	{
ebrus	0:0a673c671a56	460	/* if the previous operation is completed, proceed to erase the page */
ebrus	0:0a673c671a56	461	FLASH->CR2\|= CR_PER_Set;
ebrus	0:0a673c671a56	462	FLASH->AR2 = Page_Address;
ebrus	0:0a673c671a56	463	FLASH->CR2\|= CR_STRT_Set;
ebrus	0:0a673c671a56	464
ebrus	0:0a673c671a56	465	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	466	status = FLASH_WaitForLastBank2Operation(EraseTimeout);
ebrus	0:0a673c671a56	467
ebrus	0:0a673c671a56	468	/* Disable the PER Bit */
ebrus	0:0a673c671a56	469	FLASH->CR2 &= CR_PER_Reset;
ebrus	0:0a673c671a56	470	}
ebrus	0:0a673c671a56	471	}
ebrus	0:0a673c671a56	472	#else
ebrus	0:0a673c671a56	473	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	474	status = FLASH_WaitForLastOperation(EraseTimeout);
ebrus	0:0a673c671a56	475
ebrus	0:0a673c671a56	476	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	477	{
ebrus	0:0a673c671a56	478	/* if the previous operation is completed, proceed to erase the page */
ebrus	0:0a673c671a56	479	FLASH->CR\|= CR_PER_Set;
ebrus	0:0a673c671a56	480	FLASH->AR = Page_Address;
ebrus	0:0a673c671a56	481	FLASH->CR\|= CR_STRT_Set;
ebrus	0:0a673c671a56	482
ebrus	0:0a673c671a56	483	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	484	status = FLASH_WaitForLastOperation(EraseTimeout);
ebrus	0:0a673c671a56	485
ebrus	0:0a673c671a56	486	/* Disable the PER Bit */
ebrus	0:0a673c671a56	487	FLASH->CR &= CR_PER_Reset;
ebrus	0:0a673c671a56	488	}
ebrus	0:0a673c671a56	489	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	490
ebrus	0:0a673c671a56	491	/* Return the Erase Status */
ebrus	0:0a673c671a56	492	return status;
ebrus	0:0a673c671a56	493	}
ebrus	0:0a673c671a56	494
ebrus	0:0a673c671a56	495	/**
ebrus	0:0a673c671a56	496	* @brief Erases all FLASH pages.
ebrus	0:0a673c671a56	497	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	498	* @param None
ebrus	0:0a673c671a56	499	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	500	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	501	*/
ebrus	0:0a673c671a56	502	FLASH_Status FLASH_EraseAllPages(void)
ebrus	0:0a673c671a56	503	{
ebrus	0:0a673c671a56	504	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	505
ebrus	0:0a673c671a56	506	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	507	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	508	status = FLASH_WaitForLastBank1Operation(EraseTimeout);
ebrus	0:0a673c671a56	509
ebrus	0:0a673c671a56	510	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	511	{
ebrus	0:0a673c671a56	512	/* if the previous operation is completed, proceed to erase all pages */
ebrus	0:0a673c671a56	513	FLASH->CR \|= CR_MER_Set;
ebrus	0:0a673c671a56	514	FLASH->CR \|= CR_STRT_Set;
ebrus	0:0a673c671a56	515
ebrus	0:0a673c671a56	516	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	517	status = FLASH_WaitForLastBank1Operation(EraseTimeout);
ebrus	0:0a673c671a56	518
ebrus	0:0a673c671a56	519	/* Disable the MER Bit */
ebrus	0:0a673c671a56	520	FLASH->CR &= CR_MER_Reset;
ebrus	0:0a673c671a56	521	}
ebrus	0:0a673c671a56	522	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	523	{
ebrus	0:0a673c671a56	524	/* if the previous operation is completed, proceed to erase all pages */
ebrus	0:0a673c671a56	525	FLASH->CR2 \|= CR_MER_Set;
ebrus	0:0a673c671a56	526	FLASH->CR2 \|= CR_STRT_Set;
ebrus	0:0a673c671a56	527
ebrus	0:0a673c671a56	528	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	529	status = FLASH_WaitForLastBank2Operation(EraseTimeout);
ebrus	0:0a673c671a56	530
ebrus	0:0a673c671a56	531	/* Disable the MER Bit */
ebrus	0:0a673c671a56	532	FLASH->CR2 &= CR_MER_Reset;
ebrus	0:0a673c671a56	533	}
ebrus	0:0a673c671a56	534	#else
ebrus	0:0a673c671a56	535	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	536	status = FLASH_WaitForLastOperation(EraseTimeout);
ebrus	0:0a673c671a56	537	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	538	{
ebrus	0:0a673c671a56	539	/* if the previous operation is completed, proceed to erase all pages */
ebrus	0:0a673c671a56	540	FLASH->CR \|= CR_MER_Set;
ebrus	0:0a673c671a56	541	FLASH->CR \|= CR_STRT_Set;
ebrus	0:0a673c671a56	542
ebrus	0:0a673c671a56	543	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	544	status = FLASH_WaitForLastOperation(EraseTimeout);
ebrus	0:0a673c671a56	545
ebrus	0:0a673c671a56	546	/* Disable the MER Bit */
ebrus	0:0a673c671a56	547	FLASH->CR &= CR_MER_Reset;
ebrus	0:0a673c671a56	548	}
ebrus	0:0a673c671a56	549	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	550
ebrus	0:0a673c671a56	551	/* Return the Erase Status */
ebrus	0:0a673c671a56	552	return status;
ebrus	0:0a673c671a56	553	}
ebrus	0:0a673c671a56	554
ebrus	0:0a673c671a56	555	/**
ebrus	0:0a673c671a56	556	* @brief Erases all Bank1 FLASH pages.
ebrus	0:0a673c671a56	557	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	558	* - For STM32F10X_XL devices this function erases all Bank1 pages.
ebrus	0:0a673c671a56	559	* - For all other devices it erases all Bank1 pages and it is equivalent
ebrus	0:0a673c671a56	560	* to FLASH_EraseAllPages function.
ebrus	0:0a673c671a56	561	* @param None
ebrus	0:0a673c671a56	562	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	563	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	564	*/
ebrus	0:0a673c671a56	565	FLASH_Status FLASH_EraseAllBank1Pages(void)
ebrus	0:0a673c671a56	566	{
ebrus	0:0a673c671a56	567	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	568	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	569	status = FLASH_WaitForLastBank1Operation(EraseTimeout);
ebrus	0:0a673c671a56	570
ebrus	0:0a673c671a56	571	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	572	{
ebrus	0:0a673c671a56	573	/* if the previous operation is completed, proceed to erase all pages */
ebrus	0:0a673c671a56	574	FLASH->CR \|= CR_MER_Set;
ebrus	0:0a673c671a56	575	FLASH->CR \|= CR_STRT_Set;
ebrus	0:0a673c671a56	576
ebrus	0:0a673c671a56	577	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	578	status = FLASH_WaitForLastBank1Operation(EraseTimeout);
ebrus	0:0a673c671a56	579
ebrus	0:0a673c671a56	580	/* Disable the MER Bit */
ebrus	0:0a673c671a56	581	FLASH->CR &= CR_MER_Reset;
ebrus	0:0a673c671a56	582	}
ebrus	0:0a673c671a56	583	/* Return the Erase Status */
ebrus	0:0a673c671a56	584	return status;
ebrus	0:0a673c671a56	585	}
ebrus	0:0a673c671a56	586
ebrus	0:0a673c671a56	587	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	588	/**
ebrus	0:0a673c671a56	589	* @brief Erases all Bank2 FLASH pages.
ebrus	0:0a673c671a56	590	* @note This function can be used only for STM32F10x_XL density devices.
ebrus	0:0a673c671a56	591	* @param None
ebrus	0:0a673c671a56	592	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	593	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	594	*/
ebrus	0:0a673c671a56	595	FLASH_Status FLASH_EraseAllBank2Pages(void)
ebrus	0:0a673c671a56	596	{
ebrus	0:0a673c671a56	597	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	598	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	599	status = FLASH_WaitForLastBank2Operation(EraseTimeout);
ebrus	0:0a673c671a56	600
ebrus	0:0a673c671a56	601	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	602	{
ebrus	0:0a673c671a56	603	/* if the previous operation is completed, proceed to erase all pages */
ebrus	0:0a673c671a56	604	FLASH->CR2 \|= CR_MER_Set;
ebrus	0:0a673c671a56	605	FLASH->CR2 \|= CR_STRT_Set;
ebrus	0:0a673c671a56	606
ebrus	0:0a673c671a56	607	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	608	status = FLASH_WaitForLastBank2Operation(EraseTimeout);
ebrus	0:0a673c671a56	609
ebrus	0:0a673c671a56	610	/* Disable the MER Bit */
ebrus	0:0a673c671a56	611	FLASH->CR2 &= CR_MER_Reset;
ebrus	0:0a673c671a56	612	}
ebrus	0:0a673c671a56	613	/* Return the Erase Status */
ebrus	0:0a673c671a56	614	return status;
ebrus	0:0a673c671a56	615	}
ebrus	0:0a673c671a56	616	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	617
ebrus	0:0a673c671a56	618	/**
ebrus	0:0a673c671a56	619	* @brief Erases the FLASH option bytes.
ebrus	0:0a673c671a56	620	* @note This functions erases all option bytes except the Read protection (RDP).
ebrus	0:0a673c671a56	621	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	622	* @param None
ebrus	0:0a673c671a56	623	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	624	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	625	*/
ebrus	0:0a673c671a56	626	FLASH_Status FLASH_EraseOptionBytes(void)
ebrus	0:0a673c671a56	627	{
ebrus	0:0a673c671a56	628	uint16_t rdptmp = RDP_Key;
ebrus	0:0a673c671a56	629
ebrus	0:0a673c671a56	630	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	631
ebrus	0:0a673c671a56	632	/* Get the actual read protection Option Byte value */
ebrus	0:0a673c671a56	633	if(FLASH_GetReadOutProtectionStatus() != RESET)
ebrus	0:0a673c671a56	634	{
ebrus	0:0a673c671a56	635	rdptmp = 0x00;
ebrus	0:0a673c671a56	636	}
ebrus	0:0a673c671a56	637
ebrus	0:0a673c671a56	638	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	639	status = FLASH_WaitForLastOperation(EraseTimeout);
ebrus	0:0a673c671a56	640	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	641	{
ebrus	0:0a673c671a56	642	/* Authorize the small information block programming */
ebrus	0:0a673c671a56	643	FLASH->OPTKEYR = FLASH_KEY1;
ebrus	0:0a673c671a56	644	FLASH->OPTKEYR = FLASH_KEY2;
ebrus	0:0a673c671a56	645
ebrus	0:0a673c671a56	646	/* if the previous operation is completed, proceed to erase the option bytes */
ebrus	0:0a673c671a56	647	FLASH->CR \|= CR_OPTER_Set;
ebrus	0:0a673c671a56	648	FLASH->CR \|= CR_STRT_Set;
ebrus	0:0a673c671a56	649	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	650	status = FLASH_WaitForLastOperation(EraseTimeout);
ebrus	0:0a673c671a56	651
ebrus	0:0a673c671a56	652	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	653	{
ebrus	0:0a673c671a56	654	/* if the erase operation is completed, disable the OPTER Bit */
ebrus	0:0a673c671a56	655	FLASH->CR &= CR_OPTER_Reset;
ebrus	0:0a673c671a56	656
ebrus	0:0a673c671a56	657	/* Enable the Option Bytes Programming operation */
ebrus	0:0a673c671a56	658	FLASH->CR \|= CR_OPTPG_Set;
ebrus	0:0a673c671a56	659	/* Restore the last read protection Option Byte value */
ebrus	0:0a673c671a56	660	OB->RDP = (uint16_t)rdptmp;
ebrus	0:0a673c671a56	661	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	662	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	663
ebrus	0:0a673c671a56	664	if(status != FLASH_TIMEOUT)
ebrus	0:0a673c671a56	665	{
ebrus	0:0a673c671a56	666	/* if the program operation is completed, disable the OPTPG Bit */
ebrus	0:0a673c671a56	667	FLASH->CR &= CR_OPTPG_Reset;
ebrus	0:0a673c671a56	668	}
ebrus	0:0a673c671a56	669	}
ebrus	0:0a673c671a56	670	else
ebrus	0:0a673c671a56	671	{
ebrus	0:0a673c671a56	672	if (status != FLASH_TIMEOUT)
ebrus	0:0a673c671a56	673	{
ebrus	0:0a673c671a56	674	/* Disable the OPTPG Bit */
ebrus	0:0a673c671a56	675	FLASH->CR &= CR_OPTPG_Reset;
ebrus	0:0a673c671a56	676	}
ebrus	0:0a673c671a56	677	}
ebrus	0:0a673c671a56	678	}
ebrus	0:0a673c671a56	679	/* Return the erase status */
ebrus	0:0a673c671a56	680	return status;
ebrus	0:0a673c671a56	681	}
ebrus	0:0a673c671a56	682
ebrus	0:0a673c671a56	683	/**
ebrus	0:0a673c671a56	684	* @brief Programs a word at a specified address.
ebrus	0:0a673c671a56	685	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	686	* @param Address: specifies the address to be programmed.
ebrus	0:0a673c671a56	687	* @param Data: specifies the data to be programmed.
ebrus	0:0a673c671a56	688	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	689	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	690	*/
ebrus	0:0a673c671a56	691	FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
ebrus	0:0a673c671a56	692	{
ebrus	0:0a673c671a56	693	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	694	__IO uint32_t tmp = 0;
ebrus	0:0a673c671a56	695
ebrus	0:0a673c671a56	696	/* Check the parameters */
ebrus	0:0a673c671a56	697	assert_param(IS_FLASH_ADDRESS(Address));
ebrus	0:0a673c671a56	698
ebrus	0:0a673c671a56	699	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	700	if(Address < FLASH_BANK1_END_ADDRESS - 2)
ebrus	0:0a673c671a56	701	{
ebrus	0:0a673c671a56	702	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	703	status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
ebrus	0:0a673c671a56	704	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	705	{
ebrus	0:0a673c671a56	706	/* if the previous operation is completed, proceed to program the new first
ebrus	0:0a673c671a56	707	half word */
ebrus	0:0a673c671a56	708	FLASH->CR \|= CR_PG_Set;
ebrus	0:0a673c671a56	709
ebrus	0:0a673c671a56	710	(__IO uint16_t)Address = (uint16_t)Data;
ebrus	0:0a673c671a56	711	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	712	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	713
ebrus	0:0a673c671a56	714	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	715	{
ebrus	0:0a673c671a56	716	/* if the previous operation is completed, proceed to program the new second
ebrus	0:0a673c671a56	717	half word */
ebrus	0:0a673c671a56	718	tmp = Address + 2;
ebrus	0:0a673c671a56	719
ebrus	0:0a673c671a56	720	(__IO uint16_t) tmp = Data >> 16;
ebrus	0:0a673c671a56	721
ebrus	0:0a673c671a56	722	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	723	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	724
ebrus	0:0a673c671a56	725	/* Disable the PG Bit */
ebrus	0:0a673c671a56	726	FLASH->CR &= CR_PG_Reset;
ebrus	0:0a673c671a56	727	}
ebrus	0:0a673c671a56	728	else
ebrus	0:0a673c671a56	729	{
ebrus	0:0a673c671a56	730	/* Disable the PG Bit */
ebrus	0:0a673c671a56	731	FLASH->CR &= CR_PG_Reset;
ebrus	0:0a673c671a56	732	}
ebrus	0:0a673c671a56	733	}
ebrus	0:0a673c671a56	734	}
ebrus	0:0a673c671a56	735	else if(Address == (FLASH_BANK1_END_ADDRESS - 1))
ebrus	0:0a673c671a56	736	{
ebrus	0:0a673c671a56	737	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	738	status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
ebrus	0:0a673c671a56	739
ebrus	0:0a673c671a56	740	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	741	{
ebrus	0:0a673c671a56	742	/* if the previous operation is completed, proceed to program the new first
ebrus	0:0a673c671a56	743	half word */
ebrus	0:0a673c671a56	744	FLASH->CR \|= CR_PG_Set;
ebrus	0:0a673c671a56	745
ebrus	0:0a673c671a56	746	(__IO uint16_t)Address = (uint16_t)Data;
ebrus	0:0a673c671a56	747
ebrus	0:0a673c671a56	748	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	749	status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
ebrus	0:0a673c671a56	750
ebrus	0:0a673c671a56	751	/* Disable the PG Bit */
ebrus	0:0a673c671a56	752	FLASH->CR &= CR_PG_Reset;
ebrus	0:0a673c671a56	753	}
ebrus	0:0a673c671a56	754	else
ebrus	0:0a673c671a56	755	{
ebrus	0:0a673c671a56	756	/* Disable the PG Bit */
ebrus	0:0a673c671a56	757	FLASH->CR &= CR_PG_Reset;
ebrus	0:0a673c671a56	758	}
ebrus	0:0a673c671a56	759
ebrus	0:0a673c671a56	760	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	761	status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
ebrus	0:0a673c671a56	762
ebrus	0:0a673c671a56	763	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	764	{
ebrus	0:0a673c671a56	765	/* if the previous operation is completed, proceed to program the new second
ebrus	0:0a673c671a56	766	half word */
ebrus	0:0a673c671a56	767	FLASH->CR2 \|= CR_PG_Set;
ebrus	0:0a673c671a56	768	tmp = Address + 2;
ebrus	0:0a673c671a56	769
ebrus	0:0a673c671a56	770	(__IO uint16_t) tmp = Data >> 16;
ebrus	0:0a673c671a56	771
ebrus	0:0a673c671a56	772	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	773	status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
ebrus	0:0a673c671a56	774
ebrus	0:0a673c671a56	775	/* Disable the PG Bit */
ebrus	0:0a673c671a56	776	FLASH->CR2 &= CR_PG_Reset;
ebrus	0:0a673c671a56	777	}
ebrus	0:0a673c671a56	778	else
ebrus	0:0a673c671a56	779	{
ebrus	0:0a673c671a56	780	/* Disable the PG Bit */
ebrus	0:0a673c671a56	781	FLASH->CR2 &= CR_PG_Reset;
ebrus	0:0a673c671a56	782	}
ebrus	0:0a673c671a56	783	}
ebrus	0:0a673c671a56	784	else
ebrus	0:0a673c671a56	785	{
ebrus	0:0a673c671a56	786	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	787	status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
ebrus	0:0a673c671a56	788
ebrus	0:0a673c671a56	789	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	790	{
ebrus	0:0a673c671a56	791	/* if the previous operation is completed, proceed to program the new first
ebrus	0:0a673c671a56	792	half word */
ebrus	0:0a673c671a56	793	FLASH->CR2 \|= CR_PG_Set;
ebrus	0:0a673c671a56	794
ebrus	0:0a673c671a56	795	(__IO uint16_t)Address = (uint16_t)Data;
ebrus	0:0a673c671a56	796	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	797	status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
ebrus	0:0a673c671a56	798
ebrus	0:0a673c671a56	799	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	800	{
ebrus	0:0a673c671a56	801	/* if the previous operation is completed, proceed to program the new second
ebrus	0:0a673c671a56	802	half word */
ebrus	0:0a673c671a56	803	tmp = Address + 2;
ebrus	0:0a673c671a56	804
ebrus	0:0a673c671a56	805	(__IO uint16_t) tmp = Data >> 16;
ebrus	0:0a673c671a56	806
ebrus	0:0a673c671a56	807	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	808	status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
ebrus	0:0a673c671a56	809
ebrus	0:0a673c671a56	810	/* Disable the PG Bit */
ebrus	0:0a673c671a56	811	FLASH->CR2 &= CR_PG_Reset;
ebrus	0:0a673c671a56	812	}
ebrus	0:0a673c671a56	813	else
ebrus	0:0a673c671a56	814	{
ebrus	0:0a673c671a56	815	/* Disable the PG Bit */
ebrus	0:0a673c671a56	816	FLASH->CR2 &= CR_PG_Reset;
ebrus	0:0a673c671a56	817	}
ebrus	0:0a673c671a56	818	}
ebrus	0:0a673c671a56	819	}
ebrus	0:0a673c671a56	820	#else
ebrus	0:0a673c671a56	821	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	822	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	823
ebrus	0:0a673c671a56	824	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	825	{
ebrus	0:0a673c671a56	826	/* if the previous operation is completed, proceed to program the new first
ebrus	0:0a673c671a56	827	half word */
ebrus	0:0a673c671a56	828	FLASH->CR \|= CR_PG_Set;
ebrus	0:0a673c671a56	829
ebrus	0:0a673c671a56	830	(__IO uint16_t)Address = (uint16_t)Data;
ebrus	0:0a673c671a56	831	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	832	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	833
ebrus	0:0a673c671a56	834	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	835	{
ebrus	0:0a673c671a56	836	/* if the previous operation is completed, proceed to program the new second
ebrus	0:0a673c671a56	837	half word */
ebrus	0:0a673c671a56	838	tmp = Address + 2;
ebrus	0:0a673c671a56	839
ebrus	0:0a673c671a56	840	(__IO uint16_t) tmp = Data >> 16;
ebrus	0:0a673c671a56	841
ebrus	0:0a673c671a56	842	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	843	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	844
ebrus	0:0a673c671a56	845	/* Disable the PG Bit */
ebrus	0:0a673c671a56	846	FLASH->CR &= CR_PG_Reset;
ebrus	0:0a673c671a56	847	}
ebrus	0:0a673c671a56	848	else
ebrus	0:0a673c671a56	849	{
ebrus	0:0a673c671a56	850	/* Disable the PG Bit */
ebrus	0:0a673c671a56	851	FLASH->CR &= CR_PG_Reset;
ebrus	0:0a673c671a56	852	}
ebrus	0:0a673c671a56	853	}
ebrus	0:0a673c671a56	854	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	855
ebrus	0:0a673c671a56	856	/* Return the Program Status */
ebrus	0:0a673c671a56	857	return status;
ebrus	0:0a673c671a56	858	}
ebrus	0:0a673c671a56	859
ebrus	0:0a673c671a56	860	/**
ebrus	0:0a673c671a56	861	* @brief Programs a half word at a specified address.
ebrus	0:0a673c671a56	862	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	863	* @param Address: specifies the address to be programmed.
ebrus	0:0a673c671a56	864	* @param Data: specifies the data to be programmed.
ebrus	0:0a673c671a56	865	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	866	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	867	*/
ebrus	0:0a673c671a56	868	FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
ebrus	0:0a673c671a56	869	{
ebrus	0:0a673c671a56	870	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	871	/* Check the parameters */
ebrus	0:0a673c671a56	872	assert_param(IS_FLASH_ADDRESS(Address));
ebrus	0:0a673c671a56	873
ebrus	0:0a673c671a56	874	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	875	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	876	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	877
ebrus	0:0a673c671a56	878	if(Address < FLASH_BANK1_END_ADDRESS)
ebrus	0:0a673c671a56	879	{
ebrus	0:0a673c671a56	880	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	881	{
ebrus	0:0a673c671a56	882	/* if the previous operation is completed, proceed to program the new data */
ebrus	0:0a673c671a56	883	FLASH->CR \|= CR_PG_Set;
ebrus	0:0a673c671a56	884
ebrus	0:0a673c671a56	885	(__IO uint16_t)Address = Data;
ebrus	0:0a673c671a56	886	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	887	status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
ebrus	0:0a673c671a56	888
ebrus	0:0a673c671a56	889	/* Disable the PG Bit */
ebrus	0:0a673c671a56	890	FLASH->CR &= CR_PG_Reset;
ebrus	0:0a673c671a56	891	}
ebrus	0:0a673c671a56	892	}
ebrus	0:0a673c671a56	893	else
ebrus	0:0a673c671a56	894	{
ebrus	0:0a673c671a56	895	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	896	{
ebrus	0:0a673c671a56	897	/* if the previous operation is completed, proceed to program the new data */
ebrus	0:0a673c671a56	898	FLASH->CR2 \|= CR_PG_Set;
ebrus	0:0a673c671a56	899
ebrus	0:0a673c671a56	900	(__IO uint16_t)Address = Data;
ebrus	0:0a673c671a56	901	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	902	status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
ebrus	0:0a673c671a56	903
ebrus	0:0a673c671a56	904	/* Disable the PG Bit */
ebrus	0:0a673c671a56	905	FLASH->CR2 &= CR_PG_Reset;
ebrus	0:0a673c671a56	906	}
ebrus	0:0a673c671a56	907	}
ebrus	0:0a673c671a56	908	#else
ebrus	0:0a673c671a56	909	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	910	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	911
ebrus	0:0a673c671a56	912	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	913	{
ebrus	0:0a673c671a56	914	/* if the previous operation is completed, proceed to program the new data */
ebrus	0:0a673c671a56	915	FLASH->CR \|= CR_PG_Set;
ebrus	0:0a673c671a56	916
ebrus	0:0a673c671a56	917	(__IO uint16_t)Address = Data;
ebrus	0:0a673c671a56	918	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	919	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	920
ebrus	0:0a673c671a56	921	/* Disable the PG Bit */
ebrus	0:0a673c671a56	922	FLASH->CR &= CR_PG_Reset;
ebrus	0:0a673c671a56	923	}
ebrus	0:0a673c671a56	924	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	925
ebrus	0:0a673c671a56	926	/* Return the Program Status */
ebrus	0:0a673c671a56	927	return status;
ebrus	0:0a673c671a56	928	}
ebrus	0:0a673c671a56	929
ebrus	0:0a673c671a56	930	/**
ebrus	0:0a673c671a56	931	* @brief Programs a half word at a specified Option Byte Data address.
ebrus	0:0a673c671a56	932	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	933	* @param Address: specifies the address to be programmed.
ebrus	0:0a673c671a56	934	* This parameter can be 0x1FFFF804 or 0x1FFFF806.
ebrus	0:0a673c671a56	935	* @param Data: specifies the data to be programmed.
ebrus	0:0a673c671a56	936	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	937	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	938	*/
ebrus	0:0a673c671a56	939	FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
ebrus	0:0a673c671a56	940	{
ebrus	0:0a673c671a56	941	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	942	/* Check the parameters */
ebrus	0:0a673c671a56	943	assert_param(IS_OB_DATA_ADDRESS(Address));
ebrus	0:0a673c671a56	944	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	945
ebrus	0:0a673c671a56	946	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	947	{
ebrus	0:0a673c671a56	948	/* Authorize the small information block programming */
ebrus	0:0a673c671a56	949	FLASH->OPTKEYR = FLASH_KEY1;
ebrus	0:0a673c671a56	950	FLASH->OPTKEYR = FLASH_KEY2;
ebrus	0:0a673c671a56	951	/* Enables the Option Bytes Programming operation */
ebrus	0:0a673c671a56	952	FLASH->CR \|= CR_OPTPG_Set;
ebrus	0:0a673c671a56	953	(__IO uint16_t)Address = Data;
ebrus	0:0a673c671a56	954
ebrus	0:0a673c671a56	955	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	956	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	957	if(status != FLASH_TIMEOUT)
ebrus	0:0a673c671a56	958	{
ebrus	0:0a673c671a56	959	/* if the program operation is completed, disable the OPTPG Bit */
ebrus	0:0a673c671a56	960	FLASH->CR &= CR_OPTPG_Reset;
ebrus	0:0a673c671a56	961	}
ebrus	0:0a673c671a56	962	}
ebrus	0:0a673c671a56	963	/* Return the Option Byte Data Program Status */
ebrus	0:0a673c671a56	964	return status;
ebrus	0:0a673c671a56	965	}
ebrus	0:0a673c671a56	966
ebrus	0:0a673c671a56	967	/**
ebrus	0:0a673c671a56	968	* @brief Write protects the desired pages
ebrus	0:0a673c671a56	969	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	970	* @param FLASH_Pages: specifies the address of the pages to be write protected.
ebrus	0:0a673c671a56	971	* This parameter can be:
ebrus	0:0a673c671a56	972	* @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31
ebrus	0:0a673c671a56	973	* @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3
ebrus	0:0a673c671a56	974	* and FLASH_WRProt_Pages124to127
ebrus	0:0a673c671a56	975	* @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and
ebrus	0:0a673c671a56	976	* FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
ebrus	0:0a673c671a56	977	* @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and
ebrus	0:0a673c671a56	978	* FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127
ebrus	0:0a673c671a56	979	* @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and
ebrus	0:0a673c671a56	980	* FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511
ebrus	0:0a673c671a56	981	* @arg FLASH_WRProt_AllPages
ebrus	0:0a673c671a56	982	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	983	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	984	*/
ebrus	0:0a673c671a56	985	FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
ebrus	0:0a673c671a56	986	{
ebrus	0:0a673c671a56	987	uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
ebrus	0:0a673c671a56	988
ebrus	0:0a673c671a56	989	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	990
ebrus	0:0a673c671a56	991	/* Check the parameters */
ebrus	0:0a673c671a56	992	assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
ebrus	0:0a673c671a56	993
ebrus	0:0a673c671a56	994	FLASH_Pages = (uint32_t)(~FLASH_Pages);
ebrus	0:0a673c671a56	995	WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
ebrus	0:0a673c671a56	996	WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
ebrus	0:0a673c671a56	997	WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
ebrus	0:0a673c671a56	998	WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
ebrus	0:0a673c671a56	999
ebrus	0:0a673c671a56	1000	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	1001	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	1002
ebrus	0:0a673c671a56	1003	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	1004	{
ebrus	0:0a673c671a56	1005	/* Authorizes the small information block programming */
ebrus	0:0a673c671a56	1006	FLASH->OPTKEYR = FLASH_KEY1;
ebrus	0:0a673c671a56	1007	FLASH->OPTKEYR = FLASH_KEY2;
ebrus	0:0a673c671a56	1008	FLASH->CR \|= CR_OPTPG_Set;
ebrus	0:0a673c671a56	1009	if(WRP0_Data != 0xFF)
ebrus	0:0a673c671a56	1010	{
ebrus	0:0a673c671a56	1011	OB->WRP0 = WRP0_Data;
ebrus	0:0a673c671a56	1012
ebrus	0:0a673c671a56	1013	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	1014	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	1015	}
ebrus	0:0a673c671a56	1016	if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
ebrus	0:0a673c671a56	1017	{
ebrus	0:0a673c671a56	1018	OB->WRP1 = WRP1_Data;
ebrus	0:0a673c671a56	1019
ebrus	0:0a673c671a56	1020	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	1021	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	1022	}
ebrus	0:0a673c671a56	1023	if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
ebrus	0:0a673c671a56	1024	{
ebrus	0:0a673c671a56	1025	OB->WRP2 = WRP2_Data;
ebrus	0:0a673c671a56	1026
ebrus	0:0a673c671a56	1027	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	1028	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	1029	}
ebrus	0:0a673c671a56	1030
ebrus	0:0a673c671a56	1031	if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
ebrus	0:0a673c671a56	1032	{
ebrus	0:0a673c671a56	1033	OB->WRP3 = WRP3_Data;
ebrus	0:0a673c671a56	1034
ebrus	0:0a673c671a56	1035	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	1036	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	1037	}
ebrus	0:0a673c671a56	1038
ebrus	0:0a673c671a56	1039	if(status != FLASH_TIMEOUT)
ebrus	0:0a673c671a56	1040	{
ebrus	0:0a673c671a56	1041	/* if the program operation is completed, disable the OPTPG Bit */
ebrus	0:0a673c671a56	1042	FLASH->CR &= CR_OPTPG_Reset;
ebrus	0:0a673c671a56	1043	}
ebrus	0:0a673c671a56	1044	}
ebrus	0:0a673c671a56	1045	/* Return the write protection operation Status */
ebrus	0:0a673c671a56	1046	return status;
ebrus	0:0a673c671a56	1047	}
ebrus	0:0a673c671a56	1048
ebrus	0:0a673c671a56	1049	/**
ebrus	0:0a673c671a56	1050	* @brief Enables or disables the read out protection.
ebrus	0:0a673c671a56	1051	* @note If the user has already programmed the other option bytes before calling
ebrus	0:0a673c671a56	1052	* this function, he must re-program them since this function erases all option bytes.
ebrus	0:0a673c671a56	1053	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	1054	* @param Newstate: new state of the ReadOut Protection.
ebrus	0:0a673c671a56	1055	* This parameter can be: ENABLE or DISABLE.
ebrus	0:0a673c671a56	1056	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	1057	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	1058	*/
ebrus	0:0a673c671a56	1059	FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
ebrus	0:0a673c671a56	1060	{
ebrus	0:0a673c671a56	1061	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	1062	/* Check the parameters */
ebrus	0:0a673c671a56	1063	assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus	0:0a673c671a56	1064	status = FLASH_WaitForLastOperation(EraseTimeout);
ebrus	0:0a673c671a56	1065	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	1066	{
ebrus	0:0a673c671a56	1067	/* Authorizes the small information block programming */
ebrus	0:0a673c671a56	1068	FLASH->OPTKEYR = FLASH_KEY1;
ebrus	0:0a673c671a56	1069	FLASH->OPTKEYR = FLASH_KEY2;
ebrus	0:0a673c671a56	1070	FLASH->CR \|= CR_OPTER_Set;
ebrus	0:0a673c671a56	1071	FLASH->CR \|= CR_STRT_Set;
ebrus	0:0a673c671a56	1072	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	1073	status = FLASH_WaitForLastOperation(EraseTimeout);
ebrus	0:0a673c671a56	1074	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	1075	{
ebrus	0:0a673c671a56	1076	/* if the erase operation is completed, disable the OPTER Bit */
ebrus	0:0a673c671a56	1077	FLASH->CR &= CR_OPTER_Reset;
ebrus	0:0a673c671a56	1078	/* Enable the Option Bytes Programming operation */
ebrus	0:0a673c671a56	1079	FLASH->CR \|= CR_OPTPG_Set;
ebrus	0:0a673c671a56	1080	if(NewState != DISABLE)
ebrus	0:0a673c671a56	1081	{
ebrus	0:0a673c671a56	1082	OB->RDP = 0x00;
ebrus	0:0a673c671a56	1083	}
ebrus	0:0a673c671a56	1084	else
ebrus	0:0a673c671a56	1085	{
ebrus	0:0a673c671a56	1086	OB->RDP = RDP_Key;
ebrus	0:0a673c671a56	1087	}
ebrus	0:0a673c671a56	1088	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	1089	status = FLASH_WaitForLastOperation(EraseTimeout);
ebrus	0:0a673c671a56	1090
ebrus	0:0a673c671a56	1091	if(status != FLASH_TIMEOUT)
ebrus	0:0a673c671a56	1092	{
ebrus	0:0a673c671a56	1093	/* if the program operation is completed, disable the OPTPG Bit */
ebrus	0:0a673c671a56	1094	FLASH->CR &= CR_OPTPG_Reset;
ebrus	0:0a673c671a56	1095	}
ebrus	0:0a673c671a56	1096	}
ebrus	0:0a673c671a56	1097	else
ebrus	0:0a673c671a56	1098	{
ebrus	0:0a673c671a56	1099	if(status != FLASH_TIMEOUT)
ebrus	0:0a673c671a56	1100	{
ebrus	0:0a673c671a56	1101	/* Disable the OPTER Bit */
ebrus	0:0a673c671a56	1102	FLASH->CR &= CR_OPTER_Reset;
ebrus	0:0a673c671a56	1103	}
ebrus	0:0a673c671a56	1104	}
ebrus	0:0a673c671a56	1105	}
ebrus	0:0a673c671a56	1106	/* Return the protection operation Status */
ebrus	0:0a673c671a56	1107	return status;
ebrus	0:0a673c671a56	1108	}
ebrus	0:0a673c671a56	1109
ebrus	0:0a673c671a56	1110	/**
ebrus	0:0a673c671a56	1111	* @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
ebrus	0:0a673c671a56	1112	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	1113	* @param OB_IWDG: Selects the IWDG mode
ebrus	0:0a673c671a56	1114	* This parameter can be one of the following values:
ebrus	0:0a673c671a56	1115	* @arg OB_IWDG_SW: Software IWDG selected
ebrus	0:0a673c671a56	1116	* @arg OB_IWDG_HW: Hardware IWDG selected
ebrus	0:0a673c671a56	1117	* @param OB_STOP: Reset event when entering STOP mode.
ebrus	0:0a673c671a56	1118	* This parameter can be one of the following values:
ebrus	0:0a673c671a56	1119	* @arg OB_STOP_NoRST: No reset generated when entering in STOP
ebrus	0:0a673c671a56	1120	* @arg OB_STOP_RST: Reset generated when entering in STOP
ebrus	0:0a673c671a56	1121	* @param OB_STDBY: Reset event when entering Standby mode.
ebrus	0:0a673c671a56	1122	* This parameter can be one of the following values:
ebrus	0:0a673c671a56	1123	* @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
ebrus	0:0a673c671a56	1124	* @arg OB_STDBY_RST: Reset generated when entering in STANDBY
ebrus	0:0a673c671a56	1125	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	1126	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	1127	*/
ebrus	0:0a673c671a56	1128	FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
ebrus	0:0a673c671a56	1129	{
ebrus	0:0a673c671a56	1130	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	1131
ebrus	0:0a673c671a56	1132	/* Check the parameters */
ebrus	0:0a673c671a56	1133	assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
ebrus	0:0a673c671a56	1134	assert_param(IS_OB_STOP_SOURCE(OB_STOP));
ebrus	0:0a673c671a56	1135	assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
ebrus	0:0a673c671a56	1136
ebrus	0:0a673c671a56	1137	/* Authorize the small information block programming */
ebrus	0:0a673c671a56	1138	FLASH->OPTKEYR = FLASH_KEY1;
ebrus	0:0a673c671a56	1139	FLASH->OPTKEYR = FLASH_KEY2;
ebrus	0:0a673c671a56	1140
ebrus	0:0a673c671a56	1141	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	1142	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	1143
ebrus	0:0a673c671a56	1144	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	1145	{
ebrus	0:0a673c671a56	1146	/* Enable the Option Bytes Programming operation */
ebrus	0:0a673c671a56	1147	FLASH->CR \|= CR_OPTPG_Set;
ebrus	0:0a673c671a56	1148
ebrus	0:0a673c671a56	1149	OB->USER = OB_IWDG \| (uint16_t)(OB_STOP \| (uint16_t)(OB_STDBY \| ((uint16_t)0xF8)));
ebrus	0:0a673c671a56	1150
ebrus	0:0a673c671a56	1151	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	1152	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	1153	if(status != FLASH_TIMEOUT)
ebrus	0:0a673c671a56	1154	{
ebrus	0:0a673c671a56	1155	/* if the program operation is completed, disable the OPTPG Bit */
ebrus	0:0a673c671a56	1156	FLASH->CR &= CR_OPTPG_Reset;
ebrus	0:0a673c671a56	1157	}
ebrus	0:0a673c671a56	1158	}
ebrus	0:0a673c671a56	1159	/* Return the Option Byte program Status */
ebrus	0:0a673c671a56	1160	return status;
ebrus	0:0a673c671a56	1161	}
ebrus	0:0a673c671a56	1162
ebrus	0:0a673c671a56	1163	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	1164	/**
ebrus	0:0a673c671a56	1165	* @brief Configures to boot from Bank1 or Bank2.
ebrus	0:0a673c671a56	1166	* @note This function can be used only for STM32F10x_XL density devices.
ebrus	0:0a673c671a56	1167	* @param FLASH_BOOT: select the FLASH Bank to boot from.
ebrus	0:0a673c671a56	1168	* This parameter can be one of the following values:
ebrus	0:0a673c671a56	1169	* @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash
ebrus	0:0a673c671a56	1170	* position and this parameter is selected the device will boot from Bank1(Default).
ebrus	0:0a673c671a56	1171	* @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash
ebrus	0:0a673c671a56	1172	* position and this parameter is selected the device will boot from Bank2 or Bank1,
ebrus	0:0a673c671a56	1173	* depending on the activation of the bank. The active banks are checked in
ebrus	0:0a673c671a56	1174	* the following order: Bank2, followed by Bank1.
ebrus	0:0a673c671a56	1175	* The active bank is recognized by the value programmed at the base address
ebrus	0:0a673c671a56	1176	* of the respective bank (corresponding to the initial stack pointer value
ebrus	0:0a673c671a56	1177	* in the interrupt vector table).
ebrus	0:0a673c671a56	1178	* For more information, please refer to AN2606 from www.st.com.
ebrus	0:0a673c671a56	1179	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	1180	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	1181	*/
ebrus	0:0a673c671a56	1182	FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)
ebrus	0:0a673c671a56	1183	{
ebrus	0:0a673c671a56	1184	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	1185	assert_param(IS_FLASH_BOOT(FLASH_BOOT));
ebrus	0:0a673c671a56	1186	/* Authorize the small information block programming */
ebrus	0:0a673c671a56	1187	FLASH->OPTKEYR = FLASH_KEY1;
ebrus	0:0a673c671a56	1188	FLASH->OPTKEYR = FLASH_KEY2;
ebrus	0:0a673c671a56	1189
ebrus	0:0a673c671a56	1190	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	1191	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	1192
ebrus	0:0a673c671a56	1193	if(status == FLASH_COMPLETE)
ebrus	0:0a673c671a56	1194	{
ebrus	0:0a673c671a56	1195	/* Enable the Option Bytes Programming operation */
ebrus	0:0a673c671a56	1196	FLASH->CR \|= CR_OPTPG_Set;
ebrus	0:0a673c671a56	1197
ebrus	0:0a673c671a56	1198	if(FLASH_BOOT == FLASH_BOOT_Bank1)
ebrus	0:0a673c671a56	1199	{
ebrus	0:0a673c671a56	1200	OB->USER \|= OB_USER_BFB2;
ebrus	0:0a673c671a56	1201	}
ebrus	0:0a673c671a56	1202	else
ebrus	0:0a673c671a56	1203	{
ebrus	0:0a673c671a56	1204	OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));
ebrus	0:0a673c671a56	1205	}
ebrus	0:0a673c671a56	1206	/* Wait for last operation to be completed */
ebrus	0:0a673c671a56	1207	status = FLASH_WaitForLastOperation(ProgramTimeout);
ebrus	0:0a673c671a56	1208	if(status != FLASH_TIMEOUT)
ebrus	0:0a673c671a56	1209	{
ebrus	0:0a673c671a56	1210	/* if the program operation is completed, disable the OPTPG Bit */
ebrus	0:0a673c671a56	1211	FLASH->CR &= CR_OPTPG_Reset;
ebrus	0:0a673c671a56	1212	}
ebrus	0:0a673c671a56	1213	}
ebrus	0:0a673c671a56	1214	/* Return the Option Byte program Status */
ebrus	0:0a673c671a56	1215	return status;
ebrus	0:0a673c671a56	1216	}
ebrus	0:0a673c671a56	1217	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	1218
ebrus	0:0a673c671a56	1219	/**
ebrus	0:0a673c671a56	1220	* @brief Returns the FLASH User Option Bytes values.
ebrus	0:0a673c671a56	1221	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	1222	* @param None
ebrus	0:0a673c671a56	1223	* @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
ebrus	0:0a673c671a56	1224	* and RST_STDBY(Bit2).
ebrus	0:0a673c671a56	1225	*/
ebrus	0:0a673c671a56	1226	uint32_t FLASH_GetUserOptionByte(void)
ebrus	0:0a673c671a56	1227	{
ebrus	0:0a673c671a56	1228	/* Return the User Option Byte */
ebrus	0:0a673c671a56	1229	return (uint32_t)(FLASH->OBR >> 2);
ebrus	0:0a673c671a56	1230	}
ebrus	0:0a673c671a56	1231
ebrus	0:0a673c671a56	1232	/**
ebrus	0:0a673c671a56	1233	* @brief Returns the FLASH Write Protection Option Bytes Register value.
ebrus	0:0a673c671a56	1234	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	1235	* @param None
ebrus	0:0a673c671a56	1236	* @retval The FLASH Write Protection Option Bytes Register value
ebrus	0:0a673c671a56	1237	*/
ebrus	0:0a673c671a56	1238	uint32_t FLASH_GetWriteProtectionOptionByte(void)
ebrus	0:0a673c671a56	1239	{
ebrus	0:0a673c671a56	1240	/* Return the Flash write protection Register value */
ebrus	0:0a673c671a56	1241	return (uint32_t)(FLASH->WRPR);
ebrus	0:0a673c671a56	1242	}
ebrus	0:0a673c671a56	1243
ebrus	0:0a673c671a56	1244	/**
ebrus	0:0a673c671a56	1245	* @brief Checks whether the FLASH Read Out Protection Status is set or not.
ebrus	0:0a673c671a56	1246	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	1247	* @param None
ebrus	0:0a673c671a56	1248	* @retval FLASH ReadOut Protection Status(SET or RESET)
ebrus	0:0a673c671a56	1249	*/
ebrus	0:0a673c671a56	1250	FlagStatus FLASH_GetReadOutProtectionStatus(void)
ebrus	0:0a673c671a56	1251	{
ebrus	0:0a673c671a56	1252	FlagStatus readoutstatus = RESET;
ebrus	0:0a673c671a56	1253	if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
ebrus	0:0a673c671a56	1254	{
ebrus	0:0a673c671a56	1255	readoutstatus = SET;
ebrus	0:0a673c671a56	1256	}
ebrus	0:0a673c671a56	1257	else
ebrus	0:0a673c671a56	1258	{
ebrus	0:0a673c671a56	1259	readoutstatus = RESET;
ebrus	0:0a673c671a56	1260	}
ebrus	0:0a673c671a56	1261	return readoutstatus;
ebrus	0:0a673c671a56	1262	}
ebrus	0:0a673c671a56	1263
ebrus	0:0a673c671a56	1264	/**
ebrus	0:0a673c671a56	1265	* @brief Checks whether the FLASH Prefetch Buffer status is set or not.
ebrus	0:0a673c671a56	1266	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	1267	* @param None
ebrus	0:0a673c671a56	1268	* @retval FLASH Prefetch Buffer Status (SET or RESET).
ebrus	0:0a673c671a56	1269	*/
ebrus	0:0a673c671a56	1270	FlagStatus FLASH_GetPrefetchBufferStatus(void)
ebrus	0:0a673c671a56	1271	{
ebrus	0:0a673c671a56	1272	FlagStatus bitstatus = RESET;
ebrus	0:0a673c671a56	1273
ebrus	0:0a673c671a56	1274	if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
ebrus	0:0a673c671a56	1275	{
ebrus	0:0a673c671a56	1276	bitstatus = SET;
ebrus	0:0a673c671a56	1277	}
ebrus	0:0a673c671a56	1278	else
ebrus	0:0a673c671a56	1279	{
ebrus	0:0a673c671a56	1280	bitstatus = RESET;
ebrus	0:0a673c671a56	1281	}
ebrus	0:0a673c671a56	1282	/* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
ebrus	0:0a673c671a56	1283	return bitstatus;
ebrus	0:0a673c671a56	1284	}
ebrus	0:0a673c671a56	1285
ebrus	0:0a673c671a56	1286	/**
ebrus	0:0a673c671a56	1287	* @brief Enables or disables the specified FLASH interrupts.
ebrus	0:0a673c671a56	1288	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	1289	* - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts
ebrus	0:0a673c671a56	1290	for Bank1 and Bank2.
ebrus	0:0a673c671a56	1291	* - For other devices it enables or disables the specified FLASH interrupts for Bank1.
ebrus	0:0a673c671a56	1292	* @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
ebrus	0:0a673c671a56	1293	* This parameter can be any combination of the following values:
ebrus	0:0a673c671a56	1294	* @arg FLASH_IT_ERROR: FLASH Error Interrupt
ebrus	0:0a673c671a56	1295	* @arg FLASH_IT_EOP: FLASH end of operation Interrupt
ebrus	0:0a673c671a56	1296	* @param NewState: new state of the specified Flash interrupts.
ebrus	0:0a673c671a56	1297	* This parameter can be: ENABLE or DISABLE.
ebrus	0:0a673c671a56	1298	* @retval None
ebrus	0:0a673c671a56	1299	*/
ebrus	0:0a673c671a56	1300	void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
ebrus	0:0a673c671a56	1301	{
ebrus	0:0a673c671a56	1302	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	1303	/* Check the parameters */
ebrus	0:0a673c671a56	1304	assert_param(IS_FLASH_IT(FLASH_IT));
ebrus	0:0a673c671a56	1305	assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus	0:0a673c671a56	1306
ebrus	0:0a673c671a56	1307	if((FLASH_IT & 0x80000000) != 0x0)
ebrus	0:0a673c671a56	1308	{
ebrus	0:0a673c671a56	1309	if(NewState != DISABLE)
ebrus	0:0a673c671a56	1310	{
ebrus	0:0a673c671a56	1311	/* Enable the interrupt sources */
ebrus	0:0a673c671a56	1312	FLASH->CR2 \|= (FLASH_IT & 0x7FFFFFFF);
ebrus	0:0a673c671a56	1313	}
ebrus	0:0a673c671a56	1314	else
ebrus	0:0a673c671a56	1315	{
ebrus	0:0a673c671a56	1316	/* Disable the interrupt sources */
ebrus	0:0a673c671a56	1317	FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);
ebrus	0:0a673c671a56	1318	}
ebrus	0:0a673c671a56	1319	}
ebrus	0:0a673c671a56	1320	else
ebrus	0:0a673c671a56	1321	{
ebrus	0:0a673c671a56	1322	if(NewState != DISABLE)
ebrus	0:0a673c671a56	1323	{
ebrus	0:0a673c671a56	1324	/* Enable the interrupt sources */
ebrus	0:0a673c671a56	1325	FLASH->CR \|= FLASH_IT;
ebrus	0:0a673c671a56	1326	}
ebrus	0:0a673c671a56	1327	else
ebrus	0:0a673c671a56	1328	{
ebrus	0:0a673c671a56	1329	/* Disable the interrupt sources */
ebrus	0:0a673c671a56	1330	FLASH->CR &= ~(uint32_t)FLASH_IT;
ebrus	0:0a673c671a56	1331	}
ebrus	0:0a673c671a56	1332	}
ebrus	0:0a673c671a56	1333	#else
ebrus	0:0a673c671a56	1334	/* Check the parameters */
ebrus	0:0a673c671a56	1335	assert_param(IS_FLASH_IT(FLASH_IT));
ebrus	0:0a673c671a56	1336	assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus	0:0a673c671a56	1337
ebrus	0:0a673c671a56	1338	if(NewState != DISABLE)
ebrus	0:0a673c671a56	1339	{
ebrus	0:0a673c671a56	1340	/* Enable the interrupt sources */
ebrus	0:0a673c671a56	1341	FLASH->CR \|= FLASH_IT;
ebrus	0:0a673c671a56	1342	}
ebrus	0:0a673c671a56	1343	else
ebrus	0:0a673c671a56	1344	{
ebrus	0:0a673c671a56	1345	/* Disable the interrupt sources */
ebrus	0:0a673c671a56	1346	FLASH->CR &= ~(uint32_t)FLASH_IT;
ebrus	0:0a673c671a56	1347	}
ebrus	0:0a673c671a56	1348	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	1349	}
ebrus	0:0a673c671a56	1350
ebrus	0:0a673c671a56	1351	/**
ebrus	0:0a673c671a56	1352	* @brief Checks whether the specified FLASH flag is set or not.
ebrus	0:0a673c671a56	1353	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	1354	* - For STM32F10X_XL devices, this function checks whether the specified
ebrus	0:0a673c671a56	1355	* Bank1 or Bank2 flag is set or not.
ebrus	0:0a673c671a56	1356	* - For other devices, it checks whether the specified Bank1 flag is
ebrus	0:0a673c671a56	1357	* set or not.
ebrus	0:0a673c671a56	1358	* @param FLASH_FLAG: specifies the FLASH flag to check.
ebrus	0:0a673c671a56	1359	* This parameter can be one of the following values:
ebrus	0:0a673c671a56	1360	* @arg FLASH_FLAG_BSY: FLASH Busy flag
ebrus	0:0a673c671a56	1361	* @arg FLASH_FLAG_PGERR: FLASH Program error flag
ebrus	0:0a673c671a56	1362	* @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
ebrus	0:0a673c671a56	1363	* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
ebrus	0:0a673c671a56	1364	* @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag
ebrus	0:0a673c671a56	1365	* @retval The new state of FLASH_FLAG (SET or RESET).
ebrus	0:0a673c671a56	1366	*/
ebrus	0:0a673c671a56	1367	FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
ebrus	0:0a673c671a56	1368	{
ebrus	0:0a673c671a56	1369	FlagStatus bitstatus = RESET;
ebrus	0:0a673c671a56	1370
ebrus	0:0a673c671a56	1371	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	1372	/* Check the parameters */
ebrus	0:0a673c671a56	1373	assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
ebrus	0:0a673c671a56	1374	if(FLASH_FLAG == FLASH_FLAG_OPTERR)
ebrus	0:0a673c671a56	1375	{
ebrus	0:0a673c671a56	1376	if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
ebrus	0:0a673c671a56	1377	{
ebrus	0:0a673c671a56	1378	bitstatus = SET;
ebrus	0:0a673c671a56	1379	}
ebrus	0:0a673c671a56	1380	else
ebrus	0:0a673c671a56	1381	{
ebrus	0:0a673c671a56	1382	bitstatus = RESET;
ebrus	0:0a673c671a56	1383	}
ebrus	0:0a673c671a56	1384	}
ebrus	0:0a673c671a56	1385	else
ebrus	0:0a673c671a56	1386	{
ebrus	0:0a673c671a56	1387	if((FLASH_FLAG & 0x80000000) != 0x0)
ebrus	0:0a673c671a56	1388	{
ebrus	0:0a673c671a56	1389	if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)
ebrus	0:0a673c671a56	1390	{
ebrus	0:0a673c671a56	1391	bitstatus = SET;
ebrus	0:0a673c671a56	1392	}
ebrus	0:0a673c671a56	1393	else
ebrus	0:0a673c671a56	1394	{
ebrus	0:0a673c671a56	1395	bitstatus = RESET;
ebrus	0:0a673c671a56	1396	}
ebrus	0:0a673c671a56	1397	}
ebrus	0:0a673c671a56	1398	else
ebrus	0:0a673c671a56	1399	{
ebrus	0:0a673c671a56	1400	if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
ebrus	0:0a673c671a56	1401	{
ebrus	0:0a673c671a56	1402	bitstatus = SET;
ebrus	0:0a673c671a56	1403	}
ebrus	0:0a673c671a56	1404	else
ebrus	0:0a673c671a56	1405	{
ebrus	0:0a673c671a56	1406	bitstatus = RESET;
ebrus	0:0a673c671a56	1407	}
ebrus	0:0a673c671a56	1408	}
ebrus	0:0a673c671a56	1409	}
ebrus	0:0a673c671a56	1410	#else
ebrus	0:0a673c671a56	1411	/* Check the parameters */
ebrus	0:0a673c671a56	1412	assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
ebrus	0:0a673c671a56	1413	if(FLASH_FLAG == FLASH_FLAG_OPTERR)
ebrus	0:0a673c671a56	1414	{
ebrus	0:0a673c671a56	1415	if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
ebrus	0:0a673c671a56	1416	{
ebrus	0:0a673c671a56	1417	bitstatus = SET;
ebrus	0:0a673c671a56	1418	}
ebrus	0:0a673c671a56	1419	else
ebrus	0:0a673c671a56	1420	{
ebrus	0:0a673c671a56	1421	bitstatus = RESET;
ebrus	0:0a673c671a56	1422	}
ebrus	0:0a673c671a56	1423	}
ebrus	0:0a673c671a56	1424	else
ebrus	0:0a673c671a56	1425	{
ebrus	0:0a673c671a56	1426	if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
ebrus	0:0a673c671a56	1427	{
ebrus	0:0a673c671a56	1428	bitstatus = SET;
ebrus	0:0a673c671a56	1429	}
ebrus	0:0a673c671a56	1430	else
ebrus	0:0a673c671a56	1431	{
ebrus	0:0a673c671a56	1432	bitstatus = RESET;
ebrus	0:0a673c671a56	1433	}
ebrus	0:0a673c671a56	1434	}
ebrus	0:0a673c671a56	1435	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	1436
ebrus	0:0a673c671a56	1437	/* Return the new state of FLASH_FLAG (SET or RESET) */
ebrus	0:0a673c671a56	1438	return bitstatus;
ebrus	0:0a673c671a56	1439	}
ebrus	0:0a673c671a56	1440
ebrus	0:0a673c671a56	1441	/**
ebrus	0:0a673c671a56	1442	* @brief Clears the FLASH's pending flags.
ebrus	0:0a673c671a56	1443	* @note This function can be used for all STM32F10x devices.
ebrus	0:0a673c671a56	1444	* - For STM32F10X_XL devices, this function clears Bank1 or Bank2s pending flags
ebrus	0:0a673c671a56	1445	* - For other devices, it clears Bank1s pending flags.
ebrus	0:0a673c671a56	1446	* @param FLASH_FLAG: specifies the FLASH flags to clear.
ebrus	0:0a673c671a56	1447	* This parameter can be any combination of the following values:
ebrus	0:0a673c671a56	1448	* @arg FLASH_FLAG_PGERR: FLASH Program error flag
ebrus	0:0a673c671a56	1449	* @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
ebrus	0:0a673c671a56	1450	* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
ebrus	0:0a673c671a56	1451	* @retval None
ebrus	0:0a673c671a56	1452	*/
ebrus	0:0a673c671a56	1453	void FLASH_ClearFlag(uint32_t FLASH_FLAG)
ebrus	0:0a673c671a56	1454	{
ebrus	0:0a673c671a56	1455	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	1456	/* Check the parameters */
ebrus	0:0a673c671a56	1457	assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
ebrus	0:0a673c671a56	1458
ebrus	0:0a673c671a56	1459	if((FLASH_FLAG & 0x80000000) != 0x0)
ebrus	0:0a673c671a56	1460	{
ebrus	0:0a673c671a56	1461	/* Clear the flags */
ebrus	0:0a673c671a56	1462	FLASH->SR2 = FLASH_FLAG;
ebrus	0:0a673c671a56	1463	}
ebrus	0:0a673c671a56	1464	else
ebrus	0:0a673c671a56	1465	{
ebrus	0:0a673c671a56	1466	/* Clear the flags */
ebrus	0:0a673c671a56	1467	FLASH->SR = FLASH_FLAG;
ebrus	0:0a673c671a56	1468	}
ebrus	0:0a673c671a56	1469
ebrus	0:0a673c671a56	1470	#else
ebrus	0:0a673c671a56	1471	/* Check the parameters */
ebrus	0:0a673c671a56	1472	assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
ebrus	0:0a673c671a56	1473
ebrus	0:0a673c671a56	1474	/* Clear the flags */
ebrus	0:0a673c671a56	1475	FLASH->SR = FLASH_FLAG;
ebrus	0:0a673c671a56	1476	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	1477	}
ebrus	0:0a673c671a56	1478
ebrus	0:0a673c671a56	1479	/**
ebrus	0:0a673c671a56	1480	* @brief Returns the FLASH Status.
ebrus	0:0a673c671a56	1481	* @note This function can be used for all STM32F10x devices, it is equivalent
ebrus	0:0a673c671a56	1482	* to FLASH_GetBank1Status function.
ebrus	0:0a673c671a56	1483	* @param None
ebrus	0:0a673c671a56	1484	* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
ebrus	0:0a673c671a56	1485	* FLASH_ERROR_WRP or FLASH_COMPLETE
ebrus	0:0a673c671a56	1486	*/
ebrus	0:0a673c671a56	1487	FLASH_Status FLASH_GetStatus(void)
ebrus	0:0a673c671a56	1488	{
ebrus	0:0a673c671a56	1489	FLASH_Status flashstatus = FLASH_COMPLETE;
ebrus	0:0a673c671a56	1490
ebrus	0:0a673c671a56	1491	if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
ebrus	0:0a673c671a56	1492	{
ebrus	0:0a673c671a56	1493	flashstatus = FLASH_BUSY;
ebrus	0:0a673c671a56	1494	}
ebrus	0:0a673c671a56	1495	else
ebrus	0:0a673c671a56	1496	{
ebrus	0:0a673c671a56	1497	if((FLASH->SR & FLASH_FLAG_PGERR) != 0)
ebrus	0:0a673c671a56	1498	{
ebrus	0:0a673c671a56	1499	flashstatus = FLASH_ERROR_PG;
ebrus	0:0a673c671a56	1500	}
ebrus	0:0a673c671a56	1501	else
ebrus	0:0a673c671a56	1502	{
ebrus	0:0a673c671a56	1503	if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )
ebrus	0:0a673c671a56	1504	{
ebrus	0:0a673c671a56	1505	flashstatus = FLASH_ERROR_WRP;
ebrus	0:0a673c671a56	1506	}
ebrus	0:0a673c671a56	1507	else
ebrus	0:0a673c671a56	1508	{
ebrus	0:0a673c671a56	1509	flashstatus = FLASH_COMPLETE;
ebrus	0:0a673c671a56	1510	}
ebrus	0:0a673c671a56	1511	}
ebrus	0:0a673c671a56	1512	}
ebrus	0:0a673c671a56	1513	/* Return the Flash Status */
ebrus	0:0a673c671a56	1514	return flashstatus;
ebrus	0:0a673c671a56	1515	}
ebrus	0:0a673c671a56	1516
ebrus	0:0a673c671a56	1517	/**
ebrus	0:0a673c671a56	1518	* @brief Returns the FLASH Bank1 Status.
ebrus	0:0a673c671a56	1519	* @note This function can be used for all STM32F10x devices, it is equivalent
ebrus	0:0a673c671a56	1520	* to FLASH_GetStatus function.
ebrus	0:0a673c671a56	1521	* @param None
ebrus	0:0a673c671a56	1522	* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
ebrus	0:0a673c671a56	1523	* FLASH_ERROR_WRP or FLASH_COMPLETE
ebrus	0:0a673c671a56	1524	*/
ebrus	0:0a673c671a56	1525	FLASH_Status FLASH_GetBank1Status(void)
ebrus	0:0a673c671a56	1526	{
ebrus	0:0a673c671a56	1527	FLASH_Status flashstatus = FLASH_COMPLETE;
ebrus	0:0a673c671a56	1528
ebrus	0:0a673c671a56	1529	if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
ebrus	0:0a673c671a56	1530	{
ebrus	0:0a673c671a56	1531	flashstatus = FLASH_BUSY;
ebrus	0:0a673c671a56	1532	}
ebrus	0:0a673c671a56	1533	else
ebrus	0:0a673c671a56	1534	{
ebrus	0:0a673c671a56	1535	if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)
ebrus	0:0a673c671a56	1536	{
ebrus	0:0a673c671a56	1537	flashstatus = FLASH_ERROR_PG;
ebrus	0:0a673c671a56	1538	}
ebrus	0:0a673c671a56	1539	else
ebrus	0:0a673c671a56	1540	{
ebrus	0:0a673c671a56	1541	if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )
ebrus	0:0a673c671a56	1542	{
ebrus	0:0a673c671a56	1543	flashstatus = FLASH_ERROR_WRP;
ebrus	0:0a673c671a56	1544	}
ebrus	0:0a673c671a56	1545	else
ebrus	0:0a673c671a56	1546	{
ebrus	0:0a673c671a56	1547	flashstatus = FLASH_COMPLETE;
ebrus	0:0a673c671a56	1548	}
ebrus	0:0a673c671a56	1549	}
ebrus	0:0a673c671a56	1550	}
ebrus	0:0a673c671a56	1551	/* Return the Flash Status */
ebrus	0:0a673c671a56	1552	return flashstatus;
ebrus	0:0a673c671a56	1553	}
ebrus	0:0a673c671a56	1554
ebrus	0:0a673c671a56	1555	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	1556	/**
ebrus	0:0a673c671a56	1557	* @brief Returns the FLASH Bank2 Status.
ebrus	0:0a673c671a56	1558	* @note This function can be used for STM32F10x_XL density devices.
ebrus	0:0a673c671a56	1559	* @param None
ebrus	0:0a673c671a56	1560	* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
ebrus	0:0a673c671a56	1561	* FLASH_ERROR_WRP or FLASH_COMPLETE
ebrus	0:0a673c671a56	1562	*/
ebrus	0:0a673c671a56	1563	FLASH_Status FLASH_GetBank2Status(void)
ebrus	0:0a673c671a56	1564	{
ebrus	0:0a673c671a56	1565	FLASH_Status flashstatus = FLASH_COMPLETE;
ebrus	0:0a673c671a56	1566
ebrus	0:0a673c671a56	1567	if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF))
ebrus	0:0a673c671a56	1568	{
ebrus	0:0a673c671a56	1569	flashstatus = FLASH_BUSY;
ebrus	0:0a673c671a56	1570	}
ebrus	0:0a673c671a56	1571	else
ebrus	0:0a673c671a56	1572	{
ebrus	0:0a673c671a56	1573	if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)
ebrus	0:0a673c671a56	1574	{
ebrus	0:0a673c671a56	1575	flashstatus = FLASH_ERROR_PG;
ebrus	0:0a673c671a56	1576	}
ebrus	0:0a673c671a56	1577	else
ebrus	0:0a673c671a56	1578	{
ebrus	0:0a673c671a56	1579	if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )
ebrus	0:0a673c671a56	1580	{
ebrus	0:0a673c671a56	1581	flashstatus = FLASH_ERROR_WRP;
ebrus	0:0a673c671a56	1582	}
ebrus	0:0a673c671a56	1583	else
ebrus	0:0a673c671a56	1584	{
ebrus	0:0a673c671a56	1585	flashstatus = FLASH_COMPLETE;
ebrus	0:0a673c671a56	1586	}
ebrus	0:0a673c671a56	1587	}
ebrus	0:0a673c671a56	1588	}
ebrus	0:0a673c671a56	1589	/* Return the Flash Status */
ebrus	0:0a673c671a56	1590	return flashstatus;
ebrus	0:0a673c671a56	1591	}
ebrus	0:0a673c671a56	1592	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	1593	/**
ebrus	0:0a673c671a56	1594	* @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
ebrus	0:0a673c671a56	1595	* @note This function can be used for all STM32F10x devices,
ebrus	0:0a673c671a56	1596	* it is equivalent to FLASH_WaitForLastBank1Operation.
ebrus	0:0a673c671a56	1597	* - For STM32F10X_XL devices this function waits for a Bank1 Flash operation
ebrus	0:0a673c671a56	1598	* to complete or a TIMEOUT to occur.
ebrus	0:0a673c671a56	1599	* - For all other devices it waits for a Flash operation to complete
ebrus	0:0a673c671a56	1600	* or a TIMEOUT to occur.
ebrus	0:0a673c671a56	1601	* @param Timeout: FLASH programming Timeout
ebrus	0:0a673c671a56	1602	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	1603	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	1604	*/
ebrus	0:0a673c671a56	1605	FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
ebrus	0:0a673c671a56	1606	{
ebrus	0:0a673c671a56	1607	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	1608
ebrus	0:0a673c671a56	1609	/* Check for the Flash Status */
ebrus	0:0a673c671a56	1610	status = FLASH_GetBank1Status();
ebrus	0:0a673c671a56	1611	/* Wait for a Flash operation to complete or a TIMEOUT to occur */
ebrus	0:0a673c671a56	1612	while((status == FLASH_BUSY) && (Timeout != 0x00))
ebrus	0:0a673c671a56	1613	{
ebrus	0:0a673c671a56	1614	status = FLASH_GetBank1Status();
ebrus	0:0a673c671a56	1615	Timeout--;
ebrus	0:0a673c671a56	1616	}
ebrus	0:0a673c671a56	1617	if(Timeout == 0x00 )
ebrus	0:0a673c671a56	1618	{
ebrus	0:0a673c671a56	1619	status = FLASH_TIMEOUT;
ebrus	0:0a673c671a56	1620	}
ebrus	0:0a673c671a56	1621	/* Return the operation status */
ebrus	0:0a673c671a56	1622	return status;
ebrus	0:0a673c671a56	1623	}
ebrus	0:0a673c671a56	1624
ebrus	0:0a673c671a56	1625	/**
ebrus	0:0a673c671a56	1626	* @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
ebrus	0:0a673c671a56	1627	* @note This function can be used for all STM32F10x devices,
ebrus	0:0a673c671a56	1628	* it is equivalent to FLASH_WaitForLastOperation.
ebrus	0:0a673c671a56	1629	* @param Timeout: FLASH programming Timeout
ebrus	0:0a673c671a56	1630	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	1631	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	1632	*/
ebrus	0:0a673c671a56	1633	FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
ebrus	0:0a673c671a56	1634	{
ebrus	0:0a673c671a56	1635	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	1636
ebrus	0:0a673c671a56	1637	/* Check for the Flash Status */
ebrus	0:0a673c671a56	1638	status = FLASH_GetBank1Status();
ebrus	0:0a673c671a56	1639	/* Wait for a Flash operation to complete or a TIMEOUT to occur */
ebrus	0:0a673c671a56	1640	while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
ebrus	0:0a673c671a56	1641	{
ebrus	0:0a673c671a56	1642	status = FLASH_GetBank1Status();
ebrus	0:0a673c671a56	1643	Timeout--;
ebrus	0:0a673c671a56	1644	}
ebrus	0:0a673c671a56	1645	if(Timeout == 0x00 )
ebrus	0:0a673c671a56	1646	{
ebrus	0:0a673c671a56	1647	status = FLASH_TIMEOUT;
ebrus	0:0a673c671a56	1648	}
ebrus	0:0a673c671a56	1649	/* Return the operation status */
ebrus	0:0a673c671a56	1650	return status;
ebrus	0:0a673c671a56	1651	}
ebrus	0:0a673c671a56	1652
ebrus	0:0a673c671a56	1653	#ifdef STM32F10X_XL
ebrus	0:0a673c671a56	1654	/**
ebrus	0:0a673c671a56	1655	* @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.
ebrus	0:0a673c671a56	1656	* @note This function can be used only for STM32F10x_XL density devices.
ebrus	0:0a673c671a56	1657	* @param Timeout: FLASH programming Timeout
ebrus	0:0a673c671a56	1658	* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
ebrus	0:0a673c671a56	1659	* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
ebrus	0:0a673c671a56	1660	*/
ebrus	0:0a673c671a56	1661	FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)
ebrus	0:0a673c671a56	1662	{
ebrus	0:0a673c671a56	1663	FLASH_Status status = FLASH_COMPLETE;
ebrus	0:0a673c671a56	1664
ebrus	0:0a673c671a56	1665	/* Check for the Flash Status */
ebrus	0:0a673c671a56	1666	status = FLASH_GetBank2Status();
ebrus	0:0a673c671a56	1667	/* Wait for a Flash operation to complete or a TIMEOUT to occur */
ebrus	0:0a673c671a56	1668	while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))
ebrus	0:0a673c671a56	1669	{
ebrus	0:0a673c671a56	1670	status = FLASH_GetBank2Status();
ebrus	0:0a673c671a56	1671	Timeout--;
ebrus	0:0a673c671a56	1672	}
ebrus	0:0a673c671a56	1673	if(Timeout == 0x00 )
ebrus	0:0a673c671a56	1674	{
ebrus	0:0a673c671a56	1675	status = FLASH_TIMEOUT;
ebrus	0:0a673c671a56	1676	}
ebrus	0:0a673c671a56	1677	/* Return the operation status */
ebrus	0:0a673c671a56	1678	return status;
ebrus	0:0a673c671a56	1679	}
ebrus	0:0a673c671a56	1680	#endif /* STM32F10X_XL */
ebrus	0:0a673c671a56	1681
ebrus	0:0a673c671a56	1682	/**
ebrus	0:0a673c671a56	1683	* @}
ebrus	0:0a673c671a56	1684	*/
ebrus	0:0a673c671a56	1685
ebrus	0:0a673c671a56	1686	/**
ebrus	0:0a673c671a56	1687	* @}
ebrus	0:0a673c671a56	1688	*/
ebrus	0:0a673c671a56	1689
ebrus	0:0a673c671a56	1690	/**
ebrus	0:0a673c671a56	1691	* @}
ebrus	0:0a673c671a56	1692	*/
ebrus	0:0a673c671a56	1693
ebrus	0:0a673c671a56	1694	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Created:	27 Jul 2016
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