Ermanno Brusadin / mbed-src

mbed library sources

targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

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ebrus 0:0a673c671a56 1 /****************************************************************************
ebrus 0:0a673c671a56 2 * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
ebrus 0:0a673c671a56 3 * Project: NXP LPC8xx software example
ebrus 0:0a673c671a56 4 *
ebrus 0:0a673c671a56 5 * Description:
ebrus 0:0a673c671a56 6 * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
ebrus 0:0a673c671a56 7 * NXP LPC800 Device Series
ebrus 0:0a673c671a56 8 *
ebrus 0:0a673c671a56 9 ****************************************************************************
ebrus 0:0a673c671a56 10 * Software that is described herein is for illustrative purposes only
ebrus 0:0a673c671a56 11 * which provides customers with programming information regarding the
ebrus 0:0a673c671a56 12 * products. This software is supplied "AS IS" without any warranties.
ebrus 0:0a673c671a56 13 * NXP Semiconductors assumes no responsibility or liability for the
ebrus 0:0a673c671a56 14 * use of the software, conveys no license or title under any patent,
ebrus 0:0a673c671a56 15 * copyright, or mask work right to the product. NXP Semiconductors
ebrus 0:0a673c671a56 16 * reserves the right to make changes in the software without
ebrus 0:0a673c671a56 17 * notification. NXP Semiconductors also make no representation or
ebrus 0:0a673c671a56 18 * warranty that such application will be suitable for the specified
ebrus 0:0a673c671a56 19 * use without further testing or modification.
ebrus 0:0a673c671a56 20
ebrus 0:0a673c671a56 21 * Permission to use, copy, modify, and distribute this software and its
ebrus 0:0a673c671a56 22 * documentation is hereby granted, under NXP Semiconductors'
ebrus 0:0a673c671a56 23 * relevant copyright in the software, without fee, provided that it
ebrus 0:0a673c671a56 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
ebrus 0:0a673c671a56 25 * copyright, permission, and disclaimer notice must appear in all copies of
ebrus 0:0a673c671a56 26 * this code.
ebrus 0:0a673c671a56 27 ****************************************************************************/
ebrus 0:0a673c671a56 28 #ifndef __LPC8xx_H__
ebrus 0:0a673c671a56 29 #define __LPC8xx_H__
ebrus 0:0a673c671a56 30
ebrus 0:0a673c671a56 31 #ifdef __cplusplus
ebrus 0:0a673c671a56 32 extern "C" {
ebrus 0:0a673c671a56 33 #endif
ebrus 0:0a673c671a56 34
ebrus 0:0a673c671a56 35 /** @addtogroup LPC8xx_Definitions LPC8xx Definitions
ebrus 0:0a673c671a56 36 This file defines all structures and symbols for LPC8xx:
ebrus 0:0a673c671a56 37 - Registers and bitfields
ebrus 0:0a673c671a56 38 - peripheral base address
ebrus 0:0a673c671a56 39 - PIO definitions
ebrus 0:0a673c671a56 40 @{
ebrus 0:0a673c671a56 41 */
ebrus 0:0a673c671a56 42
ebrus 0:0a673c671a56 43
ebrus 0:0a673c671a56 44 /******************************************************************************/
ebrus 0:0a673c671a56 45 /* Processor and Core Peripherals */
ebrus 0:0a673c671a56 46 /******************************************************************************/
ebrus 0:0a673c671a56 47 /** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
ebrus 0:0a673c671a56 48 Configuration of the Cortex-M0+ Processor and Core Peripherals
ebrus 0:0a673c671a56 49 @{
ebrus 0:0a673c671a56 50 */
ebrus 0:0a673c671a56 51
ebrus 0:0a673c671a56 52 /*
ebrus 0:0a673c671a56 53 * ==========================================================================
ebrus 0:0a673c671a56 54 * ---------- Interrupt Number Definition -----------------------------------
ebrus 0:0a673c671a56 55 * ==========================================================================
ebrus 0:0a673c671a56 56 */
ebrus 0:0a673c671a56 57 typedef enum IRQn
ebrus 0:0a673c671a56 58 {
ebrus 0:0a673c671a56 59 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
ebrus 0:0a673c671a56 60 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
ebrus 0:0a673c671a56 61 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
ebrus 0:0a673c671a56 62 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
ebrus 0:0a673c671a56 63 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
ebrus 0:0a673c671a56 64 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
ebrus 0:0a673c671a56 65 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
ebrus 0:0a673c671a56 66
ebrus 0:0a673c671a56 67 /****** LPC8xx Specific Interrupt Numbers ********************************************************/
ebrus 0:0a673c671a56 68 SPI0_IRQn = 0, /*!< SPI0 */
ebrus 0:0a673c671a56 69 SPI1_IRQn = 1, /*!< SPI1 */
ebrus 0:0a673c671a56 70 Reserved0_IRQn = 2, /*!< Reserved Interrupt */
ebrus 0:0a673c671a56 71 UART0_IRQn = 3, /*!< USART0 */
ebrus 0:0a673c671a56 72 UART1_IRQn = 4, /*!< USART1 */
ebrus 0:0a673c671a56 73 UART2_IRQn = 5, /*!< USART2 */
ebrus 0:0a673c671a56 74 Reserved1_IRQn = 6, /*!< Reserved Interrupt */
ebrus 0:0a673c671a56 75 Reserved2_IRQn = 7, /*!< Reserved Interrupt */
ebrus 0:0a673c671a56 76 I2C_IRQn = 8, /*!< I2C */
ebrus 0:0a673c671a56 77 SCT_IRQn = 9, /*!< SCT */
ebrus 0:0a673c671a56 78 MRT_IRQn = 10, /*!< MRT */
ebrus 0:0a673c671a56 79 CMP_IRQn = 11, /*!< CMP */
ebrus 0:0a673c671a56 80 WDT_IRQn = 12, /*!< WDT */
ebrus 0:0a673c671a56 81 BOD_IRQn = 13, /*!< BOD */
ebrus 0:0a673c671a56 82 Reserved3_IRQn = 14, /*!< Reserved Interrupt */
ebrus 0:0a673c671a56 83 WKT_IRQn = 15, /*!< WKT Interrupt */
ebrus 0:0a673c671a56 84 Reserved4_IRQn = 16, /*!< Reserved Interrupt */
ebrus 0:0a673c671a56 85 Reserved5_IRQn = 17, /*!< Reserved Interrupt */
ebrus 0:0a673c671a56 86 Reserved6_IRQn = 18, /*!< Reserved Interrupt */
ebrus 0:0a673c671a56 87 Reserved7_IRQn = 19, /*!< Reserved Interrupt */
ebrus 0:0a673c671a56 88 Reserved8_IRQn = 20, /*!< Reserved Interrupt */
ebrus 0:0a673c671a56 89 Reserved9_IRQn = 21, /*!< Reserved Interrupt */
ebrus 0:0a673c671a56 90 Reserved10_IRQn = 22, /*!< Reserved Interrupt */
ebrus 0:0a673c671a56 91 Reserved11_IRQn = 23, /*!< Reserved Interrupt */
ebrus 0:0a673c671a56 92 PININT0_IRQn = 24, /*!< External Interrupt 0 */
ebrus 0:0a673c671a56 93 PININT1_IRQn = 25, /*!< External Interrupt 1 */
ebrus 0:0a673c671a56 94 PININT2_IRQn = 26, /*!< External Interrupt 2 */
ebrus 0:0a673c671a56 95 PININT3_IRQn = 27, /*!< External Interrupt 3 */
ebrus 0:0a673c671a56 96 PININT4_IRQn = 28, /*!< External Interrupt 4 */
ebrus 0:0a673c671a56 97 PININT5_IRQn = 29, /*!< External Interrupt 5 */
ebrus 0:0a673c671a56 98 PININT6_IRQn = 30, /*!< External Interrupt 6 */
ebrus 0:0a673c671a56 99 PININT7_IRQn = 31, /*!< External Interrupt 7 */
ebrus 0:0a673c671a56 100 } IRQn_Type;
ebrus 0:0a673c671a56 101
ebrus 0:0a673c671a56 102 /*
ebrus 0:0a673c671a56 103 * ==========================================================================
ebrus 0:0a673c671a56 104 * ----------- Processor and Core Peripheral Section ------------------------
ebrus 0:0a673c671a56 105 * ==========================================================================
ebrus 0:0a673c671a56 106 */
ebrus 0:0a673c671a56 107
ebrus 0:0a673c671a56 108 /* Configuration of the Cortex-M0+ Processor and Core Peripherals */
ebrus 0:0a673c671a56 109 #define __MPU_PRESENT 0 /*!< MPU present or not */
ebrus 0:0a673c671a56 110 #define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */
ebrus 0:0a673c671a56 111 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
ebrus 0:0a673c671a56 112 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
ebrus 0:0a673c671a56 113
ebrus 0:0a673c671a56 114 /*@}*/ /* end of group LPC8xx_CMSIS */
ebrus 0:0a673c671a56 115
ebrus 0:0a673c671a56 116
ebrus 0:0a673c671a56 117 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
ebrus 0:0a673c671a56 118 #include "system_LPC8xx.h" /* System Header */
ebrus 0:0a673c671a56 119
ebrus 0:0a673c671a56 120
ebrus 0:0a673c671a56 121 /******************************************************************************/
ebrus 0:0a673c671a56 122 /* Device Specific Peripheral Registers structures */
ebrus 0:0a673c671a56 123 /******************************************************************************/
ebrus 0:0a673c671a56 124
ebrus 0:0a673c671a56 125 #if defined ( __CC_ARM )
ebrus 0:0a673c671a56 126 #pragma anon_unions
ebrus 0:0a673c671a56 127 #endif
ebrus 0:0a673c671a56 128
ebrus 0:0a673c671a56 129 /*------------- System Control (SYSCON) --------------------------------------*/
ebrus 0:0a673c671a56 130 /** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
ebrus 0:0a673c671a56 131 @{
ebrus 0:0a673c671a56 132 */
ebrus 0:0a673c671a56 133 typedef struct
ebrus 0:0a673c671a56 134 {
ebrus 0:0a673c671a56 135 __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
ebrus 0:0a673c671a56 136 __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
ebrus 0:0a673c671a56 137 __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
ebrus 0:0a673c671a56 138 __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */
ebrus 0:0a673c671a56 139 uint32_t RESERVED0[4];
ebrus 0:0a673c671a56 140
ebrus 0:0a673c671a56 141 __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
ebrus 0:0a673c671a56 142 __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
ebrus 0:0a673c671a56 143 uint32_t RESERVED1[2];
ebrus 0:0a673c671a56 144 __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */
ebrus 0:0a673c671a56 145 uint32_t RESERVED2[3];
ebrus 0:0a673c671a56 146 __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
ebrus 0:0a673c671a56 147 __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
ebrus 0:0a673c671a56 148 uint32_t RESERVED3[10];
ebrus 0:0a673c671a56 149
ebrus 0:0a673c671a56 150 __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
ebrus 0:0a673c671a56 151 __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
ebrus 0:0a673c671a56 152 __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
ebrus 0:0a673c671a56 153 uint32_t RESERVED4[1];
ebrus 0:0a673c671a56 154
ebrus 0:0a673c671a56 155 __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
ebrus 0:0a673c671a56 156 uint32_t RESERVED5[4];
ebrus 0:0a673c671a56 157 __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */
ebrus 0:0a673c671a56 158 uint32_t RESERVED6[18];
ebrus 0:0a673c671a56 159
ebrus 0:0a673c671a56 160 __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
ebrus 0:0a673c671a56 161 __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
ebrus 0:0a673c671a56 162 __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
ebrus 0:0a673c671a56 163 uint32_t RESERVED7;
ebrus 0:0a673c671a56 164 __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
ebrus 0:0a673c671a56 165 __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
ebrus 0:0a673c671a56 166 uint32_t RESERVED8[1];
ebrus 0:0a673c671a56 167 __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
ebrus 0:0a673c671a56 168 __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
ebrus 0:0a673c671a56 169 uint32_t RESERVED9[12];
ebrus 0:0a673c671a56 170 __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
ebrus 0:0a673c671a56 171 __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
ebrus 0:0a673c671a56 172 __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
ebrus 0:0a673c671a56 173 uint32_t RESERVED10[6];
ebrus 0:0a673c671a56 174 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */
ebrus 0:0a673c671a56 175 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
ebrus 0:0a673c671a56 176 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
ebrus 0:0a673c671a56 177 uint32_t RESERVED11[27];
ebrus 0:0a673c671a56 178 __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
ebrus 0:0a673c671a56 179 uint32_t RESERVED12[3];
ebrus 0:0a673c671a56 180 __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
ebrus 0:0a673c671a56 181 uint32_t RESERVED13[6];
ebrus 0:0a673c671a56 182 __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
ebrus 0:0a673c671a56 183 __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
ebrus 0:0a673c671a56 184 __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
ebrus 0:0a673c671a56 185 uint32_t RESERVED14[110];
ebrus 0:0a673c671a56 186 __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
ebrus 0:0a673c671a56 187 } LPC_SYSCON_TypeDef;
ebrus 0:0a673c671a56 188 /*@}*/ /* end of group LPC8xx_SYSCON */
ebrus 0:0a673c671a56 189
ebrus 0:0a673c671a56 190
ebrus 0:0a673c671a56 191 /**
ebrus 0:0a673c671a56 192 * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
ebrus 0:0a673c671a56 193 */
ebrus 0:0a673c671a56 194
ebrus 0:0a673c671a56 195 typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
ebrus 0:0a673c671a56 196 __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
ebrus 0:0a673c671a56 197 __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
ebrus 0:0a673c671a56 198 __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
ebrus 0:0a673c671a56 199 __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
ebrus 0:0a673c671a56 200 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
ebrus 0:0a673c671a56 201 __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
ebrus 0:0a673c671a56 202 __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
ebrus 0:0a673c671a56 203 __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
ebrus 0:0a673c671a56 204 __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
ebrus 0:0a673c671a56 205 __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
ebrus 0:0a673c671a56 206 __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
ebrus 0:0a673c671a56 207 __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
ebrus 0:0a673c671a56 208 __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
ebrus 0:0a673c671a56 209 __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
ebrus 0:0a673c671a56 210 __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
ebrus 0:0a673c671a56 211 __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
ebrus 0:0a673c671a56 212 __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
ebrus 0:0a673c671a56 213 __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
ebrus 0:0a673c671a56 214 __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
ebrus 0:0a673c671a56 215 } LPC_IOCON_TypeDef;
ebrus 0:0a673c671a56 216 /*@}*/ /* end of group LPC8xx_IOCON */
ebrus 0:0a673c671a56 217
ebrus 0:0a673c671a56 218 /**
ebrus 0:0a673c671a56 219 * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL)
ebrus 0:0a673c671a56 220 */
ebrus 0:0a673c671a56 221 typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
ebrus 0:0a673c671a56 222 __I uint32_t RESERVED0[4];
ebrus 0:0a673c671a56 223 __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
ebrus 0:0a673c671a56 224 __I uint32_t RESERVED1[3];
ebrus 0:0a673c671a56 225 __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
ebrus 0:0a673c671a56 226 __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
ebrus 0:0a673c671a56 227 __I uint32_t RESERVED2;
ebrus 0:0a673c671a56 228 __I uint32_t FMSW0;
ebrus 0:0a673c671a56 229 } LPC_FLASHCTRL_TypeDef;
ebrus 0:0a673c671a56 230 /*@}*/ /* end of group LPC8xx_FLASHCTRL */
ebrus 0:0a673c671a56 231
ebrus 0:0a673c671a56 232
ebrus 0:0a673c671a56 233 /*------------- Power Management Unit (PMU) --------------------------*/
ebrus 0:0a673c671a56 234 /** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
ebrus 0:0a673c671a56 235 @{
ebrus 0:0a673c671a56 236 */
ebrus 0:0a673c671a56 237 typedef struct
ebrus 0:0a673c671a56 238 {
ebrus 0:0a673c671a56 239 __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
ebrus 0:0a673c671a56 240 __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
ebrus 0:0a673c671a56 241 __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
ebrus 0:0a673c671a56 242 __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
ebrus 0:0a673c671a56 243 __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
ebrus 0:0a673c671a56 244 __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
ebrus 0:0a673c671a56 245 } LPC_PMU_TypeDef;
ebrus 0:0a673c671a56 246 /*@}*/ /* end of group LPC8xx_PMU */
ebrus 0:0a673c671a56 247
ebrus 0:0a673c671a56 248
ebrus 0:0a673c671a56 249 /*------------- Switch Matrix Port --------------------------*/
ebrus 0:0a673c671a56 250 /** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
ebrus 0:0a673c671a56 251 @{
ebrus 0:0a673c671a56 252 */
ebrus 0:0a673c671a56 253 typedef struct
ebrus 0:0a673c671a56 254 {
ebrus 0:0a673c671a56 255 union {
ebrus 0:0a673c671a56 256 __IO uint32_t PINASSIGN[9];
ebrus 0:0a673c671a56 257 struct {
ebrus 0:0a673c671a56 258 __IO uint32_t PINASSIGN0;
ebrus 0:0a673c671a56 259 __IO uint32_t PINASSIGN1;
ebrus 0:0a673c671a56 260 __IO uint32_t PINASSIGN2;
ebrus 0:0a673c671a56 261 __IO uint32_t PINASSIGN3;
ebrus 0:0a673c671a56 262 __IO uint32_t PINASSIGN4;
ebrus 0:0a673c671a56 263 __IO uint32_t PINASSIGN5;
ebrus 0:0a673c671a56 264 __IO uint32_t PINASSIGN6;
ebrus 0:0a673c671a56 265 __IO uint32_t PINASSIGN7;
ebrus 0:0a673c671a56 266 __IO uint32_t PINASSIGN8;
ebrus 0:0a673c671a56 267 };
ebrus 0:0a673c671a56 268 };
ebrus 0:0a673c671a56 269 __I uint32_t RESERVED0[103];
ebrus 0:0a673c671a56 270 __IO uint32_t PINENABLE0;
ebrus 0:0a673c671a56 271 } LPC_SWM_TypeDef;
ebrus 0:0a673c671a56 272 /*@}*/ /* end of group LPC8xx_SWM */
ebrus 0:0a673c671a56 273
ebrus 0:0a673c671a56 274
ebrus 0:0a673c671a56 275 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 276 // ----- GPIO_PORT -----
ebrus 0:0a673c671a56 277 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 278
ebrus 0:0a673c671a56 279 /**
ebrus 0:0a673c671a56 280 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
ebrus 0:0a673c671a56 281 */
ebrus 0:0a673c671a56 282
ebrus 0:0a673c671a56 283 typedef struct {
ebrus 0:0a673c671a56 284 __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */
ebrus 0:0a673c671a56 285 __I uint16_t RESERVED0[2039];
ebrus 0:0a673c671a56 286 __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */
ebrus 0:0a673c671a56 287 uint32_t RESERVED1[1006];
ebrus 0:0a673c671a56 288 __IO uint32_t DIR0; /* 0x2000 */
ebrus 0:0a673c671a56 289 uint32_t RESERVED2[31];
ebrus 0:0a673c671a56 290 __IO uint32_t MASK0; /* 0x2080 */
ebrus 0:0a673c671a56 291 uint32_t RESERVED3[31];
ebrus 0:0a673c671a56 292 __IO uint32_t PIN0; /* 0x2100 */
ebrus 0:0a673c671a56 293 uint32_t RESERVED4[31];
ebrus 0:0a673c671a56 294 __IO uint32_t MPIN0; /* 0x2180 */
ebrus 0:0a673c671a56 295 uint32_t RESERVED5[31];
ebrus 0:0a673c671a56 296 __IO uint32_t SET0; /* 0x2200 */
ebrus 0:0a673c671a56 297 uint32_t RESERVED6[31];
ebrus 0:0a673c671a56 298 __O uint32_t CLR0; /* 0x2280 */
ebrus 0:0a673c671a56 299 uint32_t RESERVED7[31];
ebrus 0:0a673c671a56 300 __O uint32_t NOT0; /* 0x2300 */
ebrus 0:0a673c671a56 301
ebrus 0:0a673c671a56 302 } LPC_GPIO_PORT_TypeDef;
ebrus 0:0a673c671a56 303
ebrus 0:0a673c671a56 304
ebrus 0:0a673c671a56 305 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 306 // ----- PIN_INT -----
ebrus 0:0a673c671a56 307 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 308
ebrus 0:0a673c671a56 309 /**
ebrus 0:0a673c671a56 310 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT)
ebrus 0:0a673c671a56 311 */
ebrus 0:0a673c671a56 312
ebrus 0:0a673c671a56 313 typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
ebrus 0:0a673c671a56 314 __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
ebrus 0:0a673c671a56 315 __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
ebrus 0:0a673c671a56 316 __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
ebrus 0:0a673c671a56 317 __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
ebrus 0:0a673c671a56 318 __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
ebrus 0:0a673c671a56 319 __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
ebrus 0:0a673c671a56 320 __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
ebrus 0:0a673c671a56 321 __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
ebrus 0:0a673c671a56 322 __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
ebrus 0:0a673c671a56 323 __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
ebrus 0:0a673c671a56 324 __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
ebrus 0:0a673c671a56 325 __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
ebrus 0:0a673c671a56 326 __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
ebrus 0:0a673c671a56 327 } LPC_PIN_INT_TypeDef;
ebrus 0:0a673c671a56 328
ebrus 0:0a673c671a56 329
ebrus 0:0a673c671a56 330 /*------------- CRC Engine (CRC) -----------------------------------------*/
ebrus 0:0a673c671a56 331 /** @addtogroup LPC8xx_CRC
ebrus 0:0a673c671a56 332 @{
ebrus 0:0a673c671a56 333 */
ebrus 0:0a673c671a56 334 typedef struct
ebrus 0:0a673c671a56 335 {
ebrus 0:0a673c671a56 336 __IO uint32_t MODE;
ebrus 0:0a673c671a56 337 __IO uint32_t SEED;
ebrus 0:0a673c671a56 338 union {
ebrus 0:0a673c671a56 339 __I uint32_t SUM;
ebrus 0:0a673c671a56 340 __O uint32_t WR_DATA_DWORD;
ebrus 0:0a673c671a56 341 __O uint16_t WR_DATA_WORD;
ebrus 0:0a673c671a56 342 uint16_t RESERVED_WORD;
ebrus 0:0a673c671a56 343 __O uint8_t WR_DATA_BYTE;
ebrus 0:0a673c671a56 344 uint8_t RESERVED_BYTE[3];
ebrus 0:0a673c671a56 345 };
ebrus 0:0a673c671a56 346 } LPC_CRC_TypeDef;
ebrus 0:0a673c671a56 347 /*@}*/ /* end of group LPC8xx_CRC */
ebrus 0:0a673c671a56 348
ebrus 0:0a673c671a56 349 /*------------- Comparator (CMP) --------------------------------------------------*/
ebrus 0:0a673c671a56 350 /** @addtogroup LPC8xx_CMP LPC8xx Comparator
ebrus 0:0a673c671a56 351 @{
ebrus 0:0a673c671a56 352 */
ebrus 0:0a673c671a56 353 typedef struct { /*!< (@ 0x40024000) CMP Structure */
ebrus 0:0a673c671a56 354 __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
ebrus 0:0a673c671a56 355 __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
ebrus 0:0a673c671a56 356 } LPC_CMP_TypeDef;
ebrus 0:0a673c671a56 357 /*@}*/ /* end of group LPC8xx_CMP */
ebrus 0:0a673c671a56 358
ebrus 0:0a673c671a56 359
ebrus 0:0a673c671a56 360 /*------------- Wakeup Timer (WKT) --------------------------------------------------*/
ebrus 0:0a673c671a56 361 /** @addtogroup LPC8xx_WKT
ebrus 0:0a673c671a56 362 @{
ebrus 0:0a673c671a56 363 */
ebrus 0:0a673c671a56 364 typedef struct { /*!< (@ 0x40028000) WKT Structure */
ebrus 0:0a673c671a56 365 __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
ebrus 0:0a673c671a56 366 uint32_t Reserved[2];
ebrus 0:0a673c671a56 367 __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
ebrus 0:0a673c671a56 368 } LPC_WKT_TypeDef;
ebrus 0:0a673c671a56 369 /*@}*/ /* end of group LPC8xx_WKT */
ebrus 0:0a673c671a56 370
ebrus 0:0a673c671a56 371
ebrus 0:0a673c671a56 372 /*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
ebrus 0:0a673c671a56 373 typedef struct {
ebrus 0:0a673c671a56 374 __IO uint32_t INTVAL;
ebrus 0:0a673c671a56 375 __IO uint32_t TIMER;
ebrus 0:0a673c671a56 376 __IO uint32_t CTRL;
ebrus 0:0a673c671a56 377 __IO uint32_t STAT;
ebrus 0:0a673c671a56 378 } MRT_Channel_cfg_Type;
ebrus 0:0a673c671a56 379
ebrus 0:0a673c671a56 380 typedef struct {
ebrus 0:0a673c671a56 381 MRT_Channel_cfg_Type Channel[4];
ebrus 0:0a673c671a56 382 uint32_t Reserved0[1];
ebrus 0:0a673c671a56 383 __IO uint32_t IDLE_CH;
ebrus 0:0a673c671a56 384 __IO uint32_t IRQ_FLAG;
ebrus 0:0a673c671a56 385 } LPC_MRT_TypeDef;
ebrus 0:0a673c671a56 386
ebrus 0:0a673c671a56 387
ebrus 0:0a673c671a56 388 /*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
ebrus 0:0a673c671a56 389 /** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
ebrus 0:0a673c671a56 390 @{
ebrus 0:0a673c671a56 391 */
ebrus 0:0a673c671a56 392 /**
ebrus 0:0a673c671a56 393 * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART)
ebrus 0:0a673c671a56 394 */
ebrus 0:0a673c671a56 395 typedef struct
ebrus 0:0a673c671a56 396 {
ebrus 0:0a673c671a56 397 __IO uint32_t CFG; /* 0x00 */
ebrus 0:0a673c671a56 398 __IO uint32_t CTRL;
ebrus 0:0a673c671a56 399 __IO uint32_t STAT;
ebrus 0:0a673c671a56 400 __IO uint32_t INTENSET;
ebrus 0:0a673c671a56 401 __O uint32_t INTENCLR; /* 0x10 */
ebrus 0:0a673c671a56 402 __I uint32_t RXDATA;
ebrus 0:0a673c671a56 403 __I uint32_t RXDATA_STAT;
ebrus 0:0a673c671a56 404 __IO uint32_t TXDATA;
ebrus 0:0a673c671a56 405 __IO uint32_t BRG; /* 0x20 */
ebrus 0:0a673c671a56 406 __IO uint32_t INTSTAT;
ebrus 0:0a673c671a56 407 } LPC_USART_TypeDef;
ebrus 0:0a673c671a56 408
ebrus 0:0a673c671a56 409 /*@}*/ /* end of group LPC8xx_USART */
ebrus 0:0a673c671a56 410
ebrus 0:0a673c671a56 411
ebrus 0:0a673c671a56 412 /*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
ebrus 0:0a673c671a56 413 /** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
ebrus 0:0a673c671a56 414 @{
ebrus 0:0a673c671a56 415 */
ebrus 0:0a673c671a56 416 typedef struct
ebrus 0:0a673c671a56 417 {
ebrus 0:0a673c671a56 418 __IO uint32_t CFG; /* 0x00 */
ebrus 0:0a673c671a56 419 __IO uint32_t DLY;
ebrus 0:0a673c671a56 420 __IO uint32_t STAT;
ebrus 0:0a673c671a56 421 __IO uint32_t INTENSET;
ebrus 0:0a673c671a56 422 __O uint32_t INTENCLR; /* 0x10 */
ebrus 0:0a673c671a56 423 __I uint32_t RXDAT;
ebrus 0:0a673c671a56 424 __IO uint32_t TXDATCTL;
ebrus 0:0a673c671a56 425 __IO uint32_t TXDAT;
ebrus 0:0a673c671a56 426 __IO uint32_t TXCTRL; /* 0x20 */
ebrus 0:0a673c671a56 427 __IO uint32_t DIV;
ebrus 0:0a673c671a56 428 __I uint32_t INTSTAT;
ebrus 0:0a673c671a56 429 } LPC_SPI_TypeDef;
ebrus 0:0a673c671a56 430 /*@}*/ /* end of group LPC8xx_SPI */
ebrus 0:0a673c671a56 431
ebrus 0:0a673c671a56 432
ebrus 0:0a673c671a56 433 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
ebrus 0:0a673c671a56 434 /** @addtogroup LPC8xx_I2C I2C-Bus Interface
ebrus 0:0a673c671a56 435 @{
ebrus 0:0a673c671a56 436 */
ebrus 0:0a673c671a56 437 typedef struct
ebrus 0:0a673c671a56 438 {
ebrus 0:0a673c671a56 439 __IO uint32_t CFG; /* 0x00 */
ebrus 0:0a673c671a56 440 __IO uint32_t STAT;
ebrus 0:0a673c671a56 441 __IO uint32_t INTENSET;
ebrus 0:0a673c671a56 442 __O uint32_t INTENCLR;
ebrus 0:0a673c671a56 443 __IO uint32_t TIMEOUT; /* 0x10 */
ebrus 0:0a673c671a56 444 __IO uint32_t DIV;
ebrus 0:0a673c671a56 445 __IO uint32_t INTSTAT;
ebrus 0:0a673c671a56 446 uint32_t Reserved0[1];
ebrus 0:0a673c671a56 447 __IO uint32_t MSTCTL; /* 0x20 */
ebrus 0:0a673c671a56 448 __IO uint32_t MSTTIME;
ebrus 0:0a673c671a56 449 __IO uint32_t MSTDAT;
ebrus 0:0a673c671a56 450 uint32_t Reserved1[5];
ebrus 0:0a673c671a56 451 __IO uint32_t SLVCTL; /* 0x40 */
ebrus 0:0a673c671a56 452 __IO uint32_t SLVDAT;
ebrus 0:0a673c671a56 453 __IO uint32_t SLVADR0;
ebrus 0:0a673c671a56 454 __IO uint32_t SLVADR1;
ebrus 0:0a673c671a56 455 __IO uint32_t SLVADR2; /* 0x50 */
ebrus 0:0a673c671a56 456 __IO uint32_t SLVADR3;
ebrus 0:0a673c671a56 457 __IO uint32_t SLVQUAL0;
ebrus 0:0a673c671a56 458 uint32_t Reserved2[9];
ebrus 0:0a673c671a56 459 __I uint32_t MONRXDAT; /* 0x80 */
ebrus 0:0a673c671a56 460 } LPC_I2C_TypeDef;
ebrus 0:0a673c671a56 461
ebrus 0:0a673c671a56 462 /*@}*/ /* end of group LPC8xx_I2C */
ebrus 0:0a673c671a56 463
ebrus 0:0a673c671a56 464 /**
ebrus 0:0a673c671a56 465 * @brief State Configurable Timer (SCT) (SCT)
ebrus 0:0a673c671a56 466 */
ebrus 0:0a673c671a56 467
ebrus 0:0a673c671a56 468 /**
ebrus 0:0a673c671a56 469 * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
ebrus 0:0a673c671a56 470 */
ebrus 0:0a673c671a56 471
ebrus 0:0a673c671a56 472 #define CONFIG_SCT_nEV (6) /* Number of events */
ebrus 0:0a673c671a56 473 #define CONFIG_SCT_nRG (5) /* Number of match/compare registers */
ebrus 0:0a673c671a56 474 #define CONFIG_SCT_nOU (4) /* Number of outputs */
ebrus 0:0a673c671a56 475
ebrus 0:0a673c671a56 476 typedef struct
ebrus 0:0a673c671a56 477 {
ebrus 0:0a673c671a56 478 __IO uint32_t CONFIG; /* 0x000 Configuration Register */
ebrus 0:0a673c671a56 479 union {
ebrus 0:0a673c671a56 480 __IO uint32_t CTRL_U; /* 0x004 Control Register */
ebrus 0:0a673c671a56 481 struct {
ebrus 0:0a673c671a56 482 __IO uint16_t CTRL_L; /* 0x004 low control register */
ebrus 0:0a673c671a56 483 __IO uint16_t CTRL_H; /* 0x006 high control register */
ebrus 0:0a673c671a56 484 };
ebrus 0:0a673c671a56 485 };
ebrus 0:0a673c671a56 486 __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
ebrus 0:0a673c671a56 487 __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
ebrus 0:0a673c671a56 488 __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
ebrus 0:0a673c671a56 489 __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
ebrus 0:0a673c671a56 490 __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
ebrus 0:0a673c671a56 491 __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
ebrus 0:0a673c671a56 492 __IO uint16_t START_L; /* 0x014 start register for counter L */
ebrus 0:0a673c671a56 493 __IO uint16_t START_H; /* 0x016 start register for counter H */
ebrus 0:0a673c671a56 494 uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
ebrus 0:0a673c671a56 495 union {
ebrus 0:0a673c671a56 496 __IO uint32_t COUNT_U; /* 0x040 counter register */
ebrus 0:0a673c671a56 497 struct {
ebrus 0:0a673c671a56 498 __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
ebrus 0:0a673c671a56 499 __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
ebrus 0:0a673c671a56 500 };
ebrus 0:0a673c671a56 501 };
ebrus 0:0a673c671a56 502 __IO uint16_t STATE_L; /* 0x044 state register for counter L */
ebrus 0:0a673c671a56 503 __IO uint16_t STATE_H; /* 0x046 state register for counter H */
ebrus 0:0a673c671a56 504 __I uint32_t INPUT; /* 0x048 input register */
ebrus 0:0a673c671a56 505 __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
ebrus 0:0a673c671a56 506 __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
ebrus 0:0a673c671a56 507 __IO uint32_t OUTPUT; /* 0x050 output register */
ebrus 0:0a673c671a56 508 __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
ebrus 0:0a673c671a56 509 __IO uint32_t RES; /* 0x058 conflict resolution register */
ebrus 0:0a673c671a56 510 uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */
ebrus 0:0a673c671a56 511 __IO uint32_t EVEN; /* 0x0F0 event enable register */
ebrus 0:0a673c671a56 512 __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
ebrus 0:0a673c671a56 513 __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
ebrus 0:0a673c671a56 514 __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
ebrus 0:0a673c671a56 515
ebrus 0:0a673c671a56 516 union {
ebrus 0:0a673c671a56 517 __IO union { /* 0x100-... Match / Capture value */
ebrus 0:0a673c671a56 518 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
ebrus 0:0a673c671a56 519 struct {
ebrus 0:0a673c671a56 520 uint16_t L; /* SCTMATCH[i].L Access to L value */
ebrus 0:0a673c671a56 521 uint16_t H; /* SCTMATCH[i].H Access to H value */
ebrus 0:0a673c671a56 522 };
ebrus 0:0a673c671a56 523 } MATCH[CONFIG_SCT_nRG];
ebrus 0:0a673c671a56 524 __I union {
ebrus 0:0a673c671a56 525 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
ebrus 0:0a673c671a56 526 struct {
ebrus 0:0a673c671a56 527 uint16_t L; /* SCTCAP[i].L Access to H value */
ebrus 0:0a673c671a56 528 uint16_t H; /* SCTCAP[i].H Access to H value */
ebrus 0:0a673c671a56 529 };
ebrus 0:0a673c671a56 530 } CAP[CONFIG_SCT_nRG];
ebrus 0:0a673c671a56 531 };
ebrus 0:0a673c671a56 532
ebrus 0:0a673c671a56 533
ebrus 0:0a673c671a56 534 uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
ebrus 0:0a673c671a56 535
ebrus 0:0a673c671a56 536 union {
ebrus 0:0a673c671a56 537 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
ebrus 0:0a673c671a56 538 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
ebrus 0:0a673c671a56 539 };
ebrus 0:0a673c671a56 540 uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
ebrus 0:0a673c671a56 541 union {
ebrus 0:0a673c671a56 542 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
ebrus 0:0a673c671a56 543 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
ebrus 0:0a673c671a56 544 };
ebrus 0:0a673c671a56 545
ebrus 0:0a673c671a56 546 uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
ebrus 0:0a673c671a56 547
ebrus 0:0a673c671a56 548
ebrus 0:0a673c671a56 549 union {
ebrus 0:0a673c671a56 550 __IO union { /* 0x200-... Match Reload / Capture Control value */
ebrus 0:0a673c671a56 551 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
ebrus 0:0a673c671a56 552 struct {
ebrus 0:0a673c671a56 553 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
ebrus 0:0a673c671a56 554 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
ebrus 0:0a673c671a56 555 };
ebrus 0:0a673c671a56 556 } MATCHREL[CONFIG_SCT_nRG];
ebrus 0:0a673c671a56 557 __IO union {
ebrus 0:0a673c671a56 558 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
ebrus 0:0a673c671a56 559 struct {
ebrus 0:0a673c671a56 560 uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
ebrus 0:0a673c671a56 561 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
ebrus 0:0a673c671a56 562 };
ebrus 0:0a673c671a56 563 } CAPCTRL[CONFIG_SCT_nRG];
ebrus 0:0a673c671a56 564 };
ebrus 0:0a673c671a56 565
ebrus 0:0a673c671a56 566 uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
ebrus 0:0a673c671a56 567
ebrus 0:0a673c671a56 568 union {
ebrus 0:0a673c671a56 569 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
ebrus 0:0a673c671a56 570 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
ebrus 0:0a673c671a56 571 };
ebrus 0:0a673c671a56 572 uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
ebrus 0:0a673c671a56 573 union {
ebrus 0:0a673c671a56 574 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
ebrus 0:0a673c671a56 575 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
ebrus 0:0a673c671a56 576 };
ebrus 0:0a673c671a56 577 uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
ebrus 0:0a673c671a56 578
ebrus 0:0a673c671a56 579 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
ebrus 0:0a673c671a56 580 uint32_t STATE; /* Event State Register */
ebrus 0:0a673c671a56 581 uint32_t CTRL; /* Event Control Register */
ebrus 0:0a673c671a56 582 } EVENT[CONFIG_SCT_nEV];
ebrus 0:0a673c671a56 583
ebrus 0:0a673c671a56 584 uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
ebrus 0:0a673c671a56 585
ebrus 0:0a673c671a56 586 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
ebrus 0:0a673c671a56 587 uint32_t SET; /* Output n Set Register */
ebrus 0:0a673c671a56 588 uint32_t CLR; /* Output n Clear Register */
ebrus 0:0a673c671a56 589 } OUT[CONFIG_SCT_nOU];
ebrus 0:0a673c671a56 590
ebrus 0:0a673c671a56 591 uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
ebrus 0:0a673c671a56 592
ebrus 0:0a673c671a56 593 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
ebrus 0:0a673c671a56 594
ebrus 0:0a673c671a56 595 } LPC_SCT_TypeDef;
ebrus 0:0a673c671a56 596 /*@}*/ /* end of group LPC8xx_SCT */
ebrus 0:0a673c671a56 597
ebrus 0:0a673c671a56 598
ebrus 0:0a673c671a56 599 /*------------- Watchdog Timer (WWDT) -----------------------------------------*/
ebrus 0:0a673c671a56 600 /** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
ebrus 0:0a673c671a56 601 @{
ebrus 0:0a673c671a56 602 */
ebrus 0:0a673c671a56 603 typedef struct
ebrus 0:0a673c671a56 604 {
ebrus 0:0a673c671a56 605 __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
ebrus 0:0a673c671a56 606 __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
ebrus 0:0a673c671a56 607 __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
ebrus 0:0a673c671a56 608 __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
ebrus 0:0a673c671a56 609 uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
ebrus 0:0a673c671a56 610 __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
ebrus 0:0a673c671a56 611 __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
ebrus 0:0a673c671a56 612 } LPC_WWDT_TypeDef;
ebrus 0:0a673c671a56 613 /*@}*/ /* end of group LPC8xx_WDT */
ebrus 0:0a673c671a56 614
ebrus 0:0a673c671a56 615
ebrus 0:0a673c671a56 616 #if defined ( __CC_ARM )
ebrus 0:0a673c671a56 617 #pragma no_anon_unions
ebrus 0:0a673c671a56 618 #endif
ebrus 0:0a673c671a56 619
ebrus 0:0a673c671a56 620 /******************************************************************************/
ebrus 0:0a673c671a56 621 /* Peripheral memory map */
ebrus 0:0a673c671a56 622 /******************************************************************************/
ebrus 0:0a673c671a56 623 /* Base addresses */
ebrus 0:0a673c671a56 624 #define LPC_FLASH_BASE (0x00000000UL)
ebrus 0:0a673c671a56 625 #define LPC_RAM_BASE (0x10000000UL)
ebrus 0:0a673c671a56 626 #define LPC_ROM_BASE (0x1FFF0000UL)
ebrus 0:0a673c671a56 627 #define LPC_APB0_BASE (0x40000000UL)
ebrus 0:0a673c671a56 628 #define LPC_AHB_BASE (0x50000000UL)
ebrus 0:0a673c671a56 629
ebrus 0:0a673c671a56 630 /* APB0 peripherals */
ebrus 0:0a673c671a56 631 #define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
ebrus 0:0a673c671a56 632 #define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
ebrus 0:0a673c671a56 633 #define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
ebrus 0:0a673c671a56 634 #define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
ebrus 0:0a673c671a56 635 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
ebrus 0:0a673c671a56 636 #define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
ebrus 0:0a673c671a56 637
ebrus 0:0a673c671a56 638 #define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
ebrus 0:0a673c671a56 639 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
ebrus 0:0a673c671a56 640 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
ebrus 0:0a673c671a56 641 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000)
ebrus 0:0a673c671a56 642 #define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
ebrus 0:0a673c671a56 643 #define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
ebrus 0:0a673c671a56 644 #define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
ebrus 0:0a673c671a56 645 #define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
ebrus 0:0a673c671a56 646 #define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
ebrus 0:0a673c671a56 647
ebrus 0:0a673c671a56 648 /* AHB peripherals */
ebrus 0:0a673c671a56 649 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
ebrus 0:0a673c671a56 650 #define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
ebrus 0:0a673c671a56 651
ebrus 0:0a673c671a56 652 #define LPC_GPIO_PORT_BASE (0xA0000000)
ebrus 0:0a673c671a56 653 #define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
ebrus 0:0a673c671a56 654
ebrus 0:0a673c671a56 655 /******************************************************************************/
ebrus 0:0a673c671a56 656 /* Peripheral declaration */
ebrus 0:0a673c671a56 657 /******************************************************************************/
ebrus 0:0a673c671a56 658 #define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
ebrus 0:0a673c671a56 659 #define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
ebrus 0:0a673c671a56 660
ebrus 0:0a673c671a56 661
ebrus 0:0a673c671a56 662 #define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
ebrus 0:0a673c671a56 663 #define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
ebrus 0:0a673c671a56 664 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
ebrus 0:0a673c671a56 665 #define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
ebrus 0:0a673c671a56 666
ebrus 0:0a673c671a56 667 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
ebrus 0:0a673c671a56 668 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
ebrus 0:0a673c671a56 669 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
ebrus 0:0a673c671a56 670 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
ebrus 0:0a673c671a56 671 #define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
ebrus 0:0a673c671a56 672 #define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
ebrus 0:0a673c671a56 673 #define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
ebrus 0:0a673c671a56 674 #define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
ebrus 0:0a673c671a56 675 #define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
ebrus 0:0a673c671a56 676
ebrus 0:0a673c671a56 677 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
ebrus 0:0a673c671a56 678 #define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
ebrus 0:0a673c671a56 679
ebrus 0:0a673c671a56 680 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
ebrus 0:0a673c671a56 681 #define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
ebrus 0:0a673c671a56 682
ebrus 0:0a673c671a56 683 #ifdef __cplusplus
ebrus 0:0a673c671a56 684 }
ebrus 0:0a673c671a56 685 #endif
ebrus 0:0a673c671a56 686
ebrus 0:0a673c671a56 687 #endif /* __LPC8xx_H__ */