Ermanno Brusadin / mbed-src

mbed library sources

targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

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ebrus 0:0a673c671a56 1 /*
ebrus 0:0a673c671a56 2 * LPC43xx/LPC18xx MCU header
ebrus 0:0a673c671a56 3 *
ebrus 0:0a673c671a56 4 * Copyright(C) NXP Semiconductors, 2012
ebrus 0:0a673c671a56 5 * All rights reserved.
ebrus 0:0a673c671a56 6 *
ebrus 0:0a673c671a56 7 * Software that is described herein is for illustrative purposes only
ebrus 0:0a673c671a56 8 * which provides customers with programming information regarding the
ebrus 0:0a673c671a56 9 * LPC products. This software is supplied "AS IS" without any warranties of
ebrus 0:0a673c671a56 10 * any kind, and NXP Semiconductors and its licensor disclaim any and
ebrus 0:0a673c671a56 11 * all warranties, express or implied, including all implied warranties of
ebrus 0:0a673c671a56 12 * merchantability, fitness for a particular purpose and non-infringement of
ebrus 0:0a673c671a56 13 * intellectual property rights. NXP Semiconductors assumes no responsibility
ebrus 0:0a673c671a56 14 * or liability for the use of the software, conveys no license or rights under any
ebrus 0:0a673c671a56 15 * patent, copyright, mask work right, or any other intellectual property rights in
ebrus 0:0a673c671a56 16 * or to any products. NXP Semiconductors reserves the right to make changes
ebrus 0:0a673c671a56 17 * in the software without notification. NXP Semiconductors also makes no
ebrus 0:0a673c671a56 18 * representation or warranty that such application will be suitable for the
ebrus 0:0a673c671a56 19 * specified use without further testing or modification.
ebrus 0:0a673c671a56 20 *
ebrus 0:0a673c671a56 21 * Permission to use, copy, modify, and distribute this software and its
ebrus 0:0a673c671a56 22 * documentation is hereby granted, under NXP Semiconductors' and its
ebrus 0:0a673c671a56 23 * licensor's relevant copyrights in the software, without fee, provided that it
ebrus 0:0a673c671a56 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
ebrus 0:0a673c671a56 25 * copyright, permission, and disclaimer notice must appear in all copies of
ebrus 0:0a673c671a56 26 * this code.
ebrus 0:0a673c671a56 27 *
ebrus 0:0a673c671a56 28 * Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
ebrus 0:0a673c671a56 29 * 05/15/13 Micromint USA <support@micromint.com>
ebrus 0:0a673c671a56 30 */
ebrus 0:0a673c671a56 31
ebrus 0:0a673c671a56 32 #ifndef __LPC43XX_H
ebrus 0:0a673c671a56 33 #define __LPC43XX_H
ebrus 0:0a673c671a56 34
ebrus 0:0a673c671a56 35 #ifdef __cplusplus
ebrus 0:0a673c671a56 36 extern "C" {
ebrus 0:0a673c671a56 37 #endif
ebrus 0:0a673c671a56 38
ebrus 0:0a673c671a56 39 /* Treat __CORE_Mx as CORE_Mx */
ebrus 0:0a673c671a56 40 #if defined(__CORTEX_M0) && !defined(CORE_M0)
ebrus 0:0a673c671a56 41 #define CORE_M0
ebrus 0:0a673c671a56 42 #endif
ebrus 0:0a673c671a56 43 #if defined(__CORTEX_M3) && !defined(CORE_M3)
ebrus 0:0a673c671a56 44 #define CORE_M3
ebrus 0:0a673c671a56 45 #endif
ebrus 0:0a673c671a56 46 /* Default to M4 core if no core explicitly declared */
ebrus 0:0a673c671a56 47 #if !defined(CORE_M0) && !defined(CORE_M3)
ebrus 0:0a673c671a56 48 #define CORE_M4
ebrus 0:0a673c671a56 49 #endif
ebrus 0:0a673c671a56 50
ebrus 0:0a673c671a56 51 /* Define LPC18XX or LPC43XX according to core type */
ebrus 0:0a673c671a56 52 #if (defined(CORE_M4) || defined(CORE_M0)) && !defined(__LPC43XX__)
ebrus 0:0a673c671a56 53 #define __LPC43XX__
ebrus 0:0a673c671a56 54 #endif
ebrus 0:0a673c671a56 55 #if defined(CORE_M3) && !defined(__LPC18XX__)
ebrus 0:0a673c671a56 56 #define __LPC18XX__
ebrus 0:0a673c671a56 57 #endif
ebrus 0:0a673c671a56 58
ebrus 0:0a673c671a56 59 /* Start of section using anonymous unions */
ebrus 0:0a673c671a56 60 #if defined(__ARMCC_VERSION)
ebrus 0:0a673c671a56 61 // Kill warning "#pragma push with no matching #pragma pop"
ebrus 0:0a673c671a56 62 #pragma diag_suppress 2525
ebrus 0:0a673c671a56 63 #pragma push
ebrus 0:0a673c671a56 64 #pragma anon_unions
ebrus 0:0a673c671a56 65 #elif defined(__CWCC__)
ebrus 0:0a673c671a56 66 #pragma push
ebrus 0:0a673c671a56 67 #pragma cpp_extensions on
ebrus 0:0a673c671a56 68 #elif defined(__IAR_SYSTEMS_ICC__)
ebrus 0:0a673c671a56 69 //#pragma push // FIXME not usable for IAR
ebrus 0:0a673c671a56 70 #pragma language=extended
ebrus 0:0a673c671a56 71 #else /* defined(__GNUC__) and others */
ebrus 0:0a673c671a56 72 /* Assume anonymous unions are enabled by default */
ebrus 0:0a673c671a56 73 #endif
ebrus 0:0a673c671a56 74
ebrus 0:0a673c671a56 75 #if defined(CORE_M4)
ebrus 0:0a673c671a56 76 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 77 * LPC43xx (M4 Core) Cortex CMSIS definitions
ebrus 0:0a673c671a56 78 */
ebrus 0:0a673c671a56 79
ebrus 0:0a673c671a56 80 #define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
ebrus 0:0a673c671a56 81 #define __MPU_PRESENT 1 /* MPU present or not */
ebrus 0:0a673c671a56 82 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
ebrus 0:0a673c671a56 83 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
ebrus 0:0a673c671a56 84 #define __FPU_PRESENT 1 /* FPU present or not */
ebrus 0:0a673c671a56 85 #define CHIP_LPC43XX /* LPCOPEN compatibility */
ebrus 0:0a673c671a56 86
ebrus 0:0a673c671a56 87 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 88 * LPC43xx peripheral interrupt numbers
ebrus 0:0a673c671a56 89 */
ebrus 0:0a673c671a56 90
ebrus 0:0a673c671a56 91 typedef enum {
ebrus 0:0a673c671a56 92 /* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
ebrus 0:0a673c671a56 93 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
ebrus 0:0a673c671a56 94 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
ebrus 0:0a673c671a56 95 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
ebrus 0:0a673c671a56 96 MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
ebrus 0:0a673c671a56 97 BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
ebrus 0:0a673c671a56 98 UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
ebrus 0:0a673c671a56 99 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
ebrus 0:0a673c671a56 100 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
ebrus 0:0a673c671a56 101 PendSV_IRQn = -2,/* 14 Pendable request for system service */
ebrus 0:0a673c671a56 102 SysTick_IRQn = -1,/* 15 System Tick Timer */
ebrus 0:0a673c671a56 103
ebrus 0:0a673c671a56 104 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
ebrus 0:0a673c671a56 105 DAC_IRQn = 0,/* 0 DAC */
ebrus 0:0a673c671a56 106 M0CORE_IRQn = 1,/* 1 M0a */
ebrus 0:0a673c671a56 107 DMA_IRQn = 2,/* 2 DMA */
ebrus 0:0a673c671a56 108 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
ebrus 0:0a673c671a56 109 RESERVED2_IRQn = 4,
ebrus 0:0a673c671a56 110 ETHERNET_IRQn = 5,/* 5 ETHERNET */
ebrus 0:0a673c671a56 111 SDIO_IRQn = 6,/* 6 SDIO */
ebrus 0:0a673c671a56 112 LCD_IRQn = 7,/* 7 LCD */
ebrus 0:0a673c671a56 113 USB0_IRQn = 8,/* 8 USB0 */
ebrus 0:0a673c671a56 114 USB1_IRQn = 9,/* 9 USB1 */
ebrus 0:0a673c671a56 115 SCT_IRQn = 10,/* 10 SCT */
ebrus 0:0a673c671a56 116 RITIMER_IRQn = 11,/* 11 RITIMER */
ebrus 0:0a673c671a56 117 TIMER0_IRQn = 12,/* 12 TIMER0 */
ebrus 0:0a673c671a56 118 TIMER1_IRQn = 13,/* 13 TIMER1 */
ebrus 0:0a673c671a56 119 TIMER2_IRQn = 14,/* 14 TIMER2 */
ebrus 0:0a673c671a56 120 TIMER3_IRQn = 15,/* 15 TIMER3 */
ebrus 0:0a673c671a56 121 MCPWM_IRQn = 16,/* 16 MCPWM */
ebrus 0:0a673c671a56 122 ADC0_IRQn = 17,/* 17 ADC0 */
ebrus 0:0a673c671a56 123 I2C0_IRQn = 18,/* 18 I2C0 */
ebrus 0:0a673c671a56 124 I2C1_IRQn = 19,/* 19 I2C1 */
ebrus 0:0a673c671a56 125 SPI_INT_IRQn = 20,/* 20 SPI_INT */
ebrus 0:0a673c671a56 126 ADC1_IRQn = 21,/* 21 ADC1 */
ebrus 0:0a673c671a56 127 SSP0_IRQn = 22,/* 22 SSP0 */
ebrus 0:0a673c671a56 128 SSP1_IRQn = 23,/* 23 SSP1 */
ebrus 0:0a673c671a56 129 USART0_IRQn = 24,/* 24 USART0 */
ebrus 0:0a673c671a56 130 UART1_IRQn = 25,/* 25 UART1 */
ebrus 0:0a673c671a56 131 USART2_IRQn = 26,/* 26 USART2 */
ebrus 0:0a673c671a56 132 USART3_IRQn = 27,/* 27 USART3 */
ebrus 0:0a673c671a56 133 I2S0_IRQn = 28,/* 28 I2S0 */
ebrus 0:0a673c671a56 134 I2S1_IRQn = 29,/* 29 I2S1 */
ebrus 0:0a673c671a56 135 RESERVED4_IRQn = 30,
ebrus 0:0a673c671a56 136 SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
ebrus 0:0a673c671a56 137 PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
ebrus 0:0a673c671a56 138 PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
ebrus 0:0a673c671a56 139 PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
ebrus 0:0a673c671a56 140 PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
ebrus 0:0a673c671a56 141 PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
ebrus 0:0a673c671a56 142 PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
ebrus 0:0a673c671a56 143 PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
ebrus 0:0a673c671a56 144 PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
ebrus 0:0a673c671a56 145 GINT0_IRQn = 40,/* 40 GINT0 */
ebrus 0:0a673c671a56 146 GINT1_IRQn = 41,/* 41 GINT1 */
ebrus 0:0a673c671a56 147 EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
ebrus 0:0a673c671a56 148 C_CAN1_IRQn = 43,/* 43 C_CAN1 */
ebrus 0:0a673c671a56 149 RESERVED6_IRQn = 44,
ebrus 0:0a673c671a56 150 RESERVED7_IRQn = 45,/* 45 VADC */
ebrus 0:0a673c671a56 151 ATIMER_IRQn = 46,/* 46 ATIMER */
ebrus 0:0a673c671a56 152 RTC_IRQn = 47,/* 47 RTC */
ebrus 0:0a673c671a56 153 RESERVED8_IRQn = 48,
ebrus 0:0a673c671a56 154 WWDT_IRQn = 49,/* 49 WWDT */
ebrus 0:0a673c671a56 155 RESERVED9_IRQn = 50,
ebrus 0:0a673c671a56 156 C_CAN0_IRQn = 51,/* 51 C_CAN0 */
ebrus 0:0a673c671a56 157 QEI_IRQn = 52,/* 52 QEI */
ebrus 0:0a673c671a56 158 } IRQn_Type;
ebrus 0:0a673c671a56 159
ebrus 0:0a673c671a56 160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
ebrus 0:0a673c671a56 161
ebrus 0:0a673c671a56 162 #elif defined(CORE_M3)
ebrus 0:0a673c671a56 163 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 164 * LPC18xx (M3 Core) Cortex CMSIS definitions
ebrus 0:0a673c671a56 165 */
ebrus 0:0a673c671a56 166 #define __MPU_PRESENT 1 /* MPU present or not */
ebrus 0:0a673c671a56 167 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
ebrus 0:0a673c671a56 168 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
ebrus 0:0a673c671a56 169 #define __FPU_PRESENT 0 /* FPU present or not */
ebrus 0:0a673c671a56 170 #define CHIP_LPC18XX /* LPCOPEN compatibility */
ebrus 0:0a673c671a56 171
ebrus 0:0a673c671a56 172 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 173 * LPC18xx peripheral interrupt numbers
ebrus 0:0a673c671a56 174 */
ebrus 0:0a673c671a56 175
ebrus 0:0a673c671a56 176 typedef enum {
ebrus 0:0a673c671a56 177 /* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
ebrus 0:0a673c671a56 178 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
ebrus 0:0a673c671a56 179 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
ebrus 0:0a673c671a56 180 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
ebrus 0:0a673c671a56 181 MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
ebrus 0:0a673c671a56 182 BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
ebrus 0:0a673c671a56 183 UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
ebrus 0:0a673c671a56 184 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
ebrus 0:0a673c671a56 185 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
ebrus 0:0a673c671a56 186 PendSV_IRQn = -2,/* 14 Pendable request for system service */
ebrus 0:0a673c671a56 187 SysTick_IRQn = -1,/* 15 System Tick Timer */
ebrus 0:0a673c671a56 188
ebrus 0:0a673c671a56 189 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
ebrus 0:0a673c671a56 190 DAC_IRQn = 0,/* 0 DAC */
ebrus 0:0a673c671a56 191 RESERVED0_IRQn = 1,
ebrus 0:0a673c671a56 192 DMA_IRQn = 2,/* 2 DMA */
ebrus 0:0a673c671a56 193 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
ebrus 0:0a673c671a56 194 RESERVED2_IRQn = 4,
ebrus 0:0a673c671a56 195 ETHERNET_IRQn = 5,/* 5 ETHERNET */
ebrus 0:0a673c671a56 196 SDIO_IRQn = 6,/* 6 SDIO */
ebrus 0:0a673c671a56 197 LCD_IRQn = 7,/* 7 LCD */
ebrus 0:0a673c671a56 198 USB0_IRQn = 8,/* 8 USB0 */
ebrus 0:0a673c671a56 199 USB1_IRQn = 9,/* 9 USB1 */
ebrus 0:0a673c671a56 200 SCT_IRQn = 10,/* 10 SCT */
ebrus 0:0a673c671a56 201 RITIMER_IRQn = 11,/* 11 RITIMER */
ebrus 0:0a673c671a56 202 TIMER0_IRQn = 12,/* 12 TIMER0 */
ebrus 0:0a673c671a56 203 TIMER1_IRQn = 13,/* 13 TIMER1 */
ebrus 0:0a673c671a56 204 TIMER2_IRQn = 14,/* 14 TIMER2 */
ebrus 0:0a673c671a56 205 TIMER3_IRQn = 15,/* 15 TIMER3 */
ebrus 0:0a673c671a56 206 MCPWM_IRQn = 16,/* 16 MCPWM */
ebrus 0:0a673c671a56 207 ADC0_IRQn = 17,/* 17 ADC0 */
ebrus 0:0a673c671a56 208 I2C0_IRQn = 18,/* 18 I2C0 */
ebrus 0:0a673c671a56 209 I2C1_IRQn = 19,/* 19 I2C1 */
ebrus 0:0a673c671a56 210 RESERVED3_IRQn = 20,
ebrus 0:0a673c671a56 211 ADC1_IRQn = 21,/* 21 ADC1 */
ebrus 0:0a673c671a56 212 SSP0_IRQn = 22,/* 22 SSP0 */
ebrus 0:0a673c671a56 213 SSP1_IRQn = 23,/* 23 SSP1 */
ebrus 0:0a673c671a56 214 USART0_IRQn = 24,/* 24 USART0 */
ebrus 0:0a673c671a56 215 UART1_IRQn = 25,/* 25 UART1 */
ebrus 0:0a673c671a56 216 USART2_IRQn = 26,/* 26 USART2 */
ebrus 0:0a673c671a56 217 USART3_IRQn = 27,/* 27 USART3 */
ebrus 0:0a673c671a56 218 I2S0_IRQn = 28,/* 28 I2S0 */
ebrus 0:0a673c671a56 219 I2S1_IRQn = 29,/* 29 I2S1 */
ebrus 0:0a673c671a56 220 RESERVED4_IRQn = 30,
ebrus 0:0a673c671a56 221 RESERVED5_IRQn = 31,
ebrus 0:0a673c671a56 222 PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
ebrus 0:0a673c671a56 223 PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
ebrus 0:0a673c671a56 224 PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
ebrus 0:0a673c671a56 225 PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
ebrus 0:0a673c671a56 226 PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
ebrus 0:0a673c671a56 227 PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
ebrus 0:0a673c671a56 228 PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
ebrus 0:0a673c671a56 229 PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
ebrus 0:0a673c671a56 230 GINT0_IRQn = 40,/* 40 GINT0 */
ebrus 0:0a673c671a56 231 GINT1_IRQn = 41,/* 41 GINT1 */
ebrus 0:0a673c671a56 232 EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
ebrus 0:0a673c671a56 233 C_CAN1_IRQn = 43,/* 43 C_CAN1 */
ebrus 0:0a673c671a56 234 RESERVED6_IRQn = 44,
ebrus 0:0a673c671a56 235 RESERVED7_IRQn = 45,/* 45 VADC */
ebrus 0:0a673c671a56 236 ATIMER_IRQn = 46,/* 46 ATIMER */
ebrus 0:0a673c671a56 237 RTC_IRQn = 47,/* 47 RTC */
ebrus 0:0a673c671a56 238 RESERVED8_IRQn = 48,
ebrus 0:0a673c671a56 239 WWDT_IRQn = 49,/* 49 WWDT */
ebrus 0:0a673c671a56 240 RESERVED9_IRQn = 50,
ebrus 0:0a673c671a56 241 C_CAN0_IRQn = 51,/* 51 C_CAN0 */
ebrus 0:0a673c671a56 242 QEI_IRQn = 52,/* 52 QEI */
ebrus 0:0a673c671a56 243 } IRQn_Type;
ebrus 0:0a673c671a56 244
ebrus 0:0a673c671a56 245 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
ebrus 0:0a673c671a56 246
ebrus 0:0a673c671a56 247 #elif defined(CORE_M0)
ebrus 0:0a673c671a56 248 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 249 * LPC43xx (M0 Core) Cortex CMSIS definitions
ebrus 0:0a673c671a56 250 */
ebrus 0:0a673c671a56 251
ebrus 0:0a673c671a56 252 #define __MPU_PRESENT 0 /* MPU present or not */
ebrus 0:0a673c671a56 253 #define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
ebrus 0:0a673c671a56 254 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
ebrus 0:0a673c671a56 255 #define __FPU_PRESENT 0 /* FPU present or not */
ebrus 0:0a673c671a56 256 #define CHIP_LPC43XX /* LPCOPEN compatibility */
ebrus 0:0a673c671a56 257
ebrus 0:0a673c671a56 258 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 259 * LPC43xx (M0 Core) peripheral interrupt numbers
ebrus 0:0a673c671a56 260 */
ebrus 0:0a673c671a56 261
ebrus 0:0a673c671a56 262 typedef enum {
ebrus 0:0a673c671a56 263 /* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
ebrus 0:0a673c671a56 264 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
ebrus 0:0a673c671a56 265 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
ebrus 0:0a673c671a56 266 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
ebrus 0:0a673c671a56 267 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
ebrus 0:0a673c671a56 268 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
ebrus 0:0a673c671a56 269 PendSV_IRQn = -2,/* 14 Pendable request for system service */
ebrus 0:0a673c671a56 270 SysTick_IRQn = -1,/* 15 System Tick Timer */
ebrus 0:0a673c671a56 271
ebrus 0:0a673c671a56 272 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
ebrus 0:0a673c671a56 273 DAC_IRQn = 0,/* 0 DAC */
ebrus 0:0a673c671a56 274 M0_M4CORE_IRQn = 1,/* 1 M0a */
ebrus 0:0a673c671a56 275 DMA_IRQn = 2,/* 2 DMA r */
ebrus 0:0a673c671a56 276 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
ebrus 0:0a673c671a56 277 FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
ebrus 0:0a673c671a56 278 ETHERNET_IRQn = 5,/* 5 ETHERNET */
ebrus 0:0a673c671a56 279 SDIO_IRQn = 6,/* 6 SDIO */
ebrus 0:0a673c671a56 280 LCD_IRQn = 7,/* 7 LCD */
ebrus 0:0a673c671a56 281 USB0_IRQn = 8,/* 8 USB0 */
ebrus 0:0a673c671a56 282 USB1_IRQn = 9,/* 9 USB1 */
ebrus 0:0a673c671a56 283 SCT_IRQn = 10,/* 10 SCT */
ebrus 0:0a673c671a56 284 RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
ebrus 0:0a673c671a56 285 TIMER0_IRQn = 12,/* 12 TIMER0 */
ebrus 0:0a673c671a56 286 GINT1_IRQn = 13,/* 13 GINT1 */
ebrus 0:0a673c671a56 287 PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
ebrus 0:0a673c671a56 288 TIMER3_IRQn = 15,/* 15 TIMER3 */
ebrus 0:0a673c671a56 289 MCPWM_IRQn = 16,/* 16 MCPWM */
ebrus 0:0a673c671a56 290 ADC0_IRQn = 17,/* 17 ADC0 */
ebrus 0:0a673c671a56 291 I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
ebrus 0:0a673c671a56 292 SGPIO_INT_IRQn = 19,/* 19 SGPIO */
ebrus 0:0a673c671a56 293 SPI_INT_IRQn = 20,/* 20 SPI_INT */
ebrus 0:0a673c671a56 294 ADC1_IRQn = 21,/* 21 ADC1 */
ebrus 0:0a673c671a56 295 SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
ebrus 0:0a673c671a56 296 EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
ebrus 0:0a673c671a56 297 USART0_IRQn = 24,/* 24 USART0 */
ebrus 0:0a673c671a56 298 UART1_IRQn = 25,/* 25 UART1 */
ebrus 0:0a673c671a56 299 USART2_IRQn = 26,/* 26 USART2 */
ebrus 0:0a673c671a56 300 USART3_IRQn = 27,/* 27 USART3 */
ebrus 0:0a673c671a56 301 I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
ebrus 0:0a673c671a56 302 C_CAN0_IRQn = 29,/* 29 C_CAN0 */
ebrus 0:0a673c671a56 303 I2S1_IRQn = 29,/* 29 I2S1 */
ebrus 0:0a673c671a56 304 RESERVED2_IRQn = 30,
ebrus 0:0a673c671a56 305 RESERVED3_IRQn = 31,
ebrus 0:0a673c671a56 306 } IRQn_Type;
ebrus 0:0a673c671a56 307
ebrus 0:0a673c671a56 308 #include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
ebrus 0:0a673c671a56 309 #else
ebrus 0:0a673c671a56 310 #error Please #define CORE_M0, CORE_M3 or CORE_M4
ebrus 0:0a673c671a56 311 #endif
ebrus 0:0a673c671a56 312
ebrus 0:0a673c671a56 313 #include "system_LPC43xx.h"
ebrus 0:0a673c671a56 314
ebrus 0:0a673c671a56 315 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 316 * State Configurable Timer register block structure
ebrus 0:0a673c671a56 317 */
ebrus 0:0a673c671a56 318 #define LPC_SCT_BASE 0x40000000
ebrus 0:0a673c671a56 319 #define CONFIG_SCT_nEV (16) /* Number of events */
ebrus 0:0a673c671a56 320 #define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
ebrus 0:0a673c671a56 321 #define CONFIG_SCT_nOU (16) /* Number of outputs */
ebrus 0:0a673c671a56 322
ebrus 0:0a673c671a56 323 typedef struct {
ebrus 0:0a673c671a56 324 __IO uint32_t CONFIG; /* Configuration Register */
ebrus 0:0a673c671a56 325 union {
ebrus 0:0a673c671a56 326 __IO uint32_t CTRL_U; /* Control Register */
ebrus 0:0a673c671a56 327 struct {
ebrus 0:0a673c671a56 328 __IO uint16_t CTRL_L; /* Low control register */
ebrus 0:0a673c671a56 329 __IO uint16_t CTRL_H; /* High control register */
ebrus 0:0a673c671a56 330 };
ebrus 0:0a673c671a56 331
ebrus 0:0a673c671a56 332 };
ebrus 0:0a673c671a56 333
ebrus 0:0a673c671a56 334 __IO uint16_t LIMIT_L; /* limit register for counter L */
ebrus 0:0a673c671a56 335 __IO uint16_t LIMIT_H; /* limit register for counter H */
ebrus 0:0a673c671a56 336 __IO uint16_t HALT_L; /* halt register for counter L */
ebrus 0:0a673c671a56 337 __IO uint16_t HALT_H; /* halt register for counter H */
ebrus 0:0a673c671a56 338 __IO uint16_t STOP_L; /* stop register for counter L */
ebrus 0:0a673c671a56 339 __IO uint16_t STOP_H; /* stop register for counter H */
ebrus 0:0a673c671a56 340 __IO uint16_t START_L; /* start register for counter L */
ebrus 0:0a673c671a56 341 __IO uint16_t START_H; /* start register for counter H */
ebrus 0:0a673c671a56 342 uint32_t RESERVED1[10]; /* 0x03C reserved */
ebrus 0:0a673c671a56 343 union {
ebrus 0:0a673c671a56 344 __IO uint32_t COUNT_U; /* counter register */
ebrus 0:0a673c671a56 345 struct {
ebrus 0:0a673c671a56 346 __IO uint16_t COUNT_L; /* counter register for counter L */
ebrus 0:0a673c671a56 347 __IO uint16_t COUNT_H; /* counter register for counter H */
ebrus 0:0a673c671a56 348 };
ebrus 0:0a673c671a56 349
ebrus 0:0a673c671a56 350 };
ebrus 0:0a673c671a56 351
ebrus 0:0a673c671a56 352 __IO uint16_t STATE_L; /* state register for counter L */
ebrus 0:0a673c671a56 353 __IO uint16_t STATE_H; /* state register for counter H */
ebrus 0:0a673c671a56 354 __I uint32_t INPUT; /* input register */
ebrus 0:0a673c671a56 355 __IO uint16_t REGMODE_L; /* match - capture registers mode register L */
ebrus 0:0a673c671a56 356 __IO uint16_t REGMODE_H; /* match - capture registers mode register H */
ebrus 0:0a673c671a56 357 __IO uint32_t OUTPUT; /* output register */
ebrus 0:0a673c671a56 358 __IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
ebrus 0:0a673c671a56 359 __IO uint32_t RES; /* conflict resolution register */
ebrus 0:0a673c671a56 360 __IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
ebrus 0:0a673c671a56 361 __IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
ebrus 0:0a673c671a56 362 uint32_t RESERVED2[35];
ebrus 0:0a673c671a56 363 __IO uint32_t EVEN; /* event enable register */
ebrus 0:0a673c671a56 364 __IO uint32_t EVFLAG; /* event flag register */
ebrus 0:0a673c671a56 365 __IO uint32_t CONEN; /* conflict enable register */
ebrus 0:0a673c671a56 366 __IO uint32_t CONFLAG; /* conflict flag register */
ebrus 0:0a673c671a56 367 union {
ebrus 0:0a673c671a56 368 __IO union { /* ... Match / Capture value */
ebrus 0:0a673c671a56 369 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
ebrus 0:0a673c671a56 370 struct {
ebrus 0:0a673c671a56 371 uint16_t L; /* SCTMATCH[i].L Access to L value */
ebrus 0:0a673c671a56 372 uint16_t H; /* SCTMATCH[i].H Access to H value */
ebrus 0:0a673c671a56 373 };
ebrus 0:0a673c671a56 374
ebrus 0:0a673c671a56 375 } MATCH[CONFIG_SCT_nRG];
ebrus 0:0a673c671a56 376
ebrus 0:0a673c671a56 377 __I union {
ebrus 0:0a673c671a56 378 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
ebrus 0:0a673c671a56 379 struct {
ebrus 0:0a673c671a56 380 uint16_t L; /* SCTCAP[i].L Access to L value */
ebrus 0:0a673c671a56 381 uint16_t H; /* SCTCAP[i].H Access to H value */
ebrus 0:0a673c671a56 382 };
ebrus 0:0a673c671a56 383
ebrus 0:0a673c671a56 384 } CAP[CONFIG_SCT_nRG];
ebrus 0:0a673c671a56 385
ebrus 0:0a673c671a56 386 };
ebrus 0:0a673c671a56 387
ebrus 0:0a673c671a56 388 uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
ebrus 0:0a673c671a56 389 union {
ebrus 0:0a673c671a56 390 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
ebrus 0:0a673c671a56 391 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
ebrus 0:0a673c671a56 392 };
ebrus 0:0a673c671a56 393
ebrus 0:0a673c671a56 394 uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
ebrus 0:0a673c671a56 395 union {
ebrus 0:0a673c671a56 396 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
ebrus 0:0a673c671a56 397 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
ebrus 0:0a673c671a56 398 };
ebrus 0:0a673c671a56 399
ebrus 0:0a673c671a56 400 uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
ebrus 0:0a673c671a56 401 union {
ebrus 0:0a673c671a56 402 __IO union { /* 0x200-... Match Reload / Capture Control value */
ebrus 0:0a673c671a56 403 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
ebrus 0:0a673c671a56 404 struct {
ebrus 0:0a673c671a56 405 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
ebrus 0:0a673c671a56 406 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
ebrus 0:0a673c671a56 407 };
ebrus 0:0a673c671a56 408
ebrus 0:0a673c671a56 409 } MATCHREL[CONFIG_SCT_nRG];
ebrus 0:0a673c671a56 410
ebrus 0:0a673c671a56 411 __IO union {
ebrus 0:0a673c671a56 412 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
ebrus 0:0a673c671a56 413 struct {
ebrus 0:0a673c671a56 414 uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
ebrus 0:0a673c671a56 415 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
ebrus 0:0a673c671a56 416 };
ebrus 0:0a673c671a56 417
ebrus 0:0a673c671a56 418 } CAPCTRL[CONFIG_SCT_nRG];
ebrus 0:0a673c671a56 419
ebrus 0:0a673c671a56 420 };
ebrus 0:0a673c671a56 421
ebrus 0:0a673c671a56 422 uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
ebrus 0:0a673c671a56 423 union {
ebrus 0:0a673c671a56 424 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
ebrus 0:0a673c671a56 425 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
ebrus 0:0a673c671a56 426 };
ebrus 0:0a673c671a56 427
ebrus 0:0a673c671a56 428 uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
ebrus 0:0a673c671a56 429 union {
ebrus 0:0a673c671a56 430 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
ebrus 0:0a673c671a56 431 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
ebrus 0:0a673c671a56 432 };
ebrus 0:0a673c671a56 433
ebrus 0:0a673c671a56 434 uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
ebrus 0:0a673c671a56 435 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
ebrus 0:0a673c671a56 436 uint32_t STATE; /* Event State Register */
ebrus 0:0a673c671a56 437 uint32_t CTRL; /* Event Control Register */
ebrus 0:0a673c671a56 438 } EVENT[CONFIG_SCT_nEV];
ebrus 0:0a673c671a56 439
ebrus 0:0a673c671a56 440 uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
ebrus 0:0a673c671a56 441 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
ebrus 0:0a673c671a56 442 uint32_t SET; /* Output n Set Register */
ebrus 0:0a673c671a56 443 uint32_t CLR; /* Output n Clear Register */
ebrus 0:0a673c671a56 444 } OUT[CONFIG_SCT_nOU];
ebrus 0:0a673c671a56 445
ebrus 0:0a673c671a56 446 uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
ebrus 0:0a673c671a56 447 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
ebrus 0:0a673c671a56 448 } LPC_SCT_T;
ebrus 0:0a673c671a56 449
ebrus 0:0a673c671a56 450 /* Macro defines for SCT configuration register */
ebrus 0:0a673c671a56 451 #define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
ebrus 0:0a673c671a56 452 #define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
ebrus 0:0a673c671a56 453
ebrus 0:0a673c671a56 454 #define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
ebrus 0:0a673c671a56 455 #define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
ebrus 0:0a673c671a56 456 #define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
ebrus 0:0a673c671a56 457 #define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
ebrus 0:0a673c671a56 458
ebrus 0:0a673c671a56 459 #define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
ebrus 0:0a673c671a56 460 #define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
ebrus 0:0a673c671a56 461
ebrus 0:0a673c671a56 462 /* Macro defines for SCT control register */
ebrus 0:0a673c671a56 463 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
ebrus 0:0a673c671a56 464 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
ebrus 0:0a673c671a56 465
ebrus 0:0a673c671a56 466 #define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
ebrus 0:0a673c671a56 467 #define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
ebrus 0:0a673c671a56 468 #define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
ebrus 0:0a673c671a56 469 #define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
ebrus 0:0a673c671a56 470 #define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
ebrus 0:0a673c671a56 471
ebrus 0:0a673c671a56 472 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
ebrus 0:0a673c671a56 473 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
ebrus 0:0a673c671a56 474 #define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
ebrus 0:0a673c671a56 475 #define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
ebrus 0:0a673c671a56 476 #define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
ebrus 0:0a673c671a56 477 #define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
ebrus 0:0a673c671a56 478 #define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
ebrus 0:0a673c671a56 479
ebrus 0:0a673c671a56 480 /* Macro defines for SCT Conflict resolution register */
ebrus 0:0a673c671a56 481 #define SCT_RES_NOCHANGE (0)
ebrus 0:0a673c671a56 482 #define SCT_RES_SET_OUTPUT (1)
ebrus 0:0a673c671a56 483 #define SCT_RES_CLEAR_OUTPUT (2)
ebrus 0:0a673c671a56 484 #define SCT_RES_TOGGLE_OUTPUT (3)
ebrus 0:0a673c671a56 485
ebrus 0:0a673c671a56 486 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 487 * GPDMA Channel register block structure
ebrus 0:0a673c671a56 488 */
ebrus 0:0a673c671a56 489 #define LPC_GPDMA_BASE 0x40002000
ebrus 0:0a673c671a56 490
ebrus 0:0a673c671a56 491 typedef struct {
ebrus 0:0a673c671a56 492 __IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
ebrus 0:0a673c671a56 493 __IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
ebrus 0:0a673c671a56 494 __IO uint32_t LLI; /* DMA Channel Linked List Item Register */
ebrus 0:0a673c671a56 495 __IO uint32_t CONTROL; /* DMA Channel Control Register */
ebrus 0:0a673c671a56 496 __IO uint32_t CONFIG; /* DMA Channel Configuration Register */
ebrus 0:0a673c671a56 497 __I uint32_t RESERVED1[3];
ebrus 0:0a673c671a56 498 } LPC_GPDMA_CH_T;
ebrus 0:0a673c671a56 499
ebrus 0:0a673c671a56 500 #define GPDMA_CHANNELS 8
ebrus 0:0a673c671a56 501
ebrus 0:0a673c671a56 502 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 503 * GPDMA register block
ebrus 0:0a673c671a56 504 */
ebrus 0:0a673c671a56 505 typedef struct { /* GPDMA Structure */
ebrus 0:0a673c671a56 506 __I uint32_t INTSTAT; /* DMA Interrupt Status Register */
ebrus 0:0a673c671a56 507 __I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
ebrus 0:0a673c671a56 508 __O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
ebrus 0:0a673c671a56 509 __I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
ebrus 0:0a673c671a56 510 __O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
ebrus 0:0a673c671a56 511 __I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
ebrus 0:0a673c671a56 512 __I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
ebrus 0:0a673c671a56 513 __I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
ebrus 0:0a673c671a56 514 __IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
ebrus 0:0a673c671a56 515 __IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
ebrus 0:0a673c671a56 516 __IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
ebrus 0:0a673c671a56 517 __IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
ebrus 0:0a673c671a56 518 __IO uint32_t CONFIG; /* DMA Configuration Register */
ebrus 0:0a673c671a56 519 __IO uint32_t SYNC; /* DMA Synchronization Register */
ebrus 0:0a673c671a56 520 __I uint32_t RESERVED0[50];
ebrus 0:0a673c671a56 521 LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
ebrus 0:0a673c671a56 522 } LPC_GPDMA_T;
ebrus 0:0a673c671a56 523
ebrus 0:0a673c671a56 524 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 525 * SPIFI register block structure
ebrus 0:0a673c671a56 526 */
ebrus 0:0a673c671a56 527 #define LPC_SPIFI_BASE 0x40003000
ebrus 0:0a673c671a56 528
ebrus 0:0a673c671a56 529 typedef struct { /* SPIFI Structure */
ebrus 0:0a673c671a56 530 __IO uint32_t CTRL; /* Control register */
ebrus 0:0a673c671a56 531 __IO uint32_t CMD; /* Command register */
ebrus 0:0a673c671a56 532 __IO uint32_t ADDR; /* Address register */
ebrus 0:0a673c671a56 533 __IO uint32_t IDATA; /* Intermediate data register */
ebrus 0:0a673c671a56 534 __IO uint32_t CLIMIT; /* Cache limit register */
ebrus 0:0a673c671a56 535 union {
ebrus 0:0a673c671a56 536 __IO uint32_t DATA;
ebrus 0:0a673c671a56 537 __IO uint16_t DATA_HWORD;
ebrus 0:0a673c671a56 538 __IO uint8_t DATA_BYTE;
ebrus 0:0a673c671a56 539 }; /* Data register */
ebrus 0:0a673c671a56 540 __IO uint32_t MCMD; /* Memory command register */
ebrus 0:0a673c671a56 541 __IO uint32_t STAT; /* Status register */
ebrus 0:0a673c671a56 542 } LPC_SPIFI_T;
ebrus 0:0a673c671a56 543
ebrus 0:0a673c671a56 544 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 545 * SD/MMC & SDIO register block structure
ebrus 0:0a673c671a56 546 */
ebrus 0:0a673c671a56 547 #define LPC_SDMMC_BASE 0x40004000
ebrus 0:0a673c671a56 548
ebrus 0:0a673c671a56 549 typedef struct { /* SDMMC Structure */
ebrus 0:0a673c671a56 550 __IO uint32_t CTRL; /* Control Register */
ebrus 0:0a673c671a56 551 __IO uint32_t PWREN; /* Power Enable Register */
ebrus 0:0a673c671a56 552 __IO uint32_t CLKDIV; /* Clock Divider Register */
ebrus 0:0a673c671a56 553 __IO uint32_t CLKSRC; /* SD Clock Source Register */
ebrus 0:0a673c671a56 554 __IO uint32_t CLKENA; /* Clock Enable Register */
ebrus 0:0a673c671a56 555 __IO uint32_t TMOUT; /* Timeout Register */
ebrus 0:0a673c671a56 556 __IO uint32_t CTYPE; /* Card Type Register */
ebrus 0:0a673c671a56 557 __IO uint32_t BLKSIZ; /* Block Size Register */
ebrus 0:0a673c671a56 558 __IO uint32_t BYTCNT; /* Byte Count Register */
ebrus 0:0a673c671a56 559 __IO uint32_t INTMASK; /* Interrupt Mask Register */
ebrus 0:0a673c671a56 560 __IO uint32_t CMDARG; /* Command Argument Register */
ebrus 0:0a673c671a56 561 __IO uint32_t CMD; /* Command Register */
ebrus 0:0a673c671a56 562 __I uint32_t RESP0; /* Response Register 0 */
ebrus 0:0a673c671a56 563 __I uint32_t RESP1; /* Response Register 1 */
ebrus 0:0a673c671a56 564 __I uint32_t RESP2; /* Response Register 2 */
ebrus 0:0a673c671a56 565 __I uint32_t RESP3; /* Response Register 3 */
ebrus 0:0a673c671a56 566 __I uint32_t MINTSTS; /* Masked Interrupt Status Register */
ebrus 0:0a673c671a56 567 __IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
ebrus 0:0a673c671a56 568 __I uint32_t STATUS; /* Status Register */
ebrus 0:0a673c671a56 569 __IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
ebrus 0:0a673c671a56 570 __I uint32_t CDETECT; /* Card Detect Register */
ebrus 0:0a673c671a56 571 __I uint32_t WRTPRT; /* Write Protect Register */
ebrus 0:0a673c671a56 572 __IO uint32_t GPIO; /* General Purpose Input/Output Register */
ebrus 0:0a673c671a56 573 __I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
ebrus 0:0a673c671a56 574 __I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
ebrus 0:0a673c671a56 575 __IO uint32_t DEBNCE; /* Debounce Count Register */
ebrus 0:0a673c671a56 576 __IO uint32_t USRID; /* User ID Register */
ebrus 0:0a673c671a56 577 __I uint32_t VERID; /* Version ID Register */
ebrus 0:0a673c671a56 578 __I uint32_t RESERVED0;
ebrus 0:0a673c671a56 579 __IO uint32_t UHS_REG; /* UHS-1 Register */
ebrus 0:0a673c671a56 580 __IO uint32_t RST_N; /* Hardware Reset */
ebrus 0:0a673c671a56 581 __I uint32_t RESERVED1;
ebrus 0:0a673c671a56 582 __IO uint32_t BMOD; /* Bus Mode Register */
ebrus 0:0a673c671a56 583 __O uint32_t PLDMND; /* Poll Demand Register */
ebrus 0:0a673c671a56 584 __IO uint32_t DBADDR; /* Descriptor List Base Address Register */
ebrus 0:0a673c671a56 585 __IO uint32_t IDSTS; /* Internal DMAC Status Register */
ebrus 0:0a673c671a56 586 __IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
ebrus 0:0a673c671a56 587 __I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
ebrus 0:0a673c671a56 588 __I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
ebrus 0:0a673c671a56 589 } LPC_SDMMC_T;
ebrus 0:0a673c671a56 590
ebrus 0:0a673c671a56 591 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 592 * External Memory Controller (EMC) register block structure
ebrus 0:0a673c671a56 593 */
ebrus 0:0a673c671a56 594 #define LPC_EMC_BASE 0x40005000
ebrus 0:0a673c671a56 595
ebrus 0:0a673c671a56 596 typedef struct { /* EMC Structure */
ebrus 0:0a673c671a56 597 __IO uint32_t CONTROL; /* Controls operation of the memory controller. */
ebrus 0:0a673c671a56 598 __I uint32_t STATUS; /* Provides EMC status information. */
ebrus 0:0a673c671a56 599 __IO uint32_t CONFIG; /* Configures operation of the memory controller. */
ebrus 0:0a673c671a56 600 __I uint32_t RESERVED0[5];
ebrus 0:0a673c671a56 601 __IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
ebrus 0:0a673c671a56 602 __IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
ebrus 0:0a673c671a56 603 __IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
ebrus 0:0a673c671a56 604 __I uint32_t RESERVED1;
ebrus 0:0a673c671a56 605 __IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
ebrus 0:0a673c671a56 606 __IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
ebrus 0:0a673c671a56 607 __IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
ebrus 0:0a673c671a56 608 __IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
ebrus 0:0a673c671a56 609 __IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
ebrus 0:0a673c671a56 610 __IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
ebrus 0:0a673c671a56 611 __IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
ebrus 0:0a673c671a56 612 __IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
ebrus 0:0a673c671a56 613 __IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
ebrus 0:0a673c671a56 614 __IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
ebrus 0:0a673c671a56 615 __IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
ebrus 0:0a673c671a56 616 __I uint32_t RESERVED2[9];
ebrus 0:0a673c671a56 617 __IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
ebrus 0:0a673c671a56 618 __I uint32_t RESERVED3[31];
ebrus 0:0a673c671a56 619 __IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
ebrus 0:0a673c671a56 620 __IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
ebrus 0:0a673c671a56 621 __I uint32_t RESERVED4[6];
ebrus 0:0a673c671a56 622 __IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
ebrus 0:0a673c671a56 623 __IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
ebrus 0:0a673c671a56 624 __I uint32_t RESERVED5[6];
ebrus 0:0a673c671a56 625 __IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
ebrus 0:0a673c671a56 626 __IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
ebrus 0:0a673c671a56 627 __I uint32_t RESERVED6[6];
ebrus 0:0a673c671a56 628 __IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
ebrus 0:0a673c671a56 629 __IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
ebrus 0:0a673c671a56 630 __I uint32_t RESERVED7[38];
ebrus 0:0a673c671a56 631 __IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
ebrus 0:0a673c671a56 632 __IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
ebrus 0:0a673c671a56 633 __IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
ebrus 0:0a673c671a56 634 __IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
ebrus 0:0a673c671a56 635 __IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
ebrus 0:0a673c671a56 636 __IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
ebrus 0:0a673c671a56 637 __IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
ebrus 0:0a673c671a56 638 __I uint32_t RESERVED8;
ebrus 0:0a673c671a56 639 __IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
ebrus 0:0a673c671a56 640 __IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
ebrus 0:0a673c671a56 641 __IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
ebrus 0:0a673c671a56 642 __IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
ebrus 0:0a673c671a56 643 __IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
ebrus 0:0a673c671a56 644 __IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
ebrus 0:0a673c671a56 645 __IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
ebrus 0:0a673c671a56 646 __I uint32_t RESERVED9;
ebrus 0:0a673c671a56 647 __IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
ebrus 0:0a673c671a56 648 __IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
ebrus 0:0a673c671a56 649 __IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
ebrus 0:0a673c671a56 650 __IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
ebrus 0:0a673c671a56 651 __IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
ebrus 0:0a673c671a56 652 __IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
ebrus 0:0a673c671a56 653 __IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
ebrus 0:0a673c671a56 654 __I uint32_t RESERVED10;
ebrus 0:0a673c671a56 655 __IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
ebrus 0:0a673c671a56 656 __IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
ebrus 0:0a673c671a56 657 __IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
ebrus 0:0a673c671a56 658 __IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
ebrus 0:0a673c671a56 659 __IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
ebrus 0:0a673c671a56 660 __IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
ebrus 0:0a673c671a56 661 __IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
ebrus 0:0a673c671a56 662 } LPC_EMC_T;
ebrus 0:0a673c671a56 663
ebrus 0:0a673c671a56 664 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 665 * USB High-Speed register block structure
ebrus 0:0a673c671a56 666 */
ebrus 0:0a673c671a56 667 #define LPC_USB0_BASE 0x40006000
ebrus 0:0a673c671a56 668 #define LPC_USB1_BASE 0x40007000
ebrus 0:0a673c671a56 669
ebrus 0:0a673c671a56 670 typedef struct { /* USB Structure */
ebrus 0:0a673c671a56 671 __I uint32_t RESERVED0[64];
ebrus 0:0a673c671a56 672 __I uint32_t CAPLENGTH; /* Capability register length */
ebrus 0:0a673c671a56 673 __I uint32_t HCSPARAMS; /* Host controller structural parameters */
ebrus 0:0a673c671a56 674 __I uint32_t HCCPARAMS; /* Host controller capability parameters */
ebrus 0:0a673c671a56 675 __I uint32_t RESERVED1[5];
ebrus 0:0a673c671a56 676 __I uint32_t DCIVERSION; /* Device interface version number */
ebrus 0:0a673c671a56 677 __I uint32_t RESERVED2[7];
ebrus 0:0a673c671a56 678 union {
ebrus 0:0a673c671a56 679 __IO uint32_t USBCMD_H; /* USB command (host mode) */
ebrus 0:0a673c671a56 680 __IO uint32_t USBCMD_D; /* USB command (device mode) */
ebrus 0:0a673c671a56 681 };
ebrus 0:0a673c671a56 682
ebrus 0:0a673c671a56 683 union {
ebrus 0:0a673c671a56 684 __IO uint32_t USBSTS_H; /* USB status (host mode) */
ebrus 0:0a673c671a56 685 __IO uint32_t USBSTS_D; /* USB status (device mode) */
ebrus 0:0a673c671a56 686 };
ebrus 0:0a673c671a56 687
ebrus 0:0a673c671a56 688 union {
ebrus 0:0a673c671a56 689 __IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
ebrus 0:0a673c671a56 690 __IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
ebrus 0:0a673c671a56 691 };
ebrus 0:0a673c671a56 692
ebrus 0:0a673c671a56 693 union {
ebrus 0:0a673c671a56 694 __IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
ebrus 0:0a673c671a56 695 __I uint32_t FRINDEX_D; /* USB frame index (device mode) */
ebrus 0:0a673c671a56 696 };
ebrus 0:0a673c671a56 697
ebrus 0:0a673c671a56 698 __I uint32_t RESERVED3;
ebrus 0:0a673c671a56 699 union {
ebrus 0:0a673c671a56 700 __IO uint32_t PERIODICLISTBASE; /* Frame list base address */
ebrus 0:0a673c671a56 701 __IO uint32_t DEVICEADDR; /* USB device address */
ebrus 0:0a673c671a56 702 };
ebrus 0:0a673c671a56 703
ebrus 0:0a673c671a56 704 union {
ebrus 0:0a673c671a56 705 __IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
ebrus 0:0a673c671a56 706 __IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
ebrus 0:0a673c671a56 707 };
ebrus 0:0a673c671a56 708
ebrus 0:0a673c671a56 709 __IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
ebrus 0:0a673c671a56 710 __IO uint32_t BURSTSIZE; /* Programmable burst size */
ebrus 0:0a673c671a56 711 __IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
ebrus 0:0a673c671a56 712 __I uint32_t RESERVED4[2];
ebrus 0:0a673c671a56 713 __IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
ebrus 0:0a673c671a56 714 __IO uint32_t BINTERVAL; /* Length of virtual frame */
ebrus 0:0a673c671a56 715 __IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
ebrus 0:0a673c671a56 716 __IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
ebrus 0:0a673c671a56 717 __I uint32_t RESERVED5;
ebrus 0:0a673c671a56 718 union {
ebrus 0:0a673c671a56 719 __IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
ebrus 0:0a673c671a56 720 __IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
ebrus 0:0a673c671a56 721 };
ebrus 0:0a673c671a56 722
ebrus 0:0a673c671a56 723 __I uint32_t RESERVED6[7];
ebrus 0:0a673c671a56 724 __IO uint32_t OTGSC; /* OTG status and control */
ebrus 0:0a673c671a56 725 union {
ebrus 0:0a673c671a56 726 __IO uint32_t USBMODE_H; /* USB mode (host mode) */
ebrus 0:0a673c671a56 727 __IO uint32_t USBMODE_D; /* USB mode (device mode) */
ebrus 0:0a673c671a56 728 };
ebrus 0:0a673c671a56 729
ebrus 0:0a673c671a56 730 __IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
ebrus 0:0a673c671a56 731 __IO uint32_t ENDPTPRIME; /* Endpoint initialization */
ebrus 0:0a673c671a56 732 __IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
ebrus 0:0a673c671a56 733 __I uint32_t ENDPTSTAT; /* Endpoint status */
ebrus 0:0a673c671a56 734 __IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
ebrus 0:0a673c671a56 735 __IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
ebrus 0:0a673c671a56 736 } LPC_USBHS_T;
ebrus 0:0a673c671a56 737
ebrus 0:0a673c671a56 738 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 739 * LCD Controller register block structure
ebrus 0:0a673c671a56 740 */
ebrus 0:0a673c671a56 741 #define LPC_LCD_BASE 0x40008000
ebrus 0:0a673c671a56 742
ebrus 0:0a673c671a56 743 typedef struct { /* LCD Structure */
ebrus 0:0a673c671a56 744 __IO uint32_t TIMH; /* Horizontal Timing Control register */
ebrus 0:0a673c671a56 745 __IO uint32_t TIMV; /* Vertical Timing Control register */
ebrus 0:0a673c671a56 746 __IO uint32_t POL; /* Clock and Signal Polarity Control register */
ebrus 0:0a673c671a56 747 __IO uint32_t LE; /* Line End Control register */
ebrus 0:0a673c671a56 748 __IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
ebrus 0:0a673c671a56 749 __IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
ebrus 0:0a673c671a56 750 __IO uint32_t CTRL; /* LCD Control register */
ebrus 0:0a673c671a56 751 __IO uint32_t INTMSK; /* Interrupt Mask register */
ebrus 0:0a673c671a56 752 __I uint32_t INTRAW; /* Raw Interrupt Status register */
ebrus 0:0a673c671a56 753 __I uint32_t INTSTAT; /* Masked Interrupt Status register */
ebrus 0:0a673c671a56 754 __O uint32_t INTCLR; /* Interrupt Clear register */
ebrus 0:0a673c671a56 755 __I uint32_t UPCURR; /* Upper Panel Current Address Value register */
ebrus 0:0a673c671a56 756 __I uint32_t LPCURR; /* Lower Panel Current Address Value register */
ebrus 0:0a673c671a56 757 __I uint32_t RESERVED0[115];
ebrus 0:0a673c671a56 758 __IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
ebrus 0:0a673c671a56 759 __I uint32_t RESERVED1[256];
ebrus 0:0a673c671a56 760 __IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
ebrus 0:0a673c671a56 761 __IO uint32_t CRSR_CTRL; /* Cursor Control register */
ebrus 0:0a673c671a56 762 __IO uint32_t CRSR_CFG; /* Cursor Configuration register */
ebrus 0:0a673c671a56 763 __IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
ebrus 0:0a673c671a56 764 __IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
ebrus 0:0a673c671a56 765 __IO uint32_t CRSR_XY; /* Cursor XY Position register */
ebrus 0:0a673c671a56 766 __IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
ebrus 0:0a673c671a56 767 __I uint32_t RESERVED2[2];
ebrus 0:0a673c671a56 768 __IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
ebrus 0:0a673c671a56 769 __O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
ebrus 0:0a673c671a56 770 __I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
ebrus 0:0a673c671a56 771 __I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
ebrus 0:0a673c671a56 772 } LPC_LCD_T;
ebrus 0:0a673c671a56 773
ebrus 0:0a673c671a56 774 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 775 * EEPROM register block structure
ebrus 0:0a673c671a56 776 */
ebrus 0:0a673c671a56 777 #define LPC_EEPROM_BASE 0x4000E000
ebrus 0:0a673c671a56 778
ebrus 0:0a673c671a56 779 typedef struct { /* EEPROM Structure */
ebrus 0:0a673c671a56 780 __IO uint32_t CMD; /* EEPROM command register */
ebrus 0:0a673c671a56 781 uint32_t RESERVED0;
ebrus 0:0a673c671a56 782 __IO uint32_t RWSTATE; /* EEPROM read wait state register */
ebrus 0:0a673c671a56 783 __IO uint32_t AUTOPROG; /* EEPROM auto programming register */
ebrus 0:0a673c671a56 784 __IO uint32_t WSTATE; /* EEPROM wait state register */
ebrus 0:0a673c671a56 785 __IO uint32_t CLKDIV; /* EEPROM clock divider register */
ebrus 0:0a673c671a56 786 __IO uint32_t PWRDWN; /* EEPROM power-down register */
ebrus 0:0a673c671a56 787 uint32_t RESERVED2[1007];
ebrus 0:0a673c671a56 788 __O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
ebrus 0:0a673c671a56 789 __O uint32_t INTENSET; /* EEPROM interrupt enable set */
ebrus 0:0a673c671a56 790 __I uint32_t INTSTAT; /* EEPROM interrupt status */
ebrus 0:0a673c671a56 791 __I uint32_t INTEN; /* EEPROM interrupt enable */
ebrus 0:0a673c671a56 792 __O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
ebrus 0:0a673c671a56 793 __O uint32_t INTSTATSET; /* EEPROM interrupt status set */
ebrus 0:0a673c671a56 794 } LPC_EEPROM_T;
ebrus 0:0a673c671a56 795
ebrus 0:0a673c671a56 796 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 797 * 10/100 MII & RMII Ethernet with timestamping register block structure
ebrus 0:0a673c671a56 798 */
ebrus 0:0a673c671a56 799 #define LPC_ETHERNET_BASE 0x40010000
ebrus 0:0a673c671a56 800
ebrus 0:0a673c671a56 801 typedef struct { /* ETHERNET Structure */
ebrus 0:0a673c671a56 802 __IO uint32_t MAC_CONFIG; /* MAC configuration register */
ebrus 0:0a673c671a56 803 __IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
ebrus 0:0a673c671a56 804 __IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
ebrus 0:0a673c671a56 805 __IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
ebrus 0:0a673c671a56 806 __IO uint32_t MAC_MII_ADDR; /* MII address register */
ebrus 0:0a673c671a56 807 __IO uint32_t MAC_MII_DATA; /* MII data register */
ebrus 0:0a673c671a56 808 __IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
ebrus 0:0a673c671a56 809 __IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
ebrus 0:0a673c671a56 810 __I uint32_t RESERVED0;
ebrus 0:0a673c671a56 811 __I uint32_t MAC_DEBUG; /* Debug register */
ebrus 0:0a673c671a56 812 __IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
ebrus 0:0a673c671a56 813 __IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
ebrus 0:0a673c671a56 814 __I uint32_t RESERVED1[2];
ebrus 0:0a673c671a56 815 __I uint32_t MAC_INTR; /* Interrupt status register */
ebrus 0:0a673c671a56 816 __IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
ebrus 0:0a673c671a56 817 __IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
ebrus 0:0a673c671a56 818 __IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
ebrus 0:0a673c671a56 819 __I uint32_t RESERVED2[430];
ebrus 0:0a673c671a56 820 __IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
ebrus 0:0a673c671a56 821 __IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
ebrus 0:0a673c671a56 822 __I uint32_t SECONDS; /* System time seconds register */
ebrus 0:0a673c671a56 823 __I uint32_t NANOSECONDS; /* System time nanoseconds register */
ebrus 0:0a673c671a56 824 __IO uint32_t SECONDSUPDATE; /* System time seconds update register */
ebrus 0:0a673c671a56 825 __IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
ebrus 0:0a673c671a56 826 __IO uint32_t ADDEND; /* Time stamp addend register */
ebrus 0:0a673c671a56 827 __IO uint32_t TARGETSECONDS; /* Target time seconds register */
ebrus 0:0a673c671a56 828 __IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
ebrus 0:0a673c671a56 829 __IO uint32_t HIGHWORD; /* System time higher word seconds register */
ebrus 0:0a673c671a56 830 __I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
ebrus 0:0a673c671a56 831 __IO uint32_t PPSCTRL; /* PPS control register */
ebrus 0:0a673c671a56 832 __I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
ebrus 0:0a673c671a56 833 __I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
ebrus 0:0a673c671a56 834 __I uint32_t RESERVED3[562];
ebrus 0:0a673c671a56 835 __IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
ebrus 0:0a673c671a56 836 __IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
ebrus 0:0a673c671a56 837 __IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
ebrus 0:0a673c671a56 838 __IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
ebrus 0:0a673c671a56 839 __IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
ebrus 0:0a673c671a56 840 __IO uint32_t DMA_STAT; /* Status register */
ebrus 0:0a673c671a56 841 __IO uint32_t DMA_OP_MODE; /* Operation mode register */
ebrus 0:0a673c671a56 842 __IO uint32_t DMA_INT_EN; /* Interrupt enable register */
ebrus 0:0a673c671a56 843 __I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
ebrus 0:0a673c671a56 844 __IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
ebrus 0:0a673c671a56 845 __I uint32_t RESERVED4[8];
ebrus 0:0a673c671a56 846 __I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
ebrus 0:0a673c671a56 847 __I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
ebrus 0:0a673c671a56 848 __I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
ebrus 0:0a673c671a56 849 __I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
ebrus 0:0a673c671a56 850 } LPC_ENET_T;
ebrus 0:0a673c671a56 851
ebrus 0:0a673c671a56 852 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 853 * Alarm Timer register block structure
ebrus 0:0a673c671a56 854 */
ebrus 0:0a673c671a56 855 #define LPC_ATIMER_BASE 0x40040000
ebrus 0:0a673c671a56 856
ebrus 0:0a673c671a56 857 typedef struct { /* ATIMER Structure */
ebrus 0:0a673c671a56 858 __IO uint32_t DOWNCOUNTER; /* Downcounter register */
ebrus 0:0a673c671a56 859 __IO uint32_t PRESET; /* Preset value register */
ebrus 0:0a673c671a56 860 __I uint32_t RESERVED0[1012];
ebrus 0:0a673c671a56 861 __O uint32_t CLR_EN; /* Interrupt clear enable register */
ebrus 0:0a673c671a56 862 __O uint32_t SET_EN; /* Interrupt set enable register */
ebrus 0:0a673c671a56 863 __I uint32_t STATUS; /* Status register */
ebrus 0:0a673c671a56 864 __I uint32_t ENABLE; /* Enable register */
ebrus 0:0a673c671a56 865 __O uint32_t CLR_STAT; /* Clear register */
ebrus 0:0a673c671a56 866 __O uint32_t SET_STAT; /* Set register */
ebrus 0:0a673c671a56 867 } LPC_ATIMER_T;
ebrus 0:0a673c671a56 868
ebrus 0:0a673c671a56 869 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 870 * Register File register block structure
ebrus 0:0a673c671a56 871 */
ebrus 0:0a673c671a56 872 #define LPC_REGFILE_BASE 0x40041000
ebrus 0:0a673c671a56 873
ebrus 0:0a673c671a56 874 typedef struct {
ebrus 0:0a673c671a56 875 __IO uint32_t REGFILE[64]; /* General purpose storage register */
ebrus 0:0a673c671a56 876 } LPC_REGFILE_T;
ebrus 0:0a673c671a56 877
ebrus 0:0a673c671a56 878 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 879 * Power Management Controller register block structure
ebrus 0:0a673c671a56 880 */
ebrus 0:0a673c671a56 881 #define LPC_PMC_BASE 0x40042000
ebrus 0:0a673c671a56 882
ebrus 0:0a673c671a56 883 typedef struct { /* PMC Structure */
ebrus 0:0a673c671a56 884 __IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
ebrus 0:0a673c671a56 885 __I uint32_t RESERVED0[6];
ebrus 0:0a673c671a56 886 __IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
ebrus 0:0a673c671a56 887 } LPC_PMC_T;
ebrus 0:0a673c671a56 888
ebrus 0:0a673c671a56 889 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 890 * CREG Register Block
ebrus 0:0a673c671a56 891 */
ebrus 0:0a673c671a56 892 #define LPC_CREG_BASE 0x40043000
ebrus 0:0a673c671a56 893
ebrus 0:0a673c671a56 894 typedef struct { /* CREG Structure */
ebrus 0:0a673c671a56 895 __I uint32_t RESERVED0;
ebrus 0:0a673c671a56 896 __IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
ebrus 0:0a673c671a56 897 __I uint32_t RESERVED1[62];
ebrus 0:0a673c671a56 898 __IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
ebrus 0:0a673c671a56 899 #if defined(CHIP_LPC18XX)
ebrus 0:0a673c671a56 900 __I uint32_t RESERVED2[5];
ebrus 0:0a673c671a56 901 #else
ebrus 0:0a673c671a56 902 __I uint32_t RESERVED2;
ebrus 0:0a673c671a56 903 __I uint32_t CREG1; /* Configuration Register 1 */
ebrus 0:0a673c671a56 904 __I uint32_t CREG2; /* Configuration Register 2 */
ebrus 0:0a673c671a56 905 __I uint32_t CREG3; /* Configuration Register 3 */
ebrus 0:0a673c671a56 906 __I uint32_t CREG4; /* Configuration Register 4 */
ebrus 0:0a673c671a56 907 #endif
ebrus 0:0a673c671a56 908 __IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
ebrus 0:0a673c671a56 909 __IO uint32_t DMAMUX; /* DMA muxing control */
ebrus 0:0a673c671a56 910 __IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
ebrus 0:0a673c671a56 911 __IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
ebrus 0:0a673c671a56 912 __IO uint32_t ETBCFG; /* ETB RAM configuration */
ebrus 0:0a673c671a56 913 __IO uint32_t CREG6; /* Chip configuration register 6. */
ebrus 0:0a673c671a56 914 #if defined(CHIP_LPC18XX)
ebrus 0:0a673c671a56 915 __I uint32_t RESERVED4[52];
ebrus 0:0a673c671a56 916 #else
ebrus 0:0a673c671a56 917 __IO uint32_t M4TXEVENT; /* M4 IPC event register */
ebrus 0:0a673c671a56 918 __I uint32_t RESERVED4[51];
ebrus 0:0a673c671a56 919 #endif
ebrus 0:0a673c671a56 920 __I uint32_t CHIPID; /* Part ID */
ebrus 0:0a673c671a56 921 #if defined(CHIP_LPC18XX)
ebrus 0:0a673c671a56 922 __I uint32_t RESERVED5[191];
ebrus 0:0a673c671a56 923 #else
ebrus 0:0a673c671a56 924 __I uint32_t RESERVED5[127];
ebrus 0:0a673c671a56 925 __IO uint32_t M0TXEVENT; /* M0 IPC Event register */
ebrus 0:0a673c671a56 926 __IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
ebrus 0:0a673c671a56 927 __I uint32_t RESERVED6[62];
ebrus 0:0a673c671a56 928 #endif
ebrus 0:0a673c671a56 929 __IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
ebrus 0:0a673c671a56 930 __I uint32_t RESERVED7[63];
ebrus 0:0a673c671a56 931 __IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
ebrus 0:0a673c671a56 932 } LPC_CREG_T;
ebrus 0:0a673c671a56 933
ebrus 0:0a673c671a56 934 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 935 * Event Router register structure
ebrus 0:0a673c671a56 936 */
ebrus 0:0a673c671a56 937 #define LPC_EVRT_BASE 0x40044000
ebrus 0:0a673c671a56 938
ebrus 0:0a673c671a56 939 typedef struct { /* EVENTROUTER Structure */
ebrus 0:0a673c671a56 940 __IO uint32_t HILO; /* Level configuration register */
ebrus 0:0a673c671a56 941 __IO uint32_t EDGE; /* Edge configuration */
ebrus 0:0a673c671a56 942 __I uint32_t RESERVED0[1012];
ebrus 0:0a673c671a56 943 __O uint32_t CLR_EN; /* Event clear enable register */
ebrus 0:0a673c671a56 944 __O uint32_t SET_EN; /* Event set enable register */
ebrus 0:0a673c671a56 945 __I uint32_t STATUS; /* Status register */
ebrus 0:0a673c671a56 946 __I uint32_t ENABLE; /* Enable register */
ebrus 0:0a673c671a56 947 __O uint32_t CLR_STAT; /* Clear register */
ebrus 0:0a673c671a56 948 __O uint32_t SET_STAT; /* Set register */
ebrus 0:0a673c671a56 949 } LPC_EVRT_T;
ebrus 0:0a673c671a56 950
ebrus 0:0a673c671a56 951 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 952 * Real Time Clock register block structure
ebrus 0:0a673c671a56 953 */
ebrus 0:0a673c671a56 954 #define LPC_RTC_BASE 0x40046000
ebrus 0:0a673c671a56 955 #define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
ebrus 0:0a673c671a56 956
ebrus 0:0a673c671a56 957 typedef enum RTC_TIMEINDEX {
ebrus 0:0a673c671a56 958 RTC_TIMETYPE_SECOND, /* Second */
ebrus 0:0a673c671a56 959 RTC_TIMETYPE_MINUTE, /* Month */
ebrus 0:0a673c671a56 960 RTC_TIMETYPE_HOUR, /* Hour */
ebrus 0:0a673c671a56 961 RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
ebrus 0:0a673c671a56 962 RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
ebrus 0:0a673c671a56 963 RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
ebrus 0:0a673c671a56 964 RTC_TIMETYPE_MONTH, /* Month */
ebrus 0:0a673c671a56 965 RTC_TIMETYPE_YEAR, /* Year */
ebrus 0:0a673c671a56 966 RTC_TIMETYPE_LAST
ebrus 0:0a673c671a56 967 } RTC_TIMEINDEX_T;
ebrus 0:0a673c671a56 968
ebrus 0:0a673c671a56 969 #if RTC_EV_SUPPORT
ebrus 0:0a673c671a56 970 typedef enum LPC_RTC_EV_CHANNEL {
ebrus 0:0a673c671a56 971 RTC_EV_CHANNEL_1 = 0,
ebrus 0:0a673c671a56 972 RTC_EV_CHANNEL_2,
ebrus 0:0a673c671a56 973 RTC_EV_CHANNEL_3,
ebrus 0:0a673c671a56 974 RTC_EV_CHANNEL_NUM,
ebrus 0:0a673c671a56 975 } LPC_RTC_EV_CHANNEL_T;
ebrus 0:0a673c671a56 976 #endif /*RTC_EV_SUPPORT*/
ebrus 0:0a673c671a56 977
ebrus 0:0a673c671a56 978 typedef struct { /* RTC Structure */
ebrus 0:0a673c671a56 979 __IO uint32_t ILR; /* Interrupt Location Register */
ebrus 0:0a673c671a56 980 __I uint32_t RESERVED0;
ebrus 0:0a673c671a56 981 __IO uint32_t CCR; /* Clock Control Register */
ebrus 0:0a673c671a56 982 __IO uint32_t CIIR; /* Counter Increment Interrupt Register */
ebrus 0:0a673c671a56 983 __IO uint32_t AMR; /* Alarm Mask Register */
ebrus 0:0a673c671a56 984 __I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
ebrus 0:0a673c671a56 985 __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
ebrus 0:0a673c671a56 986 __IO uint32_t CALIBRATION; /* Calibration Value Register */
ebrus 0:0a673c671a56 987 __I uint32_t RESERVED1[7];
ebrus 0:0a673c671a56 988 __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
ebrus 0:0a673c671a56 989 #if RTC_EV_SUPPORT
ebrus 0:0a673c671a56 990 __IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
ebrus 0:0a673c671a56 991 __IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
ebrus 0:0a673c671a56 992 __I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
ebrus 0:0a673c671a56 993 __I uint32_t RESERVED2;
ebrus 0:0a673c671a56 994 __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
ebrus 0:0a673c671a56 995 __I uint32_t RESERVED3;
ebrus 0:0a673c671a56 996 __I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
ebrus 0:0a673c671a56 997 #endif /*RTC_EV_SUPPORT*/
ebrus 0:0a673c671a56 998 } LPC_RTC_T;
ebrus 0:0a673c671a56 999
ebrus 0:0a673c671a56 1000 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1001 * LPC18XX/43XX CGU register block structure
ebrus 0:0a673c671a56 1002 */
ebrus 0:0a673c671a56 1003 #define LPC_CGU_BASE 0x40050000
ebrus 0:0a673c671a56 1004 #define LPC_CCU1_BASE 0x40051000
ebrus 0:0a673c671a56 1005 #define LPC_CCU2_BASE 0x40052000
ebrus 0:0a673c671a56 1006 /*
ebrus 0:0a673c671a56 1007 * Input clocks for the CGU and can come from both external (crystal) and
ebrus 0:0a673c671a56 1008 * internal (PLL) sources. Can be routed to the base clocks.
ebrus 0:0a673c671a56 1009 */
ebrus 0:0a673c671a56 1010 typedef enum CGU_CLKIN {
ebrus 0:0a673c671a56 1011 CLKIN_32K, /* External 32KHz input */
ebrus 0:0a673c671a56 1012 CLKIN_IRC, /* Internal IRC (12MHz) input */
ebrus 0:0a673c671a56 1013 CLKIN_ENET_RX, /* External ENET_RX pin input */
ebrus 0:0a673c671a56 1014 CLKIN_ENET_TX, /* External ENET_TX pin input */
ebrus 0:0a673c671a56 1015 CLKIN_CLKIN, /* External GPCLKIN pin input */
ebrus 0:0a673c671a56 1016 CLKIN_RESERVED1,
ebrus 0:0a673c671a56 1017 CLKIN_CRYSTAL, /* External (main) crystal pin input */
ebrus 0:0a673c671a56 1018 CLKIN_USBPLL, /* Internal USB PLL input */
ebrus 0:0a673c671a56 1019 CLKIN_AUDIOPLL, /* Internal Audio PLL input */
ebrus 0:0a673c671a56 1020 CLKIN_MAINPLL, /* Internal Main PLL input */
ebrus 0:0a673c671a56 1021 CLKIN_RESERVED2,
ebrus 0:0a673c671a56 1022 CLKIN_RESERVED3,
ebrus 0:0a673c671a56 1023 CLKIN_IDIVA, /* Internal divider A input */
ebrus 0:0a673c671a56 1024 CLKIN_IDIVB, /* Internal divider B input */
ebrus 0:0a673c671a56 1025 CLKIN_IDIVC, /* Internal divider C input */
ebrus 0:0a673c671a56 1026 CLKIN_IDIVD, /* Internal divider D input */
ebrus 0:0a673c671a56 1027 CLKIN_IDIVE, /* Internal divider E input */
ebrus 0:0a673c671a56 1028 CLKINPUT_PD /* External 32KHz input */
ebrus 0:0a673c671a56 1029 } CGU_CLKIN_T;
ebrus 0:0a673c671a56 1030
ebrus 0:0a673c671a56 1031 #define CLKIN_PLL0USB CLKIN_USBPLL
ebrus 0:0a673c671a56 1032 #define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
ebrus 0:0a673c671a56 1033 #define CLKIN_PLL1 CLKIN_MAINPLL
ebrus 0:0a673c671a56 1034
ebrus 0:0a673c671a56 1035 /*
ebrus 0:0a673c671a56 1036 * CGU base clocks are clocks that are associated with a single input clock
ebrus 0:0a673c671a56 1037 * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
ebrus 0:0a673c671a56 1038 * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
ebrus 0:0a673c671a56 1039 * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
ebrus 0:0a673c671a56 1040 * CLK_PERIPH_SGPIO periphral clocks.
ebrus 0:0a673c671a56 1041 */
ebrus 0:0a673c671a56 1042 typedef enum CGU_BASE_CLK {
ebrus 0:0a673c671a56 1043 CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
ebrus 0:0a673c671a56 1044 CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
ebrus 0:0a673c671a56 1045 #if defined(CHIP_LPC43XX)
ebrus 0:0a673c671a56 1046 CLK_BASE_PERIPH, /* Base clock for SGPIO */
ebrus 0:0a673c671a56 1047 #else
ebrus 0:0a673c671a56 1048 CLK_BASE_RESERVED1,
ebrus 0:0a673c671a56 1049 #endif
ebrus 0:0a673c671a56 1050 CLK_BASE_USB1, /* Base USB clock for USB1 */
ebrus 0:0a673c671a56 1051 CLK_BASE_MX, /* Base clock for CPU core */
ebrus 0:0a673c671a56 1052 CLK_BASE_SPIFI, /* Base clock for SPIFI */
ebrus 0:0a673c671a56 1053 #if defined(CHIP_LPC43XX)
ebrus 0:0a673c671a56 1054 CLK_BASE_SPI, /* Base clock for SPI */
ebrus 0:0a673c671a56 1055 #else
ebrus 0:0a673c671a56 1056 CLK_BASE_RESERVED2,
ebrus 0:0a673c671a56 1057 #endif
ebrus 0:0a673c671a56 1058 CLK_BASE_PHY_RX, /* Base clock for PHY RX */
ebrus 0:0a673c671a56 1059 CLK_BASE_PHY_TX, /* Base clock for PHY TX */
ebrus 0:0a673c671a56 1060 CLK_BASE_APB1, /* Base clock for APB1 group */
ebrus 0:0a673c671a56 1061 CLK_BASE_APB3, /* Base clock for APB3 group */
ebrus 0:0a673c671a56 1062 CLK_BASE_LCD, /* Base clock for LCD pixel clock */
ebrus 0:0a673c671a56 1063 #if defined(CHIP_LPC43XX)
ebrus 0:0a673c671a56 1064 CLK_BASE_VADC, /* Base clock for VADC */
ebrus 0:0a673c671a56 1065 #else
ebrus 0:0a673c671a56 1066 CLK_BASE_RESERVED3,
ebrus 0:0a673c671a56 1067 #endif
ebrus 0:0a673c671a56 1068 CLK_BASE_SDIO, /* Base clock for SDIO */
ebrus 0:0a673c671a56 1069 CLK_BASE_SSP0, /* Base clock for SSP0 */
ebrus 0:0a673c671a56 1070 CLK_BASE_SSP1, /* Base clock for SSP1 */
ebrus 0:0a673c671a56 1071 CLK_BASE_UART0, /* Base clock for UART0 */
ebrus 0:0a673c671a56 1072 CLK_BASE_UART1, /* Base clock for UART1 */
ebrus 0:0a673c671a56 1073 CLK_BASE_UART2, /* Base clock for UART2 */
ebrus 0:0a673c671a56 1074 CLK_BASE_UART3, /* Base clock for UART3 */
ebrus 0:0a673c671a56 1075 CLK_BASE_OUT, /* Base clock for CLKOUT pin */
ebrus 0:0a673c671a56 1076 CLK_BASE_RESERVED4,
ebrus 0:0a673c671a56 1077 CLK_BASE_RESERVED5,
ebrus 0:0a673c671a56 1078 CLK_BASE_RESERVED6,
ebrus 0:0a673c671a56 1079 CLK_BASE_RESERVED7,
ebrus 0:0a673c671a56 1080 CLK_BASE_APLL, /* Base clock for audio PLL */
ebrus 0:0a673c671a56 1081 CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
ebrus 0:0a673c671a56 1082 CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
ebrus 0:0a673c671a56 1083 CLK_BASE_LAST,
ebrus 0:0a673c671a56 1084 CLK_BASE_NONE = CLK_BASE_LAST
ebrus 0:0a673c671a56 1085 } CGU_BASE_CLK_T;
ebrus 0:0a673c671a56 1086
ebrus 0:0a673c671a56 1087 /*
ebrus 0:0a673c671a56 1088 * CGU dividers provide an extra clock state where a specific clock can be
ebrus 0:0a673c671a56 1089 * divided before being routed to a peripheral group. A divider accepts an
ebrus 0:0a673c671a56 1090 * input clock and then divides it. To use the divided clock for a base clock
ebrus 0:0a673c671a56 1091 * group, use the divider as the input clock for the base clock (for example,
ebrus 0:0a673c671a56 1092 * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
ebrus 0:0a673c671a56 1093 */
ebrus 0:0a673c671a56 1094 typedef enum CGU_IDIV {
ebrus 0:0a673c671a56 1095 CLK_IDIV_A, /* CGU clock divider A */
ebrus 0:0a673c671a56 1096 CLK_IDIV_B, /* CGU clock divider B */
ebrus 0:0a673c671a56 1097 CLK_IDIV_C, /* CGU clock divider A */
ebrus 0:0a673c671a56 1098 CLK_IDIV_D, /* CGU clock divider D */
ebrus 0:0a673c671a56 1099 CLK_IDIV_E, /* CGU clock divider E */
ebrus 0:0a673c671a56 1100 CLK_IDIV_LAST
ebrus 0:0a673c671a56 1101 } CGU_IDIV_T;
ebrus 0:0a673c671a56 1102
ebrus 0:0a673c671a56 1103 /*
ebrus 0:0a673c671a56 1104 * Peripheral clocks are individual clocks routed to peripherals. Although
ebrus 0:0a673c671a56 1105 * multiple peripherals may share a same base clock, each peripheral's clock
ebrus 0:0a673c671a56 1106 * can be enabled or disabled individually. Some peripheral clocks also have
ebrus 0:0a673c671a56 1107 * additional dividers associated with them.
ebrus 0:0a673c671a56 1108 */
ebrus 0:0a673c671a56 1109 typedef enum CCU_CLK {
ebrus 0:0a673c671a56 1110 /* CCU1 clocks */
ebrus 0:0a673c671a56 1111 CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
ebrus 0:0a673c671a56 1112 CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
ebrus 0:0a673c671a56 1113 CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
ebrus 0:0a673c671a56 1114 CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
ebrus 0:0a673c671a56 1115 CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
ebrus 0:0a673c671a56 1116 CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
ebrus 0:0a673c671a56 1117 CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
ebrus 0:0a673c671a56 1118 CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
ebrus 0:0a673c671a56 1119 CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
ebrus 0:0a673c671a56 1120 CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
ebrus 0:0a673c671a56 1121 CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
ebrus 0:0a673c671a56 1122 CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
ebrus 0:0a673c671a56 1123 CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1124 CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1125 CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1126 CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1127 CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1128 CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1129 CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1130 CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1131 CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1132 CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1133 RESERVED_ALIGN = CLK_MX_MXCORE + 3,
ebrus 0:0a673c671a56 1134 CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1135 CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1136 CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1137 CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1138 CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1139 #if defined(CHIP_LPC43XX)
ebrus 0:0a673c671a56 1140 CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1141 CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1142 #else
ebrus 0:0a673c671a56 1143 CLK_RESERVED1,
ebrus 0:0a673c671a56 1144 CLK_RESERVED2,
ebrus 0:0a673c671a56 1145 #endif
ebrus 0:0a673c671a56 1146 CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1147 CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1148 CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1149 CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1150 CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1151 CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1152 CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1153 CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1154 CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1155 CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1156 CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1157 CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1158 CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1159 CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1160 CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1161 CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
ebrus 0:0a673c671a56 1162 #if defined(CHIP_LPC43XX)
ebrus 0:0a673c671a56 1163 CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
ebrus 0:0a673c671a56 1164 CLK_RESERVED3,
ebrus 0:0a673c671a56 1165 CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
ebrus 0:0a673c671a56 1166 CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
ebrus 0:0a673c671a56 1167 #else
ebrus 0:0a673c671a56 1168 CLK_RESERVED3 = 192,
ebrus 0:0a673c671a56 1169 CLK_RESERVED3A,
ebrus 0:0a673c671a56 1170 CLK_RESERVED4,
ebrus 0:0a673c671a56 1171 CLK_RESERVED5,
ebrus 0:0a673c671a56 1172 #endif
ebrus 0:0a673c671a56 1173 CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
ebrus 0:0a673c671a56 1174 CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
ebrus 0:0a673c671a56 1175 #if defined(CHIP_LPC43XX)
ebrus 0:0a673c671a56 1176 CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
ebrus 0:0a673c671a56 1177 CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
ebrus 0:0a673c671a56 1178 #else
ebrus 0:0a673c671a56 1179 CLK_RESERVED7 = 320,
ebrus 0:0a673c671a56 1180 CLK_RESERVED8,
ebrus 0:0a673c671a56 1181 #endif
ebrus 0:0a673c671a56 1182 CLK_CCU1_LAST,
ebrus 0:0a673c671a56 1183
ebrus 0:0a673c671a56 1184 /* CCU2 clocks */
ebrus 0:0a673c671a56 1185 CLK_CCU2_START,
ebrus 0:0a673c671a56 1186 CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
ebrus 0:0a673c671a56 1187 RESERVED_ALIGNB = CLK_CCU2_START + 31,
ebrus 0:0a673c671a56 1188 CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
ebrus 0:0a673c671a56 1189 RESERVED_ALIGNC = CLK_CCU2_START + 63,
ebrus 0:0a673c671a56 1190 CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
ebrus 0:0a673c671a56 1191 RESERVED_ALIGND = CLK_CCU2_START + 95,
ebrus 0:0a673c671a56 1192 CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
ebrus 0:0a673c671a56 1193 RESERVED_ALIGNE = CLK_CCU2_START + 127,
ebrus 0:0a673c671a56 1194 CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
ebrus 0:0a673c671a56 1195 RESERVED_ALIGNF = CLK_CCU2_START + 159,
ebrus 0:0a673c671a56 1196 CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
ebrus 0:0a673c671a56 1197 RESERVED_ALIGNG = CLK_CCU2_START + 191,
ebrus 0:0a673c671a56 1198 CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
ebrus 0:0a673c671a56 1199 RESERVED_ALIGNH = CLK_CCU2_START + 223,
ebrus 0:0a673c671a56 1200 CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
ebrus 0:0a673c671a56 1201 CLK_CCU2_LAST
ebrus 0:0a673c671a56 1202 } CCU_CLK_T;
ebrus 0:0a673c671a56 1203
ebrus 0:0a673c671a56 1204 /*
ebrus 0:0a673c671a56 1205 * Audio or USB PLL selection
ebrus 0:0a673c671a56 1206 */
ebrus 0:0a673c671a56 1207 typedef enum CGU_USB_AUDIO_PLL {
ebrus 0:0a673c671a56 1208 CGU_USB_PLL,
ebrus 0:0a673c671a56 1209 CGU_AUDIO_PLL
ebrus 0:0a673c671a56 1210 } CGU_USB_AUDIO_PLL_T;
ebrus 0:0a673c671a56 1211
ebrus 0:0a673c671a56 1212 /*
ebrus 0:0a673c671a56 1213 * PLL register block
ebrus 0:0a673c671a56 1214 */
ebrus 0:0a673c671a56 1215 typedef struct {
ebrus 0:0a673c671a56 1216 __I uint32_t PLL_STAT; /* PLL status register */
ebrus 0:0a673c671a56 1217 __IO uint32_t PLL_CTRL; /* PLL control register */
ebrus 0:0a673c671a56 1218 __IO uint32_t PLL_MDIV; /* PLL M-divider register */
ebrus 0:0a673c671a56 1219 __IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
ebrus 0:0a673c671a56 1220 } CGU_PLL_REG_T;
ebrus 0:0a673c671a56 1221
ebrus 0:0a673c671a56 1222 typedef struct { /* (@ 0x40050000) CGU Structure */
ebrus 0:0a673c671a56 1223 __I uint32_t RESERVED0[5];
ebrus 0:0a673c671a56 1224 __IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
ebrus 0:0a673c671a56 1225 __IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
ebrus 0:0a673c671a56 1226 CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
ebrus 0:0a673c671a56 1227 __IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
ebrus 0:0a673c671a56 1228 __I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
ebrus 0:0a673c671a56 1229 __IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
ebrus 0:0a673c671a56 1230 __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
ebrus 0:0a673c671a56 1231 __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
ebrus 0:0a673c671a56 1232 } LPC_CGU_T;
ebrus 0:0a673c671a56 1233
ebrus 0:0a673c671a56 1234 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1235 * CCU clock config/status register pair
ebrus 0:0a673c671a56 1236 */
ebrus 0:0a673c671a56 1237 typedef struct {
ebrus 0:0a673c671a56 1238 __IO uint32_t CFG; /* CCU clock configuration register */
ebrus 0:0a673c671a56 1239 __I uint32_t STAT; /* CCU clock status register */
ebrus 0:0a673c671a56 1240 } CCU_CFGSTAT_T;
ebrus 0:0a673c671a56 1241
ebrus 0:0a673c671a56 1242 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1243 * CCU1 register block structure
ebrus 0:0a673c671a56 1244 */
ebrus 0:0a673c671a56 1245 typedef struct { /* (@ 0x40051000) CCU1 Structure */
ebrus 0:0a673c671a56 1246 __IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
ebrus 0:0a673c671a56 1247 __I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
ebrus 0:0a673c671a56 1248 __I uint32_t RESERVED0[62];
ebrus 0:0a673c671a56 1249 CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
ebrus 0:0a673c671a56 1250 } LPC_CCU1_T;
ebrus 0:0a673c671a56 1251
ebrus 0:0a673c671a56 1252 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1253 * CCU2 register block structure
ebrus 0:0a673c671a56 1254 */
ebrus 0:0a673c671a56 1255 typedef struct { /* (@ 0x40052000) CCU2 Structure */
ebrus 0:0a673c671a56 1256 __IO uint32_t PM; /* (@ 0x40052000) Power mode register */
ebrus 0:0a673c671a56 1257 __I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
ebrus 0:0a673c671a56 1258 __I uint32_t RESERVED0[62];
ebrus 0:0a673c671a56 1259 CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
ebrus 0:0a673c671a56 1260 } LPC_CCU2_T;
ebrus 0:0a673c671a56 1261
ebrus 0:0a673c671a56 1262 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1263 * RGU register structure
ebrus 0:0a673c671a56 1264 */
ebrus 0:0a673c671a56 1265 #define LPC_RGU_BASE 0x40053000
ebrus 0:0a673c671a56 1266
ebrus 0:0a673c671a56 1267 typedef enum RGU_RST {
ebrus 0:0a673c671a56 1268 RGU_CORE_RST,
ebrus 0:0a673c671a56 1269 RGU_PERIPH_RST,
ebrus 0:0a673c671a56 1270 RGU_MASTER_RST,
ebrus 0:0a673c671a56 1271 RGU_WWDT_RST = 4,
ebrus 0:0a673c671a56 1272 RGU_CREG_RST,
ebrus 0:0a673c671a56 1273 RGU_BUS_RST = 8,
ebrus 0:0a673c671a56 1274 RGU_SCU_RST,
ebrus 0:0a673c671a56 1275 RGU_M3_RST = 13,
ebrus 0:0a673c671a56 1276 RGU_LCD_RST = 16,
ebrus 0:0a673c671a56 1277 RGU_USB0_RST,
ebrus 0:0a673c671a56 1278 RGU_USB1_RST,
ebrus 0:0a673c671a56 1279 RGU_DMA_RST,
ebrus 0:0a673c671a56 1280 RGU_SDIO_RST,
ebrus 0:0a673c671a56 1281 RGU_EMC_RST,
ebrus 0:0a673c671a56 1282 RGU_ETHERNET_RST,
ebrus 0:0a673c671a56 1283 RGU_FLASHA_RST = 25,
ebrus 0:0a673c671a56 1284 RGU_EEPROM_RST = 27,
ebrus 0:0a673c671a56 1285 RGU_GPIO_RST,
ebrus 0:0a673c671a56 1286 RGU_FLASHB_RST,
ebrus 0:0a673c671a56 1287 RGU_TIMER0_RST = 32,
ebrus 0:0a673c671a56 1288 RGU_TIMER1_RST,
ebrus 0:0a673c671a56 1289 RGU_TIMER2_RST,
ebrus 0:0a673c671a56 1290 RGU_TIMER3_RST,
ebrus 0:0a673c671a56 1291 RGU_RITIMER_RST,
ebrus 0:0a673c671a56 1292 RGU_SCT_RST,
ebrus 0:0a673c671a56 1293 RGU_MOTOCONPWM_RST,
ebrus 0:0a673c671a56 1294 RGU_QEI_RST,
ebrus 0:0a673c671a56 1295 RGU_ADC0_RST,
ebrus 0:0a673c671a56 1296 RGU_ADC1_RST,
ebrus 0:0a673c671a56 1297 RGU_DAC_RST,
ebrus 0:0a673c671a56 1298 RGU_UART0_RST = 44,
ebrus 0:0a673c671a56 1299 RGU_UART1_RST,
ebrus 0:0a673c671a56 1300 RGU_UART2_RST,
ebrus 0:0a673c671a56 1301 RGU_UART3_RST,
ebrus 0:0a673c671a56 1302 RGU_I2C0_RST,
ebrus 0:0a673c671a56 1303 RGU_I2C1_RST,
ebrus 0:0a673c671a56 1304 RGU_SSP0_RST,
ebrus 0:0a673c671a56 1305 RGU_SSP1_RST,
ebrus 0:0a673c671a56 1306 RGU_I2S_RST,
ebrus 0:0a673c671a56 1307 RGU_SPIFI_RST,
ebrus 0:0a673c671a56 1308 RGU_CAN1_RST,
ebrus 0:0a673c671a56 1309 RGU_CAN0_RST,
ebrus 0:0a673c671a56 1310 #ifdef CHIP_LPC43XX
ebrus 0:0a673c671a56 1311 RGU_M0APP_RST,
ebrus 0:0a673c671a56 1312 RGU_SGPIO_RST,
ebrus 0:0a673c671a56 1313 RGU_SPI_RST,
ebrus 0:0a673c671a56 1314 #endif
ebrus 0:0a673c671a56 1315 RGU_LAST_RST = 63,
ebrus 0:0a673c671a56 1316 } RGU_RST_T;
ebrus 0:0a673c671a56 1317
ebrus 0:0a673c671a56 1318 typedef struct { /* RGU Structure */
ebrus 0:0a673c671a56 1319 __I uint32_t RESERVED0[64];
ebrus 0:0a673c671a56 1320 __O uint32_t RESET_CTRL0; /* Reset control register 0 */
ebrus 0:0a673c671a56 1321 __O uint32_t RESET_CTRL1; /* Reset control register 1 */
ebrus 0:0a673c671a56 1322 __I uint32_t RESERVED1[2];
ebrus 0:0a673c671a56 1323 __IO uint32_t RESET_STATUS0; /* Reset status register 0 */
ebrus 0:0a673c671a56 1324 __IO uint32_t RESET_STATUS1; /* Reset status register 1 */
ebrus 0:0a673c671a56 1325 __IO uint32_t RESET_STATUS2; /* Reset status register 2 */
ebrus 0:0a673c671a56 1326 __IO uint32_t RESET_STATUS3; /* Reset status register 3 */
ebrus 0:0a673c671a56 1327 __I uint32_t RESERVED2[12];
ebrus 0:0a673c671a56 1328 __I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
ebrus 0:0a673c671a56 1329 __I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
ebrus 0:0a673c671a56 1330 __I uint32_t RESERVED3[170];
ebrus 0:0a673c671a56 1331 __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
ebrus 0:0a673c671a56 1332 } LPC_RGU_T;
ebrus 0:0a673c671a56 1333
ebrus 0:0a673c671a56 1334 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1335 * Windowed Watchdog register block structure
ebrus 0:0a673c671a56 1336 */
ebrus 0:0a673c671a56 1337 #define LPC_WWDT_BASE 0x40080000
ebrus 0:0a673c671a56 1338
ebrus 0:0a673c671a56 1339 typedef struct { /* WWDT Structure */
ebrus 0:0a673c671a56 1340 __IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
ebrus 0:0a673c671a56 1341 __IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
ebrus 0:0a673c671a56 1342 __O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
ebrus 0:0a673c671a56 1343 __I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
ebrus 0:0a673c671a56 1344 #ifdef WATCHDOG_CLKSEL_SUPPORT
ebrus 0:0a673c671a56 1345 __IO uint32_t CLKSEL; /* Watchdog clock select register. */
ebrus 0:0a673c671a56 1346 #else
ebrus 0:0a673c671a56 1347 __I uint32_t RESERVED0;
ebrus 0:0a673c671a56 1348 #endif
ebrus 0:0a673c671a56 1349 #ifdef WATCHDOG_WINDOW_SUPPORT
ebrus 0:0a673c671a56 1350 __IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
ebrus 0:0a673c671a56 1351 __IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
ebrus 0:0a673c671a56 1352 #endif
ebrus 0:0a673c671a56 1353 } LPC_WWDT_T;
ebrus 0:0a673c671a56 1354
ebrus 0:0a673c671a56 1355 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1356 * USART register block structure
ebrus 0:0a673c671a56 1357 */
ebrus 0:0a673c671a56 1358 #define LPC_USART0_BASE 0x40081000
ebrus 0:0a673c671a56 1359 #define LPC_UART1_BASE 0x40082000
ebrus 0:0a673c671a56 1360 #define LPC_USART2_BASE 0x400C1000
ebrus 0:0a673c671a56 1361 #define LPC_USART3_BASE 0x400C2000
ebrus 0:0a673c671a56 1362
ebrus 0:0a673c671a56 1363 typedef struct { /* USARTn Structure */
ebrus 0:0a673c671a56 1364
ebrus 0:0a673c671a56 1365 union {
ebrus 0:0a673c671a56 1366 __IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
ebrus 0:0a673c671a56 1367 __O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
ebrus 0:0a673c671a56 1368 __I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
ebrus 0:0a673c671a56 1369 };
ebrus 0:0a673c671a56 1370
ebrus 0:0a673c671a56 1371 union {
ebrus 0:0a673c671a56 1372 __IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
ebrus 0:0a673c671a56 1373 __IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
ebrus 0:0a673c671a56 1374 };
ebrus 0:0a673c671a56 1375
ebrus 0:0a673c671a56 1376 union {
ebrus 0:0a673c671a56 1377 __O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
ebrus 0:0a673c671a56 1378 __I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
ebrus 0:0a673c671a56 1379 };
ebrus 0:0a673c671a56 1380
ebrus 0:0a673c671a56 1381 __IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
ebrus 0:0a673c671a56 1382 __IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
ebrus 0:0a673c671a56 1383 __I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
ebrus 0:0a673c671a56 1384 __I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
ebrus 0:0a673c671a56 1385 __IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
ebrus 0:0a673c671a56 1386 __IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
ebrus 0:0a673c671a56 1387 __IO uint32_t ICR; /* IrDA control register (not all UARTS) */
ebrus 0:0a673c671a56 1388 __IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
ebrus 0:0a673c671a56 1389 __IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
ebrus 0:0a673c671a56 1390 __IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
ebrus 0:0a673c671a56 1391 uint32_t RESERVED0[3];
ebrus 0:0a673c671a56 1392 __IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
ebrus 0:0a673c671a56 1393 __I uint32_t RESERVED1[1];
ebrus 0:0a673c671a56 1394 __IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
ebrus 0:0a673c671a56 1395 __IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
ebrus 0:0a673c671a56 1396 __IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
ebrus 0:0a673c671a56 1397 __IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
ebrus 0:0a673c671a56 1398 union {
ebrus 0:0a673c671a56 1399 __IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
ebrus 0:0a673c671a56 1400 __I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
ebrus 0:0a673c671a56 1401 };
ebrus 0:0a673c671a56 1402
ebrus 0:0a673c671a56 1403 __IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
ebrus 0:0a673c671a56 1404 } LPC_USART_T;
ebrus 0:0a673c671a56 1405
ebrus 0:0a673c671a56 1406 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1407 * SSP register block structure
ebrus 0:0a673c671a56 1408 */
ebrus 0:0a673c671a56 1409 #define LPC_SSP0_BASE 0x40083000
ebrus 0:0a673c671a56 1410 #define LPC_SSP1_BASE 0x400C5000
ebrus 0:0a673c671a56 1411
ebrus 0:0a673c671a56 1412 typedef struct { /* SSPn Structure */
ebrus 0:0a673c671a56 1413 __IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
ebrus 0:0a673c671a56 1414 __IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
ebrus 0:0a673c671a56 1415 __IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
ebrus 0:0a673c671a56 1416 __I uint32_t SR; /* Status Register */
ebrus 0:0a673c671a56 1417 __IO uint32_t CPSR; /* Clock Prescale Register */
ebrus 0:0a673c671a56 1418 __IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
ebrus 0:0a673c671a56 1419 __I uint32_t RIS; /* Raw Interrupt Status Register */
ebrus 0:0a673c671a56 1420 __I uint32_t MIS; /* Masked Interrupt Status Register */
ebrus 0:0a673c671a56 1421 __O uint32_t ICR; /* SSPICR Interrupt Clear Register */
ebrus 0:0a673c671a56 1422 __IO uint32_t DMACR; /* SSPn DMA control register */
ebrus 0:0a673c671a56 1423 } LPC_SSP_T;
ebrus 0:0a673c671a56 1424
ebrus 0:0a673c671a56 1425 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1426 * 32-bit Standard timer register block structure
ebrus 0:0a673c671a56 1427 */
ebrus 0:0a673c671a56 1428 #define LPC_TIMER0_BASE 0x40084000
ebrus 0:0a673c671a56 1429 #define LPC_TIMER1_BASE 0x40085000
ebrus 0:0a673c671a56 1430 #define LPC_TIMER2_BASE 0x400C3000
ebrus 0:0a673c671a56 1431 #define LPC_TIMER3_BASE 0x400C4000
ebrus 0:0a673c671a56 1432
ebrus 0:0a673c671a56 1433 typedef struct { /* TIMERn Structure */
ebrus 0:0a673c671a56 1434 __IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
ebrus 0:0a673c671a56 1435 __IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
ebrus 0:0a673c671a56 1436 __IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
ebrus 0:0a673c671a56 1437 __IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
ebrus 0:0a673c671a56 1438 __IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
ebrus 0:0a673c671a56 1439 __IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
ebrus 0:0a673c671a56 1440 __IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
ebrus 0:0a673c671a56 1441 __IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
ebrus 0:0a673c671a56 1442 __IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
ebrus 0:0a673c671a56 1443 __IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
ebrus 0:0a673c671a56 1444 __I uint32_t RESERVED0[12];
ebrus 0:0a673c671a56 1445 __IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
ebrus 0:0a673c671a56 1446 } LPC_TIMER_T;
ebrus 0:0a673c671a56 1447
ebrus 0:0a673c671a56 1448 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1449 * System Control Unit register block
ebrus 0:0a673c671a56 1450 */
ebrus 0:0a673c671a56 1451 #define LPC_SCU_BASE 0x40086000
ebrus 0:0a673c671a56 1452
ebrus 0:0a673c671a56 1453 typedef struct {
ebrus 0:0a673c671a56 1454 __IO uint32_t SFSP[16][32];
ebrus 0:0a673c671a56 1455 __I uint32_t RESERVED0[256];
ebrus 0:0a673c671a56 1456 __IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
ebrus 0:0a673c671a56 1457 __I uint32_t RESERVED16[28];
ebrus 0:0a673c671a56 1458 __IO uint32_t SFSUSB; /* Pin configuration register for USB */
ebrus 0:0a673c671a56 1459 __IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
ebrus 0:0a673c671a56 1460 __IO uint32_t ENAIO[3]; /* Analog function select registers */
ebrus 0:0a673c671a56 1461 __I uint32_t RESERVED17[27];
ebrus 0:0a673c671a56 1462 __IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
ebrus 0:0a673c671a56 1463 __I uint32_t RESERVED18[63];
ebrus 0:0a673c671a56 1464 __IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
ebrus 0:0a673c671a56 1465 __IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
ebrus 0:0a673c671a56 1466 } LPC_SCU_T;
ebrus 0:0a673c671a56 1467
ebrus 0:0a673c671a56 1468 /*
ebrus 0:0a673c671a56 1469 * SCU function and mode selection definitions
ebrus 0:0a673c671a56 1470 * See the User Manual for specific modes and functions supoprted by the
ebrus 0:0a673c671a56 1471 * various LPC18xx/43xx devices. Functionality can vary per device.
ebrus 0:0a673c671a56 1472 */
ebrus 0:0a673c671a56 1473 #define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
ebrus 0:0a673c671a56 1474 #define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
ebrus 0:0a673c671a56 1475 #define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
ebrus 0:0a673c671a56 1476 #define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
ebrus 0:0a673c671a56 1477 #define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
ebrus 0:0a673c671a56 1478 #define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
ebrus 0:0a673c671a56 1479 #define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
ebrus 0:0a673c671a56 1480 #define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
ebrus 0:0a673c671a56 1481 #define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
ebrus 0:0a673c671a56 1482 #define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
ebrus 0:0a673c671a56 1483 #define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
ebrus 0:0a673c671a56 1484
ebrus 0:0a673c671a56 1485 #define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
ebrus 0:0a673c671a56 1486 #define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
ebrus 0:0a673c671a56 1487 #define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
ebrus 0:0a673c671a56 1488 #define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
ebrus 0:0a673c671a56 1489 #define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
ebrus 0:0a673c671a56 1490 #define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
ebrus 0:0a673c671a56 1491 #define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
ebrus 0:0a673c671a56 1492 #define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
ebrus 0:0a673c671a56 1493
ebrus 0:0a673c671a56 1494 /* Common SCU configurations */
ebrus 0:0a673c671a56 1495 #define SCU_PINIO_FAST (SCU_MODE_INACT | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
ebrus 0:0a673c671a56 1496 #define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
ebrus 0:0a673c671a56 1497 #define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
ebrus 0:0a673c671a56 1498 #define SCU_PINIO_PULLNONE (SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
ebrus 0:0a673c671a56 1499
ebrus 0:0a673c671a56 1500 /* Calculate SCU offset and register address from group and pin number */
ebrus 0:0a673c671a56 1501 #define SCU_OFF(group, num) ((group << 7) + (num << 2))
ebrus 0:0a673c671a56 1502 #define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
ebrus 0:0a673c671a56 1503
ebrus 0:0a673c671a56 1504 /**
ebrus 0:0a673c671a56 1505 * SCU function and mode selection definitions (old)
ebrus 0:0a673c671a56 1506 * For backwards compatibility.
ebrus 0:0a673c671a56 1507 */
ebrus 0:0a673c671a56 1508 #define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
ebrus 0:0a673c671a56 1509 #define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
ebrus 0:0a673c671a56 1510 #define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
ebrus 0:0a673c671a56 1511 #define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
ebrus 0:0a673c671a56 1512 #define MD_EHS (0x1 << 5) /* Enable fast slew rate */
ebrus 0:0a673c671a56 1513 #define MD_EZI (0x1 << 6) /* Input buffer enable */
ebrus 0:0a673c671a56 1514 #define MD_ZI (0x1 << 7) /* Disable input glitch filter */
ebrus 0:0a673c671a56 1515 #define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
ebrus 0:0a673c671a56 1516 #define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
ebrus 0:0a673c671a56 1517 #define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
ebrus 0:0a673c671a56 1518 #define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
ebrus 0:0a673c671a56 1519 #define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
ebrus 0:0a673c671a56 1520
ebrus 0:0a673c671a56 1521 #define FUNC0 0x0 /* Pin function 0 */
ebrus 0:0a673c671a56 1522 #define FUNC1 0x1 /* Pin function 1 */
ebrus 0:0a673c671a56 1523 #define FUNC2 0x2 /* Pin function 2 */
ebrus 0:0a673c671a56 1524 #define FUNC3 0x3 /* Pin function 3 */
ebrus 0:0a673c671a56 1525 #define FUNC4 0x4 /* Pin function 4 */
ebrus 0:0a673c671a56 1526 #define FUNC5 0x5 /* Pin function 5 */
ebrus 0:0a673c671a56 1527 #define FUNC6 0x6 /* Pin function 6 */
ebrus 0:0a673c671a56 1528 #define FUNC7 0x7 /* Pin function 7 */
ebrus 0:0a673c671a56 1529
ebrus 0:0a673c671a56 1530 #define PORT_OFFSET 0x80 /* Port offset definition */
ebrus 0:0a673c671a56 1531 #define PIN_OFFSET 0x04 /* Pin offset definition */
ebrus 0:0a673c671a56 1532
ebrus 0:0a673c671a56 1533 /* Returns the SFSP register address in the SCU for a pin and port,
ebrus 0:0a673c671a56 1534 recommend using (*(volatile int *) &LPC_SCU->SFSP[po][pi];) */
ebrus 0:0a673c671a56 1535 #define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
ebrus 0:0a673c671a56 1536 (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
ebrus 0:0a673c671a56 1537
ebrus 0:0a673c671a56 1538 /* Returns the address in the SCU for a SFSCLK clock register,
ebrus 0:0a673c671a56 1539 recommend using (*(volatile int *) &LPC_SCU->SFSCLK[c];) */
ebrus 0:0a673c671a56 1540 #define LPC_SCU_CLK(LPC_SCU_BASE, c) \
ebrus 0:0a673c671a56 1541 (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
ebrus 0:0a673c671a56 1542
ebrus 0:0a673c671a56 1543 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1544 * GPIO pin interrupt register block structure
ebrus 0:0a673c671a56 1545 */
ebrus 0:0a673c671a56 1546 #define LPC_GPIO_PIN_INT_BASE 0x40087000
ebrus 0:0a673c671a56 1547
ebrus 0:0a673c671a56 1548 typedef struct { /* GPIO_PIN_INT Structure */
ebrus 0:0a673c671a56 1549 __IO uint32_t ISEL; /* Pin Interrupt Mode register */
ebrus 0:0a673c671a56 1550 __IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
ebrus 0:0a673c671a56 1551 __O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
ebrus 0:0a673c671a56 1552 __O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
ebrus 0:0a673c671a56 1553 __IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
ebrus 0:0a673c671a56 1554 __O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
ebrus 0:0a673c671a56 1555 __O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
ebrus 0:0a673c671a56 1556 __IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
ebrus 0:0a673c671a56 1557 __IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
ebrus 0:0a673c671a56 1558 __IO uint32_t IST; /* Pin Interrupt Status register */
ebrus 0:0a673c671a56 1559 } LPC_GPIOPININT_T;
ebrus 0:0a673c671a56 1560
ebrus 0:0a673c671a56 1561 typedef enum LPC_GPIOPININT_MODE {
ebrus 0:0a673c671a56 1562 GPIOPININT_RISING_EDGE = 0x01,
ebrus 0:0a673c671a56 1563 GPIOPININT_FALLING_EDGE = 0x02,
ebrus 0:0a673c671a56 1564 GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
ebrus 0:0a673c671a56 1565 GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
ebrus 0:0a673c671a56 1566 } LPC_GPIOPININT_MODE_T;
ebrus 0:0a673c671a56 1567
ebrus 0:0a673c671a56 1568 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1569 * GPIO grouped interrupt register block structure
ebrus 0:0a673c671a56 1570 */
ebrus 0:0a673c671a56 1571 #define LPC_GPIO_GROUP_INT0_BASE 0x40088000
ebrus 0:0a673c671a56 1572 #define LPC_GPIO_GROUP_INT1_BASE 0x40089000
ebrus 0:0a673c671a56 1573
ebrus 0:0a673c671a56 1574 typedef struct { /* GPIO_GROUP_INTn Structure */
ebrus 0:0a673c671a56 1575 __IO uint32_t CTRL; /* GPIO grouped interrupt control register */
ebrus 0:0a673c671a56 1576 __I uint32_t RESERVED0[7];
ebrus 0:0a673c671a56 1577 __IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
ebrus 0:0a673c671a56 1578 __IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
ebrus 0:0a673c671a56 1579 } LPC_GPIOGROUPINT_T;
ebrus 0:0a673c671a56 1580
ebrus 0:0a673c671a56 1581 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1582 * Motor Control PWM register block structure
ebrus 0:0a673c671a56 1583 */
ebrus 0:0a673c671a56 1584 #define LPC_MCPWM_BASE 0x400A0000
ebrus 0:0a673c671a56 1585
ebrus 0:0a673c671a56 1586 typedef struct { /* MCPWM Structure */
ebrus 0:0a673c671a56 1587 __I uint32_t CON; /* PWM Control read address */
ebrus 0:0a673c671a56 1588 __O uint32_t CON_SET; /* PWM Control set address */
ebrus 0:0a673c671a56 1589 __O uint32_t CON_CLR; /* PWM Control clear address */
ebrus 0:0a673c671a56 1590 __I uint32_t CAPCON; /* Capture Control read address */
ebrus 0:0a673c671a56 1591 __O uint32_t CAPCON_SET; /* Capture Control set address */
ebrus 0:0a673c671a56 1592 __O uint32_t CAPCON_CLR; /* Event Control clear address */
ebrus 0:0a673c671a56 1593 __IO uint32_t TC[3]; /* Timer Counter register */
ebrus 0:0a673c671a56 1594 __IO uint32_t LIM[3]; /* Limit register */
ebrus 0:0a673c671a56 1595 __IO uint32_t MAT[3]; /* Match register */
ebrus 0:0a673c671a56 1596 __IO uint32_t DT; /* Dead time register */
ebrus 0:0a673c671a56 1597 __IO uint32_t CCP; /* Communication Pattern register */
ebrus 0:0a673c671a56 1598 __I uint32_t CAP[3]; /* Capture register */
ebrus 0:0a673c671a56 1599 __I uint32_t INTEN; /* Interrupt Enable read address */
ebrus 0:0a673c671a56 1600 __O uint32_t INTEN_SET; /* Interrupt Enable set address */
ebrus 0:0a673c671a56 1601 __O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
ebrus 0:0a673c671a56 1602 __I uint32_t CNTCON; /* Count Control read address */
ebrus 0:0a673c671a56 1603 __O uint32_t CNTCON_SET; /* Count Control set address */
ebrus 0:0a673c671a56 1604 __O uint32_t CNTCON_CLR; /* Count Control clear address */
ebrus 0:0a673c671a56 1605 __I uint32_t INTF; /* Interrupt flags read address */
ebrus 0:0a673c671a56 1606 __O uint32_t INTF_SET; /* Interrupt flags set address */
ebrus 0:0a673c671a56 1607 __O uint32_t INTF_CLR; /* Interrupt flags clear address */
ebrus 0:0a673c671a56 1608 __O uint32_t CAP_CLR; /* Capture clear address */
ebrus 0:0a673c671a56 1609 } LPC_MCPWM_T;
ebrus 0:0a673c671a56 1610
ebrus 0:0a673c671a56 1611 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1612 * I2C register block structure
ebrus 0:0a673c671a56 1613 */
ebrus 0:0a673c671a56 1614 #define LPC_I2C0_BASE 0x400A1000
ebrus 0:0a673c671a56 1615 #define LPC_I2C1_BASE 0x400E0000
ebrus 0:0a673c671a56 1616
ebrus 0:0a673c671a56 1617 typedef struct { /* I2C0 Structure */
ebrus 0:0a673c671a56 1618 __IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
ebrus 0:0a673c671a56 1619 __I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
ebrus 0:0a673c671a56 1620 __IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
ebrus 0:0a673c671a56 1621 __IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
ebrus 0:0a673c671a56 1622 __IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
ebrus 0:0a673c671a56 1623 __IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
ebrus 0:0a673c671a56 1624 __O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
ebrus 0:0a673c671a56 1625 __IO uint32_t MMCTRL; /* Monitor mode control register. */
ebrus 0:0a673c671a56 1626 __IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
ebrus 0:0a673c671a56 1627 __IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
ebrus 0:0a673c671a56 1628 __IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
ebrus 0:0a673c671a56 1629 __I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
ebrus 0:0a673c671a56 1630 __IO uint32_t MASK[4]; /* I2C Slave address mask register */
ebrus 0:0a673c671a56 1631 } LPC_I2C_T;
ebrus 0:0a673c671a56 1632
ebrus 0:0a673c671a56 1633 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1634 * I2S register block structure
ebrus 0:0a673c671a56 1635 */
ebrus 0:0a673c671a56 1636 #define LPC_I2S0_BASE 0x400A2000
ebrus 0:0a673c671a56 1637 #define LPC_I2S1_BASE 0x400A3000
ebrus 0:0a673c671a56 1638
ebrus 0:0a673c671a56 1639 typedef struct { /* I2S Structure */
ebrus 0:0a673c671a56 1640 __IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
ebrus 0:0a673c671a56 1641 __IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
ebrus 0:0a673c671a56 1642 __O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
ebrus 0:0a673c671a56 1643 __I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
ebrus 0:0a673c671a56 1644 __I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
ebrus 0:0a673c671a56 1645 __IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
ebrus 0:0a673c671a56 1646 __IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
ebrus 0:0a673c671a56 1647 __IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
ebrus 0:0a673c671a56 1648 __IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
ebrus 0:0a673c671a56 1649 __IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
ebrus 0:0a673c671a56 1650 __IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
ebrus 0:0a673c671a56 1651 __IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
ebrus 0:0a673c671a56 1652 __IO uint32_t TXMODE; /* I2S Transmit mode control */
ebrus 0:0a673c671a56 1653 __IO uint32_t RXMODE; /* I2S Receive mode control */
ebrus 0:0a673c671a56 1654 } LPC_I2S_T;
ebrus 0:0a673c671a56 1655
ebrus 0:0a673c671a56 1656 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1657 * CCAN Controller Area Network register block structure
ebrus 0:0a673c671a56 1658 */
ebrus 0:0a673c671a56 1659 #define LPC_C_CAN1_BASE 0x400A4000
ebrus 0:0a673c671a56 1660 #define LPC_C_CAN0_BASE 0x400E2000
ebrus 0:0a673c671a56 1661
ebrus 0:0a673c671a56 1662 typedef struct { /* C_CAN message interface Structure */
ebrus 0:0a673c671a56 1663 __IO uint32_t IF_CMDREQ; /* Message interface command request */
ebrus 0:0a673c671a56 1664 union {
ebrus 0:0a673c671a56 1665 __IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
ebrus 0:0a673c671a56 1666 __IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
ebrus 0:0a673c671a56 1667 };
ebrus 0:0a673c671a56 1668
ebrus 0:0a673c671a56 1669 __IO uint32_t IF_MSK1; /* Message interface mask 1 */
ebrus 0:0a673c671a56 1670 __IO uint32_t IF_MSK2; /* Message interface mask 2 */
ebrus 0:0a673c671a56 1671 __IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
ebrus 0:0a673c671a56 1672 __IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
ebrus 0:0a673c671a56 1673 __IO uint32_t IF_MCTRL; /* Message interface message control */
ebrus 0:0a673c671a56 1674 __IO uint32_t IF_DA1; /* Message interface data A1 */
ebrus 0:0a673c671a56 1675 __IO uint32_t IF_DA2; /* Message interface data A2 */
ebrus 0:0a673c671a56 1676 __IO uint32_t IF_DB1; /* Message interface data B1 */
ebrus 0:0a673c671a56 1677 __IO uint32_t IF_DB2; /* Message interface data B2 */
ebrus 0:0a673c671a56 1678 __I uint32_t RESERVED[13];
ebrus 0:0a673c671a56 1679 } LPC_CCAN_IF_T;
ebrus 0:0a673c671a56 1680
ebrus 0:0a673c671a56 1681 typedef struct { /* C_CAN Structure */
ebrus 0:0a673c671a56 1682 __IO uint32_t CNTL; /* CAN control */
ebrus 0:0a673c671a56 1683 __IO uint32_t STAT; /* Status register */
ebrus 0:0a673c671a56 1684 __I uint32_t EC; /* Error counter */
ebrus 0:0a673c671a56 1685 __IO uint32_t BT; /* Bit timing register */
ebrus 0:0a673c671a56 1686 __I uint32_t INT; /* Interrupt register */
ebrus 0:0a673c671a56 1687 __IO uint32_t TEST; /* Test register */
ebrus 0:0a673c671a56 1688 __IO uint32_t BRPE; /* Baud rate prescaler extension register */
ebrus 0:0a673c671a56 1689 __I uint32_t RESERVED0;
ebrus 0:0a673c671a56 1690 LPC_CCAN_IF_T IF[2];
ebrus 0:0a673c671a56 1691 __I uint32_t RESERVED2[8];
ebrus 0:0a673c671a56 1692 __I uint32_t TXREQ1; /* Transmission request 1 */
ebrus 0:0a673c671a56 1693 __I uint32_t TXREQ2; /* Transmission request 2 */
ebrus 0:0a673c671a56 1694 __I uint32_t RESERVED3[6];
ebrus 0:0a673c671a56 1695 __I uint32_t ND1; /* New data 1 */
ebrus 0:0a673c671a56 1696 __I uint32_t ND2; /* New data 2 */
ebrus 0:0a673c671a56 1697 __I uint32_t RESERVED4[6];
ebrus 0:0a673c671a56 1698 __I uint32_t IR1; /* Interrupt pending 1 */
ebrus 0:0a673c671a56 1699 __I uint32_t IR2; /* Interrupt pending 2 */
ebrus 0:0a673c671a56 1700 __I uint32_t RESERVED5[6];
ebrus 0:0a673c671a56 1701 __I uint32_t MSGV1; /* Message valid 1 */
ebrus 0:0a673c671a56 1702 __I uint32_t MSGV2; /* Message valid 2 */
ebrus 0:0a673c671a56 1703 __I uint32_t RESERVED6[6];
ebrus 0:0a673c671a56 1704 __IO uint32_t CLKDIV; /* CAN clock divider register */
ebrus 0:0a673c671a56 1705 } LPC_CCAN_T;
ebrus 0:0a673c671a56 1706
ebrus 0:0a673c671a56 1707 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1708 * Repetitive Interrupt Timer register block structure
ebrus 0:0a673c671a56 1709 */
ebrus 0:0a673c671a56 1710 #define LPC_RITIMER_BASE 0x400C0000
ebrus 0:0a673c671a56 1711
ebrus 0:0a673c671a56 1712 typedef struct { /* RITIMER Structure */
ebrus 0:0a673c671a56 1713 __IO uint32_t COMPVAL; /* Compare register */
ebrus 0:0a673c671a56 1714 __IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
ebrus 0:0a673c671a56 1715 __IO uint32_t CTRL; /* Control register. */
ebrus 0:0a673c671a56 1716 __IO uint32_t COUNTER; /* 32-bit counter */
ebrus 0:0a673c671a56 1717 } LPC_RITIMER_T;
ebrus 0:0a673c671a56 1718
ebrus 0:0a673c671a56 1719 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1720 * Quadrature Encoder Interface register block structure
ebrus 0:0a673c671a56 1721 */
ebrus 0:0a673c671a56 1722 #define LPC_QEI_BASE 0x400C6000
ebrus 0:0a673c671a56 1723
ebrus 0:0a673c671a56 1724 typedef struct { /* QEI Structure */
ebrus 0:0a673c671a56 1725 __O uint32_t CON; /* Control register */
ebrus 0:0a673c671a56 1726 __I uint32_t STAT; /* Encoder status register */
ebrus 0:0a673c671a56 1727 __IO uint32_t CONF; /* Configuration register */
ebrus 0:0a673c671a56 1728 __I uint32_t POS; /* Position register */
ebrus 0:0a673c671a56 1729 __IO uint32_t MAXPOS; /* Maximum position register */
ebrus 0:0a673c671a56 1730 __IO uint32_t CMPOS0; /* position compare register 0 */
ebrus 0:0a673c671a56 1731 __IO uint32_t CMPOS1; /* position compare register 1 */
ebrus 0:0a673c671a56 1732 __IO uint32_t CMPOS2; /* position compare register 2 */
ebrus 0:0a673c671a56 1733 __I uint32_t INXCNT; /* Index count register */
ebrus 0:0a673c671a56 1734 __IO uint32_t INXCMP0; /* Index compare register 0 */
ebrus 0:0a673c671a56 1735 __IO uint32_t LOAD; /* Velocity timer reload register */
ebrus 0:0a673c671a56 1736 __I uint32_t TIME; /* Velocity timer register */
ebrus 0:0a673c671a56 1737 __I uint32_t VEL; /* Velocity counter register */
ebrus 0:0a673c671a56 1738 __I uint32_t CAP; /* Velocity capture register */
ebrus 0:0a673c671a56 1739 __IO uint32_t VELCOMP; /* Velocity compare register */
ebrus 0:0a673c671a56 1740 __IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
ebrus 0:0a673c671a56 1741 __IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
ebrus 0:0a673c671a56 1742 __IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
ebrus 0:0a673c671a56 1743 __IO uint32_t WINDOW; /* Index acceptance window register */
ebrus 0:0a673c671a56 1744 __IO uint32_t INXCMP1; /* Index compare register 1 */
ebrus 0:0a673c671a56 1745 __IO uint32_t INXCMP2; /* Index compare register 2 */
ebrus 0:0a673c671a56 1746 __I uint32_t RESERVED0[993];
ebrus 0:0a673c671a56 1747 __O uint32_t IEC; /* Interrupt enable clear register */
ebrus 0:0a673c671a56 1748 __O uint32_t IES; /* Interrupt enable set register */
ebrus 0:0a673c671a56 1749 __I uint32_t INTSTAT; /* Interrupt status register */
ebrus 0:0a673c671a56 1750 __I uint32_t IE; /* Interrupt enable register */
ebrus 0:0a673c671a56 1751 __O uint32_t CLR; /* Interrupt status clear register */
ebrus 0:0a673c671a56 1752 __O uint32_t SET; /* Interrupt status set register */
ebrus 0:0a673c671a56 1753 } LPC_QEI_T;
ebrus 0:0a673c671a56 1754
ebrus 0:0a673c671a56 1755 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1756 * Global Input Multiplexer Array (GIMA) register block structure
ebrus 0:0a673c671a56 1757 */
ebrus 0:0a673c671a56 1758 #define LPC_GIMA_BASE 0x400C7000
ebrus 0:0a673c671a56 1759
ebrus 0:0a673c671a56 1760 typedef struct { /* GIMA Structure */
ebrus 0:0a673c671a56 1761 __IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */
ebrus 0:0a673c671a56 1762 __IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
ebrus 0:0a673c671a56 1763 __IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
ebrus 0:0a673c671a56 1764 __IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
ebrus 0:0a673c671a56 1765 __IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
ebrus 0:0a673c671a56 1766 __IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
ebrus 0:0a673c671a56 1767 __IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
ebrus 0:0a673c671a56 1768 __IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
ebrus 0:0a673c671a56 1769 } LPC_GIMA_T;
ebrus 0:0a673c671a56 1770
ebrus 0:0a673c671a56 1771 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1772 * DAC register block structure
ebrus 0:0a673c671a56 1773 */
ebrus 0:0a673c671a56 1774 #define LPC_DAC_BASE 0x400E1000
ebrus 0:0a673c671a56 1775
ebrus 0:0a673c671a56 1776 typedef struct { /* DAC Structure */
ebrus 0:0a673c671a56 1777 __IO uint32_t CR; /* DAC register. Holds the conversion data. */
ebrus 0:0a673c671a56 1778 __IO uint32_t CTRL; /* DAC control register. */
ebrus 0:0a673c671a56 1779 __IO uint32_t CNTVAL; /* DAC counter value register. */
ebrus 0:0a673c671a56 1780 } LPC_DAC_T;
ebrus 0:0a673c671a56 1781
ebrus 0:0a673c671a56 1782 /* After the selected settling time after this field is written with a
ebrus 0:0a673c671a56 1783 * new VALUE, the voltage on the AOUT pin (with respect to VSSA)
ebrus 0:0a673c671a56 1784 * is VALUE/1024 ? VREF
ebrus 0:0a673c671a56 1785 */
ebrus 0:0a673c671a56 1786 #define DAC_RANGE 0x3FF
ebrus 0:0a673c671a56 1787 #define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
ebrus 0:0a673c671a56 1788 #define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
ebrus 0:0a673c671a56 1789 #define DAC_VALUE(n) DAC_SET(n)
ebrus 0:0a673c671a56 1790 /* If this bit = 0: The settling time of the DAC is 1 microsecond max,
ebrus 0:0a673c671a56 1791 * and the maximum current is 700 microAmpere
ebrus 0:0a673c671a56 1792 * If this bit = 1: The settling time of the DAC is 2.5 microsecond
ebrus 0:0a673c671a56 1793 * and the maximum current is 350 microAmpere
ebrus 0:0a673c671a56 1794 */
ebrus 0:0a673c671a56 1795 #define DAC_BIAS_EN ((uint32_t) (1 << 16))
ebrus 0:0a673c671a56 1796 /* Value to reload interrupt DMA counter */
ebrus 0:0a673c671a56 1797 #define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
ebrus 0:0a673c671a56 1798
ebrus 0:0a673c671a56 1799 #define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
ebrus 0:0a673c671a56 1800 #define DAC_CNT_ENA ((uint32_t) (1 << 2))
ebrus 0:0a673c671a56 1801 #define DAC_DMA_ENA ((uint32_t) (1 << 3))
ebrus 0:0a673c671a56 1802 #define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
ebrus 0:0a673c671a56 1803
ebrus 0:0a673c671a56 1804 /* Current option in DAC configuration option */
ebrus 0:0a673c671a56 1805 typedef enum DAC_CURRENT_OPT {
ebrus 0:0a673c671a56 1806 DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
ebrus 0:0a673c671a56 1807 allows for a maximum update rate of 1 MHz */
ebrus 0:0a673c671a56 1808 DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
ebrus 0:0a673c671a56 1809 allows for a maximum update rate of 400 kHz */
ebrus 0:0a673c671a56 1810 } DAC_CURRENT_OPT_T;
ebrus 0:0a673c671a56 1811
ebrus 0:0a673c671a56 1812 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1813 * ADC register block structure
ebrus 0:0a673c671a56 1814 */
ebrus 0:0a673c671a56 1815 #define LPC_ADC0_BASE 0x400E3000
ebrus 0:0a673c671a56 1816 #define LPC_ADC1_BASE 0x400E4000
ebrus 0:0a673c671a56 1817 #define ADC_ACC_10BITS
ebrus 0:0a673c671a56 1818
ebrus 0:0a673c671a56 1819 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1820 * 10 or 12-bit ADC register block structure
ebrus 0:0a673c671a56 1821 */
ebrus 0:0a673c671a56 1822 typedef struct { /* ADCn Structure */
ebrus 0:0a673c671a56 1823 __IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
ebrus 0:0a673c671a56 1824 __I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
ebrus 0:0a673c671a56 1825 __I uint32_t RESERVED0;
ebrus 0:0a673c671a56 1826 __IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
ebrus 0:0a673c671a56 1827 __I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
ebrus 0:0a673c671a56 1828 __I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
ebrus 0:0a673c671a56 1829 } LPC_ADC_T;
ebrus 0:0a673c671a56 1830
ebrus 0:0a673c671a56 1831 /* ADC register support bitfields and mask */
ebrus 0:0a673c671a56 1832 #define ADC_RANGE 0x3FF
ebrus 0:0a673c671a56 1833 #define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
ebrus 0:0a673c671a56 1834 #define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
ebrus 0:0a673c671a56 1835 #define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
ebrus 0:0a673c671a56 1836 #define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
ebrus 0:0a673c671a56 1837 #define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
ebrus 0:0a673c671a56 1838 #define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
ebrus 0:0a673c671a56 1839 #define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
ebrus 0:0a673c671a56 1840 #define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
ebrus 0:0a673c671a56 1841 #define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
ebrus 0:0a673c671a56 1842 #define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
ebrus 0:0a673c671a56 1843 #define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
ebrus 0:0a673c671a56 1844 #define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
ebrus 0:0a673c671a56 1845 #define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
ebrus 0:0a673c671a56 1846 #define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
ebrus 0:0a673c671a56 1847 #define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
ebrus 0:0a673c671a56 1848 #define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
ebrus 0:0a673c671a56 1849 #define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
ebrus 0:0a673c671a56 1850 #define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07) | ADC_CR_PDN)
ebrus 0:0a673c671a56 1851
ebrus 0:0a673c671a56 1852 /* ADC status register used for IP drivers */
ebrus 0:0a673c671a56 1853 typedef enum ADC_STATUS {
ebrus 0:0a673c671a56 1854 ADC_DR_DONE_STAT, /* ADC data register staus */
ebrus 0:0a673c671a56 1855 ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
ebrus 0:0a673c671a56 1856 ADC_DR_ADINT_STAT /* ADC interrupt status */
ebrus 0:0a673c671a56 1857 } ADC_STATUS_T;
ebrus 0:0a673c671a56 1858
ebrus 0:0a673c671a56 1859 /** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
ebrus 0:0a673c671a56 1860 typedef enum ADC_START_MODE {
ebrus 0:0a673c671a56 1861 ADC_NO_START = 0,
ebrus 0:0a673c671a56 1862 ADC_START_NOW, /* Start conversion now */
ebrus 0:0a673c671a56 1863 ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
ebrus 0:0a673c671a56 1864 ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
ebrus 0:0a673c671a56 1865 ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
ebrus 0:0a673c671a56 1866 ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
ebrus 0:0a673c671a56 1867 ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
ebrus 0:0a673c671a56 1868 } ADC_START_MODE_T;
ebrus 0:0a673c671a56 1869
ebrus 0:0a673c671a56 1870 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1871 * GPIO port register block structure
ebrus 0:0a673c671a56 1872 */
ebrus 0:0a673c671a56 1873 #define LPC_GPIO_PORT_BASE 0x400F4000
ebrus 0:0a673c671a56 1874 #define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
ebrus 0:0a673c671a56 1875 #define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
ebrus 0:0a673c671a56 1876 #define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
ebrus 0:0a673c671a56 1877 #define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
ebrus 0:0a673c671a56 1878 #define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
ebrus 0:0a673c671a56 1879 #define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
ebrus 0:0a673c671a56 1880 #define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
ebrus 0:0a673c671a56 1881 #define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
ebrus 0:0a673c671a56 1882
ebrus 0:0a673c671a56 1883 typedef struct { /* GPIO_PORT Structure */
ebrus 0:0a673c671a56 1884 __IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
ebrus 0:0a673c671a56 1885 __IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
ebrus 0:0a673c671a56 1886 __IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
ebrus 0:0a673c671a56 1887 __IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
ebrus 0:0a673c671a56 1888 __IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
ebrus 0:0a673c671a56 1889 __IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
ebrus 0:0a673c671a56 1890 __IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
ebrus 0:0a673c671a56 1891 __O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
ebrus 0:0a673c671a56 1892 __O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
ebrus 0:0a673c671a56 1893 } LPC_GPIO_T;
ebrus 0:0a673c671a56 1894
ebrus 0:0a673c671a56 1895 /* Calculate GPIO offset and port register address from group and pin number */
ebrus 0:0a673c671a56 1896 #define GPIO_OFF(port, pin) ((port << 5) + pin)
ebrus 0:0a673c671a56 1897 #define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
ebrus 0:0a673c671a56 1898
ebrus 0:0a673c671a56 1899 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1900 * SPI register block structure
ebrus 0:0a673c671a56 1901 */
ebrus 0:0a673c671a56 1902 #define LPC_SPI_BASE 0x40100000
ebrus 0:0a673c671a56 1903
ebrus 0:0a673c671a56 1904 typedef struct { /* SPI Structure */
ebrus 0:0a673c671a56 1905 __IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
ebrus 0:0a673c671a56 1906 __I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
ebrus 0:0a673c671a56 1907 __IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
ebrus 0:0a673c671a56 1908 __IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
ebrus 0:0a673c671a56 1909 __I uint32_t RESERVED0[3];
ebrus 0:0a673c671a56 1910 __IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
ebrus 0:0a673c671a56 1911 } LPC_SPI_T;
ebrus 0:0a673c671a56 1912
ebrus 0:0a673c671a56 1913 /* SPI CFG Register BitMask */
ebrus 0:0a673c671a56 1914 #define SPI_CR_BITMASK ((uint32_t) 0xFFC)
ebrus 0:0a673c671a56 1915 /* Enable of controlling the number of bits per transfer */
ebrus 0:0a673c671a56 1916 #define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
ebrus 0:0a673c671a56 1917 /* Mask of field of bit controlling */
ebrus 0:0a673c671a56 1918 #define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
ebrus 0:0a673c671a56 1919 /* Set the number of bits per a transfer */
ebrus 0:0a673c671a56 1920 #define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
ebrus 0:0a673c671a56 1921 /* SPI Clock Phase Select*/
ebrus 0:0a673c671a56 1922 #define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
ebrus 0:0a673c671a56 1923 #define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
ebrus 0:0a673c671a56 1924 /* SPI Clock Polarity Select*/
ebrus 0:0a673c671a56 1925 #define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
ebrus 0:0a673c671a56 1926 #define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
ebrus 0:0a673c671a56 1927 /* SPI Slave Mode Select */
ebrus 0:0a673c671a56 1928 #define SPI_CR_SLAVE_EN ((uint32_t) 0)
ebrus 0:0a673c671a56 1929 /* SPI Master Mode Select */
ebrus 0:0a673c671a56 1930 #define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
ebrus 0:0a673c671a56 1931 /* SPI MSB First mode enable */
ebrus 0:0a673c671a56 1932 #define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
ebrus 0:0a673c671a56 1933 /* SPI LSB First mode enable */
ebrus 0:0a673c671a56 1934 #define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
ebrus 0:0a673c671a56 1935 /* SPI interrupt enable */
ebrus 0:0a673c671a56 1936 #define SPI_CR_INT_EN ((uint32_t) (1 << 7))
ebrus 0:0a673c671a56 1937 /* SPI STAT Register BitMask */
ebrus 0:0a673c671a56 1938 #define SPI_SR_BITMASK ((uint32_t) 0xF8)
ebrus 0:0a673c671a56 1939 /* Slave abort Flag */
ebrus 0:0a673c671a56 1940 #define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
ebrus 0:0a673c671a56 1941 /* Mode fault Flag */
ebrus 0:0a673c671a56 1942 #define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
ebrus 0:0a673c671a56 1943 /* Read overrun flag*/
ebrus 0:0a673c671a56 1944 #define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
ebrus 0:0a673c671a56 1945 /* Write collision flag. */
ebrus 0:0a673c671a56 1946 #define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
ebrus 0:0a673c671a56 1947 /* SPI transfer complete flag. */
ebrus 0:0a673c671a56 1948 #define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
ebrus 0:0a673c671a56 1949 /* SPI error flag */
ebrus 0:0a673c671a56 1950 #define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
ebrus 0:0a673c671a56 1951 /* Enable SPI Test Mode */
ebrus 0:0a673c671a56 1952 #define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
ebrus 0:0a673c671a56 1953 /* SPI interrupt flag */
ebrus 0:0a673c671a56 1954 #define SPI_INT_SPIF ((uint32_t) (1 << 0))
ebrus 0:0a673c671a56 1955 /* Receiver Data */
ebrus 0:0a673c671a56 1956 #define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
ebrus 0:0a673c671a56 1957
ebrus 0:0a673c671a56 1958 /* SPI Mode*/
ebrus 0:0a673c671a56 1959 typedef enum LPC_SPI_MODE {
ebrus 0:0a673c671a56 1960 SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
ebrus 0:0a673c671a56 1961 SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
ebrus 0:0a673c671a56 1962 } LPC_SPI_MODE_T;
ebrus 0:0a673c671a56 1963
ebrus 0:0a673c671a56 1964 /* SPI Clock Mode*/
ebrus 0:0a673c671a56 1965 typedef enum LPC_SPI_CLOCK_MODE {
ebrus 0:0a673c671a56 1966 SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
ebrus 0:0a673c671a56 1967 SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
ebrus 0:0a673c671a56 1968 SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
ebrus 0:0a673c671a56 1969 SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
ebrus 0:0a673c671a56 1970 SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
ebrus 0:0a673c671a56 1971 SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
ebrus 0:0a673c671a56 1972 SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
ebrus 0:0a673c671a56 1973 SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
ebrus 0:0a673c671a56 1974 } LPC_SPI_CLOCK_MODE_T;
ebrus 0:0a673c671a56 1975
ebrus 0:0a673c671a56 1976 /* SPI Data Order Mode*/
ebrus 0:0a673c671a56 1977 typedef enum LPC_SPI_DATA_ORDER {
ebrus 0:0a673c671a56 1978 SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
ebrus 0:0a673c671a56 1979 SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
ebrus 0:0a673c671a56 1980 } LPC_SPI_DATA_ORDER_T;
ebrus 0:0a673c671a56 1981
ebrus 0:0a673c671a56 1982 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 1983 * Serial GPIO register block structure
ebrus 0:0a673c671a56 1984 */
ebrus 0:0a673c671a56 1985 #define LPC_SGPIO_BASE 0x40101000
ebrus 0:0a673c671a56 1986
ebrus 0:0a673c671a56 1987 typedef struct { /* SGPIO Structure */
ebrus 0:0a673c671a56 1988 __IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
ebrus 0:0a673c671a56 1989 __IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
ebrus 0:0a673c671a56 1990 __IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
ebrus 0:0a673c671a56 1991 __IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
ebrus 0:0a673c671a56 1992 __IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
ebrus 0:0a673c671a56 1993 __IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
ebrus 0:0a673c671a56 1994 __IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
ebrus 0:0a673c671a56 1995 __IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
ebrus 0:0a673c671a56 1996 __IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
ebrus 0:0a673c671a56 1997 __IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
ebrus 0:0a673c671a56 1998 __IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
ebrus 0:0a673c671a56 1999 __IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
ebrus 0:0a673c671a56 2000 __I uint32_t GPIO_INREG; /* GPIO input status register */
ebrus 0:0a673c671a56 2001 __IO uint32_t GPIO_OUTREG; /* GPIO output control register */
ebrus 0:0a673c671a56 2002 __IO uint32_t GPIO_OENREG; /* GPIO OE control register */
ebrus 0:0a673c671a56 2003 __IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
ebrus 0:0a673c671a56 2004 __IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
ebrus 0:0a673c671a56 2005 __I uint32_t RESERVED0[823];
ebrus 0:0a673c671a56 2006 __O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
ebrus 0:0a673c671a56 2007 __O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
ebrus 0:0a673c671a56 2008 __I uint32_t ENABLE_0; /* Shift clock interrupt enable */
ebrus 0:0a673c671a56 2009 __I uint32_t STATUS_0; /* Shift clock interrupt status */
ebrus 0:0a673c671a56 2010 __O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
ebrus 0:0a673c671a56 2011 __O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
ebrus 0:0a673c671a56 2012 __I uint32_t RESERVED1[2];
ebrus 0:0a673c671a56 2013 __O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
ebrus 0:0a673c671a56 2014 __O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
ebrus 0:0a673c671a56 2015 __I uint32_t ENABLE_1; /* Capture clock interrupt enable */
ebrus 0:0a673c671a56 2016 __I uint32_t STATUS_1; /* Capture clock interrupt status */
ebrus 0:0a673c671a56 2017 __O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
ebrus 0:0a673c671a56 2018 __O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
ebrus 0:0a673c671a56 2019 __I uint32_t RESERVED2[2];
ebrus 0:0a673c671a56 2020 __O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
ebrus 0:0a673c671a56 2021 __O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
ebrus 0:0a673c671a56 2022 __I uint32_t ENABLE_2; /* Pattern match interrupt enable */
ebrus 0:0a673c671a56 2023 __I uint32_t STATUS_2; /* Pattern match interrupt status */
ebrus 0:0a673c671a56 2024 __O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
ebrus 0:0a673c671a56 2025 __O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
ebrus 0:0a673c671a56 2026 __I uint32_t RESERVED3[2];
ebrus 0:0a673c671a56 2027 __O uint32_t CLR_EN_3; /* Input interrupt clear mask */
ebrus 0:0a673c671a56 2028 __O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
ebrus 0:0a673c671a56 2029 __I uint32_t ENABLE_3; /* Input bit match interrupt enable */
ebrus 0:0a673c671a56 2030 __I uint32_t STATUS_3; /* Input bit match interrupt status */
ebrus 0:0a673c671a56 2031 __O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
ebrus 0:0a673c671a56 2032 __O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
ebrus 0:0a673c671a56 2033 } LPC_SGPIO_T;
ebrus 0:0a673c671a56 2034
ebrus 0:0a673c671a56 2035 /* End of section using anonymous unions */
ebrus 0:0a673c671a56 2036 #if defined(__ARMCC_VERSION)
ebrus 0:0a673c671a56 2037 #pragma pop
ebrus 0:0a673c671a56 2038 #elif defined(__CWCC__)
ebrus 0:0a673c671a56 2039 #pragma pop
ebrus 0:0a673c671a56 2040 #elif defined(__IAR_SYSTEMS_ICC__)
ebrus 0:0a673c671a56 2041 //#pragma pop // FIXME not usable for IAR
ebrus 0:0a673c671a56 2042 #else /* defined(__GNUC__) and others */
ebrus 0:0a673c671a56 2043 /* Leave anonymous unions enabled */
ebrus 0:0a673c671a56 2044 #endif
ebrus 0:0a673c671a56 2045
ebrus 0:0a673c671a56 2046 /* ---------------------------------------------------------------------------
ebrus 0:0a673c671a56 2047 * LPC43xx Peripheral register set declarations
ebrus 0:0a673c671a56 2048 */
ebrus 0:0a673c671a56 2049 #define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
ebrus 0:0a673c671a56 2050 #define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
ebrus 0:0a673c671a56 2051 #define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
ebrus 0:0a673c671a56 2052 #define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
ebrus 0:0a673c671a56 2053 #define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
ebrus 0:0a673c671a56 2054 #define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
ebrus 0:0a673c671a56 2055 #define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
ebrus 0:0a673c671a56 2056 #define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
ebrus 0:0a673c671a56 2057 #define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
ebrus 0:0a673c671a56 2058 #define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
ebrus 0:0a673c671a56 2059 #define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
ebrus 0:0a673c671a56 2060 #define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
ebrus 0:0a673c671a56 2061 #define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
ebrus 0:0a673c671a56 2062 #define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
ebrus 0:0a673c671a56 2063 #define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
ebrus 0:0a673c671a56 2064 #define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
ebrus 0:0a673c671a56 2065 #define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
ebrus 0:0a673c671a56 2066 #define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
ebrus 0:0a673c671a56 2067 #define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
ebrus 0:0a673c671a56 2068 #define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
ebrus 0:0a673c671a56 2069 #define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
ebrus 0:0a673c671a56 2070 #define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
ebrus 0:0a673c671a56 2071 #define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
ebrus 0:0a673c671a56 2072 #define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
ebrus 0:0a673c671a56 2073 #define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
ebrus 0:0a673c671a56 2074 #define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
ebrus 0:0a673c671a56 2075 #define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
ebrus 0:0a673c671a56 2076 #define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
ebrus 0:0a673c671a56 2077 #define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
ebrus 0:0a673c671a56 2078 #define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
ebrus 0:0a673c671a56 2079 #define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
ebrus 0:0a673c671a56 2080 #define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
ebrus 0:0a673c671a56 2081 #define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
ebrus 0:0a673c671a56 2082 #define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
ebrus 0:0a673c671a56 2083 #define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
ebrus 0:0a673c671a56 2084 #define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
ebrus 0:0a673c671a56 2085 #define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
ebrus 0:0a673c671a56 2086 #define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
ebrus 0:0a673c671a56 2087 #define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
ebrus 0:0a673c671a56 2088 #define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
ebrus 0:0a673c671a56 2089 #define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
ebrus 0:0a673c671a56 2090 #define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
ebrus 0:0a673c671a56 2091 #define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
ebrus 0:0a673c671a56 2092 #define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
ebrus 0:0a673c671a56 2093 #define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
ebrus 0:0a673c671a56 2094 #define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
ebrus 0:0a673c671a56 2095 #define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
ebrus 0:0a673c671a56 2096 #define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
ebrus 0:0a673c671a56 2097 #define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
ebrus 0:0a673c671a56 2098 #define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
ebrus 0:0a673c671a56 2099 #define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
ebrus 0:0a673c671a56 2100 #define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
ebrus 0:0a673c671a56 2101 #define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
ebrus 0:0a673c671a56 2102 #define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
ebrus 0:0a673c671a56 2103 #define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
ebrus 0:0a673c671a56 2104 #define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
ebrus 0:0a673c671a56 2105 #define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
ebrus 0:0a673c671a56 2106 #define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
ebrus 0:0a673c671a56 2107 #define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
ebrus 0:0a673c671a56 2108
ebrus 0:0a673c671a56 2109 #ifdef __cplusplus
ebrus 0:0a673c671a56 2110 }
ebrus 0:0a673c671a56 2111 #endif
ebrus 0:0a673c671a56 2112
ebrus 0:0a673c671a56 2113 #endif /* __LPC43XX_H */