Ermanno Brusadin / mbed-src

mbed library sources

targets/cmsis/TARGET_NXP/TARGET_LPC23XX/LPC23xx.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

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ebrus 0:0a673c671a56 1 /* mbed Microcontroller Library - LPC23xx CMSIS-like structs
ebrus 0:0a673c671a56 2 * Copyright (C) 2009 ARM Limited. All rights reserved.
ebrus 0:0a673c671a56 3 *
ebrus 0:0a673c671a56 4 * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
ebrus 0:0a673c671a56 5 */
ebrus 0:0a673c671a56 6
ebrus 0:0a673c671a56 7 #ifndef __LPC23xx_H
ebrus 0:0a673c671a56 8 #define __LPC23xx_H
ebrus 0:0a673c671a56 9
ebrus 0:0a673c671a56 10 #ifdef __cplusplus
ebrus 0:0a673c671a56 11 extern "C" {
ebrus 0:0a673c671a56 12 #endif
ebrus 0:0a673c671a56 13
ebrus 0:0a673c671a56 14 /*
ebrus 0:0a673c671a56 15 * ==========================================================================
ebrus 0:0a673c671a56 16 * ---------- Interrupt Number Definition -----------------------------------
ebrus 0:0a673c671a56 17 * ==========================================================================
ebrus 0:0a673c671a56 18 */
ebrus 0:0a673c671a56 19
ebrus 0:0a673c671a56 20 typedef enum IRQn
ebrus 0:0a673c671a56 21 {
ebrus 0:0a673c671a56 22 /****** LPC23xx Specific Interrupt Numbers *******************************************************/
ebrus 0:0a673c671a56 23 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
ebrus 0:0a673c671a56 24
ebrus 0:0a673c671a56 25 TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
ebrus 0:0a673c671a56 26 TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
ebrus 0:0a673c671a56 27 UART0_IRQn = 6, /*!< UART0 Interrupt */
ebrus 0:0a673c671a56 28 UART1_IRQn = 7, /*!< UART1 Interrupt */
ebrus 0:0a673c671a56 29 PWM1_IRQn = 8, /*!< PWM1 Interrupt */
ebrus 0:0a673c671a56 30 I2C0_IRQn = 9, /*!< I2C0 Interrupt */
ebrus 0:0a673c671a56 31 SPI_IRQn = 10, /*!< SPI Interrupt */
ebrus 0:0a673c671a56 32 SSP0_IRQn = 10, /*!< SSP0 Interrupt */
ebrus 0:0a673c671a56 33 SSP1_IRQn = 11, /*!< SSP1 Interrupt */
ebrus 0:0a673c671a56 34 PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
ebrus 0:0a673c671a56 35 RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
ebrus 0:0a673c671a56 36 EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
ebrus 0:0a673c671a56 37 EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
ebrus 0:0a673c671a56 38 EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
ebrus 0:0a673c671a56 39 EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
ebrus 0:0a673c671a56 40 ADC_IRQn = 18, /*!< A/D Converter Interrupt */
ebrus 0:0a673c671a56 41 I2C1_IRQn = 19, /*!< I2C1 Interrupt */
ebrus 0:0a673c671a56 42 BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
ebrus 0:0a673c671a56 43 ENET_IRQn = 21, /*!< Ethernet Interrupt */
ebrus 0:0a673c671a56 44 USB_IRQn = 22, /*!< USB Interrupt */
ebrus 0:0a673c671a56 45 CAN_IRQn = 23, /*!< CAN Interrupt */
ebrus 0:0a673c671a56 46 MIC_IRQn = 24, /*!< Multimedia Interface Controler */
ebrus 0:0a673c671a56 47 DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
ebrus 0:0a673c671a56 48 TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
ebrus 0:0a673c671a56 49 TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
ebrus 0:0a673c671a56 50 UART2_IRQn = 28, /*!< UART2 Interrupt */
ebrus 0:0a673c671a56 51 UART3_IRQn = 29, /*!< UART3 Interrupt */
ebrus 0:0a673c671a56 52 I2C2_IRQn = 30, /*!< I2C2 Interrupt */
ebrus 0:0a673c671a56 53 I2S_IRQn = 31, /*!< I2S Interrupt */
ebrus 0:0a673c671a56 54 } IRQn_Type;
ebrus 0:0a673c671a56 55
ebrus 0:0a673c671a56 56 /*
ebrus 0:0a673c671a56 57 * ==========================================================================
ebrus 0:0a673c671a56 58 * ----------- Processor and Core Peripheral Section ------------------------
ebrus 0:0a673c671a56 59 * ==========================================================================
ebrus 0:0a673c671a56 60 */
ebrus 0:0a673c671a56 61
ebrus 0:0a673c671a56 62 /* Configuration of the ARM7 Processor and Core Peripherals */
ebrus 0:0a673c671a56 63 #define __MPU_PRESENT 0 /*!< MPU present or not */
ebrus 0:0a673c671a56 64 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
ebrus 0:0a673c671a56 65 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
ebrus 0:0a673c671a56 66
ebrus 0:0a673c671a56 67
ebrus 0:0a673c671a56 68 #include <core_arm7.h>
ebrus 0:0a673c671a56 69 #include "system_LPC23xx.h" /* System Header */
ebrus 0:0a673c671a56 70
ebrus 0:0a673c671a56 71
ebrus 0:0a673c671a56 72 /******************************************************************************/
ebrus 0:0a673c671a56 73 /* Device Specific Peripheral registers structures */
ebrus 0:0a673c671a56 74 /******************************************************************************/
ebrus 0:0a673c671a56 75 #if defined ( __CC_ARM )
ebrus 0:0a673c671a56 76 #pragma anon_unions
ebrus 0:0a673c671a56 77 #endif
ebrus 0:0a673c671a56 78
ebrus 0:0a673c671a56 79 /*------------- Vector Interupt Controler (VIC) ------------------------------*/
ebrus 0:0a673c671a56 80 typedef struct
ebrus 0:0a673c671a56 81 {
ebrus 0:0a673c671a56 82 __I uint32_t IRQStatus;
ebrus 0:0a673c671a56 83 __I uint32_t FIQStatus;
ebrus 0:0a673c671a56 84 __I uint32_t RawIntr;
ebrus 0:0a673c671a56 85 __IO uint32_t IntSelect;
ebrus 0:0a673c671a56 86 __IO uint32_t IntEnable;
ebrus 0:0a673c671a56 87 __O uint32_t IntEnClr;
ebrus 0:0a673c671a56 88 __IO uint32_t SoftInt;
ebrus 0:0a673c671a56 89 __O uint32_t SoftIntClr;
ebrus 0:0a673c671a56 90 __IO uint32_t Protection;
ebrus 0:0a673c671a56 91 __IO uint32_t SWPriorityMask;
ebrus 0:0a673c671a56 92 __IO uint32_t RESERVED0[54];
ebrus 0:0a673c671a56 93 __IO uint32_t VectAddr[32];
ebrus 0:0a673c671a56 94 __IO uint32_t RESERVED1[32];
ebrus 0:0a673c671a56 95 __IO uint32_t VectPriority[32];
ebrus 0:0a673c671a56 96 __IO uint32_t RESERVED2[800];
ebrus 0:0a673c671a56 97 __IO uint32_t Address;
ebrus 0:0a673c671a56 98 } LPC_VIC_TypeDef;
ebrus 0:0a673c671a56 99
ebrus 0:0a673c671a56 100 /*------------- System Control (SC) ------------------------------------------*/
ebrus 0:0a673c671a56 101 typedef struct
ebrus 0:0a673c671a56 102 {
ebrus 0:0a673c671a56 103 __IO uint32_t MAMCR;
ebrus 0:0a673c671a56 104 __IO uint32_t MAMTIM;
ebrus 0:0a673c671a56 105 uint32_t RESERVED0[14];
ebrus 0:0a673c671a56 106 __IO uint32_t MEMMAP;
ebrus 0:0a673c671a56 107 uint32_t RESERVED1[15];
ebrus 0:0a673c671a56 108 __IO uint32_t PLL0CON; /* Clocking and Power Control */
ebrus 0:0a673c671a56 109 __IO uint32_t PLL0CFG;
ebrus 0:0a673c671a56 110 __I uint32_t PLL0STAT;
ebrus 0:0a673c671a56 111 __O uint32_t PLL0FEED;
ebrus 0:0a673c671a56 112 uint32_t RESERVED2[12];
ebrus 0:0a673c671a56 113 __IO uint32_t PCON;
ebrus 0:0a673c671a56 114 __IO uint32_t PCONP;
ebrus 0:0a673c671a56 115 uint32_t RESERVED3[15];
ebrus 0:0a673c671a56 116 __IO uint32_t CCLKCFG;
ebrus 0:0a673c671a56 117 __IO uint32_t USBCLKCFG;
ebrus 0:0a673c671a56 118 __IO uint32_t CLKSRCSEL;
ebrus 0:0a673c671a56 119 uint32_t RESERVED4[12];
ebrus 0:0a673c671a56 120 __IO uint32_t EXTINT; /* External Interrupts */
ebrus 0:0a673c671a56 121 __IO uint32_t INTWAKE;
ebrus 0:0a673c671a56 122 __IO uint32_t EXTMODE;
ebrus 0:0a673c671a56 123 __IO uint32_t EXTPOLAR;
ebrus 0:0a673c671a56 124 uint32_t RESERVED6[12];
ebrus 0:0a673c671a56 125 __IO uint32_t RSID; /* Reset */
ebrus 0:0a673c671a56 126 __IO uint32_t CSPR;
ebrus 0:0a673c671a56 127 __IO uint32_t AHBCFG1;
ebrus 0:0a673c671a56 128 __IO uint32_t AHBCFG2;
ebrus 0:0a673c671a56 129 uint32_t RESERVED7[4];
ebrus 0:0a673c671a56 130 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
ebrus 0:0a673c671a56 131 __IO uint32_t IRCTRIM; /* Clock Dividers */
ebrus 0:0a673c671a56 132 __IO uint32_t PCLKSEL0;
ebrus 0:0a673c671a56 133 __IO uint32_t PCLKSEL1;
ebrus 0:0a673c671a56 134 uint32_t RESERVED8[4];
ebrus 0:0a673c671a56 135 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
ebrus 0:0a673c671a56 136 uint32_t RESERVED9;
ebrus 0:0a673c671a56 137 // __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
ebrus 0:0a673c671a56 138 } LPC_SC_TypeDef;
ebrus 0:0a673c671a56 139
ebrus 0:0a673c671a56 140 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
ebrus 0:0a673c671a56 141 typedef struct
ebrus 0:0a673c671a56 142 {
ebrus 0:0a673c671a56 143 __IO uint32_t PINSEL0;
ebrus 0:0a673c671a56 144 __IO uint32_t PINSEL1;
ebrus 0:0a673c671a56 145 __IO uint32_t PINSEL2;
ebrus 0:0a673c671a56 146 __IO uint32_t PINSEL3;
ebrus 0:0a673c671a56 147 __IO uint32_t PINSEL4;
ebrus 0:0a673c671a56 148 __IO uint32_t PINSEL5;
ebrus 0:0a673c671a56 149 __IO uint32_t PINSEL6;
ebrus 0:0a673c671a56 150 __IO uint32_t PINSEL7;
ebrus 0:0a673c671a56 151 __IO uint32_t PINSEL8;
ebrus 0:0a673c671a56 152 __IO uint32_t PINSEL9;
ebrus 0:0a673c671a56 153 __IO uint32_t PINSEL10;
ebrus 0:0a673c671a56 154 uint32_t RESERVED0[5];
ebrus 0:0a673c671a56 155 __IO uint32_t PINMODE0;
ebrus 0:0a673c671a56 156 __IO uint32_t PINMODE1;
ebrus 0:0a673c671a56 157 __IO uint32_t PINMODE2;
ebrus 0:0a673c671a56 158 __IO uint32_t PINMODE3;
ebrus 0:0a673c671a56 159 __IO uint32_t PINMODE4;
ebrus 0:0a673c671a56 160 __IO uint32_t PINMODE5;
ebrus 0:0a673c671a56 161 __IO uint32_t PINMODE6;
ebrus 0:0a673c671a56 162 __IO uint32_t PINMODE7;
ebrus 0:0a673c671a56 163 __IO uint32_t PINMODE8;
ebrus 0:0a673c671a56 164 __IO uint32_t PINMODE9;
ebrus 0:0a673c671a56 165 __IO uint32_t PINMODE_OD0;
ebrus 0:0a673c671a56 166 __IO uint32_t PINMODE_OD1;
ebrus 0:0a673c671a56 167 __IO uint32_t PINMODE_OD2;
ebrus 0:0a673c671a56 168 __IO uint32_t PINMODE_OD3;
ebrus 0:0a673c671a56 169 __IO uint32_t PINMODE_OD4;
ebrus 0:0a673c671a56 170 } LPC_PINCON_TypeDef;
ebrus 0:0a673c671a56 171
ebrus 0:0a673c671a56 172 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
ebrus 0:0a673c671a56 173 typedef struct
ebrus 0:0a673c671a56 174 {
ebrus 0:0a673c671a56 175 __IO uint32_t FIODIR;
ebrus 0:0a673c671a56 176 uint32_t RESERVED0[3];
ebrus 0:0a673c671a56 177 __IO uint32_t FIOMASK;
ebrus 0:0a673c671a56 178 __IO uint32_t FIOPIN;
ebrus 0:0a673c671a56 179 __IO uint32_t FIOSET;
ebrus 0:0a673c671a56 180 __O uint32_t FIOCLR;
ebrus 0:0a673c671a56 181 } LPC_GPIO_TypeDef;
ebrus 0:0a673c671a56 182
ebrus 0:0a673c671a56 183 typedef struct
ebrus 0:0a673c671a56 184 {
ebrus 0:0a673c671a56 185 __I uint32_t IntStatus;
ebrus 0:0a673c671a56 186 __I uint32_t IO0IntStatR;
ebrus 0:0a673c671a56 187 __I uint32_t IO0IntStatF;
ebrus 0:0a673c671a56 188 __O uint32_t IO0IntClr;
ebrus 0:0a673c671a56 189 __IO uint32_t IO0IntEnR;
ebrus 0:0a673c671a56 190 __IO uint32_t IO0IntEnF;
ebrus 0:0a673c671a56 191 uint32_t RESERVED0[3];
ebrus 0:0a673c671a56 192 __I uint32_t IO2IntStatR;
ebrus 0:0a673c671a56 193 __I uint32_t IO2IntStatF;
ebrus 0:0a673c671a56 194 __O uint32_t IO2IntClr;
ebrus 0:0a673c671a56 195 __IO uint32_t IO2IntEnR;
ebrus 0:0a673c671a56 196 __IO uint32_t IO2IntEnF;
ebrus 0:0a673c671a56 197 } LPC_GPIOINT_TypeDef;
ebrus 0:0a673c671a56 198
ebrus 0:0a673c671a56 199 /*------------- Timer (TIM) --------------------------------------------------*/
ebrus 0:0a673c671a56 200 typedef struct
ebrus 0:0a673c671a56 201 {
ebrus 0:0a673c671a56 202 __IO uint32_t IR;
ebrus 0:0a673c671a56 203 __IO uint32_t TCR;
ebrus 0:0a673c671a56 204 __IO uint32_t TC;
ebrus 0:0a673c671a56 205 __IO uint32_t PR;
ebrus 0:0a673c671a56 206 __IO uint32_t PC;
ebrus 0:0a673c671a56 207 __IO uint32_t MCR;
ebrus 0:0a673c671a56 208 __IO uint32_t MR0;
ebrus 0:0a673c671a56 209 __IO uint32_t MR1;
ebrus 0:0a673c671a56 210 __IO uint32_t MR2;
ebrus 0:0a673c671a56 211 __IO uint32_t MR3;
ebrus 0:0a673c671a56 212 __IO uint32_t CCR;
ebrus 0:0a673c671a56 213 __I uint32_t CR0;
ebrus 0:0a673c671a56 214 __I uint32_t CR1;
ebrus 0:0a673c671a56 215 uint32_t RESERVED0[2];
ebrus 0:0a673c671a56 216 __IO uint32_t EMR;
ebrus 0:0a673c671a56 217 uint32_t RESERVED1[12];
ebrus 0:0a673c671a56 218 __IO uint32_t CTCR;
ebrus 0:0a673c671a56 219 } LPC_TIM_TypeDef;
ebrus 0:0a673c671a56 220
ebrus 0:0a673c671a56 221 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
ebrus 0:0a673c671a56 222 typedef struct
ebrus 0:0a673c671a56 223 {
ebrus 0:0a673c671a56 224 __IO uint32_t IR;
ebrus 0:0a673c671a56 225 __IO uint32_t TCR;
ebrus 0:0a673c671a56 226 __IO uint32_t TC;
ebrus 0:0a673c671a56 227 __IO uint32_t PR;
ebrus 0:0a673c671a56 228 __IO uint32_t PC;
ebrus 0:0a673c671a56 229 __IO uint32_t MCR;
ebrus 0:0a673c671a56 230 __IO uint32_t MR0;
ebrus 0:0a673c671a56 231 __IO uint32_t MR1;
ebrus 0:0a673c671a56 232 __IO uint32_t MR2;
ebrus 0:0a673c671a56 233 __IO uint32_t MR3;
ebrus 0:0a673c671a56 234 __IO uint32_t CCR;
ebrus 0:0a673c671a56 235 __I uint32_t CR0;
ebrus 0:0a673c671a56 236 __I uint32_t CR1;
ebrus 0:0a673c671a56 237 __I uint32_t CR2;
ebrus 0:0a673c671a56 238 __I uint32_t CR3;
ebrus 0:0a673c671a56 239 uint32_t RESERVED0;
ebrus 0:0a673c671a56 240 __IO uint32_t MR4;
ebrus 0:0a673c671a56 241 __IO uint32_t MR5;
ebrus 0:0a673c671a56 242 __IO uint32_t MR6;
ebrus 0:0a673c671a56 243 __IO uint32_t PCR;
ebrus 0:0a673c671a56 244 __IO uint32_t LER;
ebrus 0:0a673c671a56 245 uint32_t RESERVED1[7];
ebrus 0:0a673c671a56 246 __IO uint32_t CTCR;
ebrus 0:0a673c671a56 247 } LPC_PWM_TypeDef;
ebrus 0:0a673c671a56 248
ebrus 0:0a673c671a56 249 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
ebrus 0:0a673c671a56 250 typedef struct
ebrus 0:0a673c671a56 251 {
ebrus 0:0a673c671a56 252 union {
ebrus 0:0a673c671a56 253 __I uint8_t RBR;
ebrus 0:0a673c671a56 254 __O uint8_t THR;
ebrus 0:0a673c671a56 255 __IO uint8_t DLL;
ebrus 0:0a673c671a56 256 uint32_t RESERVED0;
ebrus 0:0a673c671a56 257 };
ebrus 0:0a673c671a56 258 union {
ebrus 0:0a673c671a56 259 __IO uint8_t DLM;
ebrus 0:0a673c671a56 260 __IO uint32_t IER;
ebrus 0:0a673c671a56 261 };
ebrus 0:0a673c671a56 262 union {
ebrus 0:0a673c671a56 263 __I uint32_t IIR;
ebrus 0:0a673c671a56 264 __O uint8_t FCR;
ebrus 0:0a673c671a56 265 };
ebrus 0:0a673c671a56 266 __IO uint8_t LCR;
ebrus 0:0a673c671a56 267 uint8_t RESERVED1[7];
ebrus 0:0a673c671a56 268 __IO uint8_t LSR;
ebrus 0:0a673c671a56 269 uint8_t RESERVED2[7];
ebrus 0:0a673c671a56 270 __IO uint8_t SCR;
ebrus 0:0a673c671a56 271 uint8_t RESERVED3[3];
ebrus 0:0a673c671a56 272 __IO uint32_t ACR;
ebrus 0:0a673c671a56 273 __IO uint8_t ICR;
ebrus 0:0a673c671a56 274 uint8_t RESERVED4[3];
ebrus 0:0a673c671a56 275 __IO uint8_t FDR;
ebrus 0:0a673c671a56 276 uint8_t RESERVED5[7];
ebrus 0:0a673c671a56 277 __IO uint8_t TER;
ebrus 0:0a673c671a56 278 uint8_t RESERVED6[27];
ebrus 0:0a673c671a56 279 __IO uint8_t RS485CTRL;
ebrus 0:0a673c671a56 280 uint8_t RESERVED7[3];
ebrus 0:0a673c671a56 281 __IO uint8_t ADRMATCH;
ebrus 0:0a673c671a56 282 } LPC_UART_TypeDef;
ebrus 0:0a673c671a56 283
ebrus 0:0a673c671a56 284 typedef struct
ebrus 0:0a673c671a56 285 {
ebrus 0:0a673c671a56 286 union {
ebrus 0:0a673c671a56 287 __I uint8_t RBR;
ebrus 0:0a673c671a56 288 __O uint8_t THR;
ebrus 0:0a673c671a56 289 __IO uint8_t DLL;
ebrus 0:0a673c671a56 290 uint32_t RESERVED0;
ebrus 0:0a673c671a56 291 };
ebrus 0:0a673c671a56 292 union {
ebrus 0:0a673c671a56 293 __IO uint8_t DLM;
ebrus 0:0a673c671a56 294 __IO uint32_t IER;
ebrus 0:0a673c671a56 295 };
ebrus 0:0a673c671a56 296 union {
ebrus 0:0a673c671a56 297 __I uint32_t IIR;
ebrus 0:0a673c671a56 298 __O uint8_t FCR;
ebrus 0:0a673c671a56 299 };
ebrus 0:0a673c671a56 300 __IO uint8_t LCR;
ebrus 0:0a673c671a56 301 uint8_t RESERVED1[3];
ebrus 0:0a673c671a56 302 __IO uint8_t MCR;
ebrus 0:0a673c671a56 303 uint8_t RESERVED2[3];
ebrus 0:0a673c671a56 304 __IO uint8_t LSR;
ebrus 0:0a673c671a56 305 uint8_t RESERVED3[3];
ebrus 0:0a673c671a56 306 __IO uint8_t MSR;
ebrus 0:0a673c671a56 307 uint8_t RESERVED4[3];
ebrus 0:0a673c671a56 308 __IO uint8_t SCR;
ebrus 0:0a673c671a56 309 uint8_t RESERVED5[3];
ebrus 0:0a673c671a56 310 __IO uint32_t ACR;
ebrus 0:0a673c671a56 311 uint32_t RESERVED6;
ebrus 0:0a673c671a56 312 __IO uint32_t FDR;
ebrus 0:0a673c671a56 313 uint32_t RESERVED7;
ebrus 0:0a673c671a56 314 __IO uint8_t TER;
ebrus 0:0a673c671a56 315 uint8_t RESERVED8[27];
ebrus 0:0a673c671a56 316 __IO uint8_t RS485CTRL;
ebrus 0:0a673c671a56 317 uint8_t RESERVED9[3];
ebrus 0:0a673c671a56 318 __IO uint8_t ADRMATCH;
ebrus 0:0a673c671a56 319 uint8_t RESERVED10[3];
ebrus 0:0a673c671a56 320 __IO uint8_t RS485DLY;
ebrus 0:0a673c671a56 321 } LPC_UART1_TypeDef;
ebrus 0:0a673c671a56 322
ebrus 0:0a673c671a56 323 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
ebrus 0:0a673c671a56 324 typedef struct
ebrus 0:0a673c671a56 325 {
ebrus 0:0a673c671a56 326 __IO uint32_t SPCR;
ebrus 0:0a673c671a56 327 __I uint32_t SPSR;
ebrus 0:0a673c671a56 328 __IO uint32_t SPDR;
ebrus 0:0a673c671a56 329 __IO uint32_t SPCCR;
ebrus 0:0a673c671a56 330 uint32_t RESERVED0[3];
ebrus 0:0a673c671a56 331 __IO uint32_t SPINT;
ebrus 0:0a673c671a56 332 } LPC_SPI_TypeDef;
ebrus 0:0a673c671a56 333
ebrus 0:0a673c671a56 334 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
ebrus 0:0a673c671a56 335 typedef struct
ebrus 0:0a673c671a56 336 {
ebrus 0:0a673c671a56 337 __IO uint32_t CR0;
ebrus 0:0a673c671a56 338 __IO uint32_t CR1;
ebrus 0:0a673c671a56 339 __IO uint32_t DR;
ebrus 0:0a673c671a56 340 __I uint32_t SR;
ebrus 0:0a673c671a56 341 __IO uint32_t CPSR;
ebrus 0:0a673c671a56 342 __IO uint32_t IMSC;
ebrus 0:0a673c671a56 343 __IO uint32_t RIS;
ebrus 0:0a673c671a56 344 __IO uint32_t MIS;
ebrus 0:0a673c671a56 345 __IO uint32_t ICR;
ebrus 0:0a673c671a56 346 __IO uint32_t DMACR;
ebrus 0:0a673c671a56 347 } LPC_SSP_TypeDef;
ebrus 0:0a673c671a56 348
ebrus 0:0a673c671a56 349 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
ebrus 0:0a673c671a56 350 typedef struct
ebrus 0:0a673c671a56 351 {
ebrus 0:0a673c671a56 352 __IO uint32_t I2CONSET;
ebrus 0:0a673c671a56 353 __I uint32_t I2STAT;
ebrus 0:0a673c671a56 354 __IO uint32_t I2DAT;
ebrus 0:0a673c671a56 355 __IO uint32_t I2ADR0;
ebrus 0:0a673c671a56 356 __IO uint32_t I2SCLH;
ebrus 0:0a673c671a56 357 __IO uint32_t I2SCLL;
ebrus 0:0a673c671a56 358 __O uint32_t I2CONCLR;
ebrus 0:0a673c671a56 359 __IO uint32_t MMCTRL;
ebrus 0:0a673c671a56 360 __IO uint32_t I2ADR1;
ebrus 0:0a673c671a56 361 __IO uint32_t I2ADR2;
ebrus 0:0a673c671a56 362 __IO uint32_t I2ADR3;
ebrus 0:0a673c671a56 363 __I uint32_t I2DATA_BUFFER;
ebrus 0:0a673c671a56 364 __IO uint32_t I2MASK0;
ebrus 0:0a673c671a56 365 __IO uint32_t I2MASK1;
ebrus 0:0a673c671a56 366 __IO uint32_t I2MASK2;
ebrus 0:0a673c671a56 367 __IO uint32_t I2MASK3;
ebrus 0:0a673c671a56 368 } LPC_I2C_TypeDef;
ebrus 0:0a673c671a56 369
ebrus 0:0a673c671a56 370 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
ebrus 0:0a673c671a56 371 typedef struct
ebrus 0:0a673c671a56 372 {
ebrus 0:0a673c671a56 373 __IO uint32_t I2SDAO;
ebrus 0:0a673c671a56 374 __I uint32_t I2SDAI;
ebrus 0:0a673c671a56 375 __O uint32_t I2STXFIFO;
ebrus 0:0a673c671a56 376 __I uint32_t I2SRXFIFO;
ebrus 0:0a673c671a56 377 __I uint32_t I2SSTATE;
ebrus 0:0a673c671a56 378 __IO uint32_t I2SDMA1;
ebrus 0:0a673c671a56 379 __IO uint32_t I2SDMA2;
ebrus 0:0a673c671a56 380 __IO uint32_t I2SIRQ;
ebrus 0:0a673c671a56 381 __IO uint32_t I2STXRATE;
ebrus 0:0a673c671a56 382 __IO uint32_t I2SRXRATE;
ebrus 0:0a673c671a56 383 __IO uint32_t I2STXBITRATE;
ebrus 0:0a673c671a56 384 __IO uint32_t I2SRXBITRATE;
ebrus 0:0a673c671a56 385 __IO uint32_t I2STXMODE;
ebrus 0:0a673c671a56 386 __IO uint32_t I2SRXMODE;
ebrus 0:0a673c671a56 387 } LPC_I2S_TypeDef;
ebrus 0:0a673c671a56 388
ebrus 0:0a673c671a56 389 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
ebrus 0:0a673c671a56 390 typedef struct
ebrus 0:0a673c671a56 391 {
ebrus 0:0a673c671a56 392 __IO uint8_t ILR;
ebrus 0:0a673c671a56 393 uint8_t RESERVED0[3];
ebrus 0:0a673c671a56 394 __IO uint8_t CTC;
ebrus 0:0a673c671a56 395 uint8_t RESERVED1[3];
ebrus 0:0a673c671a56 396 __IO uint8_t CCR;
ebrus 0:0a673c671a56 397 uint8_t RESERVED2[3];
ebrus 0:0a673c671a56 398 __IO uint8_t CIIR;
ebrus 0:0a673c671a56 399 uint8_t RESERVED3[3];
ebrus 0:0a673c671a56 400 __IO uint8_t AMR;
ebrus 0:0a673c671a56 401 uint8_t RESERVED4[3];
ebrus 0:0a673c671a56 402 __I uint32_t CTIME0;
ebrus 0:0a673c671a56 403 __I uint32_t CTIME1;
ebrus 0:0a673c671a56 404 __I uint32_t CTIME2;
ebrus 0:0a673c671a56 405 __IO uint8_t SEC;
ebrus 0:0a673c671a56 406 uint8_t RESERVED5[3];
ebrus 0:0a673c671a56 407 __IO uint8_t MIN;
ebrus 0:0a673c671a56 408 uint8_t RESERVED6[3];
ebrus 0:0a673c671a56 409 __IO uint8_t HOUR;
ebrus 0:0a673c671a56 410 uint8_t RESERVED7[3];
ebrus 0:0a673c671a56 411 __IO uint8_t DOM;
ebrus 0:0a673c671a56 412 uint8_t RESERVED8[3];
ebrus 0:0a673c671a56 413 __IO uint8_t DOW;
ebrus 0:0a673c671a56 414 uint8_t RESERVED9[3];
ebrus 0:0a673c671a56 415 __IO uint16_t DOY;
ebrus 0:0a673c671a56 416 uint16_t RESERVED10;
ebrus 0:0a673c671a56 417 __IO uint8_t MONTH;
ebrus 0:0a673c671a56 418 uint8_t RESERVED11[3];
ebrus 0:0a673c671a56 419 __IO uint16_t YEAR;
ebrus 0:0a673c671a56 420 uint16_t RESERVED12;
ebrus 0:0a673c671a56 421 __IO uint32_t CALIBRATION;
ebrus 0:0a673c671a56 422 __IO uint32_t GPREG0;
ebrus 0:0a673c671a56 423 __IO uint32_t GPREG1;
ebrus 0:0a673c671a56 424 __IO uint32_t GPREG2;
ebrus 0:0a673c671a56 425 __IO uint32_t GPREG3;
ebrus 0:0a673c671a56 426 __IO uint32_t GPREG4;
ebrus 0:0a673c671a56 427 __IO uint8_t WAKEUPDIS;
ebrus 0:0a673c671a56 428 uint8_t RESERVED13[3];
ebrus 0:0a673c671a56 429 __IO uint8_t PWRCTRL;
ebrus 0:0a673c671a56 430 uint8_t RESERVED14[3];
ebrus 0:0a673c671a56 431 __IO uint8_t ALSEC;
ebrus 0:0a673c671a56 432 uint8_t RESERVED15[3];
ebrus 0:0a673c671a56 433 __IO uint8_t ALMIN;
ebrus 0:0a673c671a56 434 uint8_t RESERVED16[3];
ebrus 0:0a673c671a56 435 __IO uint8_t ALHOUR;
ebrus 0:0a673c671a56 436 uint8_t RESERVED17[3];
ebrus 0:0a673c671a56 437 __IO uint8_t ALDOM;
ebrus 0:0a673c671a56 438 uint8_t RESERVED18[3];
ebrus 0:0a673c671a56 439 __IO uint8_t ALDOW;
ebrus 0:0a673c671a56 440 uint8_t RESERVED19[3];
ebrus 0:0a673c671a56 441 __IO uint16_t ALDOY;
ebrus 0:0a673c671a56 442 uint16_t RESERVED20;
ebrus 0:0a673c671a56 443 __IO uint8_t ALMON;
ebrus 0:0a673c671a56 444 uint8_t RESERVED21[3];
ebrus 0:0a673c671a56 445 __IO uint16_t ALYEAR;
ebrus 0:0a673c671a56 446 uint16_t RESERVED22;
ebrus 0:0a673c671a56 447 } LPC_RTC_TypeDef;
ebrus 0:0a673c671a56 448
ebrus 0:0a673c671a56 449 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
ebrus 0:0a673c671a56 450 typedef struct
ebrus 0:0a673c671a56 451 {
ebrus 0:0a673c671a56 452 __IO uint8_t WDMOD;
ebrus 0:0a673c671a56 453 uint8_t RESERVED0[3];
ebrus 0:0a673c671a56 454 __IO uint32_t WDTC;
ebrus 0:0a673c671a56 455 __O uint8_t WDFEED;
ebrus 0:0a673c671a56 456 uint8_t RESERVED1[3];
ebrus 0:0a673c671a56 457 __I uint32_t WDTV;
ebrus 0:0a673c671a56 458 __IO uint32_t WDCLKSEL;
ebrus 0:0a673c671a56 459 } LPC_WDT_TypeDef;
ebrus 0:0a673c671a56 460
ebrus 0:0a673c671a56 461 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
ebrus 0:0a673c671a56 462 typedef struct
ebrus 0:0a673c671a56 463 {
ebrus 0:0a673c671a56 464 __IO uint32_t ADCR;
ebrus 0:0a673c671a56 465 __IO uint32_t ADGDR;
ebrus 0:0a673c671a56 466 uint32_t RESERVED0;
ebrus 0:0a673c671a56 467 __IO uint32_t ADINTEN;
ebrus 0:0a673c671a56 468 __I uint32_t ADDR0;
ebrus 0:0a673c671a56 469 __I uint32_t ADDR1;
ebrus 0:0a673c671a56 470 __I uint32_t ADDR2;
ebrus 0:0a673c671a56 471 __I uint32_t ADDR3;
ebrus 0:0a673c671a56 472 __I uint32_t ADDR4;
ebrus 0:0a673c671a56 473 __I uint32_t ADDR5;
ebrus 0:0a673c671a56 474 __I uint32_t ADDR6;
ebrus 0:0a673c671a56 475 __I uint32_t ADDR7;
ebrus 0:0a673c671a56 476 __I uint32_t ADSTAT;
ebrus 0:0a673c671a56 477 __IO uint32_t ADTRM;
ebrus 0:0a673c671a56 478 } LPC_ADC_TypeDef;
ebrus 0:0a673c671a56 479
ebrus 0:0a673c671a56 480 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
ebrus 0:0a673c671a56 481 typedef struct
ebrus 0:0a673c671a56 482 {
ebrus 0:0a673c671a56 483 __IO uint32_t DACR;
ebrus 0:0a673c671a56 484 __IO uint32_t DACCTRL;
ebrus 0:0a673c671a56 485 __IO uint16_t DACCNTVAL;
ebrus 0:0a673c671a56 486 } LPC_DAC_TypeDef;
ebrus 0:0a673c671a56 487
ebrus 0:0a673c671a56 488 /*------------- Multimedia Card Interface (MCI) ------------------------------*/
ebrus 0:0a673c671a56 489 typedef struct
ebrus 0:0a673c671a56 490 {
ebrus 0:0a673c671a56 491 __IO uint32_t MCIPower; /* Power control */
ebrus 0:0a673c671a56 492 __IO uint32_t MCIClock; /* Clock control */
ebrus 0:0a673c671a56 493 __IO uint32_t MCIArgument;
ebrus 0:0a673c671a56 494 __IO uint32_t MMCCommand;
ebrus 0:0a673c671a56 495 __I uint32_t MCIRespCmd;
ebrus 0:0a673c671a56 496 __I uint32_t MCIResponse0;
ebrus 0:0a673c671a56 497 __I uint32_t MCIResponse1;
ebrus 0:0a673c671a56 498 __I uint32_t MCIResponse2;
ebrus 0:0a673c671a56 499 __I uint32_t MCIResponse3;
ebrus 0:0a673c671a56 500 __IO uint32_t MCIDataTimer;
ebrus 0:0a673c671a56 501 __IO uint32_t MCIDataLength;
ebrus 0:0a673c671a56 502 __IO uint32_t MCIDataCtrl;
ebrus 0:0a673c671a56 503 __I uint32_t MCIDataCnt;
ebrus 0:0a673c671a56 504 } LPC_MCI_TypeDef;
ebrus 0:0a673c671a56 505
ebrus 0:0a673c671a56 506 /*------------- Controller Area Network (CAN) --------------------------------*/
ebrus 0:0a673c671a56 507 typedef struct
ebrus 0:0a673c671a56 508 {
ebrus 0:0a673c671a56 509 __IO uint32_t mask[512]; /* ID Masks */
ebrus 0:0a673c671a56 510 } LPC_CANAF_RAM_TypeDef;
ebrus 0:0a673c671a56 511
ebrus 0:0a673c671a56 512 typedef struct /* Acceptance Filter Registers */
ebrus 0:0a673c671a56 513 {
ebrus 0:0a673c671a56 514 __IO uint32_t AFMR;
ebrus 0:0a673c671a56 515 __IO uint32_t SFF_sa;
ebrus 0:0a673c671a56 516 __IO uint32_t SFF_GRP_sa;
ebrus 0:0a673c671a56 517 __IO uint32_t EFF_sa;
ebrus 0:0a673c671a56 518 __IO uint32_t EFF_GRP_sa;
ebrus 0:0a673c671a56 519 __IO uint32_t ENDofTable;
ebrus 0:0a673c671a56 520 __I uint32_t LUTerrAd;
ebrus 0:0a673c671a56 521 __I uint32_t LUTerr;
ebrus 0:0a673c671a56 522 } LPC_CANAF_TypeDef;
ebrus 0:0a673c671a56 523
ebrus 0:0a673c671a56 524 typedef struct /* Central Registers */
ebrus 0:0a673c671a56 525 {
ebrus 0:0a673c671a56 526 __I uint32_t CANTxSR;
ebrus 0:0a673c671a56 527 __I uint32_t CANRxSR;
ebrus 0:0a673c671a56 528 __I uint32_t CANMSR;
ebrus 0:0a673c671a56 529 } LPC_CANCR_TypeDef;
ebrus 0:0a673c671a56 530
ebrus 0:0a673c671a56 531 typedef struct /* Controller Registers */
ebrus 0:0a673c671a56 532 {
ebrus 0:0a673c671a56 533 __IO uint32_t MOD;
ebrus 0:0a673c671a56 534 __O uint32_t CMR;
ebrus 0:0a673c671a56 535 __IO uint32_t GSR;
ebrus 0:0a673c671a56 536 __I uint32_t ICR;
ebrus 0:0a673c671a56 537 __IO uint32_t IER;
ebrus 0:0a673c671a56 538 __IO uint32_t BTR;
ebrus 0:0a673c671a56 539 __IO uint32_t EWL;
ebrus 0:0a673c671a56 540 __I uint32_t SR;
ebrus 0:0a673c671a56 541 __IO uint32_t RFS;
ebrus 0:0a673c671a56 542 __IO uint32_t RID;
ebrus 0:0a673c671a56 543 __IO uint32_t RDA;
ebrus 0:0a673c671a56 544 __IO uint32_t RDB;
ebrus 0:0a673c671a56 545 __IO uint32_t TFI1;
ebrus 0:0a673c671a56 546 __IO uint32_t TID1;
ebrus 0:0a673c671a56 547 __IO uint32_t TDA1;
ebrus 0:0a673c671a56 548 __IO uint32_t TDB1;
ebrus 0:0a673c671a56 549 __IO uint32_t TFI2;
ebrus 0:0a673c671a56 550 __IO uint32_t TID2;
ebrus 0:0a673c671a56 551 __IO uint32_t TDA2;
ebrus 0:0a673c671a56 552 __IO uint32_t TDB2;
ebrus 0:0a673c671a56 553 __IO uint32_t TFI3;
ebrus 0:0a673c671a56 554 __IO uint32_t TID3;
ebrus 0:0a673c671a56 555 __IO uint32_t TDA3;
ebrus 0:0a673c671a56 556 __IO uint32_t TDB3;
ebrus 0:0a673c671a56 557 } LPC_CAN_TypeDef;
ebrus 0:0a673c671a56 558
ebrus 0:0a673c671a56 559 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
ebrus 0:0a673c671a56 560 typedef struct /* Common Registers */
ebrus 0:0a673c671a56 561 {
ebrus 0:0a673c671a56 562 __I uint32_t DMACIntStat;
ebrus 0:0a673c671a56 563 __I uint32_t DMACIntTCStat;
ebrus 0:0a673c671a56 564 __O uint32_t DMACIntTCClear;
ebrus 0:0a673c671a56 565 __I uint32_t DMACIntErrStat;
ebrus 0:0a673c671a56 566 __O uint32_t DMACIntErrClr;
ebrus 0:0a673c671a56 567 __I uint32_t DMACRawIntTCStat;
ebrus 0:0a673c671a56 568 __I uint32_t DMACRawIntErrStat;
ebrus 0:0a673c671a56 569 __I uint32_t DMACEnbldChns;
ebrus 0:0a673c671a56 570 __IO uint32_t DMACSoftBReq;
ebrus 0:0a673c671a56 571 __IO uint32_t DMACSoftSReq;
ebrus 0:0a673c671a56 572 __IO uint32_t DMACSoftLBReq;
ebrus 0:0a673c671a56 573 __IO uint32_t DMACSoftLSReq;
ebrus 0:0a673c671a56 574 __IO uint32_t DMACConfig;
ebrus 0:0a673c671a56 575 __IO uint32_t DMACSync;
ebrus 0:0a673c671a56 576 } LPC_GPDMA_TypeDef;
ebrus 0:0a673c671a56 577
ebrus 0:0a673c671a56 578 typedef struct /* Channel Registers */
ebrus 0:0a673c671a56 579 {
ebrus 0:0a673c671a56 580 __IO uint32_t DMACCSrcAddr;
ebrus 0:0a673c671a56 581 __IO uint32_t DMACCDestAddr;
ebrus 0:0a673c671a56 582 __IO uint32_t DMACCLLI;
ebrus 0:0a673c671a56 583 __IO uint32_t DMACCControl;
ebrus 0:0a673c671a56 584 __IO uint32_t DMACCConfig;
ebrus 0:0a673c671a56 585 } LPC_GPDMACH_TypeDef;
ebrus 0:0a673c671a56 586
ebrus 0:0a673c671a56 587 /*------------- Universal Serial Bus (USB) -----------------------------------*/
ebrus 0:0a673c671a56 588 typedef struct
ebrus 0:0a673c671a56 589 {
ebrus 0:0a673c671a56 590 __I uint32_t HcRevision; /* USB Host Registers */
ebrus 0:0a673c671a56 591 __IO uint32_t HcControl;
ebrus 0:0a673c671a56 592 __IO uint32_t HcCommandStatus;
ebrus 0:0a673c671a56 593 __IO uint32_t HcInterruptStatus;
ebrus 0:0a673c671a56 594 __IO uint32_t HcInterruptEnable;
ebrus 0:0a673c671a56 595 __IO uint32_t HcInterruptDisable;
ebrus 0:0a673c671a56 596 __IO uint32_t HcHCCA;
ebrus 0:0a673c671a56 597 __I uint32_t HcPeriodCurrentED;
ebrus 0:0a673c671a56 598 __IO uint32_t HcControlHeadED;
ebrus 0:0a673c671a56 599 __IO uint32_t HcControlCurrentED;
ebrus 0:0a673c671a56 600 __IO uint32_t HcBulkHeadED;
ebrus 0:0a673c671a56 601 __IO uint32_t HcBulkCurrentED;
ebrus 0:0a673c671a56 602 __I uint32_t HcDoneHead;
ebrus 0:0a673c671a56 603 __IO uint32_t HcFmInterval;
ebrus 0:0a673c671a56 604 __I uint32_t HcFmRemaining;
ebrus 0:0a673c671a56 605 __I uint32_t HcFmNumber;
ebrus 0:0a673c671a56 606 __IO uint32_t HcPeriodicStart;
ebrus 0:0a673c671a56 607 __IO uint32_t HcLSTreshold;
ebrus 0:0a673c671a56 608 __IO uint32_t HcRhDescriptorA;
ebrus 0:0a673c671a56 609 __IO uint32_t HcRhDescriptorB;
ebrus 0:0a673c671a56 610 __IO uint32_t HcRhStatus;
ebrus 0:0a673c671a56 611 __IO uint32_t HcRhPortStatus1;
ebrus 0:0a673c671a56 612 __IO uint32_t HcRhPortStatus2;
ebrus 0:0a673c671a56 613 uint32_t RESERVED0[40];
ebrus 0:0a673c671a56 614 __I uint32_t Module_ID;
ebrus 0:0a673c671a56 615
ebrus 0:0a673c671a56 616 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
ebrus 0:0a673c671a56 617 __IO uint32_t OTGIntEn;
ebrus 0:0a673c671a56 618 __O uint32_t OTGIntSet;
ebrus 0:0a673c671a56 619 __O uint32_t OTGIntClr;
ebrus 0:0a673c671a56 620 __IO uint32_t OTGStCtrl;
ebrus 0:0a673c671a56 621 __IO uint32_t OTGTmr;
ebrus 0:0a673c671a56 622 uint32_t RESERVED1[58];
ebrus 0:0a673c671a56 623
ebrus 0:0a673c671a56 624 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
ebrus 0:0a673c671a56 625 __IO uint32_t USBDevIntEn;
ebrus 0:0a673c671a56 626 __O uint32_t USBDevIntClr;
ebrus 0:0a673c671a56 627 __O uint32_t USBDevIntSet;
ebrus 0:0a673c671a56 628
ebrus 0:0a673c671a56 629 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
ebrus 0:0a673c671a56 630 __I uint32_t USBCmdData;
ebrus 0:0a673c671a56 631
ebrus 0:0a673c671a56 632 __I uint32_t USBRxData; /* USB Device Transfer Registers */
ebrus 0:0a673c671a56 633 __O uint32_t USBTxData;
ebrus 0:0a673c671a56 634 __I uint32_t USBRxPLen;
ebrus 0:0a673c671a56 635 __O uint32_t USBTxPLen;
ebrus 0:0a673c671a56 636 __IO uint32_t USBCtrl;
ebrus 0:0a673c671a56 637 __O uint32_t USBDevIntPri;
ebrus 0:0a673c671a56 638
ebrus 0:0a673c671a56 639 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
ebrus 0:0a673c671a56 640 __IO uint32_t USBEpIntEn;
ebrus 0:0a673c671a56 641 __O uint32_t USBEpIntClr;
ebrus 0:0a673c671a56 642 __O uint32_t USBEpIntSet;
ebrus 0:0a673c671a56 643 __O uint32_t USBEpIntPri;
ebrus 0:0a673c671a56 644
ebrus 0:0a673c671a56 645 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
ebrus 0:0a673c671a56 646 __O uint32_t USBEpInd;
ebrus 0:0a673c671a56 647 __IO uint32_t USBMaxPSize;
ebrus 0:0a673c671a56 648
ebrus 0:0a673c671a56 649 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
ebrus 0:0a673c671a56 650 __O uint32_t USBDMARClr;
ebrus 0:0a673c671a56 651 __O uint32_t USBDMARSet;
ebrus 0:0a673c671a56 652 uint32_t RESERVED2[9];
ebrus 0:0a673c671a56 653 __IO uint32_t USBUDCAH;
ebrus 0:0a673c671a56 654 __I uint32_t USBEpDMASt;
ebrus 0:0a673c671a56 655 __O uint32_t USBEpDMAEn;
ebrus 0:0a673c671a56 656 __O uint32_t USBEpDMADis;
ebrus 0:0a673c671a56 657 __I uint32_t USBDMAIntSt;
ebrus 0:0a673c671a56 658 __IO uint32_t USBDMAIntEn;
ebrus 0:0a673c671a56 659 uint32_t RESERVED3[2];
ebrus 0:0a673c671a56 660 __I uint32_t USBEoTIntSt;
ebrus 0:0a673c671a56 661 __O uint32_t USBEoTIntClr;
ebrus 0:0a673c671a56 662 __O uint32_t USBEoTIntSet;
ebrus 0:0a673c671a56 663 __I uint32_t USBNDDRIntSt;
ebrus 0:0a673c671a56 664 __O uint32_t USBNDDRIntClr;
ebrus 0:0a673c671a56 665 __O uint32_t USBNDDRIntSet;
ebrus 0:0a673c671a56 666 __I uint32_t USBSysErrIntSt;
ebrus 0:0a673c671a56 667 __O uint32_t USBSysErrIntClr;
ebrus 0:0a673c671a56 668 __O uint32_t USBSysErrIntSet;
ebrus 0:0a673c671a56 669 uint32_t RESERVED4[15];
ebrus 0:0a673c671a56 670
ebrus 0:0a673c671a56 671 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
ebrus 0:0a673c671a56 672 __O uint32_t I2C_WO;
ebrus 0:0a673c671a56 673 __I uint32_t I2C_STS;
ebrus 0:0a673c671a56 674 __IO uint32_t I2C_CTL;
ebrus 0:0a673c671a56 675 __IO uint32_t I2C_CLKHI;
ebrus 0:0a673c671a56 676 __O uint32_t I2C_CLKLO;
ebrus 0:0a673c671a56 677 uint32_t RESERVED5[823];
ebrus 0:0a673c671a56 678
ebrus 0:0a673c671a56 679 union {
ebrus 0:0a673c671a56 680 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
ebrus 0:0a673c671a56 681 __IO uint32_t OTGClkCtrl;
ebrus 0:0a673c671a56 682 };
ebrus 0:0a673c671a56 683 union {
ebrus 0:0a673c671a56 684 __I uint32_t USBClkSt;
ebrus 0:0a673c671a56 685 __I uint32_t OTGClkSt;
ebrus 0:0a673c671a56 686 };
ebrus 0:0a673c671a56 687 } LPC_USB_TypeDef;
ebrus 0:0a673c671a56 688
ebrus 0:0a673c671a56 689 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
ebrus 0:0a673c671a56 690 typedef struct
ebrus 0:0a673c671a56 691 {
ebrus 0:0a673c671a56 692 __IO uint32_t MAC1; /* MAC Registers */
ebrus 0:0a673c671a56 693 __IO uint32_t MAC2;
ebrus 0:0a673c671a56 694 __IO uint32_t IPGT;
ebrus 0:0a673c671a56 695 __IO uint32_t IPGR;
ebrus 0:0a673c671a56 696 __IO uint32_t CLRT;
ebrus 0:0a673c671a56 697 __IO uint32_t MAXF;
ebrus 0:0a673c671a56 698 __IO uint32_t SUPP;
ebrus 0:0a673c671a56 699 __IO uint32_t TEST;
ebrus 0:0a673c671a56 700 __IO uint32_t MCFG;
ebrus 0:0a673c671a56 701 __IO uint32_t MCMD;
ebrus 0:0a673c671a56 702 __IO uint32_t MADR;
ebrus 0:0a673c671a56 703 __O uint32_t MWTD;
ebrus 0:0a673c671a56 704 __I uint32_t MRDD;
ebrus 0:0a673c671a56 705 __I uint32_t MIND;
ebrus 0:0a673c671a56 706 uint32_t RESERVED0[2];
ebrus 0:0a673c671a56 707 __IO uint32_t SA0;
ebrus 0:0a673c671a56 708 __IO uint32_t SA1;
ebrus 0:0a673c671a56 709 __IO uint32_t SA2;
ebrus 0:0a673c671a56 710 uint32_t RESERVED1[45];
ebrus 0:0a673c671a56 711 __IO uint32_t Command; /* Control Registers */
ebrus 0:0a673c671a56 712 __I uint32_t Status;
ebrus 0:0a673c671a56 713 __IO uint32_t RxDescriptor;
ebrus 0:0a673c671a56 714 __IO uint32_t RxStatus;
ebrus 0:0a673c671a56 715 __IO uint32_t RxDescriptorNumber;
ebrus 0:0a673c671a56 716 __I uint32_t RxProduceIndex;
ebrus 0:0a673c671a56 717 __IO uint32_t RxConsumeIndex;
ebrus 0:0a673c671a56 718 __IO uint32_t TxDescriptor;
ebrus 0:0a673c671a56 719 __IO uint32_t TxStatus;
ebrus 0:0a673c671a56 720 __IO uint32_t TxDescriptorNumber;
ebrus 0:0a673c671a56 721 __IO uint32_t TxProduceIndex;
ebrus 0:0a673c671a56 722 __I uint32_t TxConsumeIndex;
ebrus 0:0a673c671a56 723 uint32_t RESERVED2[10];
ebrus 0:0a673c671a56 724 __I uint32_t TSV0;
ebrus 0:0a673c671a56 725 __I uint32_t TSV1;
ebrus 0:0a673c671a56 726 __I uint32_t RSV;
ebrus 0:0a673c671a56 727 uint32_t RESERVED3[3];
ebrus 0:0a673c671a56 728 __IO uint32_t FlowControlCounter;
ebrus 0:0a673c671a56 729 __I uint32_t FlowControlStatus;
ebrus 0:0a673c671a56 730 uint32_t RESERVED4[34];
ebrus 0:0a673c671a56 731 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
ebrus 0:0a673c671a56 732 __IO uint32_t RxFilterWoLStatus;
ebrus 0:0a673c671a56 733 __IO uint32_t RxFilterWoLClear;
ebrus 0:0a673c671a56 734 uint32_t RESERVED5;
ebrus 0:0a673c671a56 735 __IO uint32_t HashFilterL;
ebrus 0:0a673c671a56 736 __IO uint32_t HashFilterH;
ebrus 0:0a673c671a56 737 uint32_t RESERVED6[882];
ebrus 0:0a673c671a56 738 __I uint32_t IntStatus; /* Module Control Registers */
ebrus 0:0a673c671a56 739 __IO uint32_t IntEnable;
ebrus 0:0a673c671a56 740 __O uint32_t IntClear;
ebrus 0:0a673c671a56 741 __O uint32_t IntSet;
ebrus 0:0a673c671a56 742 uint32_t RESERVED7;
ebrus 0:0a673c671a56 743 __IO uint32_t PowerDown;
ebrus 0:0a673c671a56 744 uint32_t RESERVED8;
ebrus 0:0a673c671a56 745 __IO uint32_t Module_ID;
ebrus 0:0a673c671a56 746 } LPC_EMAC_TypeDef;
ebrus 0:0a673c671a56 747
ebrus 0:0a673c671a56 748 #if defined ( __CC_ARM )
ebrus 0:0a673c671a56 749 #pragma no_anon_unions
ebrus 0:0a673c671a56 750 #endif
ebrus 0:0a673c671a56 751
ebrus 0:0a673c671a56 752 /******************************************************************************/
ebrus 0:0a673c671a56 753 /* Peripheral memory map */
ebrus 0:0a673c671a56 754 /******************************************************************************/
ebrus 0:0a673c671a56 755 /* Base addresses */
ebrus 0:0a673c671a56 756
ebrus 0:0a673c671a56 757 /* AHB Peripheral # 0 */
ebrus 0:0a673c671a56 758
ebrus 0:0a673c671a56 759 /*
ebrus 0:0a673c671a56 760 #define FLASH_BASE (0x00000000UL)
ebrus 0:0a673c671a56 761 #define RAM_BASE (0x10000000UL)
ebrus 0:0a673c671a56 762 #define GPIO_BASE (0x2009C000UL)
ebrus 0:0a673c671a56 763 #define APB0_BASE (0x40000000UL)
ebrus 0:0a673c671a56 764 #define APB1_BASE (0x40080000UL)
ebrus 0:0a673c671a56 765 #define AHB_BASE (0x50000000UL)
ebrus 0:0a673c671a56 766 #define CM3_BASE (0xE0000000UL)
ebrus 0:0a673c671a56 767 */
ebrus 0:0a673c671a56 768
ebrus 0:0a673c671a56 769 // TODO - #define VIC_BASE_ADDR 0xFFFFF000
ebrus 0:0a673c671a56 770
ebrus 0:0a673c671a56 771 #define LPC_WDT_BASE (0xE0000000)
ebrus 0:0a673c671a56 772 #define LPC_TIM0_BASE (0xE0004000)
ebrus 0:0a673c671a56 773 #define LPC_TIM1_BASE (0xE0008000)
ebrus 0:0a673c671a56 774 #define LPC_UART0_BASE (0xE000C000)
ebrus 0:0a673c671a56 775 #define LPC_UART1_BASE (0xE0010000)
ebrus 0:0a673c671a56 776 #define LPC_PWM1_BASE (0xE0018000)
ebrus 0:0a673c671a56 777 #define LPC_I2C0_BASE (0xE001C000)
ebrus 0:0a673c671a56 778 #define LPC_SPI_BASE (0xE0020000)
ebrus 0:0a673c671a56 779 #define LPC_RTC_BASE (0xE0024000)
ebrus 0:0a673c671a56 780 #define LPC_GPIOINT_BASE (0xE0028080)
ebrus 0:0a673c671a56 781 #define LPC_PINCON_BASE (0xE002C000)
ebrus 0:0a673c671a56 782 #define LPC_SSP1_BASE (0xE0030000)
ebrus 0:0a673c671a56 783 #define LPC_ADC_BASE (0xE0034000)
ebrus 0:0a673c671a56 784 #define LPC_CANAF_RAM_BASE (0xE0038000)
ebrus 0:0a673c671a56 785 #define LPC_CANAF_BASE (0xE003C000)
ebrus 0:0a673c671a56 786 #define LPC_CANCR_BASE (0xE0040000)
ebrus 0:0a673c671a56 787 #define LPC_CAN1_BASE (0xE0044000)
ebrus 0:0a673c671a56 788 #define LPC_CAN2_BASE (0xE0048000)
ebrus 0:0a673c671a56 789 #define LPC_I2C1_BASE (0xE005C000)
ebrus 0:0a673c671a56 790 #define LPC_SSP0_BASE (0xE0068000)
ebrus 0:0a673c671a56 791 #define LPC_DAC_BASE (0xE006C000)
ebrus 0:0a673c671a56 792 #define LPC_TIM2_BASE (0xE0070000)
ebrus 0:0a673c671a56 793 #define LPC_TIM3_BASE (0xE0074000)
ebrus 0:0a673c671a56 794 #define LPC_UART2_BASE (0xE0078000)
ebrus 0:0a673c671a56 795 #define LPC_UART3_BASE (0xE007C000)
ebrus 0:0a673c671a56 796 #define LPC_I2C2_BASE (0xE0080000)
ebrus 0:0a673c671a56 797 #define LPC_I2S_BASE (0xE0088000)
ebrus 0:0a673c671a56 798 #define LPC_MCI_BASE (0xE008C000)
ebrus 0:0a673c671a56 799 #define LPC_SC_BASE (0xE01FC000)
ebrus 0:0a673c671a56 800 #define LPC_EMAC_BASE (0xFFE00000)
ebrus 0:0a673c671a56 801 #define LPC_GPDMA_BASE (0xFFE04000)
ebrus 0:0a673c671a56 802 #define LPC_GPDMACH0_BASE (0xFFE04100)
ebrus 0:0a673c671a56 803 #define LPC_GPDMACH1_BASE (0xFFE04120)
ebrus 0:0a673c671a56 804 #define LPC_USB_BASE (0xFFE0C000)
ebrus 0:0a673c671a56 805 #define LPC_VIC_BASE (0xFFFFF000)
ebrus 0:0a673c671a56 806
ebrus 0:0a673c671a56 807 /* GPIOs */
ebrus 0:0a673c671a56 808 #define LPC_GPIO0_BASE (0x3FFFC000)
ebrus 0:0a673c671a56 809 #define LPC_GPIO1_BASE (0x3FFFC020)
ebrus 0:0a673c671a56 810 #define LPC_GPIO2_BASE (0x3FFFC040)
ebrus 0:0a673c671a56 811 #define LPC_GPIO3_BASE (0x3FFFC060)
ebrus 0:0a673c671a56 812 #define LPC_GPIO4_BASE (0x3FFFC080)
ebrus 0:0a673c671a56 813
ebrus 0:0a673c671a56 814
ebrus 0:0a673c671a56 815 /******************************************************************************/
ebrus 0:0a673c671a56 816 /* Peripheral declaration */
ebrus 0:0a673c671a56 817 /******************************************************************************/
ebrus 0:0a673c671a56 818 #define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
ebrus 0:0a673c671a56 819 #define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
ebrus 0:0a673c671a56 820 #define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
ebrus 0:0a673c671a56 821 #define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
ebrus 0:0a673c671a56 822 #define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
ebrus 0:0a673c671a56 823 #define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
ebrus 0:0a673c671a56 824 #define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
ebrus 0:0a673c671a56 825 #define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
ebrus 0:0a673c671a56 826 #define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
ebrus 0:0a673c671a56 827 #define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
ebrus 0:0a673c671a56 828 #define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
ebrus 0:0a673c671a56 829 #define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
ebrus 0:0a673c671a56 830 #define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
ebrus 0:0a673c671a56 831 #define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
ebrus 0:0a673c671a56 832 #define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
ebrus 0:0a673c671a56 833 #define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
ebrus 0:0a673c671a56 834 #define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
ebrus 0:0a673c671a56 835 #define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
ebrus 0:0a673c671a56 836 #define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
ebrus 0:0a673c671a56 837 #define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
ebrus 0:0a673c671a56 838 #define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
ebrus 0:0a673c671a56 839 #define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
ebrus 0:0a673c671a56 840 #define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
ebrus 0:0a673c671a56 841 #define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
ebrus 0:0a673c671a56 842 #define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
ebrus 0:0a673c671a56 843 #define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
ebrus 0:0a673c671a56 844 #define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
ebrus 0:0a673c671a56 845 #define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
ebrus 0:0a673c671a56 846 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
ebrus 0:0a673c671a56 847 #define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
ebrus 0:0a673c671a56 848 #define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
ebrus 0:0a673c671a56 849 #define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
ebrus 0:0a673c671a56 850 #define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
ebrus 0:0a673c671a56 851 #define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
ebrus 0:0a673c671a56 852 #define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
ebrus 0:0a673c671a56 853 #define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
ebrus 0:0a673c671a56 854 #define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
ebrus 0:0a673c671a56 855 #define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
ebrus 0:0a673c671a56 856 #define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
ebrus 0:0a673c671a56 857 #define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
ebrus 0:0a673c671a56 858
ebrus 0:0a673c671a56 859 #ifdef __cplusplus
ebrus 0:0a673c671a56 860 }
ebrus 0:0a673c671a56 861 #endif
ebrus 0:0a673c671a56 862
ebrus 0:0a673c671a56 863 #endif // __LPC23xx_H
ebrus 0:0a673c671a56 864