Ermanno Brusadin / mbed-src

mbed library sources

targets/cmsis/TARGET_NXP/TARGET_LPC176X/LPC17xx.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

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ebrus 0:0a673c671a56 1 /**************************************************************************//**
ebrus 0:0a673c671a56 2 * @file LPC17xx.h
ebrus 0:0a673c671a56 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
ebrus 0:0a673c671a56 4 * NXP LPC17xx Device Series
ebrus 0:0a673c671a56 5 * @version: V1.09
ebrus 0:0a673c671a56 6 * @date: 17. March 2010
ebrus 0:0a673c671a56 7
ebrus 0:0a673c671a56 8 *
ebrus 0:0a673c671a56 9 * @note
ebrus 0:0a673c671a56 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
ebrus 0:0a673c671a56 11 *
ebrus 0:0a673c671a56 12 * @par
ebrus 0:0a673c671a56 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
ebrus 0:0a673c671a56 14 * processor based microcontrollers. This file can be freely distributed
ebrus 0:0a673c671a56 15 * within development tools that are supporting such ARM based processors.
ebrus 0:0a673c671a56 16 *
ebrus 0:0a673c671a56 17 * @par
ebrus 0:0a673c671a56 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
ebrus 0:0a673c671a56 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
ebrus 0:0a673c671a56 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
ebrus 0:0a673c671a56 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
ebrus 0:0a673c671a56 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
ebrus 0:0a673c671a56 23 *
ebrus 0:0a673c671a56 24 ******************************************************************************/
ebrus 0:0a673c671a56 25
ebrus 0:0a673c671a56 26
ebrus 0:0a673c671a56 27 #ifndef __LPC17xx_H__
ebrus 0:0a673c671a56 28 #define __LPC17xx_H__
ebrus 0:0a673c671a56 29
ebrus 0:0a673c671a56 30 /*
ebrus 0:0a673c671a56 31 * ==========================================================================
ebrus 0:0a673c671a56 32 * ---------- Interrupt Number Definition -----------------------------------
ebrus 0:0a673c671a56 33 * ==========================================================================
ebrus 0:0a673c671a56 34 */
ebrus 0:0a673c671a56 35
ebrus 0:0a673c671a56 36 typedef enum IRQn
ebrus 0:0a673c671a56 37 {
ebrus 0:0a673c671a56 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
ebrus 0:0a673c671a56 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
ebrus 0:0a673c671a56 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
ebrus 0:0a673c671a56 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
ebrus 0:0a673c671a56 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
ebrus 0:0a673c671a56 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
ebrus 0:0a673c671a56 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
ebrus 0:0a673c671a56 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
ebrus 0:0a673c671a56 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
ebrus 0:0a673c671a56 47
ebrus 0:0a673c671a56 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
ebrus 0:0a673c671a56 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
ebrus 0:0a673c671a56 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
ebrus 0:0a673c671a56 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
ebrus 0:0a673c671a56 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
ebrus 0:0a673c671a56 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
ebrus 0:0a673c671a56 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
ebrus 0:0a673c671a56 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
ebrus 0:0a673c671a56 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
ebrus 0:0a673c671a56 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
ebrus 0:0a673c671a56 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
ebrus 0:0a673c671a56 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
ebrus 0:0a673c671a56 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
ebrus 0:0a673c671a56 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
ebrus 0:0a673c671a56 62 SPI_IRQn = 13, /*!< SPI Interrupt */
ebrus 0:0a673c671a56 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
ebrus 0:0a673c671a56 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
ebrus 0:0a673c671a56 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
ebrus 0:0a673c671a56 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
ebrus 0:0a673c671a56 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
ebrus 0:0a673c671a56 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
ebrus 0:0a673c671a56 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
ebrus 0:0a673c671a56 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
ebrus 0:0a673c671a56 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
ebrus 0:0a673c671a56 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
ebrus 0:0a673c671a56 73 USB_IRQn = 24, /*!< USB Interrupt */
ebrus 0:0a673c671a56 74 CAN_IRQn = 25, /*!< CAN Interrupt */
ebrus 0:0a673c671a56 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
ebrus 0:0a673c671a56 76 I2S_IRQn = 27, /*!< I2S Interrupt */
ebrus 0:0a673c671a56 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
ebrus 0:0a673c671a56 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
ebrus 0:0a673c671a56 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
ebrus 0:0a673c671a56 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
ebrus 0:0a673c671a56 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
ebrus 0:0a673c671a56 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
ebrus 0:0a673c671a56 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
ebrus 0:0a673c671a56 84 } IRQn_Type;
ebrus 0:0a673c671a56 85
ebrus 0:0a673c671a56 86
ebrus 0:0a673c671a56 87 /*
ebrus 0:0a673c671a56 88 * ==========================================================================
ebrus 0:0a673c671a56 89 * ----------- Processor and Core Peripheral Section ------------------------
ebrus 0:0a673c671a56 90 * ==========================================================================
ebrus 0:0a673c671a56 91 */
ebrus 0:0a673c671a56 92
ebrus 0:0a673c671a56 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
ebrus 0:0a673c671a56 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
ebrus 0:0a673c671a56 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
ebrus 0:0a673c671a56 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
ebrus 0:0a673c671a56 97
ebrus 0:0a673c671a56 98
ebrus 0:0a673c671a56 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
ebrus 0:0a673c671a56 100 #include "system_LPC17xx.h" /* System Header */
ebrus 0:0a673c671a56 101
ebrus 0:0a673c671a56 102
ebrus 0:0a673c671a56 103 /******************************************************************************/
ebrus 0:0a673c671a56 104 /* Device Specific Peripheral registers structures */
ebrus 0:0a673c671a56 105 /******************************************************************************/
ebrus 0:0a673c671a56 106
ebrus 0:0a673c671a56 107 #if defined ( __CC_ARM )
ebrus 0:0a673c671a56 108 #pragma anon_unions
ebrus 0:0a673c671a56 109 #endif
ebrus 0:0a673c671a56 110
ebrus 0:0a673c671a56 111 /*------------- System Control (SC) ------------------------------------------*/
ebrus 0:0a673c671a56 112 typedef struct
ebrus 0:0a673c671a56 113 {
ebrus 0:0a673c671a56 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
ebrus 0:0a673c671a56 115 uint32_t RESERVED0[31];
ebrus 0:0a673c671a56 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
ebrus 0:0a673c671a56 117 __IO uint32_t PLL0CFG;
ebrus 0:0a673c671a56 118 __I uint32_t PLL0STAT;
ebrus 0:0a673c671a56 119 __O uint32_t PLL0FEED;
ebrus 0:0a673c671a56 120 uint32_t RESERVED1[4];
ebrus 0:0a673c671a56 121 __IO uint32_t PLL1CON;
ebrus 0:0a673c671a56 122 __IO uint32_t PLL1CFG;
ebrus 0:0a673c671a56 123 __I uint32_t PLL1STAT;
ebrus 0:0a673c671a56 124 __O uint32_t PLL1FEED;
ebrus 0:0a673c671a56 125 uint32_t RESERVED2[4];
ebrus 0:0a673c671a56 126 __IO uint32_t PCON;
ebrus 0:0a673c671a56 127 __IO uint32_t PCONP;
ebrus 0:0a673c671a56 128 uint32_t RESERVED3[15];
ebrus 0:0a673c671a56 129 __IO uint32_t CCLKCFG;
ebrus 0:0a673c671a56 130 __IO uint32_t USBCLKCFG;
ebrus 0:0a673c671a56 131 __IO uint32_t CLKSRCSEL;
ebrus 0:0a673c671a56 132 __IO uint32_t CANSLEEPCLR;
ebrus 0:0a673c671a56 133 __IO uint32_t CANWAKEFLAGS;
ebrus 0:0a673c671a56 134 uint32_t RESERVED4[10];
ebrus 0:0a673c671a56 135 __IO uint32_t EXTINT; /* External Interrupts */
ebrus 0:0a673c671a56 136 uint32_t RESERVED5;
ebrus 0:0a673c671a56 137 __IO uint32_t EXTMODE;
ebrus 0:0a673c671a56 138 __IO uint32_t EXTPOLAR;
ebrus 0:0a673c671a56 139 uint32_t RESERVED6[12];
ebrus 0:0a673c671a56 140 __IO uint32_t RSID; /* Reset */
ebrus 0:0a673c671a56 141 uint32_t RESERVED7[7];
ebrus 0:0a673c671a56 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
ebrus 0:0a673c671a56 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
ebrus 0:0a673c671a56 144 __IO uint32_t PCLKSEL0;
ebrus 0:0a673c671a56 145 __IO uint32_t PCLKSEL1;
ebrus 0:0a673c671a56 146 uint32_t RESERVED8[4];
ebrus 0:0a673c671a56 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
ebrus 0:0a673c671a56 148 __IO uint32_t DMAREQSEL;
ebrus 0:0a673c671a56 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
ebrus 0:0a673c671a56 150 } LPC_SC_TypeDef;
ebrus 0:0a673c671a56 151
ebrus 0:0a673c671a56 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
ebrus 0:0a673c671a56 153 typedef struct
ebrus 0:0a673c671a56 154 {
ebrus 0:0a673c671a56 155 __IO uint32_t PINSEL0;
ebrus 0:0a673c671a56 156 __IO uint32_t PINSEL1;
ebrus 0:0a673c671a56 157 __IO uint32_t PINSEL2;
ebrus 0:0a673c671a56 158 __IO uint32_t PINSEL3;
ebrus 0:0a673c671a56 159 __IO uint32_t PINSEL4;
ebrus 0:0a673c671a56 160 __IO uint32_t PINSEL5;
ebrus 0:0a673c671a56 161 __IO uint32_t PINSEL6;
ebrus 0:0a673c671a56 162 __IO uint32_t PINSEL7;
ebrus 0:0a673c671a56 163 __IO uint32_t PINSEL8;
ebrus 0:0a673c671a56 164 __IO uint32_t PINSEL9;
ebrus 0:0a673c671a56 165 __IO uint32_t PINSEL10;
ebrus 0:0a673c671a56 166 uint32_t RESERVED0[5];
ebrus 0:0a673c671a56 167 __IO uint32_t PINMODE0;
ebrus 0:0a673c671a56 168 __IO uint32_t PINMODE1;
ebrus 0:0a673c671a56 169 __IO uint32_t PINMODE2;
ebrus 0:0a673c671a56 170 __IO uint32_t PINMODE3;
ebrus 0:0a673c671a56 171 __IO uint32_t PINMODE4;
ebrus 0:0a673c671a56 172 __IO uint32_t PINMODE5;
ebrus 0:0a673c671a56 173 __IO uint32_t PINMODE6;
ebrus 0:0a673c671a56 174 __IO uint32_t PINMODE7;
ebrus 0:0a673c671a56 175 __IO uint32_t PINMODE8;
ebrus 0:0a673c671a56 176 __IO uint32_t PINMODE9;
ebrus 0:0a673c671a56 177 __IO uint32_t PINMODE_OD0;
ebrus 0:0a673c671a56 178 __IO uint32_t PINMODE_OD1;
ebrus 0:0a673c671a56 179 __IO uint32_t PINMODE_OD2;
ebrus 0:0a673c671a56 180 __IO uint32_t PINMODE_OD3;
ebrus 0:0a673c671a56 181 __IO uint32_t PINMODE_OD4;
ebrus 0:0a673c671a56 182 __IO uint32_t I2CPADCFG;
ebrus 0:0a673c671a56 183 } LPC_PINCON_TypeDef;
ebrus 0:0a673c671a56 184
ebrus 0:0a673c671a56 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
ebrus 0:0a673c671a56 186 typedef struct
ebrus 0:0a673c671a56 187 {
ebrus 0:0a673c671a56 188 union {
ebrus 0:0a673c671a56 189 __IO uint32_t FIODIR;
ebrus 0:0a673c671a56 190 struct {
ebrus 0:0a673c671a56 191 __IO uint16_t FIODIRL;
ebrus 0:0a673c671a56 192 __IO uint16_t FIODIRH;
ebrus 0:0a673c671a56 193 };
ebrus 0:0a673c671a56 194 struct {
ebrus 0:0a673c671a56 195 __IO uint8_t FIODIR0;
ebrus 0:0a673c671a56 196 __IO uint8_t FIODIR1;
ebrus 0:0a673c671a56 197 __IO uint8_t FIODIR2;
ebrus 0:0a673c671a56 198 __IO uint8_t FIODIR3;
ebrus 0:0a673c671a56 199 };
ebrus 0:0a673c671a56 200 };
ebrus 0:0a673c671a56 201 uint32_t RESERVED0[3];
ebrus 0:0a673c671a56 202 union {
ebrus 0:0a673c671a56 203 __IO uint32_t FIOMASK;
ebrus 0:0a673c671a56 204 struct {
ebrus 0:0a673c671a56 205 __IO uint16_t FIOMASKL;
ebrus 0:0a673c671a56 206 __IO uint16_t FIOMASKH;
ebrus 0:0a673c671a56 207 };
ebrus 0:0a673c671a56 208 struct {
ebrus 0:0a673c671a56 209 __IO uint8_t FIOMASK0;
ebrus 0:0a673c671a56 210 __IO uint8_t FIOMASK1;
ebrus 0:0a673c671a56 211 __IO uint8_t FIOMASK2;
ebrus 0:0a673c671a56 212 __IO uint8_t FIOMASK3;
ebrus 0:0a673c671a56 213 };
ebrus 0:0a673c671a56 214 };
ebrus 0:0a673c671a56 215 union {
ebrus 0:0a673c671a56 216 __IO uint32_t FIOPIN;
ebrus 0:0a673c671a56 217 struct {
ebrus 0:0a673c671a56 218 __IO uint16_t FIOPINL;
ebrus 0:0a673c671a56 219 __IO uint16_t FIOPINH;
ebrus 0:0a673c671a56 220 };
ebrus 0:0a673c671a56 221 struct {
ebrus 0:0a673c671a56 222 __IO uint8_t FIOPIN0;
ebrus 0:0a673c671a56 223 __IO uint8_t FIOPIN1;
ebrus 0:0a673c671a56 224 __IO uint8_t FIOPIN2;
ebrus 0:0a673c671a56 225 __IO uint8_t FIOPIN3;
ebrus 0:0a673c671a56 226 };
ebrus 0:0a673c671a56 227 };
ebrus 0:0a673c671a56 228 union {
ebrus 0:0a673c671a56 229 __IO uint32_t FIOSET;
ebrus 0:0a673c671a56 230 struct {
ebrus 0:0a673c671a56 231 __IO uint16_t FIOSETL;
ebrus 0:0a673c671a56 232 __IO uint16_t FIOSETH;
ebrus 0:0a673c671a56 233 };
ebrus 0:0a673c671a56 234 struct {
ebrus 0:0a673c671a56 235 __IO uint8_t FIOSET0;
ebrus 0:0a673c671a56 236 __IO uint8_t FIOSET1;
ebrus 0:0a673c671a56 237 __IO uint8_t FIOSET2;
ebrus 0:0a673c671a56 238 __IO uint8_t FIOSET3;
ebrus 0:0a673c671a56 239 };
ebrus 0:0a673c671a56 240 };
ebrus 0:0a673c671a56 241 union {
ebrus 0:0a673c671a56 242 __O uint32_t FIOCLR;
ebrus 0:0a673c671a56 243 struct {
ebrus 0:0a673c671a56 244 __O uint16_t FIOCLRL;
ebrus 0:0a673c671a56 245 __O uint16_t FIOCLRH;
ebrus 0:0a673c671a56 246 };
ebrus 0:0a673c671a56 247 struct {
ebrus 0:0a673c671a56 248 __O uint8_t FIOCLR0;
ebrus 0:0a673c671a56 249 __O uint8_t FIOCLR1;
ebrus 0:0a673c671a56 250 __O uint8_t FIOCLR2;
ebrus 0:0a673c671a56 251 __O uint8_t FIOCLR3;
ebrus 0:0a673c671a56 252 };
ebrus 0:0a673c671a56 253 };
ebrus 0:0a673c671a56 254 } LPC_GPIO_TypeDef;
ebrus 0:0a673c671a56 255
ebrus 0:0a673c671a56 256 typedef struct
ebrus 0:0a673c671a56 257 {
ebrus 0:0a673c671a56 258 __I uint32_t IntStatus;
ebrus 0:0a673c671a56 259 __I uint32_t IO0IntStatR;
ebrus 0:0a673c671a56 260 __I uint32_t IO0IntStatF;
ebrus 0:0a673c671a56 261 __O uint32_t IO0IntClr;
ebrus 0:0a673c671a56 262 __IO uint32_t IO0IntEnR;
ebrus 0:0a673c671a56 263 __IO uint32_t IO0IntEnF;
ebrus 0:0a673c671a56 264 uint32_t RESERVED0[3];
ebrus 0:0a673c671a56 265 __I uint32_t IO2IntStatR;
ebrus 0:0a673c671a56 266 __I uint32_t IO2IntStatF;
ebrus 0:0a673c671a56 267 __O uint32_t IO2IntClr;
ebrus 0:0a673c671a56 268 __IO uint32_t IO2IntEnR;
ebrus 0:0a673c671a56 269 __IO uint32_t IO2IntEnF;
ebrus 0:0a673c671a56 270 } LPC_GPIOINT_TypeDef;
ebrus 0:0a673c671a56 271
ebrus 0:0a673c671a56 272 /*------------- Timer (TIM) --------------------------------------------------*/
ebrus 0:0a673c671a56 273 typedef struct
ebrus 0:0a673c671a56 274 {
ebrus 0:0a673c671a56 275 __IO uint32_t IR;
ebrus 0:0a673c671a56 276 __IO uint32_t TCR;
ebrus 0:0a673c671a56 277 __IO uint32_t TC;
ebrus 0:0a673c671a56 278 __IO uint32_t PR;
ebrus 0:0a673c671a56 279 __IO uint32_t PC;
ebrus 0:0a673c671a56 280 __IO uint32_t MCR;
ebrus 0:0a673c671a56 281 __IO uint32_t MR0;
ebrus 0:0a673c671a56 282 __IO uint32_t MR1;
ebrus 0:0a673c671a56 283 __IO uint32_t MR2;
ebrus 0:0a673c671a56 284 __IO uint32_t MR3;
ebrus 0:0a673c671a56 285 __IO uint32_t CCR;
ebrus 0:0a673c671a56 286 __I uint32_t CR0;
ebrus 0:0a673c671a56 287 __I uint32_t CR1;
ebrus 0:0a673c671a56 288 uint32_t RESERVED0[2];
ebrus 0:0a673c671a56 289 __IO uint32_t EMR;
ebrus 0:0a673c671a56 290 uint32_t RESERVED1[12];
ebrus 0:0a673c671a56 291 __IO uint32_t CTCR;
ebrus 0:0a673c671a56 292 } LPC_TIM_TypeDef;
ebrus 0:0a673c671a56 293
ebrus 0:0a673c671a56 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
ebrus 0:0a673c671a56 295 typedef struct
ebrus 0:0a673c671a56 296 {
ebrus 0:0a673c671a56 297 __IO uint32_t IR;
ebrus 0:0a673c671a56 298 __IO uint32_t TCR;
ebrus 0:0a673c671a56 299 __IO uint32_t TC;
ebrus 0:0a673c671a56 300 __IO uint32_t PR;
ebrus 0:0a673c671a56 301 __IO uint32_t PC;
ebrus 0:0a673c671a56 302 __IO uint32_t MCR;
ebrus 0:0a673c671a56 303 __IO uint32_t MR0;
ebrus 0:0a673c671a56 304 __IO uint32_t MR1;
ebrus 0:0a673c671a56 305 __IO uint32_t MR2;
ebrus 0:0a673c671a56 306 __IO uint32_t MR3;
ebrus 0:0a673c671a56 307 __IO uint32_t CCR;
ebrus 0:0a673c671a56 308 __I uint32_t CR0;
ebrus 0:0a673c671a56 309 __I uint32_t CR1;
ebrus 0:0a673c671a56 310 __I uint32_t CR2;
ebrus 0:0a673c671a56 311 __I uint32_t CR3;
ebrus 0:0a673c671a56 312 uint32_t RESERVED0;
ebrus 0:0a673c671a56 313 __IO uint32_t MR4;
ebrus 0:0a673c671a56 314 __IO uint32_t MR5;
ebrus 0:0a673c671a56 315 __IO uint32_t MR6;
ebrus 0:0a673c671a56 316 __IO uint32_t PCR;
ebrus 0:0a673c671a56 317 __IO uint32_t LER;
ebrus 0:0a673c671a56 318 uint32_t RESERVED1[7];
ebrus 0:0a673c671a56 319 __IO uint32_t CTCR;
ebrus 0:0a673c671a56 320 } LPC_PWM_TypeDef;
ebrus 0:0a673c671a56 321
ebrus 0:0a673c671a56 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
ebrus 0:0a673c671a56 323 typedef struct
ebrus 0:0a673c671a56 324 {
ebrus 0:0a673c671a56 325 union {
ebrus 0:0a673c671a56 326 __I uint8_t RBR;
ebrus 0:0a673c671a56 327 __O uint8_t THR;
ebrus 0:0a673c671a56 328 __IO uint8_t DLL;
ebrus 0:0a673c671a56 329 uint32_t RESERVED0;
ebrus 0:0a673c671a56 330 };
ebrus 0:0a673c671a56 331 union {
ebrus 0:0a673c671a56 332 __IO uint8_t DLM;
ebrus 0:0a673c671a56 333 __IO uint32_t IER;
ebrus 0:0a673c671a56 334 };
ebrus 0:0a673c671a56 335 union {
ebrus 0:0a673c671a56 336 __I uint32_t IIR;
ebrus 0:0a673c671a56 337 __O uint8_t FCR;
ebrus 0:0a673c671a56 338 };
ebrus 0:0a673c671a56 339 __IO uint8_t LCR;
ebrus 0:0a673c671a56 340 uint8_t RESERVED1[7];
ebrus 0:0a673c671a56 341 __I uint8_t LSR;
ebrus 0:0a673c671a56 342 uint8_t RESERVED2[7];
ebrus 0:0a673c671a56 343 __IO uint8_t SCR;
ebrus 0:0a673c671a56 344 uint8_t RESERVED3[3];
ebrus 0:0a673c671a56 345 __IO uint32_t ACR;
ebrus 0:0a673c671a56 346 __IO uint8_t ICR;
ebrus 0:0a673c671a56 347 uint8_t RESERVED4[3];
ebrus 0:0a673c671a56 348 __IO uint8_t FDR;
ebrus 0:0a673c671a56 349 uint8_t RESERVED5[7];
ebrus 0:0a673c671a56 350 __IO uint8_t TER;
ebrus 0:0a673c671a56 351 uint8_t RESERVED6[39];
ebrus 0:0a673c671a56 352 __IO uint32_t FIFOLVL;
ebrus 0:0a673c671a56 353 } LPC_UART_TypeDef;
ebrus 0:0a673c671a56 354
ebrus 0:0a673c671a56 355 typedef struct
ebrus 0:0a673c671a56 356 {
ebrus 0:0a673c671a56 357 union {
ebrus 0:0a673c671a56 358 __I uint8_t RBR;
ebrus 0:0a673c671a56 359 __O uint8_t THR;
ebrus 0:0a673c671a56 360 __IO uint8_t DLL;
ebrus 0:0a673c671a56 361 uint32_t RESERVED0;
ebrus 0:0a673c671a56 362 };
ebrus 0:0a673c671a56 363 union {
ebrus 0:0a673c671a56 364 __IO uint8_t DLM;
ebrus 0:0a673c671a56 365 __IO uint32_t IER;
ebrus 0:0a673c671a56 366 };
ebrus 0:0a673c671a56 367 union {
ebrus 0:0a673c671a56 368 __I uint32_t IIR;
ebrus 0:0a673c671a56 369 __O uint8_t FCR;
ebrus 0:0a673c671a56 370 };
ebrus 0:0a673c671a56 371 __IO uint8_t LCR;
ebrus 0:0a673c671a56 372 uint8_t RESERVED1[7];
ebrus 0:0a673c671a56 373 __I uint8_t LSR;
ebrus 0:0a673c671a56 374 uint8_t RESERVED2[7];
ebrus 0:0a673c671a56 375 __IO uint8_t SCR;
ebrus 0:0a673c671a56 376 uint8_t RESERVED3[3];
ebrus 0:0a673c671a56 377 __IO uint32_t ACR;
ebrus 0:0a673c671a56 378 __IO uint8_t ICR;
ebrus 0:0a673c671a56 379 uint8_t RESERVED4[3];
ebrus 0:0a673c671a56 380 __IO uint8_t FDR;
ebrus 0:0a673c671a56 381 uint8_t RESERVED5[7];
ebrus 0:0a673c671a56 382 __IO uint8_t TER;
ebrus 0:0a673c671a56 383 uint8_t RESERVED6[39];
ebrus 0:0a673c671a56 384 __IO uint32_t FIFOLVL;
ebrus 0:0a673c671a56 385 } LPC_UART0_TypeDef;
ebrus 0:0a673c671a56 386
ebrus 0:0a673c671a56 387 typedef struct
ebrus 0:0a673c671a56 388 {
ebrus 0:0a673c671a56 389 union {
ebrus 0:0a673c671a56 390 __I uint8_t RBR;
ebrus 0:0a673c671a56 391 __O uint8_t THR;
ebrus 0:0a673c671a56 392 __IO uint8_t DLL;
ebrus 0:0a673c671a56 393 uint32_t RESERVED0;
ebrus 0:0a673c671a56 394 };
ebrus 0:0a673c671a56 395 union {
ebrus 0:0a673c671a56 396 __IO uint8_t DLM;
ebrus 0:0a673c671a56 397 __IO uint32_t IER;
ebrus 0:0a673c671a56 398 };
ebrus 0:0a673c671a56 399 union {
ebrus 0:0a673c671a56 400 __I uint32_t IIR;
ebrus 0:0a673c671a56 401 __O uint8_t FCR;
ebrus 0:0a673c671a56 402 };
ebrus 0:0a673c671a56 403 __IO uint8_t LCR;
ebrus 0:0a673c671a56 404 uint8_t RESERVED1[3];
ebrus 0:0a673c671a56 405 __IO uint8_t MCR;
ebrus 0:0a673c671a56 406 uint8_t RESERVED2[3];
ebrus 0:0a673c671a56 407 __I uint8_t LSR;
ebrus 0:0a673c671a56 408 uint8_t RESERVED3[3];
ebrus 0:0a673c671a56 409 __I uint8_t MSR;
ebrus 0:0a673c671a56 410 uint8_t RESERVED4[3];
ebrus 0:0a673c671a56 411 __IO uint8_t SCR;
ebrus 0:0a673c671a56 412 uint8_t RESERVED5[3];
ebrus 0:0a673c671a56 413 __IO uint32_t ACR;
ebrus 0:0a673c671a56 414 uint32_t RESERVED6;
ebrus 0:0a673c671a56 415 __IO uint32_t FDR;
ebrus 0:0a673c671a56 416 uint32_t RESERVED7;
ebrus 0:0a673c671a56 417 __IO uint8_t TER;
ebrus 0:0a673c671a56 418 uint8_t RESERVED8[27];
ebrus 0:0a673c671a56 419 __IO uint8_t RS485CTRL;
ebrus 0:0a673c671a56 420 uint8_t RESERVED9[3];
ebrus 0:0a673c671a56 421 __IO uint8_t ADRMATCH;
ebrus 0:0a673c671a56 422 uint8_t RESERVED10[3];
ebrus 0:0a673c671a56 423 __IO uint8_t RS485DLY;
ebrus 0:0a673c671a56 424 uint8_t RESERVED11[3];
ebrus 0:0a673c671a56 425 __IO uint32_t FIFOLVL;
ebrus 0:0a673c671a56 426 } LPC_UART1_TypeDef;
ebrus 0:0a673c671a56 427
ebrus 0:0a673c671a56 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
ebrus 0:0a673c671a56 429 typedef struct
ebrus 0:0a673c671a56 430 {
ebrus 0:0a673c671a56 431 __IO uint32_t SPCR;
ebrus 0:0a673c671a56 432 __I uint32_t SPSR;
ebrus 0:0a673c671a56 433 __IO uint32_t SPDR;
ebrus 0:0a673c671a56 434 __IO uint32_t SPCCR;
ebrus 0:0a673c671a56 435 uint32_t RESERVED0[3];
ebrus 0:0a673c671a56 436 __IO uint32_t SPINT;
ebrus 0:0a673c671a56 437 } LPC_SPI_TypeDef;
ebrus 0:0a673c671a56 438
ebrus 0:0a673c671a56 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
ebrus 0:0a673c671a56 440 typedef struct
ebrus 0:0a673c671a56 441 {
ebrus 0:0a673c671a56 442 __IO uint32_t CR0;
ebrus 0:0a673c671a56 443 __IO uint32_t CR1;
ebrus 0:0a673c671a56 444 __IO uint32_t DR;
ebrus 0:0a673c671a56 445 __I uint32_t SR;
ebrus 0:0a673c671a56 446 __IO uint32_t CPSR;
ebrus 0:0a673c671a56 447 __IO uint32_t IMSC;
ebrus 0:0a673c671a56 448 __IO uint32_t RIS;
ebrus 0:0a673c671a56 449 __IO uint32_t MIS;
ebrus 0:0a673c671a56 450 __IO uint32_t ICR;
ebrus 0:0a673c671a56 451 __IO uint32_t DMACR;
ebrus 0:0a673c671a56 452 } LPC_SSP_TypeDef;
ebrus 0:0a673c671a56 453
ebrus 0:0a673c671a56 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
ebrus 0:0a673c671a56 455 typedef struct
ebrus 0:0a673c671a56 456 {
ebrus 0:0a673c671a56 457 __IO uint32_t I2CONSET;
ebrus 0:0a673c671a56 458 __I uint32_t I2STAT;
ebrus 0:0a673c671a56 459 __IO uint32_t I2DAT;
ebrus 0:0a673c671a56 460 __IO uint32_t I2ADR0;
ebrus 0:0a673c671a56 461 __IO uint32_t I2SCLH;
ebrus 0:0a673c671a56 462 __IO uint32_t I2SCLL;
ebrus 0:0a673c671a56 463 __O uint32_t I2CONCLR;
ebrus 0:0a673c671a56 464 __IO uint32_t MMCTRL;
ebrus 0:0a673c671a56 465 __IO uint32_t I2ADR1;
ebrus 0:0a673c671a56 466 __IO uint32_t I2ADR2;
ebrus 0:0a673c671a56 467 __IO uint32_t I2ADR3;
ebrus 0:0a673c671a56 468 __I uint32_t I2DATA_BUFFER;
ebrus 0:0a673c671a56 469 __IO uint32_t I2MASK0;
ebrus 0:0a673c671a56 470 __IO uint32_t I2MASK1;
ebrus 0:0a673c671a56 471 __IO uint32_t I2MASK2;
ebrus 0:0a673c671a56 472 __IO uint32_t I2MASK3;
ebrus 0:0a673c671a56 473 } LPC_I2C_TypeDef;
ebrus 0:0a673c671a56 474
ebrus 0:0a673c671a56 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
ebrus 0:0a673c671a56 476 typedef struct
ebrus 0:0a673c671a56 477 {
ebrus 0:0a673c671a56 478 __IO uint32_t I2SDAO;
ebrus 0:0a673c671a56 479 __IO uint32_t I2SDAI;
ebrus 0:0a673c671a56 480 __O uint32_t I2STXFIFO;
ebrus 0:0a673c671a56 481 __I uint32_t I2SRXFIFO;
ebrus 0:0a673c671a56 482 __I uint32_t I2SSTATE;
ebrus 0:0a673c671a56 483 __IO uint32_t I2SDMA1;
ebrus 0:0a673c671a56 484 __IO uint32_t I2SDMA2;
ebrus 0:0a673c671a56 485 __IO uint32_t I2SIRQ;
ebrus 0:0a673c671a56 486 __IO uint32_t I2STXRATE;
ebrus 0:0a673c671a56 487 __IO uint32_t I2SRXRATE;
ebrus 0:0a673c671a56 488 __IO uint32_t I2STXBITRATE;
ebrus 0:0a673c671a56 489 __IO uint32_t I2SRXBITRATE;
ebrus 0:0a673c671a56 490 __IO uint32_t I2STXMODE;
ebrus 0:0a673c671a56 491 __IO uint32_t I2SRXMODE;
ebrus 0:0a673c671a56 492 } LPC_I2S_TypeDef;
ebrus 0:0a673c671a56 493
ebrus 0:0a673c671a56 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
ebrus 0:0a673c671a56 495 typedef struct
ebrus 0:0a673c671a56 496 {
ebrus 0:0a673c671a56 497 __IO uint32_t RICOMPVAL;
ebrus 0:0a673c671a56 498 __IO uint32_t RIMASK;
ebrus 0:0a673c671a56 499 __IO uint8_t RICTRL;
ebrus 0:0a673c671a56 500 uint8_t RESERVED0[3];
ebrus 0:0a673c671a56 501 __IO uint32_t RICOUNTER;
ebrus 0:0a673c671a56 502 } LPC_RIT_TypeDef;
ebrus 0:0a673c671a56 503
ebrus 0:0a673c671a56 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
ebrus 0:0a673c671a56 505 typedef struct
ebrus 0:0a673c671a56 506 {
ebrus 0:0a673c671a56 507 __IO uint8_t ILR;
ebrus 0:0a673c671a56 508 uint8_t RESERVED0[7];
ebrus 0:0a673c671a56 509 __IO uint8_t CCR;
ebrus 0:0a673c671a56 510 uint8_t RESERVED1[3];
ebrus 0:0a673c671a56 511 __IO uint8_t CIIR;
ebrus 0:0a673c671a56 512 uint8_t RESERVED2[3];
ebrus 0:0a673c671a56 513 __IO uint8_t AMR;
ebrus 0:0a673c671a56 514 uint8_t RESERVED3[3];
ebrus 0:0a673c671a56 515 __I uint32_t CTIME0;
ebrus 0:0a673c671a56 516 __I uint32_t CTIME1;
ebrus 0:0a673c671a56 517 __I uint32_t CTIME2;
ebrus 0:0a673c671a56 518 __IO uint8_t SEC;
ebrus 0:0a673c671a56 519 uint8_t RESERVED4[3];
ebrus 0:0a673c671a56 520 __IO uint8_t MIN;
ebrus 0:0a673c671a56 521 uint8_t RESERVED5[3];
ebrus 0:0a673c671a56 522 __IO uint8_t HOUR;
ebrus 0:0a673c671a56 523 uint8_t RESERVED6[3];
ebrus 0:0a673c671a56 524 __IO uint8_t DOM;
ebrus 0:0a673c671a56 525 uint8_t RESERVED7[3];
ebrus 0:0a673c671a56 526 __IO uint8_t DOW;
ebrus 0:0a673c671a56 527 uint8_t RESERVED8[3];
ebrus 0:0a673c671a56 528 __IO uint16_t DOY;
ebrus 0:0a673c671a56 529 uint16_t RESERVED9;
ebrus 0:0a673c671a56 530 __IO uint8_t MONTH;
ebrus 0:0a673c671a56 531 uint8_t RESERVED10[3];
ebrus 0:0a673c671a56 532 __IO uint16_t YEAR;
ebrus 0:0a673c671a56 533 uint16_t RESERVED11;
ebrus 0:0a673c671a56 534 __IO uint32_t CALIBRATION;
ebrus 0:0a673c671a56 535 __IO uint32_t GPREG0;
ebrus 0:0a673c671a56 536 __IO uint32_t GPREG1;
ebrus 0:0a673c671a56 537 __IO uint32_t GPREG2;
ebrus 0:0a673c671a56 538 __IO uint32_t GPREG3;
ebrus 0:0a673c671a56 539 __IO uint32_t GPREG4;
ebrus 0:0a673c671a56 540 __IO uint8_t RTC_AUXEN;
ebrus 0:0a673c671a56 541 uint8_t RESERVED12[3];
ebrus 0:0a673c671a56 542 __IO uint8_t RTC_AUX;
ebrus 0:0a673c671a56 543 uint8_t RESERVED13[3];
ebrus 0:0a673c671a56 544 __IO uint8_t ALSEC;
ebrus 0:0a673c671a56 545 uint8_t RESERVED14[3];
ebrus 0:0a673c671a56 546 __IO uint8_t ALMIN;
ebrus 0:0a673c671a56 547 uint8_t RESERVED15[3];
ebrus 0:0a673c671a56 548 __IO uint8_t ALHOUR;
ebrus 0:0a673c671a56 549 uint8_t RESERVED16[3];
ebrus 0:0a673c671a56 550 __IO uint8_t ALDOM;
ebrus 0:0a673c671a56 551 uint8_t RESERVED17[3];
ebrus 0:0a673c671a56 552 __IO uint8_t ALDOW;
ebrus 0:0a673c671a56 553 uint8_t RESERVED18[3];
ebrus 0:0a673c671a56 554 __IO uint16_t ALDOY;
ebrus 0:0a673c671a56 555 uint16_t RESERVED19;
ebrus 0:0a673c671a56 556 __IO uint8_t ALMON;
ebrus 0:0a673c671a56 557 uint8_t RESERVED20[3];
ebrus 0:0a673c671a56 558 __IO uint16_t ALYEAR;
ebrus 0:0a673c671a56 559 uint16_t RESERVED21;
ebrus 0:0a673c671a56 560 } LPC_RTC_TypeDef;
ebrus 0:0a673c671a56 561
ebrus 0:0a673c671a56 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
ebrus 0:0a673c671a56 563 typedef struct
ebrus 0:0a673c671a56 564 {
ebrus 0:0a673c671a56 565 __IO uint8_t WDMOD;
ebrus 0:0a673c671a56 566 uint8_t RESERVED0[3];
ebrus 0:0a673c671a56 567 __IO uint32_t WDTC;
ebrus 0:0a673c671a56 568 __O uint8_t WDFEED;
ebrus 0:0a673c671a56 569 uint8_t RESERVED1[3];
ebrus 0:0a673c671a56 570 __I uint32_t WDTV;
ebrus 0:0a673c671a56 571 __IO uint32_t WDCLKSEL;
ebrus 0:0a673c671a56 572 } LPC_WDT_TypeDef;
ebrus 0:0a673c671a56 573
ebrus 0:0a673c671a56 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
ebrus 0:0a673c671a56 575 typedef struct
ebrus 0:0a673c671a56 576 {
ebrus 0:0a673c671a56 577 __IO uint32_t ADCR;
ebrus 0:0a673c671a56 578 __IO uint32_t ADGDR;
ebrus 0:0a673c671a56 579 uint32_t RESERVED0;
ebrus 0:0a673c671a56 580 __IO uint32_t ADINTEN;
ebrus 0:0a673c671a56 581 __I uint32_t ADDR0;
ebrus 0:0a673c671a56 582 __I uint32_t ADDR1;
ebrus 0:0a673c671a56 583 __I uint32_t ADDR2;
ebrus 0:0a673c671a56 584 __I uint32_t ADDR3;
ebrus 0:0a673c671a56 585 __I uint32_t ADDR4;
ebrus 0:0a673c671a56 586 __I uint32_t ADDR5;
ebrus 0:0a673c671a56 587 __I uint32_t ADDR6;
ebrus 0:0a673c671a56 588 __I uint32_t ADDR7;
ebrus 0:0a673c671a56 589 __I uint32_t ADSTAT;
ebrus 0:0a673c671a56 590 __IO uint32_t ADTRM;
ebrus 0:0a673c671a56 591 } LPC_ADC_TypeDef;
ebrus 0:0a673c671a56 592
ebrus 0:0a673c671a56 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
ebrus 0:0a673c671a56 594 typedef struct
ebrus 0:0a673c671a56 595 {
ebrus 0:0a673c671a56 596 __IO uint32_t DACR;
ebrus 0:0a673c671a56 597 __IO uint32_t DACCTRL;
ebrus 0:0a673c671a56 598 __IO uint16_t DACCNTVAL;
ebrus 0:0a673c671a56 599 } LPC_DAC_TypeDef;
ebrus 0:0a673c671a56 600
ebrus 0:0a673c671a56 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
ebrus 0:0a673c671a56 602 typedef struct
ebrus 0:0a673c671a56 603 {
ebrus 0:0a673c671a56 604 __I uint32_t MCCON;
ebrus 0:0a673c671a56 605 __O uint32_t MCCON_SET;
ebrus 0:0a673c671a56 606 __O uint32_t MCCON_CLR;
ebrus 0:0a673c671a56 607 __I uint32_t MCCAPCON;
ebrus 0:0a673c671a56 608 __O uint32_t MCCAPCON_SET;
ebrus 0:0a673c671a56 609 __O uint32_t MCCAPCON_CLR;
ebrus 0:0a673c671a56 610 __IO uint32_t MCTIM0;
ebrus 0:0a673c671a56 611 __IO uint32_t MCTIM1;
ebrus 0:0a673c671a56 612 __IO uint32_t MCTIM2;
ebrus 0:0a673c671a56 613 __IO uint32_t MCPER0;
ebrus 0:0a673c671a56 614 __IO uint32_t MCPER1;
ebrus 0:0a673c671a56 615 __IO uint32_t MCPER2;
ebrus 0:0a673c671a56 616 __IO uint32_t MCPW0;
ebrus 0:0a673c671a56 617 __IO uint32_t MCPW1;
ebrus 0:0a673c671a56 618 __IO uint32_t MCPW2;
ebrus 0:0a673c671a56 619 __IO uint32_t MCDEADTIME;
ebrus 0:0a673c671a56 620 __IO uint32_t MCCCP;
ebrus 0:0a673c671a56 621 __IO uint32_t MCCR0;
ebrus 0:0a673c671a56 622 __IO uint32_t MCCR1;
ebrus 0:0a673c671a56 623 __IO uint32_t MCCR2;
ebrus 0:0a673c671a56 624 __I uint32_t MCINTEN;
ebrus 0:0a673c671a56 625 __O uint32_t MCINTEN_SET;
ebrus 0:0a673c671a56 626 __O uint32_t MCINTEN_CLR;
ebrus 0:0a673c671a56 627 __I uint32_t MCCNTCON;
ebrus 0:0a673c671a56 628 __O uint32_t MCCNTCON_SET;
ebrus 0:0a673c671a56 629 __O uint32_t MCCNTCON_CLR;
ebrus 0:0a673c671a56 630 __I uint32_t MCINTFLAG;
ebrus 0:0a673c671a56 631 __O uint32_t MCINTFLAG_SET;
ebrus 0:0a673c671a56 632 __O uint32_t MCINTFLAG_CLR;
ebrus 0:0a673c671a56 633 __O uint32_t MCCAP_CLR;
ebrus 0:0a673c671a56 634 } LPC_MCPWM_TypeDef;
ebrus 0:0a673c671a56 635
ebrus 0:0a673c671a56 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
ebrus 0:0a673c671a56 637 typedef struct
ebrus 0:0a673c671a56 638 {
ebrus 0:0a673c671a56 639 __O uint32_t QEICON;
ebrus 0:0a673c671a56 640 __I uint32_t QEISTAT;
ebrus 0:0a673c671a56 641 __IO uint32_t QEICONF;
ebrus 0:0a673c671a56 642 __I uint32_t QEIPOS;
ebrus 0:0a673c671a56 643 __IO uint32_t QEIMAXPOS;
ebrus 0:0a673c671a56 644 __IO uint32_t CMPOS0;
ebrus 0:0a673c671a56 645 __IO uint32_t CMPOS1;
ebrus 0:0a673c671a56 646 __IO uint32_t CMPOS2;
ebrus 0:0a673c671a56 647 __I uint32_t INXCNT;
ebrus 0:0a673c671a56 648 __IO uint32_t INXCMP;
ebrus 0:0a673c671a56 649 __IO uint32_t QEILOAD;
ebrus 0:0a673c671a56 650 __I uint32_t QEITIME;
ebrus 0:0a673c671a56 651 __I uint32_t QEIVEL;
ebrus 0:0a673c671a56 652 __I uint32_t QEICAP;
ebrus 0:0a673c671a56 653 __IO uint32_t VELCOMP;
ebrus 0:0a673c671a56 654 __IO uint32_t FILTER;
ebrus 0:0a673c671a56 655 uint32_t RESERVED0[998];
ebrus 0:0a673c671a56 656 __O uint32_t QEIIEC;
ebrus 0:0a673c671a56 657 __O uint32_t QEIIES;
ebrus 0:0a673c671a56 658 __I uint32_t QEIINTSTAT;
ebrus 0:0a673c671a56 659 __I uint32_t QEIIE;
ebrus 0:0a673c671a56 660 __O uint32_t QEICLR;
ebrus 0:0a673c671a56 661 __O uint32_t QEISET;
ebrus 0:0a673c671a56 662 } LPC_QEI_TypeDef;
ebrus 0:0a673c671a56 663
ebrus 0:0a673c671a56 664 /*------------- Controller Area Network (CAN) --------------------------------*/
ebrus 0:0a673c671a56 665 typedef struct
ebrus 0:0a673c671a56 666 {
ebrus 0:0a673c671a56 667 __IO uint32_t mask[512]; /* ID Masks */
ebrus 0:0a673c671a56 668 } LPC_CANAF_RAM_TypeDef;
ebrus 0:0a673c671a56 669
ebrus 0:0a673c671a56 670 typedef struct /* Acceptance Filter Registers */
ebrus 0:0a673c671a56 671 {
ebrus 0:0a673c671a56 672 __IO uint32_t AFMR;
ebrus 0:0a673c671a56 673 __IO uint32_t SFF_sa;
ebrus 0:0a673c671a56 674 __IO uint32_t SFF_GRP_sa;
ebrus 0:0a673c671a56 675 __IO uint32_t EFF_sa;
ebrus 0:0a673c671a56 676 __IO uint32_t EFF_GRP_sa;
ebrus 0:0a673c671a56 677 __IO uint32_t ENDofTable;
ebrus 0:0a673c671a56 678 __I uint32_t LUTerrAd;
ebrus 0:0a673c671a56 679 __I uint32_t LUTerr;
ebrus 0:0a673c671a56 680 __IO uint32_t FCANIE;
ebrus 0:0a673c671a56 681 __IO uint32_t FCANIC0;
ebrus 0:0a673c671a56 682 __IO uint32_t FCANIC1;
ebrus 0:0a673c671a56 683 } LPC_CANAF_TypeDef;
ebrus 0:0a673c671a56 684
ebrus 0:0a673c671a56 685 typedef struct /* Central Registers */
ebrus 0:0a673c671a56 686 {
ebrus 0:0a673c671a56 687 __I uint32_t CANTxSR;
ebrus 0:0a673c671a56 688 __I uint32_t CANRxSR;
ebrus 0:0a673c671a56 689 __I uint32_t CANMSR;
ebrus 0:0a673c671a56 690 } LPC_CANCR_TypeDef;
ebrus 0:0a673c671a56 691
ebrus 0:0a673c671a56 692 typedef struct /* Controller Registers */
ebrus 0:0a673c671a56 693 {
ebrus 0:0a673c671a56 694 __IO uint32_t MOD;
ebrus 0:0a673c671a56 695 __O uint32_t CMR;
ebrus 0:0a673c671a56 696 __IO uint32_t GSR;
ebrus 0:0a673c671a56 697 __I uint32_t ICR;
ebrus 0:0a673c671a56 698 __IO uint32_t IER;
ebrus 0:0a673c671a56 699 __IO uint32_t BTR;
ebrus 0:0a673c671a56 700 __IO uint32_t EWL;
ebrus 0:0a673c671a56 701 __I uint32_t SR;
ebrus 0:0a673c671a56 702 __IO uint32_t RFS;
ebrus 0:0a673c671a56 703 __IO uint32_t RID;
ebrus 0:0a673c671a56 704 __IO uint32_t RDA;
ebrus 0:0a673c671a56 705 __IO uint32_t RDB;
ebrus 0:0a673c671a56 706 __IO uint32_t TFI1;
ebrus 0:0a673c671a56 707 __IO uint32_t TID1;
ebrus 0:0a673c671a56 708 __IO uint32_t TDA1;
ebrus 0:0a673c671a56 709 __IO uint32_t TDB1;
ebrus 0:0a673c671a56 710 __IO uint32_t TFI2;
ebrus 0:0a673c671a56 711 __IO uint32_t TID2;
ebrus 0:0a673c671a56 712 __IO uint32_t TDA2;
ebrus 0:0a673c671a56 713 __IO uint32_t TDB2;
ebrus 0:0a673c671a56 714 __IO uint32_t TFI3;
ebrus 0:0a673c671a56 715 __IO uint32_t TID3;
ebrus 0:0a673c671a56 716 __IO uint32_t TDA3;
ebrus 0:0a673c671a56 717 __IO uint32_t TDB3;
ebrus 0:0a673c671a56 718 } LPC_CAN_TypeDef;
ebrus 0:0a673c671a56 719
ebrus 0:0a673c671a56 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
ebrus 0:0a673c671a56 721 typedef struct /* Common Registers */
ebrus 0:0a673c671a56 722 {
ebrus 0:0a673c671a56 723 __I uint32_t DMACIntStat;
ebrus 0:0a673c671a56 724 __I uint32_t DMACIntTCStat;
ebrus 0:0a673c671a56 725 __O uint32_t DMACIntTCClear;
ebrus 0:0a673c671a56 726 __I uint32_t DMACIntErrStat;
ebrus 0:0a673c671a56 727 __O uint32_t DMACIntErrClr;
ebrus 0:0a673c671a56 728 __I uint32_t DMACRawIntTCStat;
ebrus 0:0a673c671a56 729 __I uint32_t DMACRawIntErrStat;
ebrus 0:0a673c671a56 730 __I uint32_t DMACEnbldChns;
ebrus 0:0a673c671a56 731 __IO uint32_t DMACSoftBReq;
ebrus 0:0a673c671a56 732 __IO uint32_t DMACSoftSReq;
ebrus 0:0a673c671a56 733 __IO uint32_t DMACSoftLBReq;
ebrus 0:0a673c671a56 734 __IO uint32_t DMACSoftLSReq;
ebrus 0:0a673c671a56 735 __IO uint32_t DMACConfig;
ebrus 0:0a673c671a56 736 __IO uint32_t DMACSync;
ebrus 0:0a673c671a56 737 } LPC_GPDMA_TypeDef;
ebrus 0:0a673c671a56 738
ebrus 0:0a673c671a56 739 typedef struct /* Channel Registers */
ebrus 0:0a673c671a56 740 {
ebrus 0:0a673c671a56 741 __IO uint32_t DMACCSrcAddr;
ebrus 0:0a673c671a56 742 __IO uint32_t DMACCDestAddr;
ebrus 0:0a673c671a56 743 __IO uint32_t DMACCLLI;
ebrus 0:0a673c671a56 744 __IO uint32_t DMACCControl;
ebrus 0:0a673c671a56 745 __IO uint32_t DMACCConfig;
ebrus 0:0a673c671a56 746 } LPC_GPDMACH_TypeDef;
ebrus 0:0a673c671a56 747
ebrus 0:0a673c671a56 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
ebrus 0:0a673c671a56 749 typedef struct
ebrus 0:0a673c671a56 750 {
ebrus 0:0a673c671a56 751 __I uint32_t HcRevision; /* USB Host Registers */
ebrus 0:0a673c671a56 752 __IO uint32_t HcControl;
ebrus 0:0a673c671a56 753 __IO uint32_t HcCommandStatus;
ebrus 0:0a673c671a56 754 __IO uint32_t HcInterruptStatus;
ebrus 0:0a673c671a56 755 __IO uint32_t HcInterruptEnable;
ebrus 0:0a673c671a56 756 __IO uint32_t HcInterruptDisable;
ebrus 0:0a673c671a56 757 __IO uint32_t HcHCCA;
ebrus 0:0a673c671a56 758 __I uint32_t HcPeriodCurrentED;
ebrus 0:0a673c671a56 759 __IO uint32_t HcControlHeadED;
ebrus 0:0a673c671a56 760 __IO uint32_t HcControlCurrentED;
ebrus 0:0a673c671a56 761 __IO uint32_t HcBulkHeadED;
ebrus 0:0a673c671a56 762 __IO uint32_t HcBulkCurrentED;
ebrus 0:0a673c671a56 763 __I uint32_t HcDoneHead;
ebrus 0:0a673c671a56 764 __IO uint32_t HcFmInterval;
ebrus 0:0a673c671a56 765 __I uint32_t HcFmRemaining;
ebrus 0:0a673c671a56 766 __I uint32_t HcFmNumber;
ebrus 0:0a673c671a56 767 __IO uint32_t HcPeriodicStart;
ebrus 0:0a673c671a56 768 __IO uint32_t HcLSTreshold;
ebrus 0:0a673c671a56 769 __IO uint32_t HcRhDescriptorA;
ebrus 0:0a673c671a56 770 __IO uint32_t HcRhDescriptorB;
ebrus 0:0a673c671a56 771 __IO uint32_t HcRhStatus;
ebrus 0:0a673c671a56 772 __IO uint32_t HcRhPortStatus1;
ebrus 0:0a673c671a56 773 __IO uint32_t HcRhPortStatus2;
ebrus 0:0a673c671a56 774 uint32_t RESERVED0[40];
ebrus 0:0a673c671a56 775 __I uint32_t Module_ID;
ebrus 0:0a673c671a56 776
ebrus 0:0a673c671a56 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
ebrus 0:0a673c671a56 778 __IO uint32_t OTGIntEn;
ebrus 0:0a673c671a56 779 __O uint32_t OTGIntSet;
ebrus 0:0a673c671a56 780 __O uint32_t OTGIntClr;
ebrus 0:0a673c671a56 781 __IO uint32_t OTGStCtrl;
ebrus 0:0a673c671a56 782 __IO uint32_t OTGTmr;
ebrus 0:0a673c671a56 783 uint32_t RESERVED1[58];
ebrus 0:0a673c671a56 784
ebrus 0:0a673c671a56 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
ebrus 0:0a673c671a56 786 __IO uint32_t USBDevIntEn;
ebrus 0:0a673c671a56 787 __O uint32_t USBDevIntClr;
ebrus 0:0a673c671a56 788 __O uint32_t USBDevIntSet;
ebrus 0:0a673c671a56 789
ebrus 0:0a673c671a56 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
ebrus 0:0a673c671a56 791 __I uint32_t USBCmdData;
ebrus 0:0a673c671a56 792
ebrus 0:0a673c671a56 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
ebrus 0:0a673c671a56 794 __O uint32_t USBTxData;
ebrus 0:0a673c671a56 795 __I uint32_t USBRxPLen;
ebrus 0:0a673c671a56 796 __O uint32_t USBTxPLen;
ebrus 0:0a673c671a56 797 __IO uint32_t USBCtrl;
ebrus 0:0a673c671a56 798 __O uint32_t USBDevIntPri;
ebrus 0:0a673c671a56 799
ebrus 0:0a673c671a56 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
ebrus 0:0a673c671a56 801 __IO uint32_t USBEpIntEn;
ebrus 0:0a673c671a56 802 __O uint32_t USBEpIntClr;
ebrus 0:0a673c671a56 803 __O uint32_t USBEpIntSet;
ebrus 0:0a673c671a56 804 __O uint32_t USBEpIntPri;
ebrus 0:0a673c671a56 805
ebrus 0:0a673c671a56 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
ebrus 0:0a673c671a56 807 __O uint32_t USBEpInd;
ebrus 0:0a673c671a56 808 __IO uint32_t USBMaxPSize;
ebrus 0:0a673c671a56 809
ebrus 0:0a673c671a56 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
ebrus 0:0a673c671a56 811 __O uint32_t USBDMARClr;
ebrus 0:0a673c671a56 812 __O uint32_t USBDMARSet;
ebrus 0:0a673c671a56 813 uint32_t RESERVED2[9];
ebrus 0:0a673c671a56 814 __IO uint32_t USBUDCAH;
ebrus 0:0a673c671a56 815 __I uint32_t USBEpDMASt;
ebrus 0:0a673c671a56 816 __O uint32_t USBEpDMAEn;
ebrus 0:0a673c671a56 817 __O uint32_t USBEpDMADis;
ebrus 0:0a673c671a56 818 __I uint32_t USBDMAIntSt;
ebrus 0:0a673c671a56 819 __IO uint32_t USBDMAIntEn;
ebrus 0:0a673c671a56 820 uint32_t RESERVED3[2];
ebrus 0:0a673c671a56 821 __I uint32_t USBEoTIntSt;
ebrus 0:0a673c671a56 822 __O uint32_t USBEoTIntClr;
ebrus 0:0a673c671a56 823 __O uint32_t USBEoTIntSet;
ebrus 0:0a673c671a56 824 __I uint32_t USBNDDRIntSt;
ebrus 0:0a673c671a56 825 __O uint32_t USBNDDRIntClr;
ebrus 0:0a673c671a56 826 __O uint32_t USBNDDRIntSet;
ebrus 0:0a673c671a56 827 __I uint32_t USBSysErrIntSt;
ebrus 0:0a673c671a56 828 __O uint32_t USBSysErrIntClr;
ebrus 0:0a673c671a56 829 __O uint32_t USBSysErrIntSet;
ebrus 0:0a673c671a56 830 uint32_t RESERVED4[15];
ebrus 0:0a673c671a56 831
ebrus 0:0a673c671a56 832 union {
ebrus 0:0a673c671a56 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
ebrus 0:0a673c671a56 834 __O uint32_t I2C_TX;
ebrus 0:0a673c671a56 835 };
ebrus 0:0a673c671a56 836 __I uint32_t I2C_STS;
ebrus 0:0a673c671a56 837 __IO uint32_t I2C_CTL;
ebrus 0:0a673c671a56 838 __IO uint32_t I2C_CLKHI;
ebrus 0:0a673c671a56 839 __O uint32_t I2C_CLKLO;
ebrus 0:0a673c671a56 840 uint32_t RESERVED5[824];
ebrus 0:0a673c671a56 841
ebrus 0:0a673c671a56 842 union {
ebrus 0:0a673c671a56 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
ebrus 0:0a673c671a56 844 __IO uint32_t OTGClkCtrl;
ebrus 0:0a673c671a56 845 };
ebrus 0:0a673c671a56 846 union {
ebrus 0:0a673c671a56 847 __I uint32_t USBClkSt;
ebrus 0:0a673c671a56 848 __I uint32_t OTGClkSt;
ebrus 0:0a673c671a56 849 };
ebrus 0:0a673c671a56 850 } LPC_USB_TypeDef;
ebrus 0:0a673c671a56 851
ebrus 0:0a673c671a56 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
ebrus 0:0a673c671a56 853 typedef struct
ebrus 0:0a673c671a56 854 {
ebrus 0:0a673c671a56 855 __IO uint32_t MAC1; /* MAC Registers */
ebrus 0:0a673c671a56 856 __IO uint32_t MAC2;
ebrus 0:0a673c671a56 857 __IO uint32_t IPGT;
ebrus 0:0a673c671a56 858 __IO uint32_t IPGR;
ebrus 0:0a673c671a56 859 __IO uint32_t CLRT;
ebrus 0:0a673c671a56 860 __IO uint32_t MAXF;
ebrus 0:0a673c671a56 861 __IO uint32_t SUPP;
ebrus 0:0a673c671a56 862 __IO uint32_t TEST;
ebrus 0:0a673c671a56 863 __IO uint32_t MCFG;
ebrus 0:0a673c671a56 864 __IO uint32_t MCMD;
ebrus 0:0a673c671a56 865 __IO uint32_t MADR;
ebrus 0:0a673c671a56 866 __O uint32_t MWTD;
ebrus 0:0a673c671a56 867 __I uint32_t MRDD;
ebrus 0:0a673c671a56 868 __I uint32_t MIND;
ebrus 0:0a673c671a56 869 uint32_t RESERVED0[2];
ebrus 0:0a673c671a56 870 __IO uint32_t SA0;
ebrus 0:0a673c671a56 871 __IO uint32_t SA1;
ebrus 0:0a673c671a56 872 __IO uint32_t SA2;
ebrus 0:0a673c671a56 873 uint32_t RESERVED1[45];
ebrus 0:0a673c671a56 874 __IO uint32_t Command; /* Control Registers */
ebrus 0:0a673c671a56 875 __I uint32_t Status;
ebrus 0:0a673c671a56 876 __IO uint32_t RxDescriptor;
ebrus 0:0a673c671a56 877 __IO uint32_t RxStatus;
ebrus 0:0a673c671a56 878 __IO uint32_t RxDescriptorNumber;
ebrus 0:0a673c671a56 879 __I uint32_t RxProduceIndex;
ebrus 0:0a673c671a56 880 __IO uint32_t RxConsumeIndex;
ebrus 0:0a673c671a56 881 __IO uint32_t TxDescriptor;
ebrus 0:0a673c671a56 882 __IO uint32_t TxStatus;
ebrus 0:0a673c671a56 883 __IO uint32_t TxDescriptorNumber;
ebrus 0:0a673c671a56 884 __IO uint32_t TxProduceIndex;
ebrus 0:0a673c671a56 885 __I uint32_t TxConsumeIndex;
ebrus 0:0a673c671a56 886 uint32_t RESERVED2[10];
ebrus 0:0a673c671a56 887 __I uint32_t TSV0;
ebrus 0:0a673c671a56 888 __I uint32_t TSV1;
ebrus 0:0a673c671a56 889 __I uint32_t RSV;
ebrus 0:0a673c671a56 890 uint32_t RESERVED3[3];
ebrus 0:0a673c671a56 891 __IO uint32_t FlowControlCounter;
ebrus 0:0a673c671a56 892 __I uint32_t FlowControlStatus;
ebrus 0:0a673c671a56 893 uint32_t RESERVED4[34];
ebrus 0:0a673c671a56 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
ebrus 0:0a673c671a56 895 __IO uint32_t RxFilterWoLStatus;
ebrus 0:0a673c671a56 896 __IO uint32_t RxFilterWoLClear;
ebrus 0:0a673c671a56 897 uint32_t RESERVED5;
ebrus 0:0a673c671a56 898 __IO uint32_t HashFilterL;
ebrus 0:0a673c671a56 899 __IO uint32_t HashFilterH;
ebrus 0:0a673c671a56 900 uint32_t RESERVED6[882];
ebrus 0:0a673c671a56 901 __I uint32_t IntStatus; /* Module Control Registers */
ebrus 0:0a673c671a56 902 __IO uint32_t IntEnable;
ebrus 0:0a673c671a56 903 __O uint32_t IntClear;
ebrus 0:0a673c671a56 904 __O uint32_t IntSet;
ebrus 0:0a673c671a56 905 uint32_t RESERVED7;
ebrus 0:0a673c671a56 906 __IO uint32_t PowerDown;
ebrus 0:0a673c671a56 907 uint32_t RESERVED8;
ebrus 0:0a673c671a56 908 __IO uint32_t Module_ID;
ebrus 0:0a673c671a56 909 } LPC_EMAC_TypeDef;
ebrus 0:0a673c671a56 910
ebrus 0:0a673c671a56 911 #if defined ( __CC_ARM )
ebrus 0:0a673c671a56 912 #pragma no_anon_unions
ebrus 0:0a673c671a56 913 #endif
ebrus 0:0a673c671a56 914
ebrus 0:0a673c671a56 915
ebrus 0:0a673c671a56 916 /******************************************************************************/
ebrus 0:0a673c671a56 917 /* Peripheral memory map */
ebrus 0:0a673c671a56 918 /******************************************************************************/
ebrus 0:0a673c671a56 919 /* Base addresses */
ebrus 0:0a673c671a56 920 #define LPC_FLASH_BASE (0x00000000UL)
ebrus 0:0a673c671a56 921 #define LPC_RAM_BASE (0x10000000UL)
ebrus 0:0a673c671a56 922 #define LPC_GPIO_BASE (0x2009C000UL)
ebrus 0:0a673c671a56 923 #define LPC_APB0_BASE (0x40000000UL)
ebrus 0:0a673c671a56 924 #define LPC_APB1_BASE (0x40080000UL)
ebrus 0:0a673c671a56 925 #define LPC_AHB_BASE (0x50000000UL)
ebrus 0:0a673c671a56 926 #define LPC_CM3_BASE (0xE0000000UL)
ebrus 0:0a673c671a56 927
ebrus 0:0a673c671a56 928 /* APB0 peripherals */
ebrus 0:0a673c671a56 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
ebrus 0:0a673c671a56 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
ebrus 0:0a673c671a56 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
ebrus 0:0a673c671a56 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
ebrus 0:0a673c671a56 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
ebrus 0:0a673c671a56 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
ebrus 0:0a673c671a56 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
ebrus 0:0a673c671a56 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
ebrus 0:0a673c671a56 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
ebrus 0:0a673c671a56 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
ebrus 0:0a673c671a56 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
ebrus 0:0a673c671a56 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
ebrus 0:0a673c671a56 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
ebrus 0:0a673c671a56 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
ebrus 0:0a673c671a56 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
ebrus 0:0a673c671a56 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
ebrus 0:0a673c671a56 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
ebrus 0:0a673c671a56 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
ebrus 0:0a673c671a56 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
ebrus 0:0a673c671a56 948
ebrus 0:0a673c671a56 949 /* APB1 peripherals */
ebrus 0:0a673c671a56 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
ebrus 0:0a673c671a56 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
ebrus 0:0a673c671a56 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
ebrus 0:0a673c671a56 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
ebrus 0:0a673c671a56 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
ebrus 0:0a673c671a56 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
ebrus 0:0a673c671a56 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
ebrus 0:0a673c671a56 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
ebrus 0:0a673c671a56 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
ebrus 0:0a673c671a56 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
ebrus 0:0a673c671a56 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
ebrus 0:0a673c671a56 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
ebrus 0:0a673c671a56 962
ebrus 0:0a673c671a56 963 /* AHB peripherals */
ebrus 0:0a673c671a56 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
ebrus 0:0a673c671a56 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
ebrus 0:0a673c671a56 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
ebrus 0:0a673c671a56 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
ebrus 0:0a673c671a56 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
ebrus 0:0a673c671a56 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
ebrus 0:0a673c671a56 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
ebrus 0:0a673c671a56 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
ebrus 0:0a673c671a56 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
ebrus 0:0a673c671a56 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
ebrus 0:0a673c671a56 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
ebrus 0:0a673c671a56 975
ebrus 0:0a673c671a56 976 /* GPIOs */
ebrus 0:0a673c671a56 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
ebrus 0:0a673c671a56 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
ebrus 0:0a673c671a56 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
ebrus 0:0a673c671a56 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
ebrus 0:0a673c671a56 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
ebrus 0:0a673c671a56 982
ebrus 0:0a673c671a56 983
ebrus 0:0a673c671a56 984 /******************************************************************************/
ebrus 0:0a673c671a56 985 /* Peripheral declaration */
ebrus 0:0a673c671a56 986 /******************************************************************************/
ebrus 0:0a673c671a56 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
ebrus 0:0a673c671a56 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
ebrus 0:0a673c671a56 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
ebrus 0:0a673c671a56 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
ebrus 0:0a673c671a56 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
ebrus 0:0a673c671a56 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
ebrus 0:0a673c671a56 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
ebrus 0:0a673c671a56 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
ebrus 0:0a673c671a56 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
ebrus 0:0a673c671a56 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
ebrus 0:0a673c671a56 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
ebrus 0:0a673c671a56 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
ebrus 0:0a673c671a56 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
ebrus 0:0a673c671a56 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
ebrus 0:0a673c671a56 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
ebrus 0:0a673c671a56 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
ebrus 0:0a673c671a56 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
ebrus 0:0a673c671a56 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
ebrus 0:0a673c671a56 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
ebrus 0:0a673c671a56 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
ebrus 0:0a673c671a56 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
ebrus 0:0a673c671a56 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
ebrus 0:0a673c671a56 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
ebrus 0:0a673c671a56 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
ebrus 0:0a673c671a56 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
ebrus 0:0a673c671a56 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
ebrus 0:0a673c671a56 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
ebrus 0:0a673c671a56 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
ebrus 0:0a673c671a56 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
ebrus 0:0a673c671a56 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
ebrus 0:0a673c671a56 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
ebrus 0:0a673c671a56 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
ebrus 0:0a673c671a56 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
ebrus 0:0a673c671a56 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
ebrus 0:0a673c671a56 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
ebrus 0:0a673c671a56 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
ebrus 0:0a673c671a56 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
ebrus 0:0a673c671a56 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
ebrus 0:0a673c671a56 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
ebrus 0:0a673c671a56 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
ebrus 0:0a673c671a56 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
ebrus 0:0a673c671a56 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
ebrus 0:0a673c671a56 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
ebrus 0:0a673c671a56 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
ebrus 0:0a673c671a56 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
ebrus 0:0a673c671a56 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
ebrus 0:0a673c671a56 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
ebrus 0:0a673c671a56 1034
ebrus 0:0a673c671a56 1035 #endif // __LPC17xx_H__