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targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:: ebrus
Date:: Wed Jul 27 18:35:32 2016 +0000
Revision:: 0:0a673c671a56

Who changed what in which revision?

User	Revision	Line number	New contents of line
ebrus	0:0a673c671a56	1
ebrus	0:0a673c671a56	2	/**************************************************************************************************//
ebrus	0:0a673c671a56	3	* @file LPC15xx.h
ebrus	0:0a673c671a56	4	*
ebrus	0:0a673c671a56	5	* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
ebrus	0:0a673c671a56	6	* LPC15xx from .
ebrus	0:0a673c671a56	7	*
ebrus	0:0a673c671a56	8	* @version V0.3
ebrus	0:0a673c671a56	9	* @date 17. July 2013
ebrus	0:0a673c671a56	10	*
ebrus	0:0a673c671a56	11	* @note Generated with SVDConv V2.80
ebrus	0:0a673c671a56	12	* from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
ebrus	0:0a673c671a56	13	*
ebrus	0:0a673c671a56	14	* modified by Keil
ebrus	0:0a673c671a56	15	* modified by ytsuboi
ebrus	0:0a673c671a56	16	*******************************************************************************************************/
ebrus	0:0a673c671a56	17
ebrus	0:0a673c671a56	18
ebrus	0:0a673c671a56	19
ebrus	0:0a673c671a56	20	/** @addtogroup (null)
ebrus	0:0a673c671a56	21	* @{
ebrus	0:0a673c671a56	22	*/
ebrus	0:0a673c671a56	23
ebrus	0:0a673c671a56	24	/** @addtogroup LPC15xx
ebrus	0:0a673c671a56	25	* @{
ebrus	0:0a673c671a56	26	*/
ebrus	0:0a673c671a56	27
ebrus	0:0a673c671a56	28	#ifndef LPC15XX_H
ebrus	0:0a673c671a56	29	#define LPC15XX_H
ebrus	0:0a673c671a56	30
ebrus	0:0a673c671a56	31	#ifdef __cplusplus
ebrus	0:0a673c671a56	32	extern "C" {
ebrus	0:0a673c671a56	33	#endif
ebrus	0:0a673c671a56	34
ebrus	0:0a673c671a56	35
ebrus	0:0a673c671a56	36	/* ------------------------- Interrupt Number Definition ------------------------ */
ebrus	0:0a673c671a56	37
ebrus	0:0a673c671a56	38	typedef enum {
ebrus	0:0a673c671a56	39	/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
ebrus	0:0a673c671a56	40	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
ebrus	0:0a673c671a56	41	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
ebrus	0:0a673c671a56	42	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
ebrus	0:0a673c671a56	43	MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
ebrus	0:0a673c671a56	44	and No Match */
ebrus	0:0a673c671a56	45	BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
ebrus	0:0a673c671a56	46	related Fault */
ebrus	0:0a673c671a56	47	UsageFault_IRQn = -10, /!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition /
ebrus	0:0a673c671a56	48	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
ebrus	0:0a673c671a56	49	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
ebrus	0:0a673c671a56	50	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
ebrus	0:0a673c671a56	51	SysTick_IRQn = -1, /!< 15 System Tick Timer /
ebrus	0:0a673c671a56	52	/* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
ebrus	0:0a673c671a56	53	WDT_IRQn = 0, /!< 0 WDT /
ebrus	0:0a673c671a56	54	BOD_IRQn = 1, /!< 1 BOD /
ebrus	0:0a673c671a56	55	FLASH_IRQn = 2, /!< 2 FLASH /
ebrus	0:0a673c671a56	56	EE_IRQn = 3, /!< 3 EE /
ebrus	0:0a673c671a56	57	DMA_IRQn = 4, /!< 4 DMA /
ebrus	0:0a673c671a56	58	GINT0_IRQn = 5, /!< 5 GINT0 /
ebrus	0:0a673c671a56	59	GINT1_IRQn = 6, /!< 6 GINT1 /
ebrus	0:0a673c671a56	60	PIN_INT0_IRQn = 7, /!< 7 PIN_INT0 /
ebrus	0:0a673c671a56	61	PIN_INT1_IRQn = 8, /!< 8 PIN_INT1 /
ebrus	0:0a673c671a56	62	PIN_INT2_IRQn = 9, /!< 9 PIN_INT2 /
ebrus	0:0a673c671a56	63	PIN_INT3_IRQn = 10, /!< 10 PIN_INT3 /
ebrus	0:0a673c671a56	64	PIN_INT4_IRQn = 11, /!< 11 PIN_INT4 /
ebrus	0:0a673c671a56	65	PIN_INT5_IRQn = 12, /!< 12 PIN_INT5 /
ebrus	0:0a673c671a56	66	PIN_INT6_IRQn = 13, /!< 13 PIN_INT6 /
ebrus	0:0a673c671a56	67	PIN_INT7_IRQn = 14, /!< 14 PIN_INT7 /
ebrus	0:0a673c671a56	68	RIT_IRQn = 15, /!< 15 RIT /
ebrus	0:0a673c671a56	69	SCT0_IRQn = 16, /!< 16 SCT0 /
ebrus	0:0a673c671a56	70	SCT1_IRQn = 17, /!< 17 SCT1 /
ebrus	0:0a673c671a56	71	SCT2_IRQn = 18, /!< 18 SCT2 /
ebrus	0:0a673c671a56	72	SCT3_IRQn = 19, /!< 19 SCT3 /
ebrus	0:0a673c671a56	73	MRT_IRQn = 20, /!< 20 MRT /
ebrus	0:0a673c671a56	74	UART0_IRQn = 21, /!< 21 UART0 /
ebrus	0:0a673c671a56	75	UART1_IRQn = 22, /!< 22 UART1 /
ebrus	0:0a673c671a56	76	UART2_IRQn = 23, /!< 23 UART2 /
ebrus	0:0a673c671a56	77	I2C0_IRQn = 24, /!< 24 I2C0 /
ebrus	0:0a673c671a56	78	SPI0_IRQn = 25, /!< 25 SPI0 /
ebrus	0:0a673c671a56	79	SPI1_IRQn = 26, /!< 26 SPI1 /
ebrus	0:0a673c671a56	80	C_CAN0_IRQn = 27, /!< 27 C_CAN0 /
ebrus	0:0a673c671a56	81	USB_IRQ_IRQn = 28, /!< 28 USB_IRQ /
ebrus	0:0a673c671a56	82	USB_FIQ_IRQn = 29, /!< 29 USB_FIQ /
ebrus	0:0a673c671a56	83	USBWAKEUP_IRQn = 30, /!< 30 USBWAKEUP /
ebrus	0:0a673c671a56	84	ADC0_SEQA_IRQn = 31, /!< 31 ADC0_SEQA /
ebrus	0:0a673c671a56	85	ADC0_SEQB_IRQn = 32, /!< 32 ADC0_SEQB /
ebrus	0:0a673c671a56	86	ADC0_THCMP_IRQn = 33, /!< 33 ADC0_THCMP /
ebrus	0:0a673c671a56	87	ADC0_OVR_IRQn = 34, /!< 34 ADC0_OVR /
ebrus	0:0a673c671a56	88	ADC1_SEQA_IRQn = 35, /!< 35 ADC1_SEQA /
ebrus	0:0a673c671a56	89	ADC1_SEQB_IRQn = 36, /!< 36 ADC1_SEQB /
ebrus	0:0a673c671a56	90	ADC1_THCMP_IRQn = 37, /!< 37 ADC1_THCMP /
ebrus	0:0a673c671a56	91	ADC1_OVR_IRQn = 38, /!< 38 ADC1_OVR /
ebrus	0:0a673c671a56	92	DAC_IRQn = 39, /!< 39 DAC /
ebrus	0:0a673c671a56	93	CMP0_IRQn = 40, /!< 40 CMP0 /
ebrus	0:0a673c671a56	94	CMP1_IRQn = 41, /!< 41 CMP1 /
ebrus	0:0a673c671a56	95	CMP2_IRQn = 42, /!< 42 CMP2 /
ebrus	0:0a673c671a56	96	CMP3_IRQn = 43, /!< 43 CMP3 /
ebrus	0:0a673c671a56	97	QEI_IRQn = 44, /!< 44 QEI /
ebrus	0:0a673c671a56	98	RTC_ALARM_IRQn = 45, /!< 45 RTC_ALARM /
ebrus	0:0a673c671a56	99	RTC_WAKE_IRQn = 46 /!< 46 RTC_WAKE /
ebrus	0:0a673c671a56	100	} IRQn_Type;
ebrus	0:0a673c671a56	101
ebrus	0:0a673c671a56	102
ebrus	0:0a673c671a56	103	/** @addtogroup Configuration_of_CMSIS
ebrus	0:0a673c671a56	104	* @{
ebrus	0:0a673c671a56	105	*/
ebrus	0:0a673c671a56	106
ebrus	0:0a673c671a56	107
ebrus	0:0a673c671a56	108	/* ================================================================================ */
ebrus	0:0a673c671a56	109	/* ================ Processor and Core Peripheral Section ================ */
ebrus	0:0a673c671a56	110	/* ================================================================================ */
ebrus	0:0a673c671a56	111
ebrus	0:0a673c671a56	112	/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
ebrus	0:0a673c671a56	113	#define __CM3_REV 0x0201 /!< Cortex-M3 Core Revision /
ebrus	0:0a673c671a56	114	#define __MPU_PRESENT 0 /!< MPU present or not /
ebrus	0:0a673c671a56	115	#define __NVIC_PRIO_BITS 3 /!< Number of Bits used for Priority Levels /
ebrus	0:0a673c671a56	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
ebrus	0:0a673c671a56	117	/** @} / / End of group Configuration_of_CMSIS */
ebrus	0:0a673c671a56	118
ebrus	0:0a673c671a56	119	#include "core_cm3.h" /!< Cortex-M3 processor and core peripherals /
ebrus	0:0a673c671a56	120	#include "system_LPC15xx.h" /!< LPC15xx System /
ebrus	0:0a673c671a56	121
ebrus	0:0a673c671a56	122
ebrus	0:0a673c671a56	123	/* ================================================================================ */
ebrus	0:0a673c671a56	124	/* ================ Device Specific Peripheral Section ================ */
ebrus	0:0a673c671a56	125	/* ================================================================================ */
ebrus	0:0a673c671a56	126
ebrus	0:0a673c671a56	127
ebrus	0:0a673c671a56	128	/** @addtogroup Device_Peripheral_Registers
ebrus	0:0a673c671a56	129	* @{
ebrus	0:0a673c671a56	130	*/
ebrus	0:0a673c671a56	131
ebrus	0:0a673c671a56	132
ebrus	0:0a673c671a56	133	/* ------------------- Start of section using anonymous unions ------------------ */
ebrus	0:0a673c671a56	134	#if defined(__CC_ARM)
ebrus	0:0a673c671a56	135	#pragma push
ebrus	0:0a673c671a56	136	#pragma anon_unions
ebrus	0:0a673c671a56	137	#elif defined(__ICCARM__)
ebrus	0:0a673c671a56	138	#pragma language=extended
ebrus	0:0a673c671a56	139	#elif defined(__GNUC__)
ebrus	0:0a673c671a56	140	/* anonymous unions are enabled by default */
ebrus	0:0a673c671a56	141	#elif defined(__TMS470__)
ebrus	0:0a673c671a56	142	/* anonymous unions are enabled by default */
ebrus	0:0a673c671a56	143	#elif defined(__TASKING__)
ebrus	0:0a673c671a56	144	#pragma warning 586
ebrus	0:0a673c671a56	145	#else
ebrus	0:0a673c671a56	146	#warning Not supported compiler type
ebrus	0:0a673c671a56	147	#endif
ebrus	0:0a673c671a56	148
ebrus	0:0a673c671a56	149
ebrus	0:0a673c671a56	150
ebrus	0:0a673c671a56	151	/* ================================================================================ */
ebrus	0:0a673c671a56	152	/* ================ GPIO_PORT ================ */
ebrus	0:0a673c671a56	153	/* ================================================================================ */
ebrus	0:0a673c671a56	154
ebrus	0:0a673c671a56	155
ebrus	0:0a673c671a56	156	/**
ebrus	0:0a673c671a56	157	* @brief General Purpose I/O (GPIO) (GPIO_PORT)
ebrus	0:0a673c671a56	158	*/
ebrus	0:0a673c671a56	159
ebrus	0:0a673c671a56	160	typedef struct { /!< GPIO_PORT Structure /
ebrus	0:0a673c671a56	161	__IO uint8_t B[76]; /!< Byte pin registers /
ebrus	0:0a673c671a56	162	__I uint32_t RESERVED0[45];
ebrus	0:0a673c671a56	163	__IO uint32_t W[76]; /!< Word pin registers /
ebrus	0:0a673c671a56	164	__I uint32_t RESERVED1[1908];
ebrus	0:0a673c671a56	165	__IO uint32_t DIR[3]; /!< Port Direction registers /
ebrus	0:0a673c671a56	166	__I uint32_t RESERVED2[29];
ebrus	0:0a673c671a56	167	__IO uint32_t MASK[3]; /!< Port Mask register /
ebrus	0:0a673c671a56	168	__I uint32_t RESERVED3[29];
ebrus	0:0a673c671a56	169	__IO uint32_t PIN[3]; /!< Port pin register /
ebrus	0:0a673c671a56	170	__I uint32_t RESERVED4[29];
ebrus	0:0a673c671a56	171	__IO uint32_t MPIN[3]; /!< Masked port register /
ebrus	0:0a673c671a56	172	__I uint32_t RESERVED5[29];
ebrus	0:0a673c671a56	173	__IO uint32_t SET[3]; /!< Write: Set port register Read: port output bits /
ebrus	0:0a673c671a56	174	__I uint32_t RESERVED6[29];
ebrus	0:0a673c671a56	175	__O uint32_t CLR[3]; /!< Clear port /
ebrus	0:0a673c671a56	176	__I uint32_t RESERVED7[29];
ebrus	0:0a673c671a56	177	__O uint32_t NOT[3]; /!< Toggle port /
ebrus	0:0a673c671a56	178	} LPC_GPIO_PORT_Type;
ebrus	0:0a673c671a56	179
ebrus	0:0a673c671a56	180
ebrus	0:0a673c671a56	181	/* ================================================================================ */
ebrus	0:0a673c671a56	182	/* ================ DMA ================ */
ebrus	0:0a673c671a56	183	/* ================================================================================ */
ebrus	0:0a673c671a56	184
ebrus	0:0a673c671a56	185
ebrus	0:0a673c671a56	186	/**
ebrus	0:0a673c671a56	187	* @brief DMA controller (DMA)
ebrus	0:0a673c671a56	188	*/
ebrus	0:0a673c671a56	189
ebrus	0:0a673c671a56	190	typedef struct { /!< DMA Structure /
ebrus	0:0a673c671a56	191	__IO uint32_t CTRL; /!< DMA control. /
ebrus	0:0a673c671a56	192	__I uint32_t INTSTAT; /!< Interrupt status. /
ebrus	0:0a673c671a56	193	__IO uint32_t SRAMBASE; /!< SRAM address of the channel configuration table. /
ebrus	0:0a673c671a56	194	__I uint32_t RESERVED0[5];
ebrus	0:0a673c671a56	195	__IO uint32_t ENABLESET0; /!< Channel Enable read and Set for all DMA channels. /
ebrus	0:0a673c671a56	196	__I uint32_t RESERVED1;
ebrus	0:0a673c671a56	197	__O uint32_t ENABLECLR0; /!< Channel Enable Clear for all DMA channels. /
ebrus	0:0a673c671a56	198	__I uint32_t RESERVED2;
ebrus	0:0a673c671a56	199	__I uint32_t ACTIVE0; /!< Channel Active status for all DMA channels. /
ebrus	0:0a673c671a56	200	__I uint32_t RESERVED3;
ebrus	0:0a673c671a56	201	__I uint32_t BUSY0; /!< Channel Busy status for all DMA channels. /
ebrus	0:0a673c671a56	202	__I uint32_t RESERVED4;
ebrus	0:0a673c671a56	203	__IO uint32_t ERRINT0; /!< Error Interrupt status for all DMA channels. /
ebrus	0:0a673c671a56	204	__I uint32_t RESERVED5;
ebrus	0:0a673c671a56	205	__IO uint32_t INTENSET0; /!< Interrupt Enable read and Set for all DMA channels. /
ebrus	0:0a673c671a56	206	__I uint32_t RESERVED6;
ebrus	0:0a673c671a56	207	__O uint32_t INTENCLR0; /!< Interrupt Enable Clear for all DMA channels. /
ebrus	0:0a673c671a56	208	__I uint32_t RESERVED7;
ebrus	0:0a673c671a56	209	__IO uint32_t INTA0; /!< Interrupt A status for all DMA channels. /
ebrus	0:0a673c671a56	210	__I uint32_t RESERVED8;
ebrus	0:0a673c671a56	211	__IO uint32_t INTB0; /!< Interrupt B status for all DMA channels. /
ebrus	0:0a673c671a56	212	__I uint32_t RESERVED9;
ebrus	0:0a673c671a56	213	__O uint32_t SETVALID0; /!< Set ValidPending control bits for all DMA channels. /
ebrus	0:0a673c671a56	214	__I uint32_t RESERVED10;
ebrus	0:0a673c671a56	215	__O uint32_t SETTRIG0; /!< Set Trigger control bits for all DMA channels. /
ebrus	0:0a673c671a56	216	__I uint32_t RESERVED11;
ebrus	0:0a673c671a56	217	__O uint32_t ABORT0; /!< Channel Abort control for all DMA channels. /
ebrus	0:0a673c671a56	218	__I uint32_t RESERVED12[225];
ebrus	0:0a673c671a56	219	__IO uint32_t CFG0; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	220	__I uint32_t CTLSTAT0; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	221	__IO uint32_t XFERCFG0; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	222	__I uint32_t RESERVED13;
ebrus	0:0a673c671a56	223	__IO uint32_t CFG1; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	224	__I uint32_t CTLSTAT1; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	225	__IO uint32_t XFERCFG1; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	226	__I uint32_t RESERVED14;
ebrus	0:0a673c671a56	227	__IO uint32_t CFG2; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	228	__I uint32_t CTLSTAT2; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	229	__IO uint32_t XFERCFG2; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	230	__I uint32_t RESERVED15;
ebrus	0:0a673c671a56	231	__IO uint32_t CFG3; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	232	__I uint32_t CTLSTAT3; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	233	__IO uint32_t XFERCFG3; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	234	__I uint32_t RESERVED16;
ebrus	0:0a673c671a56	235	__IO uint32_t CFG4; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	236	__I uint32_t CTLSTAT4; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	237	__IO uint32_t XFERCFG4; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	238	__I uint32_t RESERVED17;
ebrus	0:0a673c671a56	239	__IO uint32_t CFG5; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	240	__I uint32_t CTLSTAT5; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	241	__IO uint32_t XFERCFG5; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	242	__I uint32_t RESERVED18;
ebrus	0:0a673c671a56	243	__IO uint32_t CFG6; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	244	__I uint32_t CTLSTAT6; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	245	__IO uint32_t XFERCFG6; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	246	__I uint32_t RESERVED19;
ebrus	0:0a673c671a56	247	__IO uint32_t CFG7; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	248	__I uint32_t CTLSTAT7; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	249	__IO uint32_t XFERCFG7; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	250	__I uint32_t RESERVED20;
ebrus	0:0a673c671a56	251	__IO uint32_t CFG8; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	252	__I uint32_t CTLSTAT8; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	253	__IO uint32_t XFERCFG8; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	254	__I uint32_t RESERVED21;
ebrus	0:0a673c671a56	255	__IO uint32_t CFG9; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	256	__I uint32_t CTLSTAT9; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	257	__IO uint32_t XFERCFG9; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	258	__I uint32_t RESERVED22;
ebrus	0:0a673c671a56	259	__IO uint32_t CFG10; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	260	__I uint32_t CTLSTAT10; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	261	__IO uint32_t XFERCFG10; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	262	__I uint32_t RESERVED23;
ebrus	0:0a673c671a56	263	__IO uint32_t CFG11; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	264	__I uint32_t CTLSTAT11; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	265	__IO uint32_t XFERCFG11; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	266	__I uint32_t RESERVED24;
ebrus	0:0a673c671a56	267	__IO uint32_t CFG12; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	268	__I uint32_t CTLSTAT12; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	269	__IO uint32_t XFERCFG12; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	270	__I uint32_t RESERVED25;
ebrus	0:0a673c671a56	271	__IO uint32_t CFG13; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	272	__I uint32_t CTLSTAT13; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	273	__IO uint32_t XFERCFG13; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	274	__I uint32_t RESERVED26;
ebrus	0:0a673c671a56	275	__IO uint32_t CFG14; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	276	__I uint32_t CTLSTAT14; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	277	__IO uint32_t XFERCFG14; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	278	__I uint32_t RESERVED27;
ebrus	0:0a673c671a56	279	__IO uint32_t CFG15; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	280	__I uint32_t CTLSTAT15; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	281	__IO uint32_t XFERCFG15; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	282	__I uint32_t RESERVED28;
ebrus	0:0a673c671a56	283	__IO uint32_t CFG16; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	284	__I uint32_t CTLSTAT16; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	285	__IO uint32_t XFERCFG16; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	286	__I uint32_t RESERVED29;
ebrus	0:0a673c671a56	287	__IO uint32_t CFG17; /!< Configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	288	__I uint32_t CTLSTAT17; /!< Control and status register for DMA channel 0. /
ebrus	0:0a673c671a56	289	__IO uint32_t XFERCFG17; /!< Transfer configuration register for DMA channel 0. /
ebrus	0:0a673c671a56	290	} LPC_DMA_Type;
ebrus	0:0a673c671a56	291
ebrus	0:0a673c671a56	292
ebrus	0:0a673c671a56	293	/* ================================================================================ */
ebrus	0:0a673c671a56	294	/* ================ USB ================ */
ebrus	0:0a673c671a56	295	/* ================================================================================ */
ebrus	0:0a673c671a56	296
ebrus	0:0a673c671a56	297
ebrus	0:0a673c671a56	298	/**
ebrus	0:0a673c671a56	299	* @brief USB device controller (USB)
ebrus	0:0a673c671a56	300	*/
ebrus	0:0a673c671a56	301
ebrus	0:0a673c671a56	302	typedef struct { /!< USB Structure /
ebrus	0:0a673c671a56	303	__IO uint32_t DEVCMDSTAT; /!< USB Device Command/Status register /
ebrus	0:0a673c671a56	304	__IO uint32_t INFO; /!< USB Info register /
ebrus	0:0a673c671a56	305	__IO uint32_t EPLISTSTART; /!< USB EP Command/Status List start address /
ebrus	0:0a673c671a56	306	__IO uint32_t DATABUFSTART; /!< USB Data buffer start address /
ebrus	0:0a673c671a56	307	__IO uint32_t LPM; /!< Link Power Management register /
ebrus	0:0a673c671a56	308	__IO uint32_t EPSKIP; /!< USB Endpoint skip /
ebrus	0:0a673c671a56	309	__IO uint32_t EPINUSE; /!< USB Endpoint Buffer in use /
ebrus	0:0a673c671a56	310	__IO uint32_t EPBUFCFG; /!< USB Endpoint Buffer Configuration register /
ebrus	0:0a673c671a56	311	__IO uint32_t INTSTAT; /!< USB interrupt status register /
ebrus	0:0a673c671a56	312	__IO uint32_t INTEN; /!< USB interrupt enable register /
ebrus	0:0a673c671a56	313	__IO uint32_t INTSETSTAT; /!< USB set interrupt status register /
ebrus	0:0a673c671a56	314	__IO uint32_t INTROUTING; /!< USB interrupt routing register /
ebrus	0:0a673c671a56	315	__I uint32_t RESERVED0;
ebrus	0:0a673c671a56	316	__I uint32_t EPTOGGLE; /!< USB Endpoint toggle register /
ebrus	0:0a673c671a56	317	} LPC_USB_Type;
ebrus	0:0a673c671a56	318
ebrus	0:0a673c671a56	319
ebrus	0:0a673c671a56	320	/* ================================================================================ */
ebrus	0:0a673c671a56	321	/* ================ CRC ================ */
ebrus	0:0a673c671a56	322	/* ================================================================================ */
ebrus	0:0a673c671a56	323
ebrus	0:0a673c671a56	324
ebrus	0:0a673c671a56	325	/**
ebrus	0:0a673c671a56	326	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
ebrus	0:0a673c671a56	327	*/
ebrus	0:0a673c671a56	328
ebrus	0:0a673c671a56	329	typedef struct { /!< CRC Structure /
ebrus	0:0a673c671a56	330	__IO uint32_t MODE; /!< CRC mode register /
ebrus	0:0a673c671a56	331	__IO uint32_t SEED; /!< CRC seed register /
ebrus	0:0a673c671a56	332
ebrus	0:0a673c671a56	333	union {
ebrus	0:0a673c671a56	334	__O uint32_t WR_DATA; /!< CRC data register /
ebrus	0:0a673c671a56	335	__I uint32_t SUM; /!< CRC checksum register /
ebrus	0:0a673c671a56	336	};
ebrus	0:0a673c671a56	337	} LPC_CRC_Type;
ebrus	0:0a673c671a56	338
ebrus	0:0a673c671a56	339
ebrus	0:0a673c671a56	340	/* ================================================================================ */
ebrus	0:0a673c671a56	341	/* ================ SCT0 ================ */
ebrus	0:0a673c671a56	342	/* ================================================================================ */
ebrus	0:0a673c671a56	343
ebrus	0:0a673c671a56	344
ebrus	0:0a673c671a56	345	/**
ebrus	0:0a673c671a56	346	* @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
ebrus	0:0a673c671a56	347	*/
ebrus	0:0a673c671a56	348
ebrus	0:0a673c671a56	349	typedef struct { /!< SCT0 Structure /
ebrus	0:0a673c671a56	350	__IO uint32_t CONFIG; /!< SCT configuration register /
ebrus	0:0a673c671a56	351	__IO uint32_t CTRL; /!< SCT control register /
ebrus	0:0a673c671a56	352	__IO uint32_t LIMIT; /!< SCT limit register /
ebrus	0:0a673c671a56	353	__IO uint32_t HALT; /!< SCT halt condition register /
ebrus	0:0a673c671a56	354	__IO uint32_t STOP; /!< SCT stop condition register /
ebrus	0:0a673c671a56	355	__IO uint32_t START; /!< SCT start condition register /
ebrus	0:0a673c671a56	356	__IO uint32_t DITHER; /!< SCT dither condition register /
ebrus	0:0a673c671a56	357	__I uint32_t RESERVED0[9];
ebrus	0:0a673c671a56	358	__IO uint32_t COUNT; /!< SCT counter register /
ebrus	0:0a673c671a56	359	__IO uint32_t STATE; /!< SCT state register /
ebrus	0:0a673c671a56	360	__I uint32_t INPUT; /!< SCT input register /
ebrus	0:0a673c671a56	361	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
ebrus	0:0a673c671a56	362	__IO uint32_t OUTPUT; /!< SCT output register /
ebrus	0:0a673c671a56	363	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
ebrus	0:0a673c671a56	364	__IO uint32_t RES; /!< SCT conflict resolution register /
ebrus	0:0a673c671a56	365	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
ebrus	0:0a673c671a56	366	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
ebrus	0:0a673c671a56	367	__I uint32_t RESERVED1[35];
ebrus	0:0a673c671a56	368	__IO uint32_t EVEN; /!< SCT event enable register /
ebrus	0:0a673c671a56	369	__IO uint32_t EVFLAG; /!< SCT event flag register /
ebrus	0:0a673c671a56	370	__IO uint32_t CONEN; /!< SCT conflict enable register /
ebrus	0:0a673c671a56	371	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
ebrus	0:0a673c671a56	372
ebrus	0:0a673c671a56	373	union {
ebrus	0:0a673c671a56	374	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	375	REGMODE15 = 1 */
ebrus	0:0a673c671a56	376	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	377	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	378	};
ebrus	0:0a673c671a56	379
ebrus	0:0a673c671a56	380	union {
ebrus	0:0a673c671a56	381	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	382	REGMODE15 = 1 */
ebrus	0:0a673c671a56	383	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	384	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	385	};
ebrus	0:0a673c671a56	386
ebrus	0:0a673c671a56	387	union {
ebrus	0:0a673c671a56	388	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	389	REGMODE15 = 1 */
ebrus	0:0a673c671a56	390	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	391	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	392	};
ebrus	0:0a673c671a56	393
ebrus	0:0a673c671a56	394	union {
ebrus	0:0a673c671a56	395	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	396	REGMODE15 = 1 */
ebrus	0:0a673c671a56	397	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	398	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	399	};
ebrus	0:0a673c671a56	400
ebrus	0:0a673c671a56	401	union {
ebrus	0:0a673c671a56	402	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	403	REGMODE15 = 1 */
ebrus	0:0a673c671a56	404	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	405	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	406	};
ebrus	0:0a673c671a56	407
ebrus	0:0a673c671a56	408	union {
ebrus	0:0a673c671a56	409	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	410	REGMODE15 = 1 */
ebrus	0:0a673c671a56	411	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	412	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	413	};
ebrus	0:0a673c671a56	414
ebrus	0:0a673c671a56	415	union {
ebrus	0:0a673c671a56	416	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	417	REGMODE15 = 1 */
ebrus	0:0a673c671a56	418	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	419	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	420	};
ebrus	0:0a673c671a56	421
ebrus	0:0a673c671a56	422	union {
ebrus	0:0a673c671a56	423	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	424	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	425	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	426	REGMODE15 = 1 */
ebrus	0:0a673c671a56	427	};
ebrus	0:0a673c671a56	428
ebrus	0:0a673c671a56	429	union {
ebrus	0:0a673c671a56	430	__I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	431	REGMODE15 = 1 */
ebrus	0:0a673c671a56	432	__IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	433	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	434	};
ebrus	0:0a673c671a56	435
ebrus	0:0a673c671a56	436	union {
ebrus	0:0a673c671a56	437	__IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	438	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	439	__I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	440	REGMODE15 = 1 */
ebrus	0:0a673c671a56	441	};
ebrus	0:0a673c671a56	442
ebrus	0:0a673c671a56	443	union {
ebrus	0:0a673c671a56	444	__IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	445	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	446	__I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	447	REGMODE15 = 1 */
ebrus	0:0a673c671a56	448	};
ebrus	0:0a673c671a56	449
ebrus	0:0a673c671a56	450	union {
ebrus	0:0a673c671a56	451	__IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	452	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	453	__I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	454	REGMODE15 = 1 */
ebrus	0:0a673c671a56	455	};
ebrus	0:0a673c671a56	456
ebrus	0:0a673c671a56	457	union {
ebrus	0:0a673c671a56	458	__IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	459	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	460	__I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	461	REGMODE15 = 1 */
ebrus	0:0a673c671a56	462	};
ebrus	0:0a673c671a56	463
ebrus	0:0a673c671a56	464	union {
ebrus	0:0a673c671a56	465	__IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	466	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	467	__I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	468	REGMODE15 = 1 */
ebrus	0:0a673c671a56	469	};
ebrus	0:0a673c671a56	470
ebrus	0:0a673c671a56	471	union {
ebrus	0:0a673c671a56	472	__I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	473	REGMODE15 = 1 */
ebrus	0:0a673c671a56	474	__IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	475	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	476	};
ebrus	0:0a673c671a56	477
ebrus	0:0a673c671a56	478	union {
ebrus	0:0a673c671a56	479	__IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
ebrus	0:0a673c671a56	480	to REGMODE15 = 0 */
ebrus	0:0a673c671a56	481	__I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
ebrus	0:0a673c671a56	482	REGMODE15 = 1 */
ebrus	0:0a673c671a56	483	};
ebrus	0:0a673c671a56	484	__IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
ebrus	0:0a673c671a56	485	0 to 5. */
ebrus	0:0a673c671a56	486	__IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
ebrus	0:0a673c671a56	487	0 to 5. */
ebrus	0:0a673c671a56	488	__IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
ebrus	0:0a673c671a56	489	0 to 5. */
ebrus	0:0a673c671a56	490	__IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
ebrus	0:0a673c671a56	491	0 to 5. */
ebrus	0:0a673c671a56	492	__IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
ebrus	0:0a673c671a56	493	0 to 5. */
ebrus	0:0a673c671a56	494	__IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
ebrus	0:0a673c671a56	495	0 to 5. */
ebrus	0:0a673c671a56	496	__I uint32_t RESERVED2[42];
ebrus	0:0a673c671a56	497
ebrus	0:0a673c671a56	498	union {
ebrus	0:0a673c671a56	499	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	500	= 1 */
ebrus	0:0a673c671a56	501	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	502	= 0 */
ebrus	0:0a673c671a56	503	};
ebrus	0:0a673c671a56	504
ebrus	0:0a673c671a56	505	union {
ebrus	0:0a673c671a56	506	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	507	= 0 */
ebrus	0:0a673c671a56	508	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	509	= 1 */
ebrus	0:0a673c671a56	510	};
ebrus	0:0a673c671a56	511
ebrus	0:0a673c671a56	512	union {
ebrus	0:0a673c671a56	513	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	514	= 0 */
ebrus	0:0a673c671a56	515	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	516	= 1 */
ebrus	0:0a673c671a56	517	};
ebrus	0:0a673c671a56	518
ebrus	0:0a673c671a56	519	union {
ebrus	0:0a673c671a56	520	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	521	= 1 */
ebrus	0:0a673c671a56	522	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	523	= 0 */
ebrus	0:0a673c671a56	524	};
ebrus	0:0a673c671a56	525
ebrus	0:0a673c671a56	526	union {
ebrus	0:0a673c671a56	527	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	528	= 1 */
ebrus	0:0a673c671a56	529	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	530	= 0 */
ebrus	0:0a673c671a56	531	};
ebrus	0:0a673c671a56	532
ebrus	0:0a673c671a56	533	union {
ebrus	0:0a673c671a56	534	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	535	= 1 */
ebrus	0:0a673c671a56	536	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	537	= 0 */
ebrus	0:0a673c671a56	538	};
ebrus	0:0a673c671a56	539
ebrus	0:0a673c671a56	540	union {
ebrus	0:0a673c671a56	541	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	542	= 0 */
ebrus	0:0a673c671a56	543	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	544	= 1 */
ebrus	0:0a673c671a56	545	};
ebrus	0:0a673c671a56	546
ebrus	0:0a673c671a56	547	union {
ebrus	0:0a673c671a56	548	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	549	= 0 */
ebrus	0:0a673c671a56	550	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	551	= 1 */
ebrus	0:0a673c671a56	552	};
ebrus	0:0a673c671a56	553
ebrus	0:0a673c671a56	554	union {
ebrus	0:0a673c671a56	555	__IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	556	= 1 */
ebrus	0:0a673c671a56	557	__IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	558	= 0 */
ebrus	0:0a673c671a56	559	};
ebrus	0:0a673c671a56	560
ebrus	0:0a673c671a56	561	union {
ebrus	0:0a673c671a56	562	__IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	563	= 1 */
ebrus	0:0a673c671a56	564	__IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	565	= 0 */
ebrus	0:0a673c671a56	566	};
ebrus	0:0a673c671a56	567
ebrus	0:0a673c671a56	568	union {
ebrus	0:0a673c671a56	569	__IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	570	= 1 */
ebrus	0:0a673c671a56	571	__IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	572	= 0 */
ebrus	0:0a673c671a56	573	};
ebrus	0:0a673c671a56	574
ebrus	0:0a673c671a56	575	union {
ebrus	0:0a673c671a56	576	__IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	577	= 1 */
ebrus	0:0a673c671a56	578	__IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	579	= 0 */
ebrus	0:0a673c671a56	580	};
ebrus	0:0a673c671a56	581
ebrus	0:0a673c671a56	582	union {
ebrus	0:0a673c671a56	583	__IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	584	= 0 */
ebrus	0:0a673c671a56	585	__IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	586	= 1 */
ebrus	0:0a673c671a56	587	};
ebrus	0:0a673c671a56	588
ebrus	0:0a673c671a56	589	union {
ebrus	0:0a673c671a56	590	__IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	591	= 0 */
ebrus	0:0a673c671a56	592	__IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	593	= 1 */
ebrus	0:0a673c671a56	594	};
ebrus	0:0a673c671a56	595
ebrus	0:0a673c671a56	596	union {
ebrus	0:0a673c671a56	597	__IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	598	= 1 */
ebrus	0:0a673c671a56	599	__IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	600	= 0 */
ebrus	0:0a673c671a56	601	};
ebrus	0:0a673c671a56	602
ebrus	0:0a673c671a56	603	union {
ebrus	0:0a673c671a56	604	__IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
ebrus	0:0a673c671a56	605	= 1 */
ebrus	0:0a673c671a56	606	__IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
ebrus	0:0a673c671a56	607	= 0 */
ebrus	0:0a673c671a56	608	};
ebrus	0:0a673c671a56	609	__IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
ebrus	0:0a673c671a56	610	registers 0 to 5. */
ebrus	0:0a673c671a56	611	__IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
ebrus	0:0a673c671a56	612	registers 0 to 5. */
ebrus	0:0a673c671a56	613	__IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
ebrus	0:0a673c671a56	614	registers 0 to 5. */
ebrus	0:0a673c671a56	615	__IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
ebrus	0:0a673c671a56	616	registers 0 to 5. */
ebrus	0:0a673c671a56	617	__IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
ebrus	0:0a673c671a56	618	registers 0 to 5. */
ebrus	0:0a673c671a56	619	__IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
ebrus	0:0a673c671a56	620	registers 0 to 5. */
ebrus	0:0a673c671a56	621	__I uint32_t RESERVED3[42];
ebrus	0:0a673c671a56	622	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	623	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	624	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	625	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	626	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	627	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	628	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	629	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	630	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	631	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	632	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	633	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	634	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	635	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	636	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	637	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	638	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	639	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	640	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	641	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	642	__IO uint32_t EV10_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	643	__IO uint32_t EV10_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	644	__IO uint32_t EV11_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	645	__IO uint32_t EV11_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	646	__IO uint32_t EV12_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	647	__IO uint32_t EV12_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	648	__IO uint32_t EV13_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	649	__IO uint32_t EV13_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	650	__IO uint32_t EV14_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	651	__IO uint32_t EV14_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	652	__IO uint32_t EV15_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	653	__IO uint32_t EV15_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	654	__I uint32_t RESERVED4[96];
ebrus	0:0a673c671a56	655	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	656	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	657	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	658	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	659	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	660	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	661	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	662	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	663	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	664	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	665	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	666	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	667	__IO uint32_t OUT6_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	668	__IO uint32_t OUT6_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	669	__IO uint32_t OUT7_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	670	__IO uint32_t OUT7_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	671	__IO uint32_t OUT8_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	672	__IO uint32_t OUT8_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	673	__IO uint32_t OUT9_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	674	__IO uint32_t OUT9_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	675	} LPC_SCT0_Type;
ebrus	0:0a673c671a56	676
ebrus	0:0a673c671a56	677
ebrus	0:0a673c671a56	678	/* ================================================================================ */
ebrus	0:0a673c671a56	679	/* ================ SCT2 ================ */
ebrus	0:0a673c671a56	680	/* ================================================================================ */
ebrus	0:0a673c671a56	681
ebrus	0:0a673c671a56	682
ebrus	0:0a673c671a56	683	/**
ebrus	0:0a673c671a56	684	* @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
ebrus	0:0a673c671a56	685	*/
ebrus	0:0a673c671a56	686
ebrus	0:0a673c671a56	687	typedef struct { /!< SCT2 Structure /
ebrus	0:0a673c671a56	688	__IO uint32_t CONFIG; /!< SCT configuration register /
ebrus	0:0a673c671a56	689	__IO uint32_t CTRL; /!< SCT control register /
ebrus	0:0a673c671a56	690	__IO uint32_t LIMIT; /!< SCT limit register /
ebrus	0:0a673c671a56	691	__IO uint32_t HALT; /!< SCT halt condition register /
ebrus	0:0a673c671a56	692	__IO uint32_t STOP; /!< SCT stop condition register /
ebrus	0:0a673c671a56	693	__IO uint32_t START; /!< SCT start condition register /
ebrus	0:0a673c671a56	694	__I uint32_t RESERVED0[10];
ebrus	0:0a673c671a56	695	__IO uint32_t COUNT; /!< SCT counter register /
ebrus	0:0a673c671a56	696	__IO uint32_t STATE; /!< SCT state register /
ebrus	0:0a673c671a56	697	__I uint32_t INPUT; /!< SCT input register /
ebrus	0:0a673c671a56	698	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
ebrus	0:0a673c671a56	699	__IO uint32_t OUTPUT; /!< SCT output register /
ebrus	0:0a673c671a56	700	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
ebrus	0:0a673c671a56	701	__IO uint32_t RES; /!< SCT conflict resolution register /
ebrus	0:0a673c671a56	702	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
ebrus	0:0a673c671a56	703	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
ebrus	0:0a673c671a56	704	__I uint32_t RESERVED1[35];
ebrus	0:0a673c671a56	705	__IO uint32_t EVEN; /!< SCT event enable register /
ebrus	0:0a673c671a56	706	__IO uint32_t EVFLAG; /!< SCT event flag register /
ebrus	0:0a673c671a56	707	__IO uint32_t CONEN; /!< SCT conflict enable register /
ebrus	0:0a673c671a56	708	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
ebrus	0:0a673c671a56	709
ebrus	0:0a673c671a56	710	union {
ebrus	0:0a673c671a56	711	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
ebrus	0:0a673c671a56	712	= 1 */
ebrus	0:0a673c671a56	713	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
ebrus	0:0a673c671a56	714	REGMODE7 = 0 */
ebrus	0:0a673c671a56	715	};
ebrus	0:0a673c671a56	716
ebrus	0:0a673c671a56	717	union {
ebrus	0:0a673c671a56	718	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
ebrus	0:0a673c671a56	719	= 1 */
ebrus	0:0a673c671a56	720	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
ebrus	0:0a673c671a56	721	REGMODE7 = 0 */
ebrus	0:0a673c671a56	722	};
ebrus	0:0a673c671a56	723
ebrus	0:0a673c671a56	724	union {
ebrus	0:0a673c671a56	725	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
ebrus	0:0a673c671a56	726	= 1 */
ebrus	0:0a673c671a56	727	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
ebrus	0:0a673c671a56	728	REGMODE7 = 0 */
ebrus	0:0a673c671a56	729	};
ebrus	0:0a673c671a56	730
ebrus	0:0a673c671a56	731	union {
ebrus	0:0a673c671a56	732	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
ebrus	0:0a673c671a56	733	REGMODE7 = 0 */
ebrus	0:0a673c671a56	734	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
ebrus	0:0a673c671a56	735	= 1 */
ebrus	0:0a673c671a56	736	};
ebrus	0:0a673c671a56	737
ebrus	0:0a673c671a56	738	union {
ebrus	0:0a673c671a56	739	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
ebrus	0:0a673c671a56	740	= 1 */
ebrus	0:0a673c671a56	741	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
ebrus	0:0a673c671a56	742	REGMODE7 = 0 */
ebrus	0:0a673c671a56	743	};
ebrus	0:0a673c671a56	744
ebrus	0:0a673c671a56	745	union {
ebrus	0:0a673c671a56	746	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
ebrus	0:0a673c671a56	747	REGMODE7 = 0 */
ebrus	0:0a673c671a56	748	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
ebrus	0:0a673c671a56	749	= 1 */
ebrus	0:0a673c671a56	750	};
ebrus	0:0a673c671a56	751
ebrus	0:0a673c671a56	752	union {
ebrus	0:0a673c671a56	753	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
ebrus	0:0a673c671a56	754	= 1 */
ebrus	0:0a673c671a56	755	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
ebrus	0:0a673c671a56	756	REGMODE7 = 0 */
ebrus	0:0a673c671a56	757	};
ebrus	0:0a673c671a56	758
ebrus	0:0a673c671a56	759	union {
ebrus	0:0a673c671a56	760	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
ebrus	0:0a673c671a56	761	= 1 */
ebrus	0:0a673c671a56	762	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
ebrus	0:0a673c671a56	763	REGMODE7 = 0 */
ebrus	0:0a673c671a56	764	};
ebrus	0:0a673c671a56	765	__I uint32_t RESERVED2[56];
ebrus	0:0a673c671a56	766
ebrus	0:0a673c671a56	767	union {
ebrus	0:0a673c671a56	768	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
ebrus	0:0a673c671a56	769	= 1 */
ebrus	0:0a673c671a56	770	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
ebrus	0:0a673c671a56	771	= 0 */
ebrus	0:0a673c671a56	772	};
ebrus	0:0a673c671a56	773
ebrus	0:0a673c671a56	774	union {
ebrus	0:0a673c671a56	775	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
ebrus	0:0a673c671a56	776	= 1 */
ebrus	0:0a673c671a56	777	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
ebrus	0:0a673c671a56	778	= 0 */
ebrus	0:0a673c671a56	779	};
ebrus	0:0a673c671a56	780
ebrus	0:0a673c671a56	781	union {
ebrus	0:0a673c671a56	782	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
ebrus	0:0a673c671a56	783	= 1 */
ebrus	0:0a673c671a56	784	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
ebrus	0:0a673c671a56	785	= 0 */
ebrus	0:0a673c671a56	786	};
ebrus	0:0a673c671a56	787
ebrus	0:0a673c671a56	788	union {
ebrus	0:0a673c671a56	789	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
ebrus	0:0a673c671a56	790	= 0 */
ebrus	0:0a673c671a56	791	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
ebrus	0:0a673c671a56	792	= 1 */
ebrus	0:0a673c671a56	793	};
ebrus	0:0a673c671a56	794
ebrus	0:0a673c671a56	795	union {
ebrus	0:0a673c671a56	796	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
ebrus	0:0a673c671a56	797	= 1 */
ebrus	0:0a673c671a56	798	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
ebrus	0:0a673c671a56	799	= 0 */
ebrus	0:0a673c671a56	800	};
ebrus	0:0a673c671a56	801
ebrus	0:0a673c671a56	802	union {
ebrus	0:0a673c671a56	803	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
ebrus	0:0a673c671a56	804	= 0 */
ebrus	0:0a673c671a56	805	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
ebrus	0:0a673c671a56	806	= 1 */
ebrus	0:0a673c671a56	807	};
ebrus	0:0a673c671a56	808
ebrus	0:0a673c671a56	809	union {
ebrus	0:0a673c671a56	810	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
ebrus	0:0a673c671a56	811	= 1 */
ebrus	0:0a673c671a56	812	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
ebrus	0:0a673c671a56	813	= 0 */
ebrus	0:0a673c671a56	814	};
ebrus	0:0a673c671a56	815
ebrus	0:0a673c671a56	816	union {
ebrus	0:0a673c671a56	817	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
ebrus	0:0a673c671a56	818	= 1 */
ebrus	0:0a673c671a56	819	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
ebrus	0:0a673c671a56	820	= 0 */
ebrus	0:0a673c671a56	821	};
ebrus	0:0a673c671a56	822	__I uint32_t RESERVED3[56];
ebrus	0:0a673c671a56	823	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	824	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	825	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	826	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	827	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	828	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	829	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	830	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	831	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	832	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	833	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	834	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	835	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	836	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	837	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	838	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	839	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	840	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	841	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
ebrus	0:0a673c671a56	842	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
ebrus	0:0a673c671a56	843	__I uint32_t RESERVED4[108];
ebrus	0:0a673c671a56	844	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	845	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	846	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	847	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	848	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	849	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	850	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	851	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	852	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	853	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	854	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
ebrus	0:0a673c671a56	855	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
ebrus	0:0a673c671a56	856	} LPC_SCT2_Type;
ebrus	0:0a673c671a56	857
ebrus	0:0a673c671a56	858
ebrus	0:0a673c671a56	859	/* ================================================================================ */
ebrus	0:0a673c671a56	860	/* ================ ADC0 ================ */
ebrus	0:0a673c671a56	861	/* ================================================================================ */
ebrus	0:0a673c671a56	862
ebrus	0:0a673c671a56	863
ebrus	0:0a673c671a56	864	/**
ebrus	0:0a673c671a56	865	* @brief 12-bit ADC controller ADC0/1 (ADC0)
ebrus	0:0a673c671a56	866	*/
ebrus	0:0a673c671a56	867
ebrus	0:0a673c671a56	868	typedef struct { /!< ADC0 Structure /
ebrus	0:0a673c671a56	869	__IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
ebrus	0:0a673c671a56	870	bits for each sequence and the A/D power-down bit. */
ebrus	0:0a673c671a56	871	__IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
ebrus	0:0a673c671a56	872	internal source for various channels */
ebrus	0:0a673c671a56	873	__IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
ebrus	0:0a673c671a56	874	and channel selection for conversion sequence-A. Also specifies
ebrus	0:0a673c671a56	875	interrupt mode for sequence-A. */
ebrus	0:0a673c671a56	876	__IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
ebrus	0:0a673c671a56	877	and channel selection for conversion sequence-B. Also specifies
ebrus	0:0a673c671a56	878	interrupt mode for sequence-B. */
ebrus	0:0a673c671a56	879	__IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
ebrus	0:0a673c671a56	880	the result of the most recent A/D conversion performed under
ebrus	0:0a673c671a56	881	sequence-A */
ebrus	0:0a673c671a56	882	__IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
ebrus	0:0a673c671a56	883	the result of the most recent A/D conversion performed under
ebrus	0:0a673c671a56	884	sequence-B */
ebrus	0:0a673c671a56	885	__I uint32_t RESERVED0[2];
ebrus	0:0a673c671a56	886	__I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
ebrus	0:0a673c671a56	887	of the most recent conversion completed on channel 0. */
ebrus	0:0a673c671a56	888	__IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
ebrus	0:0a673c671a56	889	level for automatic threshold comparison for any channels linked
ebrus	0:0a673c671a56	890	to threshold pair 0. */
ebrus	0:0a673c671a56	891	__IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
ebrus	0:0a673c671a56	892	level for automatic threshold comparison for any channels linked
ebrus	0:0a673c671a56	893	to threshold pair 1. */
ebrus	0:0a673c671a56	894	__IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
ebrus	0:0a673c671a56	895	level for automatic threshold comparison for any channels linked
ebrus	0:0a673c671a56	896	to threshold pair 0. */
ebrus	0:0a673c671a56	897	__IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
ebrus	0:0a673c671a56	898	level for automatic threshold comparison for any channels linked
ebrus	0:0a673c671a56	899	to threshold pair 1. */
ebrus	0:0a673c671a56	900	__I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
ebrus	0:0a673c671a56	901	threshold compare registers are to be used for each channel */
ebrus	0:0a673c671a56	902	__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
ebrus	0:0a673c671a56	903	bits that enable the sequence-A, sequence-B, threshold compare
ebrus	0:0a673c671a56	904	and data overrun interrupts to be generated. */
ebrus	0:0a673c671a56	905	__I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
ebrus	0:0a673c671a56	906	and the individual component overrun and threshold-compare flags.
ebrus	0:0a673c671a56	907	(The overrun bits replicate information stored in the result
ebrus	0:0a673c671a56	908	registers). */
ebrus	0:0a673c671a56	909	__IO uint32_t TRM; /!< ADC trim register. /
ebrus	0:0a673c671a56	910	} LPC_ADC0_Type;
ebrus	0:0a673c671a56	911
ebrus	0:0a673c671a56	912
ebrus	0:0a673c671a56	913	/* ================================================================================ */
ebrus	0:0a673c671a56	914	/* ================ DAC ================ */
ebrus	0:0a673c671a56	915	/* ================================================================================ */
ebrus	0:0a673c671a56	916
ebrus	0:0a673c671a56	917
ebrus	0:0a673c671a56	918	/**
ebrus	0:0a673c671a56	919	* @brief 12-bit DAC Modification (DAC)
ebrus	0:0a673c671a56	920	*/
ebrus	0:0a673c671a56	921
ebrus	0:0a673c671a56	922	typedef struct { /!< DAC Structure /
ebrus	0:0a673c671a56	923	__IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
ebrus	0:0a673c671a56	924	value to be converted to analog. */
ebrus	0:0a673c671a56	925	__IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
ebrus	0:0a673c671a56	926	DAC operation and the interrupt/dma request flag. */
ebrus	0:0a673c671a56	927	__IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
ebrus	0:0a673c671a56	928	value for the internal DAC DMA/Interrupt timer. */
ebrus	0:0a673c671a56	929	} LPC_DAC_Type;
ebrus	0:0a673c671a56	930
ebrus	0:0a673c671a56	931
ebrus	0:0a673c671a56	932	/* ================================================================================ */
ebrus	0:0a673c671a56	933	/* ================ ACMP ================ */
ebrus	0:0a673c671a56	934	/* ================================================================================ */
ebrus	0:0a673c671a56	935
ebrus	0:0a673c671a56	936
ebrus	0:0a673c671a56	937	/**
ebrus	0:0a673c671a56	938	* @brief Analog comparators ACMP0/1/2/3 (ACMP)
ebrus	0:0a673c671a56	939	*/
ebrus	0:0a673c671a56	940
ebrus	0:0a673c671a56	941	typedef struct { /!< ACMP Structure /
ebrus	0:0a673c671a56	942	__IO uint32_t CTRL; /!< Comparator block control register /
ebrus	0:0a673c671a56	943	__IO uint32_t CMP0; /!< Comparator 0 source control /
ebrus	0:0a673c671a56	944	__IO uint32_t CMPFILTR0; /!< Comparator 0 pin filter set-up /
ebrus	0:0a673c671a56	945	__IO uint32_t CMP1; /!< Comparator 1 source control /
ebrus	0:0a673c671a56	946	__IO uint32_t CMPFILTR1; /!< Comparator 0 pin filter set-up /
ebrus	0:0a673c671a56	947	__IO uint32_t CMP2; /!< Comparator 2 source control /
ebrus	0:0a673c671a56	948	__IO uint32_t CMPFILTR2; /!< Comparator 0 pin filter set-up /
ebrus	0:0a673c671a56	949	__IO uint32_t CMP3; /!< Comparator 3 source control /
ebrus	0:0a673c671a56	950	__IO uint32_t CMPFILTR3; /!< Comparator 0 pin filter set-up /
ebrus	0:0a673c671a56	951	} LPC_ACMP_Type;
ebrus	0:0a673c671a56	952
ebrus	0:0a673c671a56	953
ebrus	0:0a673c671a56	954	/* ================================================================================ */
ebrus	0:0a673c671a56	955	/* ================ INMUX ================ */
ebrus	0:0a673c671a56	956	/* ================================================================================ */
ebrus	0:0a673c671a56	957
ebrus	0:0a673c671a56	958
ebrus	0:0a673c671a56	959	/**
ebrus	0:0a673c671a56	960	* @brief Input multiplexing (INMUX) (INMUX)
ebrus	0:0a673c671a56	961	*/
ebrus	0:0a673c671a56	962
ebrus	0:0a673c671a56	963	typedef struct { /!< INMUX Structure /
ebrus	0:0a673c671a56	964	__IO uint32_t SCT0_INMUX[7]; /!< Pinmux register for SCT0 input 0 /
ebrus	0:0a673c671a56	965	__I uint32_t RESERVED0;
ebrus	0:0a673c671a56	966	__IO uint32_t SCT1_INMUX[7]; /!< Pinmux register for SCT1 input 0 /
ebrus	0:0a673c671a56	967	__I uint32_t RESERVED1;
ebrus	0:0a673c671a56	968	__IO uint32_t SCT2_INMUX[3]; /!< Pinmux register for SCT2 input 0 /
ebrus	0:0a673c671a56	969	__I uint32_t RESERVED2[5];
ebrus	0:0a673c671a56	970	__IO uint32_t SCT3_INMUX[3]; /!< Pinmux register for SCT3 input 0 /
ebrus	0:0a673c671a56	971	__I uint32_t RESERVED3[21];
ebrus	0:0a673c671a56	972	__IO uint32_t PINTSEL[8]; /!< Pin interrupt select register 0 /
ebrus	0:0a673c671a56	973	__IO uint32_t DMA_ITRIG_INMUX[18]; /!< Trigger input for DMA channel 0 select register. /
ebrus	0:0a673c671a56	974	__I uint32_t RESERVED4[14];
ebrus	0:0a673c671a56	975	__IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
ebrus	0:0a673c671a56	976	clock */
ebrus	0:0a673c671a56	977	__IO uint32_t FREQMEAS_TARGET; /!< Clock selection for frequency measurement function target clock /
ebrus	0:0a673c671a56	978	} LPC_INMUX_Type;
ebrus	0:0a673c671a56	979
ebrus	0:0a673c671a56	980
ebrus	0:0a673c671a56	981	/* ================================================================================ */
ebrus	0:0a673c671a56	982	/* ================ RTC ================ */
ebrus	0:0a673c671a56	983	/* ================================================================================ */
ebrus	0:0a673c671a56	984
ebrus	0:0a673c671a56	985
ebrus	0:0a673c671a56	986	/**
ebrus	0:0a673c671a56	987	* @brief Real-Time Clock (RTC) (RTC)
ebrus	0:0a673c671a56	988	*/
ebrus	0:0a673c671a56	989
ebrus	0:0a673c671a56	990	typedef struct { /!< RTC Structure /
ebrus	0:0a673c671a56	991	__IO uint32_t CTRL; /!< RTC control register /
ebrus	0:0a673c671a56	992	__IO uint32_t MATCH; /!< RTC match register /
ebrus	0:0a673c671a56	993	__IO uint32_t COUNT; /!< RTC counter register /
ebrus	0:0a673c671a56	994	__IO uint32_t WAKE; /!< RTC high-resolution/wake-up timer control register /
ebrus	0:0a673c671a56	995	} LPC_RTC_Type;
ebrus	0:0a673c671a56	996
ebrus	0:0a673c671a56	997
ebrus	0:0a673c671a56	998	/* ================================================================================ */
ebrus	0:0a673c671a56	999	/* ================ WWDT ================ */
ebrus	0:0a673c671a56	1000	/* ================================================================================ */
ebrus	0:0a673c671a56	1001
ebrus	0:0a673c671a56	1002
ebrus	0:0a673c671a56	1003	/**
ebrus	0:0a673c671a56	1004	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
ebrus	0:0a673c671a56	1005	*/
ebrus	0:0a673c671a56	1006
ebrus	0:0a673c671a56	1007	typedef struct { /!< WWDT Structure /
ebrus	0:0a673c671a56	1008	__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
ebrus	0:0a673c671a56	1009	and status of the Watchdog Timer. */
ebrus	0:0a673c671a56	1010	__IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
ebrus	0:0a673c671a56	1011	the time-out value. */
ebrus	0:0a673c671a56	1012	__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
ebrus	0:0a673c671a56	1013	to this register reloads the Watchdog timer with the value contained
ebrus	0:0a673c671a56	1014	in WDTC. */
ebrus	0:0a673c671a56	1015	__I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
ebrus	0:0a673c671a56	1016	the current value of the Watchdog timer. */
ebrus	0:0a673c671a56	1017	__I uint32_t RESERVED0;
ebrus	0:0a673c671a56	1018	__IO uint32_t WARNINT; /!< Watchdog Warning Interrupt compare value. /
ebrus	0:0a673c671a56	1019	__IO uint32_t WINDOW; /!< Watchdog Window compare value. /
ebrus	0:0a673c671a56	1020	} LPC_WWDT_Type;
ebrus	0:0a673c671a56	1021
ebrus	0:0a673c671a56	1022
ebrus	0:0a673c671a56	1023	/* ================================================================================ */
ebrus	0:0a673c671a56	1024	/* ================ SWM ================ */
ebrus	0:0a673c671a56	1025	/* ================================================================================ */
ebrus	0:0a673c671a56	1026
ebrus	0:0a673c671a56	1027
ebrus	0:0a673c671a56	1028	/**
ebrus	0:0a673c671a56	1029	* @brief Switch Matrix (SWM) (SWM)
ebrus	0:0a673c671a56	1030	*/
ebrus	0:0a673c671a56	1031
ebrus	0:0a673c671a56	1032	typedef struct { /!< SWM Structure /
ebrus	0:0a673c671a56	1033	union {
ebrus	0:0a673c671a56	1034	__IO uint32_t PINASSIGN[16];
ebrus	0:0a673c671a56	1035	struct {
ebrus	0:0a673c671a56	1036	__IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
ebrus	0:0a673c671a56	1037	U0_RTS, U0_CTS. */
ebrus	0:0a673c671a56	1038	__IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
ebrus	0:0a673c671a56	1039	U1_RXD, U1_RTS. */
ebrus	0:0a673c671a56	1040	__IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
ebrus	0:0a673c671a56	1041	U2_TXD, U2_RXD. */
ebrus	0:0a673c671a56	1042	__IO uint32_t PINASSIGN3; /!< Pin assign register 3. Assign movable function . /
ebrus	0:0a673c671a56	1043	__IO uint32_t PINASSIGN4; /!< Pin assign register 4. Assign movable functions /
ebrus	0:0a673c671a56	1044	__IO uint32_t PINASSIGN5; /!< Pin assign register 5. Assign movable functions /
ebrus	0:0a673c671a56	1045	__IO uint32_t PINASSIGN6; /!< Pin assign register 6. Assign movable functions /
ebrus	0:0a673c671a56	1046	__IO uint32_t PINASSIGN7; /!< Pin assign register 7. Assign movable functions /
ebrus	0:0a673c671a56	1047	__IO uint32_t PINASSIGN8; /!< Pin assign register 8. Assign movable functions /
ebrus	0:0a673c671a56	1048	__IO uint32_t PINASSIGN9; /!< Pin assign register 9. Assign movable functions /
ebrus	0:0a673c671a56	1049	__IO uint32_t PINASSIGN10; /!< Pin assign register 10. Assign movable functions /
ebrus	0:0a673c671a56	1050	__IO uint32_t PINASSIGN11; /!< Pin assign register 11. Assign movable functions /
ebrus	0:0a673c671a56	1051	__IO uint32_t PINASSIGN12; /!< Pin assign register 12. Assign movable functions /
ebrus	0:0a673c671a56	1052	__IO uint32_t PINASSIGN13; /!< Pin assign register 13. Assign movable functions /
ebrus	0:0a673c671a56	1053	__IO uint32_t PINASSIGN14; /!< Pin assign register 14. Assign movable functions /
ebrus	0:0a673c671a56	1054	__IO uint32_t PINASSIGN15; /!< Pin assign register 15. Assign movable functions /
ebrus	0:0a673c671a56	1055	};
ebrus	0:0a673c671a56	1056	};
ebrus	0:0a673c671a56	1057	__I uint32_t RESERVED0[96];
ebrus	0:0a673c671a56	1058	__IO uint32_t PINENABLE0; /!< Pin enable register 0. Enables fixed-pin functions /
ebrus	0:0a673c671a56	1059	__IO uint32_t PINENABLE1; /!< Pin enable register 0. Enables fixed-pin functions /
ebrus	0:0a673c671a56	1060	} LPC_SWM_Type;
ebrus	0:0a673c671a56	1061
ebrus	0:0a673c671a56	1062
ebrus	0:0a673c671a56	1063	/* ================================================================================ */
ebrus	0:0a673c671a56	1064	/* ================ PMU ================ */
ebrus	0:0a673c671a56	1065	/* ================================================================================ */
ebrus	0:0a673c671a56	1066
ebrus	0:0a673c671a56	1067
ebrus	0:0a673c671a56	1068	/**
ebrus	0:0a673c671a56	1069	* @brief Power Management Unit (PMU) (PMU)
ebrus	0:0a673c671a56	1070	*/
ebrus	0:0a673c671a56	1071
ebrus	0:0a673c671a56	1072	typedef struct { /!< PMU Structure /
ebrus	0:0a673c671a56	1073	__IO uint32_t PCON; /!< Power control register /
ebrus	0:0a673c671a56	1074	__IO uint32_t GPREG0; /!< General purpose register 0 /
ebrus	0:0a673c671a56	1075	__IO uint32_t GPREG1; /!< General purpose register 0 /
ebrus	0:0a673c671a56	1076	__IO uint32_t GPREG2; /!< General purpose register 0 /
ebrus	0:0a673c671a56	1077	__IO uint32_t GPREG3; /!< General purpose register 0 /
ebrus	0:0a673c671a56	1078	__IO uint32_t DPDCTRL; /!< Deep power-down control register /
ebrus	0:0a673c671a56	1079	} LPC_PMU_Type;
ebrus	0:0a673c671a56	1080
ebrus	0:0a673c671a56	1081
ebrus	0:0a673c671a56	1082	/* ================================================================================ */
ebrus	0:0a673c671a56	1083	/* ================ USART0 ================ */
ebrus	0:0a673c671a56	1084	/* ================================================================================ */
ebrus	0:0a673c671a56	1085
ebrus	0:0a673c671a56	1086
ebrus	0:0a673c671a56	1087	/**
ebrus	0:0a673c671a56	1088	* @brief USART0 (USART0)
ebrus	0:0a673c671a56	1089	*/
ebrus	0:0a673c671a56	1090
ebrus	0:0a673c671a56	1091	typedef struct { /!< USART0 Structure /
ebrus	0:0a673c671a56	1092	__IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
ebrus	0:0a673c671a56	1093	that typically are not changed during operation. */
ebrus	0:0a673c671a56	1094	__IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
ebrus	0:0a673c671a56	1095	likely to change during operation. */
ebrus	0:0a673c671a56	1096	__IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
ebrus	0:0a673c671a56	1097	here. Writing ones clears some bits in the register. Some bits
ebrus	0:0a673c671a56	1098	can be cleared by writing a 1 to them. */
ebrus	0:0a673c671a56	1099	__IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
ebrus	0:0a673c671a56	1100	interrupt enable bit for each potential USART interrupt. A complete
ebrus	0:0a673c671a56	1101	value may be read from this register. Writing a 1 to any implemented
ebrus	0:0a673c671a56	1102	bit position causes that bit to be set. */
ebrus	0:0a673c671a56	1103	__O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
ebrus	0:0a673c671a56	1104	of bits in the INTENSET register. Writing a 1 to any implemented
ebrus	0:0a673c671a56	1105	bit position causes the corresponding bit to be cleared. */
ebrus	0:0a673c671a56	1106	__I uint32_t RXDATA; /!< Receiver Data register. Contains the last character received. /
ebrus	0:0a673c671a56	1107	__I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
ebrus	0:0a673c671a56	1108	received with the current USART receive status. Allows DMA or
ebrus	0:0a673c671a56	1109	software to recover incoming data and status together. */
ebrus	0:0a673c671a56	1110	__IO uint32_t TXDATA; /!< Transmit Data register. Data to be transmitted is written here. /
ebrus	0:0a673c671a56	1111	__IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
ebrus	0:0a673c671a56	1112	value. */
ebrus	0:0a673c671a56	1113	__I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
ebrus	0:0a673c671a56	1114	enabled. */
ebrus	0:0a673c671a56	1115	} LPC_USART0_Type;
ebrus	0:0a673c671a56	1116
ebrus	0:0a673c671a56	1117
ebrus	0:0a673c671a56	1118	/* ================================================================================ */
ebrus	0:0a673c671a56	1119	/* ================ SPI0 ================ */
ebrus	0:0a673c671a56	1120	/* ================================================================================ */
ebrus	0:0a673c671a56	1121
ebrus	0:0a673c671a56	1122
ebrus	0:0a673c671a56	1123	/**
ebrus	0:0a673c671a56	1124	* @brief SPI0 (SPI0)
ebrus	0:0a673c671a56	1125	*/
ebrus	0:0a673c671a56	1126
ebrus	0:0a673c671a56	1127	typedef struct { /!< SPI0 Structure /
ebrus	0:0a673c671a56	1128	__IO uint32_t CFG; /!< SPI Configuration register /
ebrus	0:0a673c671a56	1129	__IO uint32_t DLY; /!< SPI Delay register /
ebrus	0:0a673c671a56	1130	__IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
ebrus	0:0a673c671a56	1131	to that bit position */
ebrus	0:0a673c671a56	1132	__IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
ebrus	0:0a673c671a56	1133	from this register. Writing a 1 to any implemented bit position
ebrus	0:0a673c671a56	1134	causes that bit to be set. */
ebrus	0:0a673c671a56	1135	__O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
ebrus	0:0a673c671a56	1136	position causes the corresponding bit in INTENSET to be cleared. */
ebrus	0:0a673c671a56	1137	__I uint32_t RXDAT; /!< SPI Receive Data /
ebrus	0:0a673c671a56	1138	__IO uint32_t TXDATCTL; /!< SPI Transmit Data with Control /
ebrus	0:0a673c671a56	1139	__IO uint32_t TXDAT; /!< SPI Transmit Data with Control /
ebrus	0:0a673c671a56	1140	__IO uint32_t TXCTL; /!< SPI Transmit Control /
ebrus	0:0a673c671a56	1141	__IO uint32_t DIV; /!< SPI clock Divider /
ebrus	0:0a673c671a56	1142	__I uint32_t INTSTAT; /!< SPI Interrupt Status /
ebrus	0:0a673c671a56	1143	} LPC_SPI0_Type;
ebrus	0:0a673c671a56	1144
ebrus	0:0a673c671a56	1145
ebrus	0:0a673c671a56	1146	/* ================================================================================ */
ebrus	0:0a673c671a56	1147	/* ================ I2C0 ================ */
ebrus	0:0a673c671a56	1148	/* ================================================================================ */
ebrus	0:0a673c671a56	1149
ebrus	0:0a673c671a56	1150
ebrus	0:0a673c671a56	1151	/**
ebrus	0:0a673c671a56	1152	* @brief I2C-bus interface (I2C0)
ebrus	0:0a673c671a56	1153	*/
ebrus	0:0a673c671a56	1154
ebrus	0:0a673c671a56	1155	typedef struct { /!< I2C0 Structure /
ebrus	0:0a673c671a56	1156	__IO uint32_t CFG; /!< Configuration for shared functions. /
ebrus	0:0a673c671a56	1157	__IO uint32_t STAT; /!< Status register for Master, Slave, and Monitor functions. /
ebrus	0:0a673c671a56	1158	__IO uint32_t INTENSET; /!< Interrupt Enable Set and read register. /
ebrus	0:0a673c671a56	1159	__O uint32_t INTENCLR; /!< Interrupt Enable Clear register. /
ebrus	0:0a673c671a56	1160	__IO uint32_t TIMEOUT; /!< Time-out value register. /
ebrus	0:0a673c671a56	1161	__IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
ebrus	0:0a673c671a56	1162	what time increments are used for the MSTTIME and SLVTIME registers. */
ebrus	0:0a673c671a56	1163	__I uint32_t INTSTAT; /!< Interrupt Status register for Master, Slave, and Monitor functions. /
ebrus	0:0a673c671a56	1164	__I uint32_t RESERVED0;
ebrus	0:0a673c671a56	1165	__IO uint32_t MSTCTL; /!< Master control register. /
ebrus	0:0a673c671a56	1166	__IO uint32_t MSTTIME; /!< Master timing configuration. /
ebrus	0:0a673c671a56	1167	__IO uint32_t MSTDAT; /!< Combined Master receiver and transmitter data register. /
ebrus	0:0a673c671a56	1168	__I uint32_t RESERVED1[5];
ebrus	0:0a673c671a56	1169	__IO uint32_t SLVCTL; /!< Slave control register. /
ebrus	0:0a673c671a56	1170	__IO uint32_t SLVDAT; /!< Combined Slave receiver and transmitter data register. /
ebrus	0:0a673c671a56	1171	__IO uint32_t SLVADR0; /!< Slave address 0. /
ebrus	0:0a673c671a56	1172	__IO uint32_t SLVADR1; /!< Slave address 0. /
ebrus	0:0a673c671a56	1173	__IO uint32_t SLVADR2; /!< Slave address 0. /
ebrus	0:0a673c671a56	1174	__IO uint32_t SLVADR3; /!< Slave address 0. /
ebrus	0:0a673c671a56	1175	__IO uint32_t SLVQUAL0; /!< Slave Qualification for address 0. /
ebrus	0:0a673c671a56	1176	__I uint32_t RESERVED2[9];
ebrus	0:0a673c671a56	1177	__I uint32_t MONRXDAT; /!< Monitor receiver data register. /
ebrus	0:0a673c671a56	1178	} LPC_I2C0_Type;
ebrus	0:0a673c671a56	1179
ebrus	0:0a673c671a56	1180
ebrus	0:0a673c671a56	1181	/* ================================================================================ */
ebrus	0:0a673c671a56	1182	/* ================ QEI ================ */
ebrus	0:0a673c671a56	1183	/* ================================================================================ */
ebrus	0:0a673c671a56	1184
ebrus	0:0a673c671a56	1185
ebrus	0:0a673c671a56	1186	/**
ebrus	0:0a673c671a56	1187	* @brief Quadrature Encoder Interface (QEI) (QEI)
ebrus	0:0a673c671a56	1188	*/
ebrus	0:0a673c671a56	1189
ebrus	0:0a673c671a56	1190	typedef struct { /!< QEI Structure /
ebrus	0:0a673c671a56	1191	__O uint32_t CON; /!< Control register /
ebrus	0:0a673c671a56	1192	__I uint32_t STAT; /!< Encoder status register /
ebrus	0:0a673c671a56	1193	__IO uint32_t CONF; /!< Configuration register /
ebrus	0:0a673c671a56	1194	__I uint32_t POS; /!< Position register /
ebrus	0:0a673c671a56	1195	__IO uint32_t MAXPOS; /!< Maximum position register /
ebrus	0:0a673c671a56	1196	__IO uint32_t CMPOS0; /!< position compare register 0 /
ebrus	0:0a673c671a56	1197	__IO uint32_t CMPOS1; /!< position compare register 1 /
ebrus	0:0a673c671a56	1198	__IO uint32_t CMPOS2; /!< position compare register 2 /
ebrus	0:0a673c671a56	1199	__I uint32_t INXCNT; /!< Index count register /
ebrus	0:0a673c671a56	1200	__IO uint32_t INXCMP0; /!< Index compare register 0 /
ebrus	0:0a673c671a56	1201	__IO uint32_t LOAD; /!< Velocity timer reload register /
ebrus	0:0a673c671a56	1202	__I uint32_t TIME; /!< Velocity timer register /
ebrus	0:0a673c671a56	1203	__I uint32_t VEL; /!< Velocity counter register /
ebrus	0:0a673c671a56	1204	__I uint32_t CAP; /!< Velocity capture register /
ebrus	0:0a673c671a56	1205	__IO uint32_t VELCOMP; /!< Velocity compare register /
ebrus	0:0a673c671a56	1206	__IO uint32_t FILTERPHA; /!< Digital filter register on input phase A (QEI_A) /
ebrus	0:0a673c671a56	1207	__IO uint32_t FILTERPHB; /!< Digital filter register on input phase B (QEI_B) /
ebrus	0:0a673c671a56	1208	__IO uint32_t FILTERINX; /!< Digital filter register on input index (QEI_IDX) /
ebrus	0:0a673c671a56	1209	__IO uint32_t WINDOW; /!< Index acceptance window register /
ebrus	0:0a673c671a56	1210	__IO uint32_t INXCMP1; /!< Index compare register 1 /
ebrus	0:0a673c671a56	1211	__IO uint32_t INXCMP2; /!< Index compare register 2 /
ebrus	0:0a673c671a56	1212	__I uint32_t RESERVED0[993];
ebrus	0:0a673c671a56	1213	__O uint32_t IEC; /!< Interrupt enable clear register /
ebrus	0:0a673c671a56	1214	__O uint32_t IES; /!< Interrupt enable set register /
ebrus	0:0a673c671a56	1215	__I uint32_t INTSTAT; /!< Interrupt status register /
ebrus	0:0a673c671a56	1216	__O uint32_t IE; /!< Interrupt enable clear register /
ebrus	0:0a673c671a56	1217	__O uint32_t CLR; /!< Interrupt status clear register /
ebrus	0:0a673c671a56	1218	__O uint32_t SET; /!< Interrupt status set register /
ebrus	0:0a673c671a56	1219	} LPC_QEI_Type;
ebrus	0:0a673c671a56	1220
ebrus	0:0a673c671a56	1221
ebrus	0:0a673c671a56	1222	/* ================================================================================ */
ebrus	0:0a673c671a56	1223	/* ================ SYSCON ================ */
ebrus	0:0a673c671a56	1224	/* ================================================================================ */
ebrus	0:0a673c671a56	1225
ebrus	0:0a673c671a56	1226
ebrus	0:0a673c671a56	1227	/**
ebrus	0:0a673c671a56	1228	* @brief System configuration (SYSCON) (SYSCON)
ebrus	0:0a673c671a56	1229	*/
ebrus	0:0a673c671a56	1230
ebrus	0:0a673c671a56	1231	typedef struct { /!< SYSCON Structure /
ebrus	0:0a673c671a56	1232	__IO uint32_t SYSMEMREMAP; /!< System memory remap /
ebrus	0:0a673c671a56	1233	__I uint32_t RESERVED0[4];
ebrus	0:0a673c671a56	1234	__IO uint32_t SYSTCKCAL; /!< System tick counter calibration /
ebrus	0:0a673c671a56	1235	__I uint32_t RESERVED1;
ebrus	0:0a673c671a56	1236	__IO uint32_t NMISRC; /!< NMI Source Control /
ebrus	0:0a673c671a56	1237	__I uint32_t RESERVED2[8];
ebrus	0:0a673c671a56	1238	__IO uint32_t SYSRSTSTAT; /!< System reset status register /
ebrus	0:0a673c671a56	1239	__IO uint32_t PRESETCTRL0; /!< Peripheral reset control 0 /
ebrus	0:0a673c671a56	1240	__IO uint32_t PRESETCTRL1; /!< Peripheral reset control 1 /
ebrus	0:0a673c671a56	1241	__I uint32_t PIOPORCAP0; /!< POR captured PIO status 0 /
ebrus	0:0a673c671a56	1242	__I uint32_t PIOPORCAP1; /!< POR captured PIO status 1 /
ebrus	0:0a673c671a56	1243	__I uint32_t PIOPORCAP2; /!< POR captured PIO status 2 /
ebrus	0:0a673c671a56	1244	__I uint32_t RESERVED3[10];
ebrus	0:0a673c671a56	1245	__IO uint32_t MAINCLKSELA; /!< Main clock source select A /
ebrus	0:0a673c671a56	1246	__IO uint32_t MAINCLKSELB; /!< Main clock source select B /
ebrus	0:0a673c671a56	1247	__IO uint32_t USBCLKSEL; /!< USB clock source select /
ebrus	0:0a673c671a56	1248	__IO uint32_t ADCASYNCCLKSEL; /!< ADC asynchronous clock source select /
ebrus	0:0a673c671a56	1249	__I uint32_t RESERVED4;
ebrus	0:0a673c671a56	1250	__IO uint32_t CLKOUTSELA; /!< CLKOUT clock source select A /
ebrus	0:0a673c671a56	1251	__IO uint32_t CLKOUTSELB; /!< CLKOUT clock source select B /
ebrus	0:0a673c671a56	1252	__I uint32_t RESERVED5;
ebrus	0:0a673c671a56	1253	__IO uint32_t SYSPLLCLKSEL; /!< System PLL clock source select /
ebrus	0:0a673c671a56	1254	__IO uint32_t USBPLLCLKSEL; /!< USB PLL clock source select /
ebrus	0:0a673c671a56	1255	__IO uint32_t SCTPLLCLKSEL; /!< SCT PLL clock source select /
ebrus	0:0a673c671a56	1256	__I uint32_t RESERVED6[5];
ebrus	0:0a673c671a56	1257	__IO uint32_t SYSAHBCLKDIV; /!< System clock divider /
ebrus	0:0a673c671a56	1258	__IO uint32_t SYSAHBCLKCTRL0; /!< System clock control 0 /
ebrus	0:0a673c671a56	1259	__IO uint32_t SYSAHBCLKCTRL1; /!< System clock control 1 /
ebrus	0:0a673c671a56	1260	__IO uint32_t SYSTICKCLKDIV; /!< SYSTICK clock divider /
ebrus	0:0a673c671a56	1261	__IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
ebrus	0:0a673c671a56	1262	baud rate generator. */
ebrus	0:0a673c671a56	1263	__IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
ebrus	0:0a673c671a56	1264	filter */
ebrus	0:0a673c671a56	1265	__IO uint32_t TRACECLKDIV; /!< ARM trace clock divider /
ebrus	0:0a673c671a56	1266	__I uint32_t RESERVED7[4];
ebrus	0:0a673c671a56	1267	__IO uint32_t USBCLKDIV; /!< USB clock divider /
ebrus	0:0a673c671a56	1268	__IO uint32_t ADCASYNCCLKDIV; /!< Asynchronous ADC clock divider /
ebrus	0:0a673c671a56	1269	__I uint32_t RESERVED8;
ebrus	0:0a673c671a56	1270	__IO uint32_t CLKOUTDIV; /!< CLKOUT clock divider /
ebrus	0:0a673c671a56	1271	__I uint32_t RESERVED9[11];
ebrus	0:0a673c671a56	1272	__IO uint32_t FRGCTRL; /!< USART fractional baud rate generator control /
ebrus	0:0a673c671a56	1273	__IO uint32_t USBCLKCTRL; /!< USB clock control /
ebrus	0:0a673c671a56	1274	__IO uint32_t USBCLKST; /!< USB clock status /
ebrus	0:0a673c671a56	1275	__I uint32_t RESERVED10[19];
ebrus	0:0a673c671a56	1276	__IO uint32_t BODCTRL; /!< Brown-Out Detect /
ebrus	0:0a673c671a56	1277	__I uint32_t RESERVED11;
ebrus	0:0a673c671a56	1278	__IO uint32_t SYSOSCCTRL; /!< System oscillator control /
ebrus	0:0a673c671a56	1279	__I uint32_t RESERVED12;
ebrus	0:0a673c671a56	1280	__IO uint32_t RTCOSCCTRL; /!< RTC oscillator control /
ebrus	0:0a673c671a56	1281	__I uint32_t RESERVED13;
ebrus	0:0a673c671a56	1282	__IO uint32_t SYSPLLCTRL; /!< System PLL control /
ebrus	0:0a673c671a56	1283	__I uint32_t SYSPLLSTAT; /!< System PLL status /
ebrus	0:0a673c671a56	1284	__IO uint32_t USBPLLCTRL; /!< USB PLL control /
ebrus	0:0a673c671a56	1285	__I uint32_t USBPLLSTAT; /!< USB PLL status /
ebrus	0:0a673c671a56	1286	__IO uint32_t SCTPLLCTRL; /!< SCT PLL control /
ebrus	0:0a673c671a56	1287	__I uint32_t SCTPLLSTAT; /!< SCT PLL status /
ebrus	0:0a673c671a56	1288	__I uint32_t RESERVED14[21];
ebrus	0:0a673c671a56	1289	__IO uint32_t PDAWAKECFG; /!< Power-down states for wake-up from deep-sleep /
ebrus	0:0a673c671a56	1290	__IO uint32_t PDRUNCFG; /!< Power configuration register /
ebrus	0:0a673c671a56	1291	__I uint32_t RESERVED15[3];
ebrus	0:0a673c671a56	1292	__IO uint32_t STARTERP0; /!< Start logic 0 wake-up enable register /
ebrus	0:0a673c671a56	1293	__IO uint32_t STARTERP1; /!< Start logic 1 wake-up enable register /
ebrus	0:0a673c671a56	1294	} LPC_SYSCON_Type;
ebrus	0:0a673c671a56	1295
ebrus	0:0a673c671a56	1296
ebrus	0:0a673c671a56	1297	/* ================================================================================ */
ebrus	0:0a673c671a56	1298	/* ================ MRT ================ */
ebrus	0:0a673c671a56	1299	/* ================================================================================ */
ebrus	0:0a673c671a56	1300
ebrus	0:0a673c671a56	1301
ebrus	0:0a673c671a56	1302	/**
ebrus	0:0a673c671a56	1303	* @brief Multi-Rate Timer (MRT) (MRT)
ebrus	0:0a673c671a56	1304	*/
ebrus	0:0a673c671a56	1305
ebrus	0:0a673c671a56	1306	typedef struct { /!< MRT Structure /
ebrus	0:0a673c671a56	1307	__IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
ebrus	0:0a673c671a56	1308	the TIMER0 register. */
ebrus	0:0a673c671a56	1309	__I uint32_t TIMER0; /!< MRT0 Timer register. This register reads the value of the down-counter. /
ebrus	0:0a673c671a56	1310	__IO uint32_t CTRL0; /!< MRT0 Control register. This register controls the MRT0 modes. /
ebrus	0:0a673c671a56	1311	__IO uint32_t STAT0; /!< MRT0 Status register. /
ebrus	0:0a673c671a56	1312	__IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
ebrus	0:0a673c671a56	1313	the TIMER0 register. */
ebrus	0:0a673c671a56	1314	__I uint32_t TIMER1; /!< MRT0 Timer register. This register reads the value of the down-counter. /
ebrus	0:0a673c671a56	1315	__IO uint32_t CTRL1; /!< MRT0 Control register. This register controls the MRT0 modes. /
ebrus	0:0a673c671a56	1316	__IO uint32_t STAT1; /!< MRT0 Status register. /
ebrus	0:0a673c671a56	1317	__IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
ebrus	0:0a673c671a56	1318	the TIMER0 register. */
ebrus	0:0a673c671a56	1319	__I uint32_t TIMER2; /!< MRT0 Timer register. This register reads the value of the down-counter. /
ebrus	0:0a673c671a56	1320	__IO uint32_t CTRL2; /!< MRT0 Control register. This register controls the MRT0 modes. /
ebrus	0:0a673c671a56	1321	__IO uint32_t STAT2; /!< MRT0 Status register. /
ebrus	0:0a673c671a56	1322	__IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
ebrus	0:0a673c671a56	1323	the TIMER0 register. */
ebrus	0:0a673c671a56	1324	__I uint32_t TIMER3; /!< MRT0 Timer register. This register reads the value of the down-counter. /
ebrus	0:0a673c671a56	1325	__IO uint32_t CTRL3; /!< MRT0 Control register. This register controls the MRT0 modes. /
ebrus	0:0a673c671a56	1326	__IO uint32_t STAT3; /!< MRT0 Status register. /
ebrus	0:0a673c671a56	1327	__I uint32_t RESERVED0[45];
ebrus	0:0a673c671a56	1328	__I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
ebrus	0:0a673c671a56	1329	first idle channel. */
ebrus	0:0a673c671a56	1330	__IO uint32_t IRQ_FLAG; /!< Global interrupt flag register /
ebrus	0:0a673c671a56	1331	} LPC_MRT_Type;
ebrus	0:0a673c671a56	1332
ebrus	0:0a673c671a56	1333
ebrus	0:0a673c671a56	1334	/* ================================================================================ */
ebrus	0:0a673c671a56	1335	/* ================ PINT ================ */
ebrus	0:0a673c671a56	1336	/* ================================================================================ */
ebrus	0:0a673c671a56	1337
ebrus	0:0a673c671a56	1338
ebrus	0:0a673c671a56	1339	/**
ebrus	0:0a673c671a56	1340	* @brief Pin interruptand pattern match (PINT) (PINT)
ebrus	0:0a673c671a56	1341	*/
ebrus	0:0a673c671a56	1342
ebrus	0:0a673c671a56	1343	typedef struct { /!< PINT Structure /
ebrus	0:0a673c671a56	1344	__IO uint32_t ISEL; /!< Pin Interrupt Mode register /
ebrus	0:0a673c671a56	1345	__IO uint32_t IENR; /!< Pin interrupt level or rising edge interrupt enable register /
ebrus	0:0a673c671a56	1346	__O uint32_t SIENR; /!< Pin interrupt level or rising edge interrupt set register /
ebrus	0:0a673c671a56	1347	__O uint32_t CIENR; /!< Pin interrupt level (rising edge interrupt) clear register /
ebrus	0:0a673c671a56	1348	__IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
ebrus	0:0a673c671a56	1349	register */
ebrus	0:0a673c671a56	1350	__O uint32_t SIENF; /!< Pin interrupt active level or falling edge interrupt set register /
ebrus	0:0a673c671a56	1351	__O uint32_t CIENF; /!< Pin interrupt active level or falling edge interrupt clear register /
ebrus	0:0a673c671a56	1352	__IO uint32_t RISE; /!< Pin interrupt rising edge register /
ebrus	0:0a673c671a56	1353	__IO uint32_t FALL; /!< Pin interrupt falling edge register /
ebrus	0:0a673c671a56	1354	__IO uint32_t IST; /!< Pin interrupt status register /
ebrus	0:0a673c671a56	1355	__IO uint32_t PMCTRL; /!< Pattern match interrupt control register /
ebrus	0:0a673c671a56	1356	__IO uint32_t PMSRC; /!< Pattern match interrupt bit-slice source register /
ebrus	0:0a673c671a56	1357	__IO uint32_t PMCFG; /!< Pattern match interrupt bit slice configuration register /
ebrus	0:0a673c671a56	1358	} LPC_PINT_Type;
ebrus	0:0a673c671a56	1359
ebrus	0:0a673c671a56	1360
ebrus	0:0a673c671a56	1361	/* ================================================================================ */
ebrus	0:0a673c671a56	1362	/* ================ GINT0 ================ */
ebrus	0:0a673c671a56	1363	/* ================================================================================ */
ebrus	0:0a673c671a56	1364
ebrus	0:0a673c671a56	1365
ebrus	0:0a673c671a56	1366	/**
ebrus	0:0a673c671a56	1367	* @brief Group interrupt 0/1 (GINT0/1) (GINT0)
ebrus	0:0a673c671a56	1368	*/
ebrus	0:0a673c671a56	1369
ebrus	0:0a673c671a56	1370	typedef struct { /!< GINT0 Structure /
ebrus	0:0a673c671a56	1371	__IO uint32_t CTRL; /!< GPIO grouped interrupt control register /
ebrus	0:0a673c671a56	1372	__I uint32_t RESERVED0[7];
ebrus	0:0a673c671a56	1373	__IO uint32_t PORT_POL[3]; /!< GPIO grouped interrupt port 0 polarity register /
ebrus	0:0a673c671a56	1374	__I uint32_t RESERVED1[5];
ebrus	0:0a673c671a56	1375	__IO uint32_t PORT_ENA[3]; /!< GPIO grouped interrupt port 0 enable register /
ebrus	0:0a673c671a56	1376	} LPC_GINT0_Type;
ebrus	0:0a673c671a56	1377
ebrus	0:0a673c671a56	1378
ebrus	0:0a673c671a56	1379	/* ================================================================================ */
ebrus	0:0a673c671a56	1380	/* ================ RIT ================ */
ebrus	0:0a673c671a56	1381	/* ================================================================================ */
ebrus	0:0a673c671a56	1382
ebrus	0:0a673c671a56	1383
ebrus	0:0a673c671a56	1384	/**
ebrus	0:0a673c671a56	1385	* @brief Repetitive Interrupt Timer (RIT) (RIT)
ebrus	0:0a673c671a56	1386	*/
ebrus	0:0a673c671a56	1387
ebrus	0:0a673c671a56	1388	typedef struct { /!< RIT Structure /
ebrus	0:0a673c671a56	1389	__IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
ebrus	0:0a673c671a56	1390	value. */
ebrus	0:0a673c671a56	1391	__IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
ebrus	0:0a673c671a56	1392	value. A 1 written to any bit will force a compare on the corresponding
ebrus	0:0a673c671a56	1393	bit of the counter and compare register. */
ebrus	0:0a673c671a56	1394	__IO uint32_t CTRL; /!< Control register. /
ebrus	0:0a673c671a56	1395	__IO uint32_t COUNTER; /!< Counter LSB register. 32 LSBs of the counter. /
ebrus	0:0a673c671a56	1396	__IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
ebrus	0:0a673c671a56	1397	value. */
ebrus	0:0a673c671a56	1398	__IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
ebrus	0:0a673c671a56	1399	value. A 1 written to any bit will force a compare on the corresponding
ebrus	0:0a673c671a56	1400	bit of the counter and compare register. */
ebrus	0:0a673c671a56	1401	__I uint32_t RESERVED0;
ebrus	0:0a673c671a56	1402	__IO uint32_t COUNTER_H; /!< Counter MSB register. 16 MSBs of the counter. /
ebrus	0:0a673c671a56	1403	} LPC_RIT_Type;
ebrus	0:0a673c671a56	1404
ebrus	0:0a673c671a56	1405
ebrus	0:0a673c671a56	1406	/* ================================================================================ */
ebrus	0:0a673c671a56	1407	/* ================ SCTIPU ================ */
ebrus	0:0a673c671a56	1408	/* ================================================================================ */
ebrus	0:0a673c671a56	1409
ebrus	0:0a673c671a56	1410
ebrus	0:0a673c671a56	1411	/**
ebrus	0:0a673c671a56	1412	* @brief SCT Input Processing Unit (IPU) (SCTIPU)
ebrus	0:0a673c671a56	1413	*/
ebrus	0:0a673c671a56	1414
ebrus	0:0a673c671a56	1415	typedef struct { /!< SCTIPU Structure /
ebrus	0:0a673c671a56	1416	__IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
ebrus	0:0a673c671a56	1417	latch/sample-enable mux selects, and sample overrride bits for
ebrus	0:0a673c671a56	1418	the SAMPLE module. */
ebrus	0:0a673c671a56	1419	__I uint32_t RESERVED0[7];
ebrus	0:0a673c671a56	1420	__IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
ebrus	0:0a673c671a56	1421	to ORed Abort Output 0. */
ebrus	0:0a673c671a56	1422	__IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
ebrus	0:0a673c671a56	1423	input source caused abort output 0. */
ebrus	0:0a673c671a56	1424	__I uint32_t RESERVED1[6];
ebrus	0:0a673c671a56	1425	__IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
ebrus	0:0a673c671a56	1426	to ORed Abort Output 0. */
ebrus	0:0a673c671a56	1427	__IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
ebrus	0:0a673c671a56	1428	input source caused abort output 0. */
ebrus	0:0a673c671a56	1429	__I uint32_t RESERVED2[6];
ebrus	0:0a673c671a56	1430	__IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
ebrus	0:0a673c671a56	1431	to ORed Abort Output 0. */
ebrus	0:0a673c671a56	1432	__IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
ebrus	0:0a673c671a56	1433	input source caused abort output 0. */
ebrus	0:0a673c671a56	1434	__I uint32_t RESERVED3[6];
ebrus	0:0a673c671a56	1435	__IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
ebrus	0:0a673c671a56	1436	to ORed Abort Output 0. */
ebrus	0:0a673c671a56	1437	__IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
ebrus	0:0a673c671a56	1438	input source caused abort output 0. */
ebrus	0:0a673c671a56	1439	} LPC_SCTIPU_Type;
ebrus	0:0a673c671a56	1440
ebrus	0:0a673c671a56	1441
ebrus	0:0a673c671a56	1442	/* ================================================================================ */
ebrus	0:0a673c671a56	1443	/* ================ FLASHCTRL ================ */
ebrus	0:0a673c671a56	1444	/* ================================================================================ */
ebrus	0:0a673c671a56	1445
ebrus	0:0a673c671a56	1446
ebrus	0:0a673c671a56	1447	/**
ebrus	0:0a673c671a56	1448	* @brief Flash controller (FLASHCTRL)
ebrus	0:0a673c671a56	1449	*/
ebrus	0:0a673c671a56	1450
ebrus	0:0a673c671a56	1451	typedef struct { /!< FLASHCTRL Structure /
ebrus	0:0a673c671a56	1452	__I uint32_t RESERVED0[8];
ebrus	0:0a673c671a56	1453	__IO uint32_t FMSSTART; /!< Signature start address register /
ebrus	0:0a673c671a56	1454	__IO uint32_t FMSSTOP; /!< Signature stop-address register /
ebrus	0:0a673c671a56	1455	__I uint32_t RESERVED1;
ebrus	0:0a673c671a56	1456	__I uint32_t FMSW0; /!< Signature word /
ebrus	0:0a673c671a56	1457	} LPC_FLASHCTRL_Type;
ebrus	0:0a673c671a56	1458
ebrus	0:0a673c671a56	1459
ebrus	0:0a673c671a56	1460	/* ================================================================================ */
ebrus	0:0a673c671a56	1461	/* ================ C_CAN0 ================ */
ebrus	0:0a673c671a56	1462	/* ================================================================================ */
ebrus	0:0a673c671a56	1463
ebrus	0:0a673c671a56	1464
ebrus	0:0a673c671a56	1465	/**
ebrus	0:0a673c671a56	1466	* @brief Controller Area Network C_CAN0 (C_CAN0)
ebrus	0:0a673c671a56	1467	*/
ebrus	0:0a673c671a56	1468
ebrus	0:0a673c671a56	1469	typedef struct { /!< C_CAN0 Structure /
ebrus	0:0a673c671a56	1470	__IO uint32_t CANCNTL; /!< CAN control /
ebrus	0:0a673c671a56	1471	__IO uint32_t CANSTAT; /!< Status register /
ebrus	0:0a673c671a56	1472	__I uint32_t CANEC; /!< Error counter /
ebrus	0:0a673c671a56	1473	__IO uint32_t CANBT; /!< Bit timing register /
ebrus	0:0a673c671a56	1474	__I uint32_t CANINT; /!< Interrupt register /
ebrus	0:0a673c671a56	1475	__IO uint32_t CANTEST; /!< Test register /
ebrus	0:0a673c671a56	1476	__IO uint32_t CANBRPE; /!< Baud rate prescaler extension register /
ebrus	0:0a673c671a56	1477	__I uint32_t RESERVED0;
ebrus	0:0a673c671a56	1478	__IO uint32_t CANIF1_CMDREQ; /!< Message interface 1 command request /
ebrus	0:0a673c671a56	1479
ebrus	0:0a673c671a56	1480	union {
ebrus	0:0a673c671a56	1481	__IO uint32_t CANIF1_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
ebrus	0:0a673c671a56	1482	__IO uint32_t CANIF1_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
ebrus	0:0a673c671a56	1483	};
ebrus	0:0a673c671a56	1484	__IO uint32_t CANIF1_MSK1; /!< Message interface 1 mask 1 /
ebrus	0:0a673c671a56	1485	__IO uint32_t CANIF1_MSK2; /!< Message interface 1 mask 2 /
ebrus	0:0a673c671a56	1486	__IO uint32_t CANIF1_ARB1; /!< Message interface 1 arbitration 1 /
ebrus	0:0a673c671a56	1487	__IO uint32_t CANIF1_ARB2; /!< Message interface 1 arbitration 2 /
ebrus	0:0a673c671a56	1488	__IO uint32_t CANIF1_MCTRL; /!< Message interface 1 message control /
ebrus	0:0a673c671a56	1489	__IO uint32_t CANIF1_DA1; /!< Message interface 1 data A1 /
ebrus	0:0a673c671a56	1490	__IO uint32_t CANIF1_DA2; /!< Message interface 1 data A2 /
ebrus	0:0a673c671a56	1491	__IO uint32_t CANIF1_DB1; /!< Message interface 1 data B1 /
ebrus	0:0a673c671a56	1492	__IO uint32_t CANIF1_DB2; /!< Message interface 1 data B2 /
ebrus	0:0a673c671a56	1493	__I uint32_t RESERVED1[13];
ebrus	0:0a673c671a56	1494	__IO uint32_t CANIF2_CMDREQ; /!< Message interface 1 command request /
ebrus	0:0a673c671a56	1495
ebrus	0:0a673c671a56	1496	union {
ebrus	0:0a673c671a56	1497	__IO uint32_t CANIF2_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
ebrus	0:0a673c671a56	1498	__IO uint32_t CANIF2_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
ebrus	0:0a673c671a56	1499	};
ebrus	0:0a673c671a56	1500	__IO uint32_t CANIF2_MSK1; /!< Message interface 1 mask 1 /
ebrus	0:0a673c671a56	1501	__IO uint32_t CANIF2_MSK2; /!< Message interface 1 mask 2 /
ebrus	0:0a673c671a56	1502	__IO uint32_t CANIF2_ARB1; /!< Message interface 1 arbitration 1 /
ebrus	0:0a673c671a56	1503	__IO uint32_t CANIF2_ARB2; /!< Message interface 1 arbitration 2 /
ebrus	0:0a673c671a56	1504	__IO uint32_t CANIF2_MCTRL; /!< Message interface 1 message control /
ebrus	0:0a673c671a56	1505	__IO uint32_t CANIF2_DA1; /!< Message interface 2 data A1 /
ebrus	0:0a673c671a56	1506	__IO uint32_t CANIF2_DA2; /!< Message interface 2 data A2 /
ebrus	0:0a673c671a56	1507	__IO uint32_t CANIF2_DB1; /!< Message interface 2 data B1 /
ebrus	0:0a673c671a56	1508	__IO uint32_t CANIF2_DB2; /!< Message interface 2 data B2 /
ebrus	0:0a673c671a56	1509	__I uint32_t RESERVED2[21];
ebrus	0:0a673c671a56	1510	__I uint32_t CANTXREQ1; /!< Transmission request 1 /
ebrus	0:0a673c671a56	1511	__I uint32_t CANTXREQ2; /!< Transmission request 2 /
ebrus	0:0a673c671a56	1512	__I uint32_t RESERVED3[6];
ebrus	0:0a673c671a56	1513	__I uint32_t CANND1; /!< New data 1 /
ebrus	0:0a673c671a56	1514	__I uint32_t CANND2; /!< New data 2 /
ebrus	0:0a673c671a56	1515	__I uint32_t RESERVED4[6];
ebrus	0:0a673c671a56	1516	__I uint32_t CANIR1; /!< Interrupt pending 1 /
ebrus	0:0a673c671a56	1517	__I uint32_t CANIR2; /!< Interrupt pending 2 /
ebrus	0:0a673c671a56	1518	__I uint32_t RESERVED5[6];
ebrus	0:0a673c671a56	1519	__I uint32_t CANMSGV1; /!< Message valid 1 /
ebrus	0:0a673c671a56	1520	__I uint32_t CANMSGV2; /!< Message valid 2 /
ebrus	0:0a673c671a56	1521	__I uint32_t RESERVED6[6];
ebrus	0:0a673c671a56	1522	__IO uint32_t CANCLKDIV; /!< Can clock divider register /
ebrus	0:0a673c671a56	1523	} LPC_C_CAN0_Type;
ebrus	0:0a673c671a56	1524
ebrus	0:0a673c671a56	1525
ebrus	0:0a673c671a56	1526	/* ================================================================================ */
ebrus	0:0a673c671a56	1527	/* ================ IOCON ================ */
ebrus	0:0a673c671a56	1528	/* ================================================================================ */
ebrus	0:0a673c671a56	1529
ebrus	0:0a673c671a56	1530
ebrus	0:0a673c671a56	1531	/**
ebrus	0:0a673c671a56	1532	* @brief I/O pin configuration (IOCON) (IOCON)
ebrus	0:0a673c671a56	1533	*/
ebrus	0:0a673c671a56	1534
ebrus	0:0a673c671a56	1535	typedef struct { /!< IOCON Structure /
ebrus	0:0a673c671a56	1536	__IO uint32_t PIO0_0; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1537	__IO uint32_t PIO0_1; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1538	__IO uint32_t PIO0_2; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1539	__IO uint32_t PIO0_3; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1540	__IO uint32_t PIO0_4; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1541	__IO uint32_t PIO0_5; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1542	__IO uint32_t PIO0_6; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1543	__IO uint32_t PIO0_7; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1544	__IO uint32_t PIO0_8; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1545	__IO uint32_t PIO0_9; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1546	__IO uint32_t PIO0_10; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1547	__IO uint32_t PIO0_11; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1548	__IO uint32_t PIO0_12; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1549	__IO uint32_t PIO0_13; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1550	__IO uint32_t PIO0_14; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1551	__IO uint32_t PIO0_15; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1552	__IO uint32_t PIO0_16; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1553	__IO uint32_t PIO0_17; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1554	__IO uint32_t PIO0_18; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1555	__IO uint32_t PIO0_19; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1556	__IO uint32_t PIO0_20; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1557	__IO uint32_t PIO0_21; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
ebrus	0:0a673c671a56	1558	__IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
ebrus	0:0a673c671a56	1559	the I2C-bus SCL function. */
ebrus	0:0a673c671a56	1560	__IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
ebrus	0:0a673c671a56	1561	the I2C-bus SCL function. */
ebrus	0:0a673c671a56	1562	__IO uint32_t PIO0_24; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
ebrus	0:0a673c671a56	1563	__IO uint32_t PIO0_25; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
ebrus	0:0a673c671a56	1564	__IO uint32_t PIO0_26; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
ebrus	0:0a673c671a56	1565	__IO uint32_t PIO0_27; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
ebrus	0:0a673c671a56	1566	__IO uint32_t PIO0_28; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
ebrus	0:0a673c671a56	1567	__IO uint32_t PIO0_29; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
ebrus	0:0a673c671a56	1568	__IO uint32_t PIO0_30; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
ebrus	0:0a673c671a56	1569	__IO uint32_t PIO0_31; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
ebrus	0:0a673c671a56	1570	__IO uint32_t PIO1_0; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1571	__IO uint32_t PIO1_1; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1572	__IO uint32_t PIO1_2; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1573	__IO uint32_t PIO1_3; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1574	__IO uint32_t PIO1_4; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1575	__IO uint32_t PIO1_5; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1576	__IO uint32_t PIO1_6; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1577	__IO uint32_t PIO1_7; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1578	__IO uint32_t PIO1_8; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1579	__IO uint32_t PIO1_9; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1580	__IO uint32_t PIO1_10; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1581	__IO uint32_t PIO1_11; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1582	__IO uint32_t PIO1_12; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1583	__IO uint32_t PIO1_13; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1584	__IO uint32_t PIO1_14; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1585	__IO uint32_t PIO1_15; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1586	__IO uint32_t PIO1_16; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1587	__IO uint32_t PIO1_17; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1588	__IO uint32_t PIO1_18; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1589	__IO uint32_t PIO1_19; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1590	__IO uint32_t PIO1_20; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1591	__IO uint32_t PIO1_21; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1592	__IO uint32_t PIO1_22; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1593	__IO uint32_t PIO1_23; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1594	__IO uint32_t PIO1_24; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1595	__IO uint32_t PIO1_25; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1596	__IO uint32_t PIO1_26; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1597	__IO uint32_t PIO1_27; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1598	__IO uint32_t PIO1_28; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1599	__IO uint32_t PIO1_29; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1600	__IO uint32_t PIO1_30; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1601	__IO uint32_t PIO1_31; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
ebrus	0:0a673c671a56	1602	__IO uint32_t PIO2_0; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
ebrus	0:0a673c671a56	1603	__IO uint32_t PIO2_1; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
ebrus	0:0a673c671a56	1604	__IO uint32_t PIO2_2; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
ebrus	0:0a673c671a56	1605	__IO uint32_t PIO2_3; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
ebrus	0:0a673c671a56	1606	__IO uint32_t PIO2_4; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
ebrus	0:0a673c671a56	1607	__IO uint32_t PIO2_5; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
ebrus	0:0a673c671a56	1608	__IO uint32_t PIO2_6; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
ebrus	0:0a673c671a56	1609	__IO uint32_t PIO2_7; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
ebrus	0:0a673c671a56	1610	__IO uint32_t PIO2_8; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
ebrus	0:0a673c671a56	1611	__IO uint32_t PIO2_9; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
ebrus	0:0a673c671a56	1612	__IO uint32_t PIO2_10; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
ebrus	0:0a673c671a56	1613	__IO uint32_t PIO2_11; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
ebrus	0:0a673c671a56	1614	} LPC_IOCON_Type;
ebrus	0:0a673c671a56	1615
ebrus	0:0a673c671a56	1616
ebrus	0:0a673c671a56	1617	/* -------------------- End of section using anonymous unions ------------------- */
ebrus	0:0a673c671a56	1618	#if defined(__CC_ARM)
ebrus	0:0a673c671a56	1619	#pragma pop
ebrus	0:0a673c671a56	1620	#elif defined(__ICCARM__)
ebrus	0:0a673c671a56	1621	/* leave anonymous unions enabled */
ebrus	0:0a673c671a56	1622	#elif defined(__GNUC__)
ebrus	0:0a673c671a56	1623	/* anonymous unions are enabled by default */
ebrus	0:0a673c671a56	1624	#elif defined(__TMS470__)
ebrus	0:0a673c671a56	1625	/* anonymous unions are enabled by default */
ebrus	0:0a673c671a56	1626	#elif defined(__TASKING__)
ebrus	0:0a673c671a56	1627	#pragma warning restore
ebrus	0:0a673c671a56	1628	#else
ebrus	0:0a673c671a56	1629	#warning Not supported compiler type
ebrus	0:0a673c671a56	1630	#endif
ebrus	0:0a673c671a56	1631
ebrus	0:0a673c671a56	1632
ebrus	0:0a673c671a56	1633
ebrus	0:0a673c671a56	1634
ebrus	0:0a673c671a56	1635	/* ================================================================================ */
ebrus	0:0a673c671a56	1636	/* ================ Peripheral memory map ================ */
ebrus	0:0a673c671a56	1637	/* ================================================================================ */
ebrus	0:0a673c671a56	1638
ebrus	0:0a673c671a56	1639	#define LPC_GPIO_PORT_BASE 0x1C000000UL
ebrus	0:0a673c671a56	1640	#define LPC_DMA_BASE 0x1C004000UL
ebrus	0:0a673c671a56	1641	#define LPC_USB_BASE 0x1C00C000UL
ebrus	0:0a673c671a56	1642	#define LPC_CRC_BASE 0x1C010000UL
ebrus	0:0a673c671a56	1643	#define LPC_SCT0_BASE 0x1C018000UL
ebrus	0:0a673c671a56	1644	#define LPC_SCT1_BASE 0x1C01C000UL
ebrus	0:0a673c671a56	1645	#define LPC_SCT2_BASE 0x1C020000UL
ebrus	0:0a673c671a56	1646	#define LPC_SCT3_BASE 0x1C024000UL
ebrus	0:0a673c671a56	1647	#define LPC_ADC0_BASE 0x40000000UL
ebrus	0:0a673c671a56	1648	#define LPC_DAC_BASE 0x40004000UL
ebrus	0:0a673c671a56	1649	#define LPC_ACMP_BASE 0x40008000UL
ebrus	0:0a673c671a56	1650	#define LPC_INMUX_BASE 0x40014000UL
ebrus	0:0a673c671a56	1651	#define LPC_RTC_BASE 0x40028000UL
ebrus	0:0a673c671a56	1652	#define LPC_WWDT_BASE 0x4002C000UL
ebrus	0:0a673c671a56	1653	#define LPC_SWM_BASE 0x40038000UL
ebrus	0:0a673c671a56	1654	#define LPC_PMU_BASE 0x4003C000UL
ebrus	0:0a673c671a56	1655	#define LPC_USART0_BASE 0x40040000UL
ebrus	0:0a673c671a56	1656	#define LPC_USART1_BASE 0x40044000UL
ebrus	0:0a673c671a56	1657	#define LPC_SPI0_BASE 0x40048000UL
ebrus	0:0a673c671a56	1658	#define LPC_SPI1_BASE 0x4004C000UL
ebrus	0:0a673c671a56	1659	#define LPC_I2C0_BASE 0x40050000UL
ebrus	0:0a673c671a56	1660	#define LPC_QEI_BASE 0x40058000UL
ebrus	0:0a673c671a56	1661	#define LPC_SYSCON_BASE 0x40074000UL
ebrus	0:0a673c671a56	1662	#define LPC_ADC1_BASE 0x40080000UL
ebrus	0:0a673c671a56	1663	#define LPC_MRT_BASE 0x400A0000UL
ebrus	0:0a673c671a56	1664	#define LPC_PINT_BASE 0x400A4000UL
ebrus	0:0a673c671a56	1665	#define LPC_GINT0_BASE 0x400A8000UL
ebrus	0:0a673c671a56	1666	#define LPC_GINT1_BASE 0x400AC000UL
ebrus	0:0a673c671a56	1667	#define LPC_RIT_BASE 0x400B4000UL
ebrus	0:0a673c671a56	1668	#define LPC_SCTIPU_BASE 0x400B8000UL
ebrus	0:0a673c671a56	1669	#define LPC_FLASHCTRL_BASE 0x400BC000UL
ebrus	0:0a673c671a56	1670	#define LPC_USART2_BASE 0x400C0000UL
ebrus	0:0a673c671a56	1671	#define LPC_C_CAN0_BASE 0x400F0000UL
ebrus	0:0a673c671a56	1672	#define LPC_IOCON_BASE 0x400F8000UL
ebrus	0:0a673c671a56	1673
ebrus	0:0a673c671a56	1674
ebrus	0:0a673c671a56	1675	/* ================================================================================ */
ebrus	0:0a673c671a56	1676	/* ================ Peripheral declaration ================ */
ebrus	0:0a673c671a56	1677	/* ================================================================================ */
ebrus	0:0a673c671a56	1678
ebrus	0:0a673c671a56	1679	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
ebrus	0:0a673c671a56	1680	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
ebrus	0:0a673c671a56	1681	#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
ebrus	0:0a673c671a56	1682	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
ebrus	0:0a673c671a56	1683	#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
ebrus	0:0a673c671a56	1684	#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
ebrus	0:0a673c671a56	1685	#define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
ebrus	0:0a673c671a56	1686	#define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
ebrus	0:0a673c671a56	1687	#define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
ebrus	0:0a673c671a56	1688	#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
ebrus	0:0a673c671a56	1689	#define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
ebrus	0:0a673c671a56	1690	#define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
ebrus	0:0a673c671a56	1691	#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
ebrus	0:0a673c671a56	1692	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
ebrus	0:0a673c671a56	1693	#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
ebrus	0:0a673c671a56	1694	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
ebrus	0:0a673c671a56	1695	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
ebrus	0:0a673c671a56	1696	#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
ebrus	0:0a673c671a56	1697	#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
ebrus	0:0a673c671a56	1698	#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
ebrus	0:0a673c671a56	1699	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
ebrus	0:0a673c671a56	1700	#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
ebrus	0:0a673c671a56	1701	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
ebrus	0:0a673c671a56	1702	#define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
ebrus	0:0a673c671a56	1703	#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
ebrus	0:0a673c671a56	1704	#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
ebrus	0:0a673c671a56	1705	#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
ebrus	0:0a673c671a56	1706	#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
ebrus	0:0a673c671a56	1707	#define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
ebrus	0:0a673c671a56	1708	#define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
ebrus	0:0a673c671a56	1709	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
ebrus	0:0a673c671a56	1710	#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
ebrus	0:0a673c671a56	1711	#define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
ebrus	0:0a673c671a56	1712	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
ebrus	0:0a673c671a56	1713
ebrus	0:0a673c671a56	1714
ebrus	0:0a673c671a56	1715	/** @} / / End of group Device_Peripheral_Registers */
ebrus	0:0a673c671a56	1716	/** @} / / End of group LPC15xx */
ebrus	0:0a673c671a56	1717	/** @} / / End of group (null) */
ebrus	0:0a673c671a56	1718
ebrus	0:0a673c671a56	1719	#ifdef __cplusplus
ebrus	0:0a673c671a56	1720	}
ebrus	0:0a673c671a56	1721	#endif
ebrus	0:0a673c671a56	1722
ebrus	0:0a673c671a56	1723
ebrus	0:0a673c671a56	1724	#endif /* LPC15XX_H */
ebrus	0:0a673c671a56	1725

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Type:	Library
Created:	27 Jul 2016
Imports:	961
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targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h@0:0a673c671a56, 2016-07-27 (annotated)

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