Ermanno Brusadin / mbed-src

mbed library sources

targets/cmsis/TARGET_NXP/TARGET_LPC13XX/LPC13Uxx.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

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ebrus 0:0a673c671a56 1
ebrus 0:0a673c671a56 2 /****************************************************************************************************//**
ebrus 0:0a673c671a56 3 * @file LPC13Uxx.h
ebrus 0:0a673c671a56 4 *
ebrus 0:0a673c671a56 5 *
ebrus 0:0a673c671a56 6 *
ebrus 0:0a673c671a56 7 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
ebrus 0:0a673c671a56 8 * default LPC13Uxx Device Series
ebrus 0:0a673c671a56 9 *
ebrus 0:0a673c671a56 10 * @version V0.1
ebrus 0:0a673c671a56 11 * @date 18. Jan 2012
ebrus 0:0a673c671a56 12 *
ebrus 0:0a673c671a56 13 * @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
ebrus 0:0a673c671a56 14 *
ebrus 0:0a673c671a56 15 * from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
ebrus 0:0a673c671a56 16 * created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
ebrus 0:0a673c671a56 17 *
ebrus 0:0a673c671a56 18 *******************************************************************************************************/
ebrus 0:0a673c671a56 19
ebrus 0:0a673c671a56 20 /** @addtogroup NXP
ebrus 0:0a673c671a56 21 * @{
ebrus 0:0a673c671a56 22 */
ebrus 0:0a673c671a56 23
ebrus 0:0a673c671a56 24 /** @addtogroup LPC13Uxx
ebrus 0:0a673c671a56 25 * @{
ebrus 0:0a673c671a56 26 */
ebrus 0:0a673c671a56 27
ebrus 0:0a673c671a56 28 #ifndef __LPC13UXX_H__
ebrus 0:0a673c671a56 29 #define __LPC13UXX_H__
ebrus 0:0a673c671a56 30
ebrus 0:0a673c671a56 31 #ifdef __cplusplus
ebrus 0:0a673c671a56 32 extern "C" {
ebrus 0:0a673c671a56 33 #endif
ebrus 0:0a673c671a56 34
ebrus 0:0a673c671a56 35
ebrus 0:0a673c671a56 36 #if defined ( __CC_ARM )
ebrus 0:0a673c671a56 37 #pragma anon_unions
ebrus 0:0a673c671a56 38 #endif
ebrus 0:0a673c671a56 39
ebrus 0:0a673c671a56 40 /* Interrupt Number Definition */
ebrus 0:0a673c671a56 41
ebrus 0:0a673c671a56 42 typedef enum {
ebrus 0:0a673c671a56 43 // ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
ebrus 0:0a673c671a56 44 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
ebrus 0:0a673c671a56 45 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
ebrus 0:0a673c671a56 46 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
ebrus 0:0a673c671a56 47 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
ebrus 0:0a673c671a56 48 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
ebrus 0:0a673c671a56 49 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
ebrus 0:0a673c671a56 50 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
ebrus 0:0a673c671a56 51 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
ebrus 0:0a673c671a56 52 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
ebrus 0:0a673c671a56 53 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
ebrus 0:0a673c671a56 54 // ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
ebrus 0:0a673c671a56 55 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
ebrus 0:0a673c671a56 56 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
ebrus 0:0a673c671a56 57 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
ebrus 0:0a673c671a56 58 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
ebrus 0:0a673c671a56 59 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
ebrus 0:0a673c671a56 60 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
ebrus 0:0a673c671a56 61 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
ebrus 0:0a673c671a56 62 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
ebrus 0:0a673c671a56 63 GINT0_IRQn = 8, /*!< 8 GINT0 */
ebrus 0:0a673c671a56 64 GINT1_IRQn = 9, /*!< 9 GINT1 */
ebrus 0:0a673c671a56 65 Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
ebrus 0:0a673c671a56 66 Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
ebrus 0:0a673c671a56 67 RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
ebrus 0:0a673c671a56 68 Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
ebrus 0:0a673c671a56 69 SSP1_IRQn = 14, /*!< 14 SSP1 */
ebrus 0:0a673c671a56 70 I2C_IRQn = 15, /*!< 15 I2C */
ebrus 0:0a673c671a56 71 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
ebrus 0:0a673c671a56 72 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
ebrus 0:0a673c671a56 73 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
ebrus 0:0a673c671a56 74 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
ebrus 0:0a673c671a56 75 SSP0_IRQn = 20, /*!< 20 SSP0 */
ebrus 0:0a673c671a56 76 USART_IRQn = 21, /*!< 21 USART */
ebrus 0:0a673c671a56 77 USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
ebrus 0:0a673c671a56 78 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
ebrus 0:0a673c671a56 79 ADC_IRQn = 24, /*!< 24 ADC */
ebrus 0:0a673c671a56 80 WDT_IRQn = 25, /*!< 25 WDT */
ebrus 0:0a673c671a56 81 BOD_IRQn = 26, /*!< 26 BOD */
ebrus 0:0a673c671a56 82 FMC_IRQn = 27, /*!< 27 FMC */
ebrus 0:0a673c671a56 83 Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
ebrus 0:0a673c671a56 84 Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
ebrus 0:0a673c671a56 85 USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
ebrus 0:0a673c671a56 86 Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
ebrus 0:0a673c671a56 87 } IRQn_Type;
ebrus 0:0a673c671a56 88
ebrus 0:0a673c671a56 89
ebrus 0:0a673c671a56 90 /** @addtogroup Configuration_of_CMSIS
ebrus 0:0a673c671a56 91 * @{
ebrus 0:0a673c671a56 92 */
ebrus 0:0a673c671a56 93
ebrus 0:0a673c671a56 94 /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
ebrus 0:0a673c671a56 95
ebrus 0:0a673c671a56 96 #define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
ebrus 0:0a673c671a56 97 #define __MPU_PRESENT 0 /*!< MPU present or not */
ebrus 0:0a673c671a56 98 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
ebrus 0:0a673c671a56 99 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
ebrus 0:0a673c671a56 100 /** @} */ /* End of group Configuration_of_CMSIS */
ebrus 0:0a673c671a56 101
ebrus 0:0a673c671a56 102 #include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
ebrus 0:0a673c671a56 103 #include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
ebrus 0:0a673c671a56 104
ebrus 0:0a673c671a56 105 /** @addtogroup Device_Peripheral_Registers
ebrus 0:0a673c671a56 106 * @{
ebrus 0:0a673c671a56 107 */
ebrus 0:0a673c671a56 108
ebrus 0:0a673c671a56 109
ebrus 0:0a673c671a56 110 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 111 // ----- I2C -----
ebrus 0:0a673c671a56 112 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 113
ebrus 0:0a673c671a56 114
ebrus 0:0a673c671a56 115
ebrus 0:0a673c671a56 116 typedef struct { /*!< (@ 0x40000000) I2C Structure */
ebrus 0:0a673c671a56 117 __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
ebrus 0:0a673c671a56 118 __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
ebrus 0:0a673c671a56 119 __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
ebrus 0:0a673c671a56 120 __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
ebrus 0:0a673c671a56 121 __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
ebrus 0:0a673c671a56 122 __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
ebrus 0:0a673c671a56 123 __O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
ebrus 0:0a673c671a56 124 __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
ebrus 0:0a673c671a56 125 union{
ebrus 0:0a673c671a56 126 __IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
ebrus 0:0a673c671a56 127 struct{
ebrus 0:0a673c671a56 128 __IO uint32_t ADR1;
ebrus 0:0a673c671a56 129 __IO uint32_t ADR2;
ebrus 0:0a673c671a56 130 __IO uint32_t ADR3;
ebrus 0:0a673c671a56 131 };
ebrus 0:0a673c671a56 132 };
ebrus 0:0a673c671a56 133 __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
ebrus 0:0a673c671a56 134 union{
ebrus 0:0a673c671a56 135 __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
ebrus 0:0a673c671a56 136 struct{
ebrus 0:0a673c671a56 137 __IO uint32_t MASK0;
ebrus 0:0a673c671a56 138 __IO uint32_t MASK1;
ebrus 0:0a673c671a56 139 __IO uint32_t MASK2;
ebrus 0:0a673c671a56 140 __IO uint32_t MASK3;
ebrus 0:0a673c671a56 141 };
ebrus 0:0a673c671a56 142 };
ebrus 0:0a673c671a56 143 } LPC_I2C_Type;
ebrus 0:0a673c671a56 144
ebrus 0:0a673c671a56 145
ebrus 0:0a673c671a56 146 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 147 // ----- WWDT -----
ebrus 0:0a673c671a56 148 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 149
ebrus 0:0a673c671a56 150
ebrus 0:0a673c671a56 151 typedef struct { /*!< (@ 0x40004000) WWDT Structure */
ebrus 0:0a673c671a56 152 __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
ebrus 0:0a673c671a56 153 __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
ebrus 0:0a673c671a56 154 __O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
ebrus 0:0a673c671a56 155 __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
ebrus 0:0a673c671a56 156 __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
ebrus 0:0a673c671a56 157 __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
ebrus 0:0a673c671a56 158 __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
ebrus 0:0a673c671a56 159 } LPC_WWDT_Type;
ebrus 0:0a673c671a56 160
ebrus 0:0a673c671a56 161
ebrus 0:0a673c671a56 162 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 163 // ----- USART -----
ebrus 0:0a673c671a56 164 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 165
ebrus 0:0a673c671a56 166
ebrus 0:0a673c671a56 167 typedef struct { /*!< (@ 0x40008000) USART Structure */
ebrus 0:0a673c671a56 168
ebrus 0:0a673c671a56 169 union {
ebrus 0:0a673c671a56 170 __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
ebrus 0:0a673c671a56 171 __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
ebrus 0:0a673c671a56 172 __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
ebrus 0:0a673c671a56 173 };
ebrus 0:0a673c671a56 174
ebrus 0:0a673c671a56 175 union {
ebrus 0:0a673c671a56 176 __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
ebrus 0:0a673c671a56 177 __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
ebrus 0:0a673c671a56 178 };
ebrus 0:0a673c671a56 179
ebrus 0:0a673c671a56 180 union {
ebrus 0:0a673c671a56 181 __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
ebrus 0:0a673c671a56 182 __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
ebrus 0:0a673c671a56 183 };
ebrus 0:0a673c671a56 184 __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
ebrus 0:0a673c671a56 185 __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
ebrus 0:0a673c671a56 186 __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
ebrus 0:0a673c671a56 187 __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
ebrus 0:0a673c671a56 188 __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
ebrus 0:0a673c671a56 189 __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
ebrus 0:0a673c671a56 190 __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
ebrus 0:0a673c671a56 191 __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
ebrus 0:0a673c671a56 192 __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
ebrus 0:0a673c671a56 193 __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
ebrus 0:0a673c671a56 194 __I uint32_t RESERVED0[3];
ebrus 0:0a673c671a56 195 __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
ebrus 0:0a673c671a56 196 __I uint32_t RESERVED1;
ebrus 0:0a673c671a56 197 __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
ebrus 0:0a673c671a56 198 __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
ebrus 0:0a673c671a56 199 __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
ebrus 0:0a673c671a56 200 __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
ebrus 0:0a673c671a56 201 __IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
ebrus 0:0a673c671a56 202 } LPC_USART_Type;
ebrus 0:0a673c671a56 203
ebrus 0:0a673c671a56 204
ebrus 0:0a673c671a56 205 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 206 // ----- CT16B0 -----
ebrus 0:0a673c671a56 207 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 208
ebrus 0:0a673c671a56 209 typedef struct { /*!< (@ 0x4000C000) LPC_CTxxBx_Type Structure */
ebrus 0:0a673c671a56 210 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
ebrus 0:0a673c671a56 211 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
ebrus 0:0a673c671a56 212 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
ebrus 0:0a673c671a56 213 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
ebrus 0:0a673c671a56 214 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
ebrus 0:0a673c671a56 215 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
ebrus 0:0a673c671a56 216 union {
ebrus 0:0a673c671a56 217 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
ebrus 0:0a673c671a56 218 struct{
ebrus 0:0a673c671a56 219 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
ebrus 0:0a673c671a56 220 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
ebrus 0:0a673c671a56 221 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
ebrus 0:0a673c671a56 222 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
ebrus 0:0a673c671a56 223 };
ebrus 0:0a673c671a56 224 };
ebrus 0:0a673c671a56 225 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
ebrus 0:0a673c671a56 226 union{
ebrus 0:0a673c671a56 227 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
ebrus 0:0a673c671a56 228 struct{
ebrus 0:0a673c671a56 229 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
ebrus 0:0a673c671a56 230 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
ebrus 0:0a673c671a56 231 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
ebrus 0:0a673c671a56 232 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
ebrus 0:0a673c671a56 233 };
ebrus 0:0a673c671a56 234 };
ebrus 0:0a673c671a56 235 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
ebrus 0:0a673c671a56 236 __I uint32_t RESERVED0[12];
ebrus 0:0a673c671a56 237 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
ebrus 0:0a673c671a56 238 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
ebrus 0:0a673c671a56 239 } LPC_CTxxBx_Type;
ebrus 0:0a673c671a56 240
ebrus 0:0a673c671a56 241 typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
ebrus 0:0a673c671a56 242 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
ebrus 0:0a673c671a56 243 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
ebrus 0:0a673c671a56 244 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
ebrus 0:0a673c671a56 245 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
ebrus 0:0a673c671a56 246 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
ebrus 0:0a673c671a56 247 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
ebrus 0:0a673c671a56 248 union {
ebrus 0:0a673c671a56 249 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
ebrus 0:0a673c671a56 250 struct{
ebrus 0:0a673c671a56 251 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
ebrus 0:0a673c671a56 252 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
ebrus 0:0a673c671a56 253 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
ebrus 0:0a673c671a56 254 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
ebrus 0:0a673c671a56 255 };
ebrus 0:0a673c671a56 256 };
ebrus 0:0a673c671a56 257 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
ebrus 0:0a673c671a56 258 union{
ebrus 0:0a673c671a56 259 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
ebrus 0:0a673c671a56 260 struct{
ebrus 0:0a673c671a56 261 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
ebrus 0:0a673c671a56 262 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
ebrus 0:0a673c671a56 263 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
ebrus 0:0a673c671a56 264 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
ebrus 0:0a673c671a56 265 };
ebrus 0:0a673c671a56 266 };
ebrus 0:0a673c671a56 267 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
ebrus 0:0a673c671a56 268 __I uint32_t RESERVED0[12];
ebrus 0:0a673c671a56 269 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
ebrus 0:0a673c671a56 270 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
ebrus 0:0a673c671a56 271 } LPC_CT16B0_Type;
ebrus 0:0a673c671a56 272
ebrus 0:0a673c671a56 273
ebrus 0:0a673c671a56 274 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 275 // ----- CT16B1 -----
ebrus 0:0a673c671a56 276 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 277
ebrus 0:0a673c671a56 278 typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
ebrus 0:0a673c671a56 279 __IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
ebrus 0:0a673c671a56 280 __IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
ebrus 0:0a673c671a56 281 __IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
ebrus 0:0a673c671a56 282 __IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
ebrus 0:0a673c671a56 283 __IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
ebrus 0:0a673c671a56 284 __IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
ebrus 0:0a673c671a56 285 union {
ebrus 0:0a673c671a56 286 __IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
ebrus 0:0a673c671a56 287 struct{
ebrus 0:0a673c671a56 288 __IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
ebrus 0:0a673c671a56 289 __IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
ebrus 0:0a673c671a56 290 __IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
ebrus 0:0a673c671a56 291 __IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
ebrus 0:0a673c671a56 292 };
ebrus 0:0a673c671a56 293 };
ebrus 0:0a673c671a56 294 __IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
ebrus 0:0a673c671a56 295 union{
ebrus 0:0a673c671a56 296 __I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
ebrus 0:0a673c671a56 297 struct{
ebrus 0:0a673c671a56 298 __I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
ebrus 0:0a673c671a56 299 __I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
ebrus 0:0a673c671a56 300 __I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
ebrus 0:0a673c671a56 301 __I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
ebrus 0:0a673c671a56 302 };
ebrus 0:0a673c671a56 303 };
ebrus 0:0a673c671a56 304 __IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
ebrus 0:0a673c671a56 305 __I uint32_t RESERVED0[12];
ebrus 0:0a673c671a56 306 __IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
ebrus 0:0a673c671a56 307 __IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
ebrus 0:0a673c671a56 308 } LPC_CT16B1_Type;
ebrus 0:0a673c671a56 309
ebrus 0:0a673c671a56 310
ebrus 0:0a673c671a56 311 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 312 // ----- CT32B0 -----
ebrus 0:0a673c671a56 313 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 314 typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
ebrus 0:0a673c671a56 315 __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
ebrus 0:0a673c671a56 316 __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
ebrus 0:0a673c671a56 317 __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
ebrus 0:0a673c671a56 318 __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
ebrus 0:0a673c671a56 319 __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
ebrus 0:0a673c671a56 320 __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
ebrus 0:0a673c671a56 321 union {
ebrus 0:0a673c671a56 322 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
ebrus 0:0a673c671a56 323 struct{
ebrus 0:0a673c671a56 324 __IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
ebrus 0:0a673c671a56 325 __IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
ebrus 0:0a673c671a56 326 __IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
ebrus 0:0a673c671a56 327 __IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
ebrus 0:0a673c671a56 328 };
ebrus 0:0a673c671a56 329 };
ebrus 0:0a673c671a56 330 __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
ebrus 0:0a673c671a56 331 union{
ebrus 0:0a673c671a56 332 __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
ebrus 0:0a673c671a56 333 struct{
ebrus 0:0a673c671a56 334 __I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
ebrus 0:0a673c671a56 335 __I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
ebrus 0:0a673c671a56 336 __I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
ebrus 0:0a673c671a56 337 __I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
ebrus 0:0a673c671a56 338 };
ebrus 0:0a673c671a56 339 };
ebrus 0:0a673c671a56 340 __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
ebrus 0:0a673c671a56 341 __I uint32_t RESERVED0[12];
ebrus 0:0a673c671a56 342 __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
ebrus 0:0a673c671a56 343 __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
ebrus 0:0a673c671a56 344 } LPC_CT32B0_Type;
ebrus 0:0a673c671a56 345
ebrus 0:0a673c671a56 346
ebrus 0:0a673c671a56 347 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 348 // ----- CT32B1 -----
ebrus 0:0a673c671a56 349 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 350 typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
ebrus 0:0a673c671a56 351 __IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
ebrus 0:0a673c671a56 352 __IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
ebrus 0:0a673c671a56 353 __IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
ebrus 0:0a673c671a56 354 __IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
ebrus 0:0a673c671a56 355 __IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
ebrus 0:0a673c671a56 356 __IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
ebrus 0:0a673c671a56 357 union {
ebrus 0:0a673c671a56 358 __IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
ebrus 0:0a673c671a56 359 struct{
ebrus 0:0a673c671a56 360 __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
ebrus 0:0a673c671a56 361 __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
ebrus 0:0a673c671a56 362 __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
ebrus 0:0a673c671a56 363 __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
ebrus 0:0a673c671a56 364 };
ebrus 0:0a673c671a56 365 };
ebrus 0:0a673c671a56 366 __IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
ebrus 0:0a673c671a56 367 union{
ebrus 0:0a673c671a56 368 __I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
ebrus 0:0a673c671a56 369 struct{
ebrus 0:0a673c671a56 370 __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
ebrus 0:0a673c671a56 371 __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
ebrus 0:0a673c671a56 372 __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
ebrus 0:0a673c671a56 373 __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
ebrus 0:0a673c671a56 374 };
ebrus 0:0a673c671a56 375 };
ebrus 0:0a673c671a56 376 __IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
ebrus 0:0a673c671a56 377 __I uint32_t RESERVED0[12];
ebrus 0:0a673c671a56 378 __IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
ebrus 0:0a673c671a56 379 __IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
ebrus 0:0a673c671a56 380 } LPC_CT32B1_Type;
ebrus 0:0a673c671a56 381
ebrus 0:0a673c671a56 382
ebrus 0:0a673c671a56 383 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 384 // ----- ADC -----
ebrus 0:0a673c671a56 385 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 386 typedef struct { /*!< (@ 0x4001C000) ADC Structure */
ebrus 0:0a673c671a56 387 __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
ebrus 0:0a673c671a56 388 __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
ebrus 0:0a673c671a56 389 __I uint32_t RESERVED0[1];
ebrus 0:0a673c671a56 390 __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
ebrus 0:0a673c671a56 391 union{
ebrus 0:0a673c671a56 392 __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
ebrus 0:0a673c671a56 393 struct{
ebrus 0:0a673c671a56 394 __I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
ebrus 0:0a673c671a56 395 __I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
ebrus 0:0a673c671a56 396 __I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
ebrus 0:0a673c671a56 397 __I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
ebrus 0:0a673c671a56 398 __I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
ebrus 0:0a673c671a56 399 __I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
ebrus 0:0a673c671a56 400 __I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
ebrus 0:0a673c671a56 401 __I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
ebrus 0:0a673c671a56 402 };
ebrus 0:0a673c671a56 403 };
ebrus 0:0a673c671a56 404 __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
ebrus 0:0a673c671a56 405 } LPC_ADC_Type;
ebrus 0:0a673c671a56 406
ebrus 0:0a673c671a56 407
ebrus 0:0a673c671a56 408 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 409 // ----- PMU -----
ebrus 0:0a673c671a56 410 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 411
ebrus 0:0a673c671a56 412 typedef struct { /*!< (@ 0x40038000) PMU Structure */
ebrus 0:0a673c671a56 413 __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
ebrus 0:0a673c671a56 414 union{
ebrus 0:0a673c671a56 415 __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
ebrus 0:0a673c671a56 416 struct{
ebrus 0:0a673c671a56 417 __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
ebrus 0:0a673c671a56 418 __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
ebrus 0:0a673c671a56 419 __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
ebrus 0:0a673c671a56 420 __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
ebrus 0:0a673c671a56 421 };
ebrus 0:0a673c671a56 422 };
ebrus 0:0a673c671a56 423 __IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
ebrus 0:0a673c671a56 424 } LPC_PMU_Type;
ebrus 0:0a673c671a56 425
ebrus 0:0a673c671a56 426
ebrus 0:0a673c671a56 427 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 428 // ----- FLASHCTRL -----
ebrus 0:0a673c671a56 429 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 430
ebrus 0:0a673c671a56 431 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
ebrus 0:0a673c671a56 432 __I uint32_t RESERVED0[4];
ebrus 0:0a673c671a56 433 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
ebrus 0:0a673c671a56 434 __I uint32_t RESERVED1[3];
ebrus 0:0a673c671a56 435 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
ebrus 0:0a673c671a56 436 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
ebrus 0:0a673c671a56 437 __I uint32_t RESERVED2[1];
ebrus 0:0a673c671a56 438 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
ebrus 0:0a673c671a56 439 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
ebrus 0:0a673c671a56 440 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
ebrus 0:0a673c671a56 441 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
ebrus 0:0a673c671a56 442 __I uint32_t RESERVED3[1001];
ebrus 0:0a673c671a56 443 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
ebrus 0:0a673c671a56 444 __I uint32_t RESERVED4[1];
ebrus 0:0a673c671a56 445 __O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
ebrus 0:0a673c671a56 446 } LPC_FLASHCTRL_Type;
ebrus 0:0a673c671a56 447
ebrus 0:0a673c671a56 448
ebrus 0:0a673c671a56 449 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 450 // ----- SSP -----
ebrus 0:0a673c671a56 451 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 452 typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
ebrus 0:0a673c671a56 453 __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
ebrus 0:0a673c671a56 454 __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
ebrus 0:0a673c671a56 455 __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
ebrus 0:0a673c671a56 456 __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
ebrus 0:0a673c671a56 457 __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
ebrus 0:0a673c671a56 458 __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
ebrus 0:0a673c671a56 459 __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
ebrus 0:0a673c671a56 460 __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
ebrus 0:0a673c671a56 461 __O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
ebrus 0:0a673c671a56 462 } LPC_SSPx_Type;
ebrus 0:0a673c671a56 463
ebrus 0:0a673c671a56 464
ebrus 0:0a673c671a56 465 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 466 // ----- IOCON -----
ebrus 0:0a673c671a56 467 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 468 typedef struct { /*!< (@ 0x40044000) IOCON Structure */
ebrus 0:0a673c671a56 469 __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
ebrus 0:0a673c671a56 470 __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
ebrus 0:0a673c671a56 471 __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
ebrus 0:0a673c671a56 472 __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
ebrus 0:0a673c671a56 473 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
ebrus 0:0a673c671a56 474 __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
ebrus 0:0a673c671a56 475 __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
ebrus 0:0a673c671a56 476 __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
ebrus 0:0a673c671a56 477 __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
ebrus 0:0a673c671a56 478 __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
ebrus 0:0a673c671a56 479 __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
ebrus 0:0a673c671a56 480 __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
ebrus 0:0a673c671a56 481 __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
ebrus 0:0a673c671a56 482 __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
ebrus 0:0a673c671a56 483 __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
ebrus 0:0a673c671a56 484 __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
ebrus 0:0a673c671a56 485 __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
ebrus 0:0a673c671a56 486 __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
ebrus 0:0a673c671a56 487 __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
ebrus 0:0a673c671a56 488 __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
ebrus 0:0a673c671a56 489 __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
ebrus 0:0a673c671a56 490 __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
ebrus 0:0a673c671a56 491 __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
ebrus 0:0a673c671a56 492 __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
ebrus 0:0a673c671a56 493 __IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
ebrus 0:0a673c671a56 494 __IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
ebrus 0:0a673c671a56 495 __IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
ebrus 0:0a673c671a56 496 __IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
ebrus 0:0a673c671a56 497 __IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
ebrus 0:0a673c671a56 498 __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
ebrus 0:0a673c671a56 499 __IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
ebrus 0:0a673c671a56 500 __IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
ebrus 0:0a673c671a56 501 __IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
ebrus 0:0a673c671a56 502 __IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
ebrus 0:0a673c671a56 503 __IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
ebrus 0:0a673c671a56 504 __IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
ebrus 0:0a673c671a56 505 __IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
ebrus 0:0a673c671a56 506 __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
ebrus 0:0a673c671a56 507 __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
ebrus 0:0a673c671a56 508 __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
ebrus 0:0a673c671a56 509 __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
ebrus 0:0a673c671a56 510 __IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
ebrus 0:0a673c671a56 511 __IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
ebrus 0:0a673c671a56 512 __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
ebrus 0:0a673c671a56 513 __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
ebrus 0:0a673c671a56 514 __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
ebrus 0:0a673c671a56 515 __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
ebrus 0:0a673c671a56 516 __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
ebrus 0:0a673c671a56 517 __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
ebrus 0:0a673c671a56 518 __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
ebrus 0:0a673c671a56 519 __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
ebrus 0:0a673c671a56 520 __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
ebrus 0:0a673c671a56 521 __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
ebrus 0:0a673c671a56 522 __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
ebrus 0:0a673c671a56 523 __IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
ebrus 0:0a673c671a56 524 __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
ebrus 0:0a673c671a56 525 } LPC_IOCON_Type;
ebrus 0:0a673c671a56 526
ebrus 0:0a673c671a56 527
ebrus 0:0a673c671a56 528 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 529 // ----- SYSCON -----
ebrus 0:0a673c671a56 530 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 531
ebrus 0:0a673c671a56 532 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
ebrus 0:0a673c671a56 533 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
ebrus 0:0a673c671a56 534 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
ebrus 0:0a673c671a56 535 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
ebrus 0:0a673c671a56 536 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
ebrus 0:0a673c671a56 537 __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
ebrus 0:0a673c671a56 538 __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
ebrus 0:0a673c671a56 539 __I uint32_t RESERVED0[2];
ebrus 0:0a673c671a56 540 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
ebrus 0:0a673c671a56 541 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
ebrus 0:0a673c671a56 542 __I uint32_t RESERVED1[2];
ebrus 0:0a673c671a56 543 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
ebrus 0:0a673c671a56 544 __I uint32_t RESERVED2[3];
ebrus 0:0a673c671a56 545 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
ebrus 0:0a673c671a56 546 __I uint32_t RESERVED3;
ebrus 0:0a673c671a56 547 __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
ebrus 0:0a673c671a56 548 __I uint32_t RESERVED4[9];
ebrus 0:0a673c671a56 549 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
ebrus 0:0a673c671a56 550 __I uint32_t RESERVED5;
ebrus 0:0a673c671a56 551 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
ebrus 0:0a673c671a56 552 __I uint32_t RESERVED6;
ebrus 0:0a673c671a56 553 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
ebrus 0:0a673c671a56 554 __I uint32_t RESERVED7[4];
ebrus 0:0a673c671a56 555 __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
ebrus 0:0a673c671a56 556 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
ebrus 0:0a673c671a56 557 __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
ebrus 0:0a673c671a56 558 __I uint32_t RESERVED8[3];
ebrus 0:0a673c671a56 559 __IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
ebrus 0:0a673c671a56 560 __IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
ebrus 0:0a673c671a56 561 __I uint32_t RESERVED9[3];
ebrus 0:0a673c671a56 562 __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
ebrus 0:0a673c671a56 563 __I uint32_t RESERVED10;
ebrus 0:0a673c671a56 564 __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
ebrus 0:0a673c671a56 565 __I uint32_t RESERVED11[5];
ebrus 0:0a673c671a56 566 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
ebrus 0:0a673c671a56 567 __I uint32_t RESERVED12;
ebrus 0:0a673c671a56 568 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
ebrus 0:0a673c671a56 569 __I uint32_t RESERVED13[5];
ebrus 0:0a673c671a56 570 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
ebrus 0:0a673c671a56 571 __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
ebrus 0:0a673c671a56 572 __I uint32_t RESERVED14[18];
ebrus 0:0a673c671a56 573 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
ebrus 0:0a673c671a56 574 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
ebrus 0:0a673c671a56 575 __I uint32_t RESERVED15[6];
ebrus 0:0a673c671a56 576 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
ebrus 0:0a673c671a56 577 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
ebrus 0:0a673c671a56 578 __IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
ebrus 0:0a673c671a56 579 __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
ebrus 0:0a673c671a56 580 __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
ebrus 0:0a673c671a56 581 __I uint32_t RESERVED16[25];
ebrus 0:0a673c671a56 582 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
ebrus 0:0a673c671a56 583 __I uint32_t RESERVED17[3];
ebrus 0:0a673c671a56 584 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
ebrus 0:0a673c671a56 585 __I uint32_t RESERVED18[6];
ebrus 0:0a673c671a56 586 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
ebrus 0:0a673c671a56 587 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
ebrus 0:0a673c671a56 588 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
ebrus 0:0a673c671a56 589 __I uint32_t RESERVED19[111];
ebrus 0:0a673c671a56 590 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
ebrus 0:0a673c671a56 591 } LPC_SYSCON_Type;
ebrus 0:0a673c671a56 592
ebrus 0:0a673c671a56 593
ebrus 0:0a673c671a56 594 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 595 // ----- GPIO_PIN_INT -----
ebrus 0:0a673c671a56 596 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 597 typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
ebrus 0:0a673c671a56 598 __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
ebrus 0:0a673c671a56 599 __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
ebrus 0:0a673c671a56 600 __O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
ebrus 0:0a673c671a56 601 __O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
ebrus 0:0a673c671a56 602 __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
ebrus 0:0a673c671a56 603 __O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
ebrus 0:0a673c671a56 604 __O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
ebrus 0:0a673c671a56 605 __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
ebrus 0:0a673c671a56 606 __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
ebrus 0:0a673c671a56 607 __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
ebrus 0:0a673c671a56 608 } LPC_GPIO_PIN_INT_Type;
ebrus 0:0a673c671a56 609
ebrus 0:0a673c671a56 610
ebrus 0:0a673c671a56 611 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 612 // ----- GPIO_GROUP_INT0 -----
ebrus 0:0a673c671a56 613 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 614 typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
ebrus 0:0a673c671a56 615 __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
ebrus 0:0a673c671a56 616 __I uint32_t RESERVED0[7];
ebrus 0:0a673c671a56 617 __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
ebrus 0:0a673c671a56 618 __I uint32_t RESERVED1[6];
ebrus 0:0a673c671a56 619 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
ebrus 0:0a673c671a56 620 } LPC_GPIO_GROUP_INT0_Type;
ebrus 0:0a673c671a56 621
ebrus 0:0a673c671a56 622
ebrus 0:0a673c671a56 623 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 624 // ----- GPIO_GROUP_INT1 -----
ebrus 0:0a673c671a56 625 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 626
ebrus 0:0a673c671a56 627 typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
ebrus 0:0a673c671a56 628 __IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
ebrus 0:0a673c671a56 629 __I uint32_t RESERVED0[7];
ebrus 0:0a673c671a56 630 __IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
ebrus 0:0a673c671a56 631 __I uint32_t RESERVED1[6];
ebrus 0:0a673c671a56 632 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
ebrus 0:0a673c671a56 633 } LPC_GPIO_GROUP_INT1_Type;
ebrus 0:0a673c671a56 634
ebrus 0:0a673c671a56 635
ebrus 0:0a673c671a56 636 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 637 // ----- Repetitive Interrupt Timer (RIT) -----
ebrus 0:0a673c671a56 638 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 639
ebrus 0:0a673c671a56 640 typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
ebrus 0:0a673c671a56 641 __IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
ebrus 0:0a673c671a56 642 __IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
ebrus 0:0a673c671a56 643 __IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
ebrus 0:0a673c671a56 644 __IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
ebrus 0:0a673c671a56 645 __IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
ebrus 0:0a673c671a56 646 __IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
ebrus 0:0a673c671a56 647 __I uint32_t RESERVED0[1];
ebrus 0:0a673c671a56 648 __IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
ebrus 0:0a673c671a56 649 } LPC_RITIMER_Type;
ebrus 0:0a673c671a56 650
ebrus 0:0a673c671a56 651
ebrus 0:0a673c671a56 652 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 653 // ----- USB -----
ebrus 0:0a673c671a56 654 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 655 typedef struct { /*!< (@ 0x40020000) USB Structure */
ebrus 0:0a673c671a56 656 __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
ebrus 0:0a673c671a56 657 __IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
ebrus 0:0a673c671a56 658 __IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
ebrus 0:0a673c671a56 659 __IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
ebrus 0:0a673c671a56 660 __IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
ebrus 0:0a673c671a56 661 __IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
ebrus 0:0a673c671a56 662 __IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
ebrus 0:0a673c671a56 663 __IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
ebrus 0:0a673c671a56 664 __IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
ebrus 0:0a673c671a56 665 __IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
ebrus 0:0a673c671a56 666 __IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
ebrus 0:0a673c671a56 667 __IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
ebrus 0:0a673c671a56 668 __I uint32_t RESERVED0[1];
ebrus 0:0a673c671a56 669 __I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
ebrus 0:0a673c671a56 670 } LPC_USB_Type;
ebrus 0:0a673c671a56 671
ebrus 0:0a673c671a56 672
ebrus 0:0a673c671a56 673 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 674 // ----- GPIO_PORT -----
ebrus 0:0a673c671a56 675 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 676
ebrus 0:0a673c671a56 677 typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
ebrus 0:0a673c671a56 678 union {
ebrus 0:0a673c671a56 679 struct {
ebrus 0:0a673c671a56 680 __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
ebrus 0:0a673c671a56 681 __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
ebrus 0:0a673c671a56 682 };
ebrus 0:0a673c671a56 683 __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
ebrus 0:0a673c671a56 684 };
ebrus 0:0a673c671a56 685 __I uint32_t RESERVED0[1008];
ebrus 0:0a673c671a56 686 union {
ebrus 0:0a673c671a56 687 struct {
ebrus 0:0a673c671a56 688 __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
ebrus 0:0a673c671a56 689 __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
ebrus 0:0a673c671a56 690 };
ebrus 0:0a673c671a56 691 __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
ebrus 0:0a673c671a56 692 };
ebrus 0:0a673c671a56 693 __I uint32_t RESERVED1[960];
ebrus 0:0a673c671a56 694 __IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
ebrus 0:0a673c671a56 695 __I uint32_t RESERVED2[30];
ebrus 0:0a673c671a56 696 __IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
ebrus 0:0a673c671a56 697 __I uint32_t RESERVED3[30];
ebrus 0:0a673c671a56 698 __IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
ebrus 0:0a673c671a56 699 __I uint32_t RESERVED4[30];
ebrus 0:0a673c671a56 700 __IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
ebrus 0:0a673c671a56 701 __I uint32_t RESERVED5[30];
ebrus 0:0a673c671a56 702 __IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
ebrus 0:0a673c671a56 703 __I uint32_t RESERVED6[30];
ebrus 0:0a673c671a56 704 __O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
ebrus 0:0a673c671a56 705 __I uint32_t RESERVED7[30];
ebrus 0:0a673c671a56 706 __O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
ebrus 0:0a673c671a56 707 } LPC_GPIO_Type;
ebrus 0:0a673c671a56 708
ebrus 0:0a673c671a56 709
ebrus 0:0a673c671a56 710 #if defined ( __CC_ARM )
ebrus 0:0a673c671a56 711 #pragma no_anon_unions
ebrus 0:0a673c671a56 712 #endif
ebrus 0:0a673c671a56 713
ebrus 0:0a673c671a56 714
ebrus 0:0a673c671a56 715 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 716 // ----- Peripheral memory map -----
ebrus 0:0a673c671a56 717 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 718
ebrus 0:0a673c671a56 719 #define LPC_I2C_BASE (0x40000000)
ebrus 0:0a673c671a56 720 #define LPC_WWDT_BASE (0x40004000)
ebrus 0:0a673c671a56 721 #define LPC_USART_BASE (0x40008000)
ebrus 0:0a673c671a56 722 #define LPC_CT16B0_BASE (0x4000C000)
ebrus 0:0a673c671a56 723 #define LPC_CT16B1_BASE (0x40010000)
ebrus 0:0a673c671a56 724 #define LPC_CT32B0_BASE (0x40014000)
ebrus 0:0a673c671a56 725 #define LPC_CT32B1_BASE (0x40018000)
ebrus 0:0a673c671a56 726 #define LPC_ADC_BASE (0x4001C000)
ebrus 0:0a673c671a56 727 #define LPC_PMU_BASE (0x40038000)
ebrus 0:0a673c671a56 728 #define LPC_FLASHCTRL_BASE (0x4003C000)
ebrus 0:0a673c671a56 729 #define LPC_SSP0_BASE (0x40040000)
ebrus 0:0a673c671a56 730 #define LPC_IOCON_BASE (0x40044000)
ebrus 0:0a673c671a56 731 #define LPC_SYSCON_BASE (0x40048000)
ebrus 0:0a673c671a56 732 #define LPC_GPIO_PIN_INT_BASE (0x4004C000)
ebrus 0:0a673c671a56 733 #define LPC_SSP1_BASE (0x40058000)
ebrus 0:0a673c671a56 734 #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
ebrus 0:0a673c671a56 735 #define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
ebrus 0:0a673c671a56 736 #define LPC_RITIMER_BASE (0x40064000)
ebrus 0:0a673c671a56 737 #define LPC_USB_BASE (0x40080000)
ebrus 0:0a673c671a56 738 #define LPC_GPIO_BASE (0x50000000)
ebrus 0:0a673c671a56 739
ebrus 0:0a673c671a56 740
ebrus 0:0a673c671a56 741 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 742 // ----- Peripheral declaration -----
ebrus 0:0a673c671a56 743 // ------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 744
ebrus 0:0a673c671a56 745 #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
ebrus 0:0a673c671a56 746 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
ebrus 0:0a673c671a56 747 #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
ebrus 0:0a673c671a56 748 #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
ebrus 0:0a673c671a56 749 #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
ebrus 0:0a673c671a56 750 #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
ebrus 0:0a673c671a56 751 #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
ebrus 0:0a673c671a56 752 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
ebrus 0:0a673c671a56 753 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
ebrus 0:0a673c671a56 754 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
ebrus 0:0a673c671a56 755 #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
ebrus 0:0a673c671a56 756 #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
ebrus 0:0a673c671a56 757 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
ebrus 0:0a673c671a56 758 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
ebrus 0:0a673c671a56 759 #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
ebrus 0:0a673c671a56 760 #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
ebrus 0:0a673c671a56 761 #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
ebrus 0:0a673c671a56 762 #define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
ebrus 0:0a673c671a56 763 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
ebrus 0:0a673c671a56 764 #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
ebrus 0:0a673c671a56 765
ebrus 0:0a673c671a56 766
ebrus 0:0a673c671a56 767 /** @} */ /* End of group Device_Peripheral_Registers */
ebrus 0:0a673c671a56 768 /** @} */ /* End of group (null) */
ebrus 0:0a673c671a56 769 /** @} */ /* End of group h1usf */
ebrus 0:0a673c671a56 770
ebrus 0:0a673c671a56 771 #ifdef __cplusplus
ebrus 0:0a673c671a56 772 }
ebrus 0:0a673c671a56 773 #endif
ebrus 0:0a673c671a56 774
ebrus 0:0a673c671a56 775
ebrus 0:0a673c671a56 776 #endif // __LPC13UXX_H__