Ermanno Brusadin / mbed-src

mbed library sources

targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

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ebrus 0:0a673c671a56 1
ebrus 0:0a673c671a56 2 /****************************************************************************************************//**
ebrus 0:0a673c671a56 3 * @file LPC11U6x.h
ebrus 0:0a673c671a56 4 *
ebrus 0:0a673c671a56 5 * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
ebrus 0:0a673c671a56 6 * LPC11U6x from .
ebrus 0:0a673c671a56 7 *
ebrus 0:0a673c671a56 8 * @version V0.4
ebrus 0:0a673c671a56 9 * @date 22. October 2013
ebrus 0:0a673c671a56 10 *
ebrus 0:0a673c671a56 11 * @note Generated with SVDConv V2.81a
ebrus 0:0a673c671a56 12 * from CMSIS SVD File 'LPC11U6x.svd' Version 0.4,
ebrus 0:0a673c671a56 13 *
ebrus 0:0a673c671a56 14 * modified by Keil
ebrus 0:0a673c671a56 15 *******************************************************************************************************/
ebrus 0:0a673c671a56 16
ebrus 0:0a673c671a56 17
ebrus 0:0a673c671a56 18
ebrus 0:0a673c671a56 19 /** @addtogroup (null)
ebrus 0:0a673c671a56 20 * @{
ebrus 0:0a673c671a56 21 */
ebrus 0:0a673c671a56 22
ebrus 0:0a673c671a56 23 /** @addtogroup LPC11U6x
ebrus 0:0a673c671a56 24 * @{
ebrus 0:0a673c671a56 25 */
ebrus 0:0a673c671a56 26
ebrus 0:0a673c671a56 27 #ifndef LPC11U6X_H
ebrus 0:0a673c671a56 28 #define LPC11U6X_H
ebrus 0:0a673c671a56 29
ebrus 0:0a673c671a56 30 #ifdef __cplusplus
ebrus 0:0a673c671a56 31 extern "C" {
ebrus 0:0a673c671a56 32 #endif
ebrus 0:0a673c671a56 33
ebrus 0:0a673c671a56 34
ebrus 0:0a673c671a56 35 /* ------------------------- Interrupt Number Definition ------------------------ */
ebrus 0:0a673c671a56 36
ebrus 0:0a673c671a56 37 typedef enum {
ebrus 0:0a673c671a56 38 /* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
ebrus 0:0a673c671a56 39 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
ebrus 0:0a673c671a56 40 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
ebrus 0:0a673c671a56 41 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
ebrus 0:0a673c671a56 42
ebrus 0:0a673c671a56 43
ebrus 0:0a673c671a56 44
ebrus 0:0a673c671a56 45 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
ebrus 0:0a673c671a56 46
ebrus 0:0a673c671a56 47
ebrus 0:0a673c671a56 48 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
ebrus 0:0a673c671a56 49 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
ebrus 0:0a673c671a56 50 /* --------------------- LPC11U6x Specific Interrupt Numbers -------------------- */
ebrus 0:0a673c671a56 51 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
ebrus 0:0a673c671a56 52 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
ebrus 0:0a673c671a56 53 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
ebrus 0:0a673c671a56 54 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
ebrus 0:0a673c671a56 55 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
ebrus 0:0a673c671a56 56 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
ebrus 0:0a673c671a56 57 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
ebrus 0:0a673c671a56 58 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
ebrus 0:0a673c671a56 59 GINT0_IRQn = 8, /*!< 8 GINT0 */
ebrus 0:0a673c671a56 60 GINT1_IRQn = 9, /*!< 9 GINT1 */
ebrus 0:0a673c671a56 61 I2C1_IRQn = 10, /*!< 10 I2C1 */
ebrus 0:0a673c671a56 62 USART1_4_IRQn = 11, /*!< 11 USART1_4 */
ebrus 0:0a673c671a56 63 USART2_3_IRQn = 12, /*!< 12 USART2_3 */
ebrus 0:0a673c671a56 64 SCT0_1_IRQn = 13, /*!< 13 SCT0_1 */
ebrus 0:0a673c671a56 65 SSP1_IRQn = 14, /*!< 14 SSP1 */
ebrus 0:0a673c671a56 66 I2C0_IRQn = 15, /*!< 15 I2C0 */
ebrus 0:0a673c671a56 67 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
ebrus 0:0a673c671a56 68 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
ebrus 0:0a673c671a56 69 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
ebrus 0:0a673c671a56 70 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
ebrus 0:0a673c671a56 71 SSP0_IRQn = 20, /*!< 20 SSP0 */
ebrus 0:0a673c671a56 72 USART0_IRQn = 21, /*!< 21 USART0 */
ebrus 0:0a673c671a56 73 USB_IRQn = 22, /*!< 22 USB */
ebrus 0:0a673c671a56 74 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
ebrus 0:0a673c671a56 75 ADC_A_IRQn = 24, /*!< 24 ADC_A */
ebrus 0:0a673c671a56 76 RTC_IRQn = 25, /*!< 25 RTC */
ebrus 0:0a673c671a56 77 BOD_WDT_IRQn = 26, /*!< 26 BOD_WDT */
ebrus 0:0a673c671a56 78 FLASH_IRQn = 27, /*!< 27 FLASH */
ebrus 0:0a673c671a56 79 DMA_IRQn = 28, /*!< 28 DMA */
ebrus 0:0a673c671a56 80 ADC_B_IRQn = 29, /*!< 29 ADC_B */
ebrus 0:0a673c671a56 81 USBWAKEUP_IRQn = 30 /*!< 30 USBWAKEUP */
ebrus 0:0a673c671a56 82 } IRQn_Type;
ebrus 0:0a673c671a56 83
ebrus 0:0a673c671a56 84
ebrus 0:0a673c671a56 85 /** @addtogroup Configuration_of_CMSIS
ebrus 0:0a673c671a56 86 * @{
ebrus 0:0a673c671a56 87 */
ebrus 0:0a673c671a56 88
ebrus 0:0a673c671a56 89
ebrus 0:0a673c671a56 90 /* ================================================================================ */
ebrus 0:0a673c671a56 91 /* ================ Processor and Core Peripheral Section ================ */
ebrus 0:0a673c671a56 92 /* ================================================================================ */
ebrus 0:0a673c671a56 93
ebrus 0:0a673c671a56 94 /* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
ebrus 0:0a673c671a56 95 #define __CM0PLUS_REV 0x0000 /*!< Cortex-M0PLUS Core Revision */
ebrus 0:0a673c671a56 96 #define __MPU_PRESENT 0 /*!< MPU present or not */
ebrus 0:0a673c671a56 97 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
ebrus 0:0a673c671a56 98 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
ebrus 0:0a673c671a56 99 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
ebrus 0:0a673c671a56 100 /** @} */ /* End of group Configuration_of_CMSIS */
ebrus 0:0a673c671a56 101
ebrus 0:0a673c671a56 102 #include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
ebrus 0:0a673c671a56 103 #include "system_LPC11U6x.h" /*!< LPC11U6x System */
ebrus 0:0a673c671a56 104
ebrus 0:0a673c671a56 105
ebrus 0:0a673c671a56 106 /* ================================================================================ */
ebrus 0:0a673c671a56 107 /* ================ Device Specific Peripheral Section ================ */
ebrus 0:0a673c671a56 108 /* ================================================================================ */
ebrus 0:0a673c671a56 109
ebrus 0:0a673c671a56 110
ebrus 0:0a673c671a56 111 /** @addtogroup Device_Peripheral_Registers
ebrus 0:0a673c671a56 112 * @{
ebrus 0:0a673c671a56 113 */
ebrus 0:0a673c671a56 114
ebrus 0:0a673c671a56 115
ebrus 0:0a673c671a56 116 /* ------------------- Start of section using anonymous unions ------------------ */
ebrus 0:0a673c671a56 117 #if defined(__CC_ARM)
ebrus 0:0a673c671a56 118 #pragma push
ebrus 0:0a673c671a56 119 #pragma anon_unions
ebrus 0:0a673c671a56 120 #elif defined(__ICCARM__)
ebrus 0:0a673c671a56 121 #pragma language=extended
ebrus 0:0a673c671a56 122 #elif defined(__GNUC__)
ebrus 0:0a673c671a56 123 /* anonymous unions are enabled by default */
ebrus 0:0a673c671a56 124 #elif defined(__TMS470__)
ebrus 0:0a673c671a56 125 /* anonymous unions are enabled by default */
ebrus 0:0a673c671a56 126 #elif defined(__TASKING__)
ebrus 0:0a673c671a56 127 #pragma warning 586
ebrus 0:0a673c671a56 128 #else
ebrus 0:0a673c671a56 129 #warning Not supported compiler type
ebrus 0:0a673c671a56 130 #endif
ebrus 0:0a673c671a56 131
ebrus 0:0a673c671a56 132
ebrus 0:0a673c671a56 133
ebrus 0:0a673c671a56 134 /* ================================================================================ */
ebrus 0:0a673c671a56 135 /* ================ I2C0 ================ */
ebrus 0:0a673c671a56 136 /* ================================================================================ */
ebrus 0:0a673c671a56 137
ebrus 0:0a673c671a56 138
ebrus 0:0a673c671a56 139 /**
ebrus 0:0a673c671a56 140 * @brief I2C-bus controller (I2C0)
ebrus 0:0a673c671a56 141 */
ebrus 0:0a673c671a56 142
ebrus 0:0a673c671a56 143 typedef struct { /*!< I2C0 Structure */
ebrus 0:0a673c671a56 144 __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of
ebrus 0:0a673c671a56 145 this register, the corresponding bit in the I2C control register
ebrus 0:0a673c671a56 146 is set. Writing a zero has no effect on the corresponding bit
ebrus 0:0a673c671a56 147 in the I2C control register. */
ebrus 0:0a673c671a56 148 __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides
ebrus 0:0a673c671a56 149 detailed status codes that allow software to determine the next
ebrus 0:0a673c671a56 150 action needed. */
ebrus 0:0a673c671a56 151 __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data
ebrus 0:0a673c671a56 152 to be transmitted is written to this register. During master
ebrus 0:0a673c671a56 153 or slave receive mode, data that has been received may be read
ebrus 0:0a673c671a56 154 from this register. */
ebrus 0:0a673c671a56 155 __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address
ebrus 0:0a673c671a56 156 for operation of the I2C interface in slave mode, and is not
ebrus 0:0a673c671a56 157 used in master mode. The least significant bit determines whether
ebrus 0:0a673c671a56 158 a slave responds to the General Call address. */
ebrus 0:0a673c671a56 159 __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high
ebrus 0:0a673c671a56 160 time of the I2C clock. */
ebrus 0:0a673c671a56 161 __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time
ebrus 0:0a673c671a56 162 of the I2C clock. I2nSCLL and I2nSCLH together determine the
ebrus 0:0a673c671a56 163 clock frequency generated by an I2C master and certain times
ebrus 0:0a673c671a56 164 used in slave mode. */
ebrus 0:0a673c671a56 165 __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of
ebrus 0:0a673c671a56 166 this register, the corresponding bit in the I2C control register
ebrus 0:0a673c671a56 167 is cleared. Writing a zero has no effect on the corresponding
ebrus 0:0a673c671a56 168 bit in the I2C control register. */
ebrus 0:0a673c671a56 169 __IO uint32_t MMCTRL; /*!< Monitor mode control register. */
ebrus 0:0a673c671a56 170 __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address
ebrus 0:0a673c671a56 171 for operation of the I2C interface in slave mode, and is not
ebrus 0:0a673c671a56 172 used in master mode. The least significant bit determines whether
ebrus 0:0a673c671a56 173 a slave responds to the General Call address. */
ebrus 0:0a673c671a56 174 __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address
ebrus 0:0a673c671a56 175 for operation of the I2C interface in slave mode, and is not
ebrus 0:0a673c671a56 176 used in master mode. The least significant bit determines whether
ebrus 0:0a673c671a56 177 a slave responds to the General Call address. */
ebrus 0:0a673c671a56 178 __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address
ebrus 0:0a673c671a56 179 for operation of the I2C interface in slave mode, and is not
ebrus 0:0a673c671a56 180 used in master mode. The least significant bit determines whether
ebrus 0:0a673c671a56 181 a slave responds to the General Call address. */
ebrus 0:0a673c671a56 182 __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the I2DAT
ebrus 0:0a673c671a56 183 shift register will be transferred to the DATA_BUFFER automatically
ebrus 0:0a673c671a56 184 after every nine bits (8 bits of data plus ACK or NACK) has
ebrus 0:0a673c671a56 185 been received on the bus. */
ebrus 0:0a673c671a56 186 __IO uint32_t MASK0; /*!< I2C Slave address mask register. This mask register is associated
ebrus 0:0a673c671a56 187 with I2ADR0 to determine an address match. The mask register
ebrus 0:0a673c671a56 188 has no effect when comparing to the General Call address (0000000). */
ebrus 0:0a673c671a56 189 __IO uint32_t MASK1; /*!< I2C Slave address mask register. This mask register is associated
ebrus 0:0a673c671a56 190 with I2ADR0 to determine an address match. The mask register
ebrus 0:0a673c671a56 191 has no effect when comparing to the General Call address (0000000). */
ebrus 0:0a673c671a56 192 __IO uint32_t MASK2; /*!< I2C Slave address mask register. This mask register is associated
ebrus 0:0a673c671a56 193 with I2ADR0 to determine an address match. The mask register
ebrus 0:0a673c671a56 194 has no effect when comparing to the General Call address (0000000). */
ebrus 0:0a673c671a56 195 __IO uint32_t MASK3; /*!< I2C Slave address mask register. This mask register is associated
ebrus 0:0a673c671a56 196 with I2ADR0 to determine an address match. The mask register
ebrus 0:0a673c671a56 197 has no effect when comparing to the General Call address (0000000). */
ebrus 0:0a673c671a56 198 } LPC_I2C0_Type;
ebrus 0:0a673c671a56 199
ebrus 0:0a673c671a56 200
ebrus 0:0a673c671a56 201 /* ================================================================================ */
ebrus 0:0a673c671a56 202 /* ================ WWDT ================ */
ebrus 0:0a673c671a56 203 /* ================================================================================ */
ebrus 0:0a673c671a56 204
ebrus 0:0a673c671a56 205
ebrus 0:0a673c671a56 206 /**
ebrus 0:0a673c671a56 207 * @brief Windowed Watchdog Timer (WWDT) (WWDT)
ebrus 0:0a673c671a56 208 */
ebrus 0:0a673c671a56 209
ebrus 0:0a673c671a56 210 typedef struct { /*!< WWDT Structure */
ebrus 0:0a673c671a56 211 __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
ebrus 0:0a673c671a56 212 and status of the Watchdog Timer. */
ebrus 0:0a673c671a56 213 __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
ebrus 0:0a673c671a56 214 the time-out value. */
ebrus 0:0a673c671a56 215 __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
ebrus 0:0a673c671a56 216 to this register reloads the Watchdog timer with the value contained
ebrus 0:0a673c671a56 217 in WDTC. */
ebrus 0:0a673c671a56 218 __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
ebrus 0:0a673c671a56 219 the current value of the Watchdog timer. */
ebrus 0:0a673c671a56 220 __IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
ebrus 0:0a673c671a56 221 __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
ebrus 0:0a673c671a56 222 __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
ebrus 0:0a673c671a56 223 } LPC_WWDT_Type;
ebrus 0:0a673c671a56 224
ebrus 0:0a673c671a56 225
ebrus 0:0a673c671a56 226 /* ================================================================================ */
ebrus 0:0a673c671a56 227 /* ================ USART0 ================ */
ebrus 0:0a673c671a56 228 /* ================================================================================ */
ebrus 0:0a673c671a56 229
ebrus 0:0a673c671a56 230
ebrus 0:0a673c671a56 231 /**
ebrus 0:0a673c671a56 232 * @brief USART0 (USART0)
ebrus 0:0a673c671a56 233 */
ebrus 0:0a673c671a56 234
ebrus 0:0a673c671a56 235 typedef struct { /*!< USART0 Structure */
ebrus 0:0a673c671a56 236
ebrus 0:0a673c671a56 237 union {
ebrus 0:0a673c671a56 238 __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor
ebrus 0:0a673c671a56 239 value. The full divisor is used to generate a baud rate from
ebrus 0:0a673c671a56 240 the fractional rate divider. (DLAB=1) */
ebrus 0:0a673c671a56 241 __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted
ebrus 0:0a673c671a56 242 is written here. (DLAB=0) */
ebrus 0:0a673c671a56 243 __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character
ebrus 0:0a673c671a56 244 to be read. (DLAB=0) */
ebrus 0:0a673c671a56 245 };
ebrus 0:0a673c671a56 246
ebrus 0:0a673c671a56 247 union {
ebrus 0:0a673c671a56 248 __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable
ebrus 0:0a673c671a56 249 bits for the 7 potential USART interrupts. (DLAB=0) */
ebrus 0:0a673c671a56 250 __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor
ebrus 0:0a673c671a56 251 value. The full divisor is used to generate a baud rate from
ebrus 0:0a673c671a56 252 the fractional rate divider. (DLAB=1) */
ebrus 0:0a673c671a56 253 };
ebrus 0:0a673c671a56 254
ebrus 0:0a673c671a56 255 union {
ebrus 0:0a673c671a56 256 __O uint32_t FCR; /*!< FIFO Control Register. Controls USART FIFO usage and modes. */
ebrus 0:0a673c671a56 257 __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
ebrus 0:0a673c671a56 258 };
ebrus 0:0a673c671a56 259 __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting
ebrus 0:0a673c671a56 260 and break generation. */
ebrus 0:0a673c671a56 261 __IO uint32_t MCR; /*!< Modem Control Register. */
ebrus 0:0a673c671a56 262 __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive
ebrus 0:0a673c671a56 263 status, including line errors. */
ebrus 0:0a673c671a56 264 __I uint32_t MSR; /*!< Modem Status Register. */
ebrus 0:0a673c671a56 265 __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
ebrus 0:0a673c671a56 266 __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud
ebrus 0:0a673c671a56 267 feature. */
ebrus 0:0a673c671a56 268 __IO uint32_t ICR; /*!< IrDA Control Register. Enables and configures the IrDA (remote
ebrus 0:0a673c671a56 269 control) mode. */
ebrus 0:0a673c671a56 270 __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the
ebrus 0:0a673c671a56 271 baud rate divider. */
ebrus 0:0a673c671a56 272 __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during
ebrus 0:0a673c671a56 273 each bit time. */
ebrus 0:0a673c671a56 274 __IO uint32_t TER; /*!< Transmit Enable Register. Turns off USART transmitter for use
ebrus 0:0a673c671a56 275 with software flow control. */
ebrus 0:0a673c671a56 276 __I uint32_t RESERVED0[3];
ebrus 0:0a673c671a56 277 __IO uint32_t HDEN; /*!< Half duplex enable register. */
ebrus 0:0a673c671a56 278 __I uint32_t RESERVED1;
ebrus 0:0a673c671a56 279 __IO uint32_t SCICTRL; /*!< Smart Card Interface Control register. Enables and configures
ebrus 0:0a673c671a56 280 the Smart Card Interface feature. */
ebrus 0:0a673c671a56 281 __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various
ebrus 0:0a673c671a56 282 aspects of RS-485/EIA-485 modes. */
ebrus 0:0a673c671a56 283 __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value
ebrus 0:0a673c671a56 284 for RS-485/EIA-485 mode. */
ebrus 0:0a673c671a56 285 __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
ebrus 0:0a673c671a56 286 __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. */
ebrus 0:0a673c671a56 287 } LPC_USART0_Type;
ebrus 0:0a673c671a56 288
ebrus 0:0a673c671a56 289
ebrus 0:0a673c671a56 290 /* ================================================================================ */
ebrus 0:0a673c671a56 291 /* ================ CT16B0 ================ */
ebrus 0:0a673c671a56 292 /* ================================================================================ */
ebrus 0:0a673c671a56 293
ebrus 0:0a673c671a56 294
ebrus 0:0a673c671a56 295 /**
ebrus 0:0a673c671a56 296 * @brief 16-bit counter/timers CT16B0 (CT16B0)
ebrus 0:0a673c671a56 297 */
ebrus 0:0a673c671a56 298
ebrus 0:0a673c671a56 299 typedef struct { /*!< CT16B0 Structure */
ebrus 0:0a673c671a56 300 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
ebrus 0:0a673c671a56 301 The IR can be read to identify which of eight possible interrupt
ebrus 0:0a673c671a56 302 sources are pending. */
ebrus 0:0a673c671a56 303 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
ebrus 0:0a673c671a56 304 Counter functions. The Timer Counter can be disabled or reset
ebrus 0:0a673c671a56 305 through the TCR. */
ebrus 0:0a673c671a56 306 __IO uint32_t TC; /*!< Timer Counter. The 16-bit TC is incremented every PR+1 cycles
ebrus 0:0a673c671a56 307 of PCLK. The TC is controlled through the TCR. */
ebrus 0:0a673c671a56 308 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
ebrus 0:0a673c671a56 309 to this value, the next clock increments the TC and clears the
ebrus 0:0a673c671a56 310 PC. */
ebrus 0:0a673c671a56 311 __IO uint32_t PC; /*!< Prescale Counter. The 16-bit PC is a counter which is incremented
ebrus 0:0a673c671a56 312 to the value stored in PR. When the value in PR is reached,
ebrus 0:0a673c671a56 313 the TC is incremented and the PC is cleared. The PC is observable
ebrus 0:0a673c671a56 314 and controllable through the bus interface. */
ebrus 0:0a673c671a56 315 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
ebrus 0:0a673c671a56 316 is generated and if the TC is reset when a Match occurs. */
ebrus 0:0a673c671a56 317 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
ebrus 0:0a673c671a56 318 TC, stop both the TC and PC, and/or generate an interrupt every
ebrus 0:0a673c671a56 319 time MR0 matches the TC. */
ebrus 0:0a673c671a56 320 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
ebrus 0:0a673c671a56 321 TC, stop both the TC and PC, and/or generate an interrupt every
ebrus 0:0a673c671a56 322 time MR0 matches the TC. */
ebrus 0:0a673c671a56 323 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
ebrus 0:0a673c671a56 324 TC, stop both the TC and PC, and/or generate an interrupt every
ebrus 0:0a673c671a56 325 time MR0 matches the TC. */
ebrus 0:0a673c671a56 326 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
ebrus 0:0a673c671a56 327 TC, stop both the TC and PC, and/or generate an interrupt every
ebrus 0:0a673c671a56 328 time MR0 matches the TC. */
ebrus 0:0a673c671a56 329 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
ebrus 0:0a673c671a56 330 capture inputs are used to load the Capture Registers and whether
ebrus 0:0a673c671a56 331 or not an interrupt is generated when a capture takes place. */
ebrus 0:0a673c671a56 332 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
ebrus 0:0a673c671a56 333 is an event on the CAP input. */
ebrus 0:0a673c671a56 334 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
ebrus 0:0a673c671a56 335 is an event on the CAP input. */
ebrus 0:0a673c671a56 336 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
ebrus 0:0a673c671a56 337 is an event on the CAP input. */
ebrus 0:0a673c671a56 338 __I uint32_t RESERVED0;
ebrus 0:0a673c671a56 339 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
ebrus 0:0a673c671a56 340 and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
ebrus 0:0a673c671a56 341 __I uint32_t RESERVED1[12];
ebrus 0:0a673c671a56 342 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
ebrus 0:0a673c671a56 343 mode, and in Counter mode selects the signal and edge(s) for
ebrus 0:0a673c671a56 344 counting. */
ebrus 0:0a673c671a56 345 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
ebrus 0:0a673c671a56 346 match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
ebrus 0:0a673c671a56 347 } LPC_CT16B0_Type;
ebrus 0:0a673c671a56 348
ebrus 0:0a673c671a56 349
ebrus 0:0a673c671a56 350 /* ================================================================================ */
ebrus 0:0a673c671a56 351 /* ================ CT32B0 ================ */
ebrus 0:0a673c671a56 352 /* ================================================================================ */
ebrus 0:0a673c671a56 353
ebrus 0:0a673c671a56 354
ebrus 0:0a673c671a56 355 /**
ebrus 0:0a673c671a56 356 * @brief 32-bit counter/timers CT32B0 (CT32B0)
ebrus 0:0a673c671a56 357 */
ebrus 0:0a673c671a56 358
ebrus 0:0a673c671a56 359 typedef struct { /*!< CT32B0 Structure */
ebrus 0:0a673c671a56 360 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
ebrus 0:0a673c671a56 361 The IR can be read to identify which of eight possible interrupt
ebrus 0:0a673c671a56 362 sources are pending. */
ebrus 0:0a673c671a56 363 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
ebrus 0:0a673c671a56 364 Counter functions. The Timer Counter can be disabled or reset
ebrus 0:0a673c671a56 365 through the TCR. */
ebrus 0:0a673c671a56 366 __IO uint32_t TC; /*!< Timer Counter. The 32-bit TC is incremented every PR+1 cycles
ebrus 0:0a673c671a56 367 of PCLK. The TC is controlled through the TCR. */
ebrus 0:0a673c671a56 368 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
ebrus 0:0a673c671a56 369 to this value, the next clock increments the TC and clears the
ebrus 0:0a673c671a56 370 PC. */
ebrus 0:0a673c671a56 371 __IO uint32_t PC; /*!< Prescale Counter. The 32-bit PC is a counter which is incremented
ebrus 0:0a673c671a56 372 to the value stored in PR. When the value in PR is reached,
ebrus 0:0a673c671a56 373 the TC is incremented and the PC is cleared. The PC is observable
ebrus 0:0a673c671a56 374 and controllable through the bus interface. */
ebrus 0:0a673c671a56 375 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
ebrus 0:0a673c671a56 376 is generated and if the TC is reset when a Match occurs. */
ebrus 0:0a673c671a56 377 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
ebrus 0:0a673c671a56 378 TC, stop both the TC and PC, and/or generate an interrupt every
ebrus 0:0a673c671a56 379 time MR0 matches the TC. */
ebrus 0:0a673c671a56 380 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
ebrus 0:0a673c671a56 381 TC, stop both the TC and PC, and/or generate an interrupt every
ebrus 0:0a673c671a56 382 time MR0 matches the TC. */
ebrus 0:0a673c671a56 383 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
ebrus 0:0a673c671a56 384 TC, stop both the TC and PC, and/or generate an interrupt every
ebrus 0:0a673c671a56 385 time MR0 matches the TC. */
ebrus 0:0a673c671a56 386 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
ebrus 0:0a673c671a56 387 TC, stop both the TC and PC, and/or generate an interrupt every
ebrus 0:0a673c671a56 388 time MR0 matches the TC. */
ebrus 0:0a673c671a56 389 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
ebrus 0:0a673c671a56 390 capture inputs are used to load the Capture Registers and whether
ebrus 0:0a673c671a56 391 or not an interrupt is generated when a capture takes place. */
ebrus 0:0a673c671a56 392 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
ebrus 0:0a673c671a56 393 is an event on the CAP input. */
ebrus 0:0a673c671a56 394 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
ebrus 0:0a673c671a56 395 is an event on the CAP input. */
ebrus 0:0a673c671a56 396 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
ebrus 0:0a673c671a56 397 is an event on the CAP input. */
ebrus 0:0a673c671a56 398 __I uint32_t RESERVED0;
ebrus 0:0a673c671a56 399 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
ebrus 0:0a673c671a56 400 and the external match pins CT32Bn_MAT[3:0]. */
ebrus 0:0a673c671a56 401 __I uint32_t RESERVED1[12];
ebrus 0:0a673c671a56 402 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
ebrus 0:0a673c671a56 403 mode, and in Counter mode selects the signal and edge(s) for
ebrus 0:0a673c671a56 404 counting. */
ebrus 0:0a673c671a56 405 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
ebrus 0:0a673c671a56 406 match pins CT32Bn_MAT[3:0]. */
ebrus 0:0a673c671a56 407 } LPC_CT32B0_Type;
ebrus 0:0a673c671a56 408
ebrus 0:0a673c671a56 409
ebrus 0:0a673c671a56 410 /* ================================================================================ */
ebrus 0:0a673c671a56 411 /* ================ ADC ================ */
ebrus 0:0a673c671a56 412 /* ================================================================================ */
ebrus 0:0a673c671a56 413
ebrus 0:0a673c671a56 414
ebrus 0:0a673c671a56 415 /**
ebrus 0:0a673c671a56 416 * @brief Product name title=Kylin UM Chapter title=Kylin12-bit Analog-to-Digital Converter (ADC) Modification date=5/13/2013 Major revision=0 Minor revision=1 (ADC)
ebrus 0:0a673c671a56 417 */
ebrus 0:0a673c671a56 418
ebrus 0:0a673c671a56 419 typedef struct { /*!< ADC Structure */
ebrus 0:0a673c671a56 420 __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
ebrus 0:0a673c671a56 421 bits for each sequence and the A/D power-down bit. */
ebrus 0:0a673c671a56 422 __I uint32_t RESERVED0;
ebrus 0:0a673c671a56 423 __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
ebrus 0:0a673c671a56 424 and channel selection for conversion sequence-A. Also specifies
ebrus 0:0a673c671a56 425 interrupt mode for sequence-A. */
ebrus 0:0a673c671a56 426 __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
ebrus 0:0a673c671a56 427 and channel selection for conversion sequence-B. Also specifies
ebrus 0:0a673c671a56 428 interrupt mode for sequence-B. */
ebrus 0:0a673c671a56 429 __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
ebrus 0:0a673c671a56 430 the result of the most recent A/D conversion performed under
ebrus 0:0a673c671a56 431 sequence-A */
ebrus 0:0a673c671a56 432 __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
ebrus 0:0a673c671a56 433 the result of the most recent A/D conversion performed under
ebrus 0:0a673c671a56 434 sequence-B */
ebrus 0:0a673c671a56 435 __I uint32_t RESERVED1[2];
ebrus 0:0a673c671a56 436 __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
ebrus 0:0a673c671a56 437 of the most recent conversion completed on channel 0. */
ebrus 0:0a673c671a56 438 __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
ebrus 0:0a673c671a56 439 level for automatic threshold comparison for any channels linked
ebrus 0:0a673c671a56 440 to threshold pair 0. */
ebrus 0:0a673c671a56 441 __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
ebrus 0:0a673c671a56 442 level for automatic threshold comparison for any channels linked
ebrus 0:0a673c671a56 443 to threshold pair 1. */
ebrus 0:0a673c671a56 444 __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
ebrus 0:0a673c671a56 445 level for automatic threshold comparison for any channels linked
ebrus 0:0a673c671a56 446 to threshold pair 0. */
ebrus 0:0a673c671a56 447 __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
ebrus 0:0a673c671a56 448 level for automatic threshold comparison for any channels linked
ebrus 0:0a673c671a56 449 to threshold pair 1. */
ebrus 0:0a673c671a56 450 __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
ebrus 0:0a673c671a56 451 threshold compare registers are to be used for each channel */
ebrus 0:0a673c671a56 452 __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
ebrus 0:0a673c671a56 453 bits that enable the sequence-A, sequence-B, threshold compare
ebrus 0:0a673c671a56 454 and data overrun interrupts to be generated. */
ebrus 0:0a673c671a56 455 __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
ebrus 0:0a673c671a56 456 and the individual component overrun and threshold-compare flags.
ebrus 0:0a673c671a56 457 (The overrun bits replicate information stored in the result
ebrus 0:0a673c671a56 458 registers). */
ebrus 0:0a673c671a56 459 __IO uint32_t TRM; /*!< ADC trim register. */
ebrus 0:0a673c671a56 460 } LPC_ADC_Type;
ebrus 0:0a673c671a56 461
ebrus 0:0a673c671a56 462
ebrus 0:0a673c671a56 463 /* ================================================================================ */
ebrus 0:0a673c671a56 464 /* ================ RTC ================ */
ebrus 0:0a673c671a56 465 /* ================================================================================ */
ebrus 0:0a673c671a56 466
ebrus 0:0a673c671a56 467
ebrus 0:0a673c671a56 468 /**
ebrus 0:0a673c671a56 469 * @brief Real-Time Clock (RTC) (RTC)
ebrus 0:0a673c671a56 470 */
ebrus 0:0a673c671a56 471
ebrus 0:0a673c671a56 472 typedef struct { /*!< RTC Structure */
ebrus 0:0a673c671a56 473 __IO uint32_t CTRL; /*!< RTC control register */
ebrus 0:0a673c671a56 474 __IO uint32_t MATCH; /*!< RTC match register */
ebrus 0:0a673c671a56 475 __IO uint32_t COUNT; /*!< RTC counter register */
ebrus 0:0a673c671a56 476 __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
ebrus 0:0a673c671a56 477 } LPC_RTC_Type;
ebrus 0:0a673c671a56 478
ebrus 0:0a673c671a56 479
ebrus 0:0a673c671a56 480 /* ================================================================================ */
ebrus 0:0a673c671a56 481 /* ================ DMATRIGMUX ================ */
ebrus 0:0a673c671a56 482 /* ================================================================================ */
ebrus 0:0a673c671a56 483
ebrus 0:0a673c671a56 484
ebrus 0:0a673c671a56 485 /**
ebrus 0:0a673c671a56 486 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMATRIGMUX)
ebrus 0:0a673c671a56 487 */
ebrus 0:0a673c671a56 488
ebrus 0:0a673c671a56 489 typedef struct { /*!< DMATRIGMUX Structure */
ebrus 0:0a673c671a56 490 __IO uint32_t DMA_ITRIG_PINMUX[16]; /*!< Trigger input select register for DMA channel 0. */
ebrus 0:0a673c671a56 491 } LPC_DMATRIGMUX_Type;
ebrus 0:0a673c671a56 492
ebrus 0:0a673c671a56 493
ebrus 0:0a673c671a56 494 /* ================================================================================ */
ebrus 0:0a673c671a56 495 /* ================ PMU ================ */
ebrus 0:0a673c671a56 496 /* ================================================================================ */
ebrus 0:0a673c671a56 497
ebrus 0:0a673c671a56 498
ebrus 0:0a673c671a56 499 /**
ebrus 0:0a673c671a56 500 * @brief Product name title=Kylin UM Chapter title=KylinPower Management Unit (PMU) Modification date=5/13/2013 Major revision=0 Minor revision=1 (PMU)
ebrus 0:0a673c671a56 501 */
ebrus 0:0a673c671a56 502
ebrus 0:0a673c671a56 503 typedef struct { /*!< PMU Structure */
ebrus 0:0a673c671a56 504 __IO uint32_t PCON; /*!< Power control register */
ebrus 0:0a673c671a56 505 __IO uint32_t GPREG0; /*!< General purpose register 0 */
ebrus 0:0a673c671a56 506 __IO uint32_t GPREG1; /*!< General purpose register 0 */
ebrus 0:0a673c671a56 507 __IO uint32_t GPREG2; /*!< General purpose register 0 */
ebrus 0:0a673c671a56 508 __IO uint32_t GPREG3; /*!< General purpose register 0 */
ebrus 0:0a673c671a56 509 __IO uint32_t DPDCTRL; /*!< Deep power down control register */
ebrus 0:0a673c671a56 510 } LPC_PMU_Type;
ebrus 0:0a673c671a56 511
ebrus 0:0a673c671a56 512
ebrus 0:0a673c671a56 513 /* ================================================================================ */
ebrus 0:0a673c671a56 514 /* ================ FLASHCTRL ================ */
ebrus 0:0a673c671a56 515 /* ================================================================================ */
ebrus 0:0a673c671a56 516
ebrus 0:0a673c671a56 517
ebrus 0:0a673c671a56 518 /**
ebrus 0:0a673c671a56 519 * @brief Flash controller (FLASHCTRL)
ebrus 0:0a673c671a56 520 */
ebrus 0:0a673c671a56 521
ebrus 0:0a673c671a56 522 typedef struct { /*!< FLASHCTRL Structure */
ebrus 0:0a673c671a56 523 __I uint32_t RESERVED0[4];
ebrus 0:0a673c671a56 524 __IO uint32_t FLASHCFG; /*!< Flash configuration register */
ebrus 0:0a673c671a56 525 __I uint32_t RESERVED1[3];
ebrus 0:0a673c671a56 526 __IO uint32_t FMSSTART; /*!< Signature start address register */
ebrus 0:0a673c671a56 527 __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
ebrus 0:0a673c671a56 528 __I uint32_t RESERVED2;
ebrus 0:0a673c671a56 529 __I uint32_t FMSW0; /*!< Signature Word */
ebrus 0:0a673c671a56 530 } LPC_FLASHCTRL_Type;
ebrus 0:0a673c671a56 531
ebrus 0:0a673c671a56 532
ebrus 0:0a673c671a56 533 /* ================================================================================ */
ebrus 0:0a673c671a56 534 /* ================ SSP0 ================ */
ebrus 0:0a673c671a56 535 /* ================================================================================ */
ebrus 0:0a673c671a56 536
ebrus 0:0a673c671a56 537
ebrus 0:0a673c671a56 538 /**
ebrus 0:0a673c671a56 539 * @brief SSP/SPI (SSP0)
ebrus 0:0a673c671a56 540 */
ebrus 0:0a673c671a56 541
ebrus 0:0a673c671a56 542 typedef struct { /*!< SSP0 Structure */
ebrus 0:0a673c671a56 543 __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type,
ebrus 0:0a673c671a56 544 and data size. */
ebrus 0:0a673c671a56 545 __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
ebrus 0:0a673c671a56 546 __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty
ebrus 0:0a673c671a56 547 the receive FIFO. */
ebrus 0:0a673c671a56 548 __I uint32_t SR; /*!< Status Register */
ebrus 0:0a673c671a56 549 __IO uint32_t CPSR; /*!< Clock Prescale Register */
ebrus 0:0a673c671a56 550 __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
ebrus 0:0a673c671a56 551 __I uint32_t RIS; /*!< Raw Interrupt Status Register */
ebrus 0:0a673c671a56 552 __I uint32_t MIS; /*!< Masked Interrupt Status Register */
ebrus 0:0a673c671a56 553 __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
ebrus 0:0a673c671a56 554 } LPC_SSP0_Type;
ebrus 0:0a673c671a56 555
ebrus 0:0a673c671a56 556
ebrus 0:0a673c671a56 557 /* ================================================================================ */
ebrus 0:0a673c671a56 558 /* ================ IOCON ================ */
ebrus 0:0a673c671a56 559 /* ================================================================================ */
ebrus 0:0a673c671a56 560
ebrus 0:0a673c671a56 561
ebrus 0:0a673c671a56 562 /**
ebrus 0:0a673c671a56 563 * @brief Product name title=Kylin UM Chapter title=KylinI/O control (IOCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (IOCON)
ebrus 0:0a673c671a56 564 */
ebrus 0:0a673c671a56 565
ebrus 0:0a673c671a56 566 typedef struct { /*!< IOCON Structure */
ebrus 0:0a673c671a56 567 __IO uint32_t PIO0_0; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 568 __IO uint32_t PIO0_1; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 569 __IO uint32_t PIO0_2; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 570 __IO uint32_t PIO0_3; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 571 __IO uint32_t PIO0_4; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 572 __IO uint32_t PIO0_5; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 573 __IO uint32_t PIO0_6; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 574 __IO uint32_t PIO0_7; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 575 __IO uint32_t PIO0_8; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 576 __IO uint32_t PIO0_9; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 577 __IO uint32_t PIO0_10; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 578 __IO uint32_t PIO0_11; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 579 __IO uint32_t PIO0_12; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 580 __IO uint32_t PIO0_13; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 581 __IO uint32_t PIO0_14; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 582 __IO uint32_t PIO0_15; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 583 __IO uint32_t PIO0_16; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 584 __IO uint32_t PIO0_17; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 585 __IO uint32_t PIO0_18; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 586 __IO uint32_t PIO0_19; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 587 __IO uint32_t PIO0_20; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 588 __IO uint32_t PIO0_21; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 589 __IO uint32_t PIO0_22; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 590 __IO uint32_t PIO0_23; /*!< I/O configuration for port PIO0 */
ebrus 0:0a673c671a56 591 __IO uint32_t PIO1_0; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 592 __IO uint32_t PIO1_1; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 593 __IO uint32_t PIO1_2; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 594 __IO uint32_t PIO1_3; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 595 __IO uint32_t PIO1_4; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 596 __IO uint32_t PIO1_5; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 597 __IO uint32_t PIO1_6; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 598 __IO uint32_t PIO1_7; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 599 __IO uint32_t PIO1_8; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 600 __IO uint32_t PIO1_9; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 601 __IO uint32_t PIO1_10; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 602 __IO uint32_t PIO1_11; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 603 __IO uint32_t PIO1_12; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 604 __IO uint32_t PIO1_13; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 605 __IO uint32_t PIO1_14; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 606 __IO uint32_t PIO1_15; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 607 __IO uint32_t PIO1_16; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 608 __IO uint32_t PIO1_17; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 609 __IO uint32_t PIO1_18; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 610 __IO uint32_t PIO1_19; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 611 __IO uint32_t PIO1_20; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 612 __IO uint32_t PIO1_21; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 613 __IO uint32_t PIO1_22; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 614 __IO uint32_t PIO1_23; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 615 __IO uint32_t PIO1_24; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 616 __IO uint32_t PIO1_25; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 617 __IO uint32_t PIO1_26; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 618 __IO uint32_t PIO1_27; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 619 __IO uint32_t PIO1_28; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 620 __IO uint32_t PIO1_29; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 621 __IO uint32_t PIO1_30; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 622 __IO uint32_t PIO1_31; /*!< I/O configuration for port PIO1 */
ebrus 0:0a673c671a56 623 __I uint32_t RESERVED0[4];
ebrus 0:0a673c671a56 624 __IO uint32_t PIO2_0; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 625 __IO uint32_t PIO2_1; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 626 __I uint32_t RESERVED1;
ebrus 0:0a673c671a56 627 __IO uint32_t PIO2_2; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 628 __IO uint32_t PIO2_3; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 629 __IO uint32_t PIO2_4; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 630 __IO uint32_t PIO2_5; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 631 __IO uint32_t PIO2_6; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 632 __IO uint32_t PIO2_7; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 633 __IO uint32_t PIO2_8; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 634 __IO uint32_t PIO2_9; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 635 __IO uint32_t PIO2_10; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 636 __IO uint32_t PIO2_11; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 637 __IO uint32_t PIO2_12; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 638 __IO uint32_t PIO2_13; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 639 __IO uint32_t PIO2_14; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 640 __IO uint32_t PIO2_15; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 641 __IO uint32_t PIO2_16; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 642 __IO uint32_t PIO2_17; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 643 __IO uint32_t PIO2_18; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 644 __IO uint32_t PIO2_19; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 645 __IO uint32_t PIO2_20; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 646 __IO uint32_t PIO2_21; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 647 __IO uint32_t PIO2_22; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 648 __IO uint32_t PIO2_23; /*!< I/O configuration for port PIO2 */
ebrus 0:0a673c671a56 649 } LPC_IOCON_Type;
ebrus 0:0a673c671a56 650
ebrus 0:0a673c671a56 651
ebrus 0:0a673c671a56 652 /* ================================================================================ */
ebrus 0:0a673c671a56 653 /* ================ SYSCON ================ */
ebrus 0:0a673c671a56 654 /* ================================================================================ */
ebrus 0:0a673c671a56 655
ebrus 0:0a673c671a56 656
ebrus 0:0a673c671a56 657 /**
ebrus 0:0a673c671a56 658 * @brief Product name title=Kylin UM Chapter title=KylinSystem configuration (SYSCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (SYSCON)
ebrus 0:0a673c671a56 659 */
ebrus 0:0a673c671a56 660
ebrus 0:0a673c671a56 661 typedef struct { /*!< SYSCON Structure */
ebrus 0:0a673c671a56 662 __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
ebrus 0:0a673c671a56 663 __IO uint32_t PRESETCTRL; /*!< Peripheral reset control */
ebrus 0:0a673c671a56 664 __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
ebrus 0:0a673c671a56 665 __I uint32_t SYSPLLSTAT; /*!< System PLL status */
ebrus 0:0a673c671a56 666 __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
ebrus 0:0a673c671a56 667 __I uint32_t USBPLLSTAT; /*!< USB PLL status */
ebrus 0:0a673c671a56 668 __I uint32_t RESERVED0;
ebrus 0:0a673c671a56 669 __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator 32 kHz output control */
ebrus 0:0a673c671a56 670 __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
ebrus 0:0a673c671a56 671 __IO uint32_t WDTOSCCTRL; /*!< Watchdog oscillator control */
ebrus 0:0a673c671a56 672 __I uint32_t RESERVED1[2];
ebrus 0:0a673c671a56 673 __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
ebrus 0:0a673c671a56 674 __I uint32_t RESERVED2[3];
ebrus 0:0a673c671a56 675 __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
ebrus 0:0a673c671a56 676 __IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable */
ebrus 0:0a673c671a56 677 __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
ebrus 0:0a673c671a56 678 __IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable */
ebrus 0:0a673c671a56 679 __I uint32_t RESERVED3[8];
ebrus 0:0a673c671a56 680 __IO uint32_t MAINCLKSEL; /*!< Main clock source select */
ebrus 0:0a673c671a56 681 __IO uint32_t MAINCLKUEN; /*!< Main clock source update enable */
ebrus 0:0a673c671a56 682 __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
ebrus 0:0a673c671a56 683 __I uint32_t RESERVED4;
ebrus 0:0a673c671a56 684 __IO uint32_t SYSAHBCLKCTRL; /*!< System clock control */
ebrus 0:0a673c671a56 685 __I uint32_t RESERVED5[4];
ebrus 0:0a673c671a56 686 __IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider */
ebrus 0:0a673c671a56 687 __IO uint32_t USART0CLKDIV; /*!< USART0 clock divider */
ebrus 0:0a673c671a56 688 __IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider */
ebrus 0:0a673c671a56 689 __IO uint32_t FRGCLKDIV; /*!< Clock divider for the common fractional baud rate generator
ebrus 0:0a673c671a56 690 of USART1 to USART4 */
ebrus 0:0a673c671a56 691 __I uint32_t RESERVED6[7];
ebrus 0:0a673c671a56 692 __IO uint32_t USBCLKSEL; /*!< USB clock source select */
ebrus 0:0a673c671a56 693 __IO uint32_t USBCLKUEN; /*!< USB clock source update enable */
ebrus 0:0a673c671a56 694 __IO uint32_t USBCLKDIV; /*!< USB clock source divider */
ebrus 0:0a673c671a56 695 __I uint32_t RESERVED7[5];
ebrus 0:0a673c671a56 696 __IO uint32_t CLKOUTSEL; /*!< CLKOUT clock source select */
ebrus 0:0a673c671a56 697 __IO uint32_t CLKOUTUEN; /*!< CLKOUT clock source update enable */
ebrus 0:0a673c671a56 698 __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
ebrus 0:0a673c671a56 699 __I uint32_t RESERVED8;
ebrus 0:0a673c671a56 700 __IO uint32_t UARTFRGDIV; /*!< USART fractional generator divider value */
ebrus 0:0a673c671a56 701 __IO uint32_t UARTFRGMULT; /*!< USART fractional generator multiplier value */
ebrus 0:0a673c671a56 702 __I uint32_t RESERVED9;
ebrus 0:0a673c671a56 703 __IO uint32_t EXTTRACECMD; /*!< External trace buffer command register */
ebrus 0:0a673c671a56 704 __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
ebrus 0:0a673c671a56 705 __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
ebrus 0:0a673c671a56 706 __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 1 */
ebrus 0:0a673c671a56 707 __I uint32_t RESERVED10[10];
ebrus 0:0a673c671a56 708 __IO uint32_t IOCONCLKDIV6; /*!< Peripheral clock 6 to the IOCON block for programmable glitch
ebrus 0:0a673c671a56 709 filter */
ebrus 0:0a673c671a56 710 __IO uint32_t IOCONCLKDIV5; /*!< Peripheral clock 5 to the IOCON block for programmable glitch
ebrus 0:0a673c671a56 711 filter */
ebrus 0:0a673c671a56 712 __IO uint32_t IOCONCLKDIV4; /*!< Peripheral clock 4 to the IOCON block for programmable glitch
ebrus 0:0a673c671a56 713 filter */
ebrus 0:0a673c671a56 714 __IO uint32_t IOCONCLKDIV3; /*!< Peripheral clock 3 to the IOCON block for programmable glitch
ebrus 0:0a673c671a56 715 filter */
ebrus 0:0a673c671a56 716 __IO uint32_t IOCONCLKDIV2; /*!< Peripheral clock 2 to the IOCON block for programmable glitch
ebrus 0:0a673c671a56 717 filter */
ebrus 0:0a673c671a56 718 __IO uint32_t IOCONCLKDIV1; /*!< Peripheral clock 1 to the IOCON block for programmable glitch
ebrus 0:0a673c671a56 719 filter */
ebrus 0:0a673c671a56 720 __IO uint32_t IOCONCLKDIV0; /*!< Peripheral clock 0 to the IOCON block for programmable glitch
ebrus 0:0a673c671a56 721 filter */
ebrus 0:0a673c671a56 722 __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
ebrus 0:0a673c671a56 723 __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
ebrus 0:0a673c671a56 724 __IO uint32_t AHBMATRIXPRIO; /*!< AHB matrix priority configuration */
ebrus 0:0a673c671a56 725 __I uint32_t RESERVED11[5];
ebrus 0:0a673c671a56 726 __IO uint32_t IRQLATENCY; /*!< IRQ delay. Allows trade-off between interrupt latency and determinism. */
ebrus 0:0a673c671a56 727 __IO uint32_t NMISRC; /*!< NMI Source Control */
ebrus 0:0a673c671a56 728 union {
ebrus 0:0a673c671a56 729 __IO uint32_t PINTSEL[8];
ebrus 0:0a673c671a56 730 struct {
ebrus 0:0a673c671a56 731 __IO uint32_t PINTSEL0; /*!< GPIO Pin Interrupt Select register 0 */
ebrus 0:0a673c671a56 732 __IO uint32_t PINTSEL1; /*!< GPIO Pin Interrupt Select register 0 */
ebrus 0:0a673c671a56 733 __IO uint32_t PINTSEL2; /*!< GPIO Pin Interrupt Select register 0 */
ebrus 0:0a673c671a56 734 __IO uint32_t PINTSEL3; /*!< GPIO Pin Interrupt Select register 0 */
ebrus 0:0a673c671a56 735 __IO uint32_t PINTSEL4; /*!< GPIO Pin Interrupt Select register 0 */
ebrus 0:0a673c671a56 736 __IO uint32_t PINTSEL5; /*!< GPIO Pin Interrupt Select register 0 */
ebrus 0:0a673c671a56 737 __IO uint32_t PINTSEL6; /*!< GPIO Pin Interrupt Select register 0 */
ebrus 0:0a673c671a56 738 __IO uint32_t PINTSEL7; /*!< GPIO Pin Interrupt Select register 0 */
ebrus 0:0a673c671a56 739 };
ebrus 0:0a673c671a56 740 };
ebrus 0:0a673c671a56 741 __IO uint32_t USBCLKCTRL; /*!< USB clock control */
ebrus 0:0a673c671a56 742 __I uint32_t USBCLKST; /*!< USB clock status */
ebrus 0:0a673c671a56 743 __I uint32_t RESERVED12[25];
ebrus 0:0a673c671a56 744 __IO uint32_t STARTERP0; /*!< Start logic 0 interrupt wake-up enable register 0 */
ebrus 0:0a673c671a56 745 __I uint32_t RESERVED13[3];
ebrus 0:0a673c671a56 746 __IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake-up enable register 1 */
ebrus 0:0a673c671a56 747 __I uint32_t RESERVED14[6];
ebrus 0:0a673c671a56 748 __IO uint32_t PDSLEEPCFG; /*!< Power-down states in deep-sleep mode */
ebrus 0:0a673c671a56 749 __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
ebrus 0:0a673c671a56 750 __IO uint32_t PDRUNCFG; /*!< Power configuration register */
ebrus 0:0a673c671a56 751 __I uint32_t RESERVED15[110];
ebrus 0:0a673c671a56 752 __I uint32_t DEVICE_ID; /*!< Device ID */
ebrus 0:0a673c671a56 753 } LPC_SYSCON_Type;
ebrus 0:0a673c671a56 754
ebrus 0:0a673c671a56 755
ebrus 0:0a673c671a56 756 /* ================================================================================ */
ebrus 0:0a673c671a56 757 /* ================ USART4 ================ */
ebrus 0:0a673c671a56 758 /* ================================================================================ */
ebrus 0:0a673c671a56 759
ebrus 0:0a673c671a56 760
ebrus 0:0a673c671a56 761 /**
ebrus 0:0a673c671a56 762 * @brief USART4 (USART4)
ebrus 0:0a673c671a56 763 */
ebrus 0:0a673c671a56 764
ebrus 0:0a673c671a56 765 typedef struct { /*!< USART4 Structure */
ebrus 0:0a673c671a56 766 __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
ebrus 0:0a673c671a56 767 that typically are not changed during operation. */
ebrus 0:0a673c671a56 768 __IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
ebrus 0:0a673c671a56 769 likely to change during operation. */
ebrus 0:0a673c671a56 770 __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
ebrus 0:0a673c671a56 771 here. Writing ones clears some bits in the register. Some bits
ebrus 0:0a673c671a56 772 can be cleared by writing a 1 to them. */
ebrus 0:0a673c671a56 773 __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
ebrus 0:0a673c671a56 774 interrupt enable bit for each potential USART interrupt. A complete
ebrus 0:0a673c671a56 775 value may be read from this register. Writing a 1 to any implemented
ebrus 0:0a673c671a56 776 bit position causes that bit to be set. */
ebrus 0:0a673c671a56 777 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
ebrus 0:0a673c671a56 778 of bits in the INTENSET register. Writing a 1 to any implemented
ebrus 0:0a673c671a56 779 bit position causes the corresponding bit to be cleared. */
ebrus 0:0a673c671a56 780 __I uint32_t RXDAT; /*!< Receiver Data register. Contains the last character received. */
ebrus 0:0a673c671a56 781 __I uint32_t RXDATSTAT; /*!< Receiver Data with Status register. Combines the last character
ebrus 0:0a673c671a56 782 received with the current USART receive status. Allows DMA or
ebrus 0:0a673c671a56 783 software to recover incoming data and status together. */
ebrus 0:0a673c671a56 784 __IO uint32_t TXDAT; /*!< Transmit Data register. Data to be transmitted is written here. */
ebrus 0:0a673c671a56 785 __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
ebrus 0:0a673c671a56 786 value. */
ebrus 0:0a673c671a56 787 __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
ebrus 0:0a673c671a56 788 enabled. */
ebrus 0:0a673c671a56 789 __IO uint32_t OSR; /*!< Oversample selection register for asynchronous communication. */
ebrus 0:0a673c671a56 790 __IO uint32_t ADDR; /*!< Address register for automatic address matching. */
ebrus 0:0a673c671a56 791 } LPC_USART4_Type;
ebrus 0:0a673c671a56 792
ebrus 0:0a673c671a56 793
ebrus 0:0a673c671a56 794 /* ================================================================================ */
ebrus 0:0a673c671a56 795 /* ================ GINT0 ================ */
ebrus 0:0a673c671a56 796 /* ================================================================================ */
ebrus 0:0a673c671a56 797
ebrus 0:0a673c671a56 798
ebrus 0:0a673c671a56 799 /**
ebrus 0:0a673c671a56 800 * @brief GPIO group interrupt 0 (GINT0)
ebrus 0:0a673c671a56 801 */
ebrus 0:0a673c671a56 802
ebrus 0:0a673c671a56 803 typedef struct { /*!< GINT0 Structure */
ebrus 0:0a673c671a56 804 __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
ebrus 0:0a673c671a56 805 __I uint32_t RESERVED0[7];
ebrus 0:0a673c671a56 806 __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
ebrus 0:0a673c671a56 807 __I uint32_t RESERVED1[5];
ebrus 0:0a673c671a56 808 __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port enable register */
ebrus 0:0a673c671a56 809 } LPC_GINT0_Type;
ebrus 0:0a673c671a56 810
ebrus 0:0a673c671a56 811
ebrus 0:0a673c671a56 812 /* ================================================================================ */
ebrus 0:0a673c671a56 813 /* ================ USB ================ */
ebrus 0:0a673c671a56 814 /* ================================================================================ */
ebrus 0:0a673c671a56 815
ebrus 0:0a673c671a56 816
ebrus 0:0a673c671a56 817 /**
ebrus 0:0a673c671a56 818 * @brief USB device controller (USB)
ebrus 0:0a673c671a56 819 */
ebrus 0:0a673c671a56 820
ebrus 0:0a673c671a56 821 typedef struct { /*!< USB Structure */
ebrus 0:0a673c671a56 822 __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
ebrus 0:0a673c671a56 823 __IO uint32_t INFO; /*!< USB Info register */
ebrus 0:0a673c671a56 824 __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
ebrus 0:0a673c671a56 825 __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
ebrus 0:0a673c671a56 826 __IO uint32_t LPM; /*!< Link Power Management register */
ebrus 0:0a673c671a56 827 __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
ebrus 0:0a673c671a56 828 __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
ebrus 0:0a673c671a56 829 __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
ebrus 0:0a673c671a56 830 __IO uint32_t INTSTAT; /*!< USB interrupt status register */
ebrus 0:0a673c671a56 831 __IO uint32_t INTEN; /*!< USB interrupt enable register */
ebrus 0:0a673c671a56 832 __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
ebrus 0:0a673c671a56 833 __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
ebrus 0:0a673c671a56 834 __I uint32_t RESERVED0;
ebrus 0:0a673c671a56 835 __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
ebrus 0:0a673c671a56 836 } LPC_USB_Type;
ebrus 0:0a673c671a56 837
ebrus 0:0a673c671a56 838
ebrus 0:0a673c671a56 839 /* ================================================================================ */
ebrus 0:0a673c671a56 840 /* ================ CRC ================ */
ebrus 0:0a673c671a56 841 /* ================================================================================ */
ebrus 0:0a673c671a56 842
ebrus 0:0a673c671a56 843
ebrus 0:0a673c671a56 844 /**
ebrus 0:0a673c671a56 845 * @brief Cyclic Redundancy Check (CRC) engine (CRC)
ebrus 0:0a673c671a56 846 */
ebrus 0:0a673c671a56 847
ebrus 0:0a673c671a56 848 typedef struct { /*!< CRC Structure */
ebrus 0:0a673c671a56 849 __IO uint32_t MODE; /*!< CRC mode register */
ebrus 0:0a673c671a56 850 __IO uint32_t SEED; /*!< CRC seed register */
ebrus 0:0a673c671a56 851
ebrus 0:0a673c671a56 852 union {
ebrus 0:0a673c671a56 853 __O uint32_t WR_DATA; /*!< CRC data register */
ebrus 0:0a673c671a56 854 __I uint32_t SUM; /*!< CRC checksum register */
ebrus 0:0a673c671a56 855 };
ebrus 0:0a673c671a56 856 } LPC_CRC_Type;
ebrus 0:0a673c671a56 857
ebrus 0:0a673c671a56 858
ebrus 0:0a673c671a56 859 /* ================================================================================ */
ebrus 0:0a673c671a56 860 /* ================ DMA ================ */
ebrus 0:0a673c671a56 861 /* ================================================================================ */
ebrus 0:0a673c671a56 862
ebrus 0:0a673c671a56 863
ebrus 0:0a673c671a56 864 /**
ebrus 0:0a673c671a56 865 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMA)
ebrus 0:0a673c671a56 866 */
ebrus 0:0a673c671a56 867
ebrus 0:0a673c671a56 868 typedef struct { /*!< DMA Structure */
ebrus 0:0a673c671a56 869 __IO uint32_t CTRL; /*!< DMA control. */
ebrus 0:0a673c671a56 870 __I uint32_t INTSTAT; /*!< Interrupt status. */
ebrus 0:0a673c671a56 871 __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
ebrus 0:0a673c671a56 872 __I uint32_t RESERVED0[5];
ebrus 0:0a673c671a56 873 __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
ebrus 0:0a673c671a56 874 __I uint32_t RESERVED1;
ebrus 0:0a673c671a56 875 __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
ebrus 0:0a673c671a56 876 __I uint32_t RESERVED2;
ebrus 0:0a673c671a56 877 __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
ebrus 0:0a673c671a56 878 __I uint32_t RESERVED3;
ebrus 0:0a673c671a56 879 __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
ebrus 0:0a673c671a56 880 __I uint32_t RESERVED4;
ebrus 0:0a673c671a56 881 __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
ebrus 0:0a673c671a56 882 __I uint32_t RESERVED5;
ebrus 0:0a673c671a56 883 __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
ebrus 0:0a673c671a56 884 __I uint32_t RESERVED6;
ebrus 0:0a673c671a56 885 __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
ebrus 0:0a673c671a56 886 __I uint32_t RESERVED7;
ebrus 0:0a673c671a56 887 __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
ebrus 0:0a673c671a56 888 __I uint32_t RESERVED8;
ebrus 0:0a673c671a56 889 __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
ebrus 0:0a673c671a56 890 __I uint32_t RESERVED9;
ebrus 0:0a673c671a56 891 __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
ebrus 0:0a673c671a56 892 __I uint32_t RESERVED10;
ebrus 0:0a673c671a56 893 __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
ebrus 0:0a673c671a56 894 __I uint32_t RESERVED11;
ebrus 0:0a673c671a56 895 __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
ebrus 0:0a673c671a56 896 __I uint32_t RESERVED12[225];
ebrus 0:0a673c671a56 897 __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 898 __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 899 __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 900 __I uint32_t RESERVED13;
ebrus 0:0a673c671a56 901 __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 902 __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 903 __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 904 __I uint32_t RESERVED14;
ebrus 0:0a673c671a56 905 __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 906 __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 907 __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 908 __I uint32_t RESERVED15;
ebrus 0:0a673c671a56 909 __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 910 __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 911 __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 912 __I uint32_t RESERVED16;
ebrus 0:0a673c671a56 913 __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 914 __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 915 __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 916 __I uint32_t RESERVED17;
ebrus 0:0a673c671a56 917 __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 918 __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 919 __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 920 __I uint32_t RESERVED18;
ebrus 0:0a673c671a56 921 __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 922 __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 923 __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 924 __I uint32_t RESERVED19;
ebrus 0:0a673c671a56 925 __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 926 __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 927 __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 928 __I uint32_t RESERVED20;
ebrus 0:0a673c671a56 929 __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 930 __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 931 __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 932 __I uint32_t RESERVED21;
ebrus 0:0a673c671a56 933 __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 934 __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 935 __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 936 __I uint32_t RESERVED22;
ebrus 0:0a673c671a56 937 __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 938 __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 939 __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 940 __I uint32_t RESERVED23;
ebrus 0:0a673c671a56 941 __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 942 __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 943 __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 944 __I uint32_t RESERVED24;
ebrus 0:0a673c671a56 945 __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 946 __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 947 __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 948 __I uint32_t RESERVED25;
ebrus 0:0a673c671a56 949 __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 950 __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 951 __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 952 __I uint32_t RESERVED26;
ebrus 0:0a673c671a56 953 __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 954 __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 955 __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 956 __I uint32_t RESERVED27;
ebrus 0:0a673c671a56 957 __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 958 __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
ebrus 0:0a673c671a56 959 __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
ebrus 0:0a673c671a56 960 } LPC_DMA_Type;
ebrus 0:0a673c671a56 961
ebrus 0:0a673c671a56 962
ebrus 0:0a673c671a56 963 /* ================================================================================ */
ebrus 0:0a673c671a56 964 /* ================ SCT0 ================ */
ebrus 0:0a673c671a56 965 /* ================================================================================ */
ebrus 0:0a673c671a56 966
ebrus 0:0a673c671a56 967
ebrus 0:0a673c671a56 968 /**
ebrus 0:0a673c671a56 969 * @brief Product name title=Kylin UM Chapter title=KylinState Configurable Timers (SCT0/1) Modification date=5/14/2013 Major revision=0 Minor revision=1 (SCT0)
ebrus 0:0a673c671a56 970 */
ebrus 0:0a673c671a56 971
ebrus 0:0a673c671a56 972 typedef struct { /*!< SCT0 Structure */
ebrus 0:0a673c671a56 973 __IO uint32_t CONFIG; /*!< SCT configuration register */
ebrus 0:0a673c671a56 974 __IO uint32_t CTRL; /*!< SCT control register */
ebrus 0:0a673c671a56 975 __IO uint32_t LIMIT; /*!< SCT limit register */
ebrus 0:0a673c671a56 976 __IO uint32_t HALT; /*!< SCT halt condition register */
ebrus 0:0a673c671a56 977 __IO uint32_t STOP; /*!< SCT stop condition register */
ebrus 0:0a673c671a56 978 __IO uint32_t START; /*!< SCT start condition register */
ebrus 0:0a673c671a56 979 __I uint32_t RESERVED0[10];
ebrus 0:0a673c671a56 980 __IO uint32_t COUNT; /*!< SCT counter register */
ebrus 0:0a673c671a56 981 __IO uint32_t STATE; /*!< SCT state register */
ebrus 0:0a673c671a56 982 __I uint32_t INPUT; /*!< SCT input register */
ebrus 0:0a673c671a56 983 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
ebrus 0:0a673c671a56 984 __IO uint32_t OUTPUT; /*!< SCT output register */
ebrus 0:0a673c671a56 985 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
ebrus 0:0a673c671a56 986 __IO uint32_t RES; /*!< SCT conflict resolution register */
ebrus 0:0a673c671a56 987 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
ebrus 0:0a673c671a56 988 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
ebrus 0:0a673c671a56 989 __I uint32_t RESERVED1[35];
ebrus 0:0a673c671a56 990 __IO uint32_t EVEN; /*!< SCT event enable register */
ebrus 0:0a673c671a56 991 __IO uint32_t EVFLAG; /*!< SCT event flag register */
ebrus 0:0a673c671a56 992 __IO uint32_t CONEN; /*!< SCT conflict enable register */
ebrus 0:0a673c671a56 993 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
ebrus 0:0a673c671a56 994
ebrus 0:0a673c671a56 995 union {
ebrus 0:0a673c671a56 996 __IO uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
ebrus 0:0a673c671a56 997 = 1 */
ebrus 0:0a673c671a56 998 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
ebrus 0:0a673c671a56 999 REGMODE4 = 0 */
ebrus 0:0a673c671a56 1000 };
ebrus 0:0a673c671a56 1001
ebrus 0:0a673c671a56 1002 union {
ebrus 0:0a673c671a56 1003 __IO uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
ebrus 0:0a673c671a56 1004 = 1 */
ebrus 0:0a673c671a56 1005 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
ebrus 0:0a673c671a56 1006 REGMODE4 = 0 */
ebrus 0:0a673c671a56 1007 };
ebrus 0:0a673c671a56 1008
ebrus 0:0a673c671a56 1009 union {
ebrus 0:0a673c671a56 1010 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
ebrus 0:0a673c671a56 1011 REGMODE4 = 0 */
ebrus 0:0a673c671a56 1012 __IO uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
ebrus 0:0a673c671a56 1013 = 1 */
ebrus 0:0a673c671a56 1014 };
ebrus 0:0a673c671a56 1015
ebrus 0:0a673c671a56 1016 union {
ebrus 0:0a673c671a56 1017 __IO uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
ebrus 0:0a673c671a56 1018 = 1 */
ebrus 0:0a673c671a56 1019 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
ebrus 0:0a673c671a56 1020 REGMODE4 = 0 */
ebrus 0:0a673c671a56 1021 };
ebrus 0:0a673c671a56 1022
ebrus 0:0a673c671a56 1023 union {
ebrus 0:0a673c671a56 1024 __IO uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
ebrus 0:0a673c671a56 1025 = 1 */
ebrus 0:0a673c671a56 1026 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
ebrus 0:0a673c671a56 1027 REGMODE4 = 0 */
ebrus 0:0a673c671a56 1028 };
ebrus 0:0a673c671a56 1029 __I uint32_t RESERVED2[59];
ebrus 0:0a673c671a56 1030
ebrus 0:0a673c671a56 1031 union {
ebrus 0:0a673c671a56 1032 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
ebrus 0:0a673c671a56 1033 = 1 */
ebrus 0:0a673c671a56 1034 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
ebrus 0:0a673c671a56 1035 = 0 */
ebrus 0:0a673c671a56 1036 };
ebrus 0:0a673c671a56 1037
ebrus 0:0a673c671a56 1038 union {
ebrus 0:0a673c671a56 1039 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
ebrus 0:0a673c671a56 1040 = 0 */
ebrus 0:0a673c671a56 1041 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
ebrus 0:0a673c671a56 1042 = 1 */
ebrus 0:0a673c671a56 1043 };
ebrus 0:0a673c671a56 1044
ebrus 0:0a673c671a56 1045 union {
ebrus 0:0a673c671a56 1046 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
ebrus 0:0a673c671a56 1047 = 0 */
ebrus 0:0a673c671a56 1048 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
ebrus 0:0a673c671a56 1049 = 1 */
ebrus 0:0a673c671a56 1050 };
ebrus 0:0a673c671a56 1051
ebrus 0:0a673c671a56 1052 union {
ebrus 0:0a673c671a56 1053 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
ebrus 0:0a673c671a56 1054 = 1 */
ebrus 0:0a673c671a56 1055 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
ebrus 0:0a673c671a56 1056 = 0 */
ebrus 0:0a673c671a56 1057 };
ebrus 0:0a673c671a56 1058
ebrus 0:0a673c671a56 1059 union {
ebrus 0:0a673c671a56 1060 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
ebrus 0:0a673c671a56 1061 = 1 */
ebrus 0:0a673c671a56 1062 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
ebrus 0:0a673c671a56 1063 = 0 */
ebrus 0:0a673c671a56 1064 };
ebrus 0:0a673c671a56 1065 __I uint32_t RESERVED3[59];
ebrus 0:0a673c671a56 1066 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
ebrus 0:0a673c671a56 1067 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
ebrus 0:0a673c671a56 1068 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
ebrus 0:0a673c671a56 1069 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
ebrus 0:0a673c671a56 1070 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
ebrus 0:0a673c671a56 1071 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
ebrus 0:0a673c671a56 1072 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
ebrus 0:0a673c671a56 1073 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
ebrus 0:0a673c671a56 1074 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
ebrus 0:0a673c671a56 1075 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
ebrus 0:0a673c671a56 1076 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
ebrus 0:0a673c671a56 1077 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
ebrus 0:0a673c671a56 1078 __I uint32_t RESERVED4[116];
ebrus 0:0a673c671a56 1079 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
ebrus 0:0a673c671a56 1080 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
ebrus 0:0a673c671a56 1081 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
ebrus 0:0a673c671a56 1082 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
ebrus 0:0a673c671a56 1083 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
ebrus 0:0a673c671a56 1084 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
ebrus 0:0a673c671a56 1085 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
ebrus 0:0a673c671a56 1086 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
ebrus 0:0a673c671a56 1087 } LPC_SCT0_Type;
ebrus 0:0a673c671a56 1088
ebrus 0:0a673c671a56 1089
ebrus 0:0a673c671a56 1090 /* ================================================================================ */
ebrus 0:0a673c671a56 1091 /* ================ GPIO_PORT ================ */
ebrus 0:0a673c671a56 1092 /* ================================================================================ */
ebrus 0:0a673c671a56 1093
ebrus 0:0a673c671a56 1094
ebrus 0:0a673c671a56 1095 /**
ebrus 0:0a673c671a56 1096 * @brief General Purpose I/O (GPIO) (GPIO_PORT)
ebrus 0:0a673c671a56 1097 */
ebrus 0:0a673c671a56 1098
ebrus 0:0a673c671a56 1099 typedef struct { /*!< GPIO_PORT Structure */
ebrus 0:0a673c671a56 1100 __IO uint8_t B[88]; /*!< Byte pin registers */
ebrus 0:0a673c671a56 1101 __I uint32_t RESERVED0[42];
ebrus 0:0a673c671a56 1102 __IO uint32_t W[88]; /*!< Word pin registers */
ebrus 0:0a673c671a56 1103 __I uint32_t RESERVED1[1896];
ebrus 0:0a673c671a56 1104 __IO uint32_t DIR[3]; /*!< Port Direction registers */
ebrus 0:0a673c671a56 1105 __I uint32_t RESERVED2[29];
ebrus 0:0a673c671a56 1106 __IO uint32_t MASK[3]; /*!< Port Mask register */
ebrus 0:0a673c671a56 1107 __I uint32_t RESERVED3[29];
ebrus 0:0a673c671a56 1108 __IO uint32_t PIN[3]; /*!< Port pin register */
ebrus 0:0a673c671a56 1109 __I uint32_t RESERVED4[29];
ebrus 0:0a673c671a56 1110 __IO uint32_t MPIN[3]; /*!< Masked port register */
ebrus 0:0a673c671a56 1111 __I uint32_t RESERVED5[29];
ebrus 0:0a673c671a56 1112 __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
ebrus 0:0a673c671a56 1113 __I uint32_t RESERVED6[29];
ebrus 0:0a673c671a56 1114 __O uint32_t CLR[3]; /*!< Clear port */
ebrus 0:0a673c671a56 1115 __I uint32_t RESERVED7[29];
ebrus 0:0a673c671a56 1116 __O uint32_t NOT[3]; /*!< Toggle port */
ebrus 0:0a673c671a56 1117 } LPC_GPIO_PORT_Type;
ebrus 0:0a673c671a56 1118
ebrus 0:0a673c671a56 1119
ebrus 0:0a673c671a56 1120 /* ================================================================================ */
ebrus 0:0a673c671a56 1121 /* ================ PINT ================ */
ebrus 0:0a673c671a56 1122 /* ================================================================================ */
ebrus 0:0a673c671a56 1123
ebrus 0:0a673c671a56 1124
ebrus 0:0a673c671a56 1125 /**
ebrus 0:0a673c671a56 1126 * @brief Pin interruptand pattern match (PINT) (PINT)
ebrus 0:0a673c671a56 1127 */
ebrus 0:0a673c671a56 1128
ebrus 0:0a673c671a56 1129 typedef struct { /*!< PINT Structure */
ebrus 0:0a673c671a56 1130 __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
ebrus 0:0a673c671a56 1131 __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
ebrus 0:0a673c671a56 1132 __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
ebrus 0:0a673c671a56 1133 __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
ebrus 0:0a673c671a56 1134 __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
ebrus 0:0a673c671a56 1135 register */
ebrus 0:0a673c671a56 1136 __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
ebrus 0:0a673c671a56 1137 __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
ebrus 0:0a673c671a56 1138 __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
ebrus 0:0a673c671a56 1139 __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
ebrus 0:0a673c671a56 1140 __IO uint32_t IST; /*!< Pin interrupt status register */
ebrus 0:0a673c671a56 1141 __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
ebrus 0:0a673c671a56 1142 __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
ebrus 0:0a673c671a56 1143 __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
ebrus 0:0a673c671a56 1144 } LPC_PINT_Type;
ebrus 0:0a673c671a56 1145
ebrus 0:0a673c671a56 1146
ebrus 0:0a673c671a56 1147 /* -------------------- End of section using anonymous unions ------------------- */
ebrus 0:0a673c671a56 1148 #if defined(__CC_ARM)
ebrus 0:0a673c671a56 1149 #pragma pop
ebrus 0:0a673c671a56 1150 #elif defined(__ICCARM__)
ebrus 0:0a673c671a56 1151 /* leave anonymous unions enabled */
ebrus 0:0a673c671a56 1152 #elif defined(__GNUC__)
ebrus 0:0a673c671a56 1153 /* anonymous unions are enabled by default */
ebrus 0:0a673c671a56 1154 #elif defined(__TMS470__)
ebrus 0:0a673c671a56 1155 /* anonymous unions are enabled by default */
ebrus 0:0a673c671a56 1156 #elif defined(__TASKING__)
ebrus 0:0a673c671a56 1157 #pragma warning restore
ebrus 0:0a673c671a56 1158 #else
ebrus 0:0a673c671a56 1159 #warning Not supported compiler type
ebrus 0:0a673c671a56 1160 #endif
ebrus 0:0a673c671a56 1161
ebrus 0:0a673c671a56 1162
ebrus 0:0a673c671a56 1163
ebrus 0:0a673c671a56 1164
ebrus 0:0a673c671a56 1165 /* ================================================================================ */
ebrus 0:0a673c671a56 1166 /* ================ Peripheral memory map ================ */
ebrus 0:0a673c671a56 1167 /* ================================================================================ */
ebrus 0:0a673c671a56 1168
ebrus 0:0a673c671a56 1169 #define LPC_I2C0_BASE 0x40000000UL
ebrus 0:0a673c671a56 1170 #define LPC_WWDT_BASE 0x40004000UL
ebrus 0:0a673c671a56 1171 #define LPC_USART0_BASE 0x40008000UL
ebrus 0:0a673c671a56 1172 #define LPC_CT16B0_BASE 0x4000C000UL
ebrus 0:0a673c671a56 1173 #define LPC_CT16B1_BASE 0x40010000UL
ebrus 0:0a673c671a56 1174 #define LPC_CT32B0_BASE 0x40014000UL
ebrus 0:0a673c671a56 1175 #define LPC_CT32B1_BASE 0x40018000UL
ebrus 0:0a673c671a56 1176 #define LPC_ADC_BASE 0x4001C000UL
ebrus 0:0a673c671a56 1177 #define LPC_I2C1_BASE 0x40020000UL
ebrus 0:0a673c671a56 1178 #define LPC_RTC_BASE 0x40024000UL
ebrus 0:0a673c671a56 1179 #define LPC_DMATRIGMUX_BASE 0x40028000UL
ebrus 0:0a673c671a56 1180 #define LPC_PMU_BASE 0x40038000UL
ebrus 0:0a673c671a56 1181 #define LPC_FLASHCTRL_BASE 0x4003C000UL
ebrus 0:0a673c671a56 1182 #define LPC_SSP0_BASE 0x40040000UL
ebrus 0:0a673c671a56 1183 #define LPC_IOCON_BASE 0x40044000UL
ebrus 0:0a673c671a56 1184 #define LPC_SYSCON_BASE 0x40048000UL
ebrus 0:0a673c671a56 1185 #define LPC_USART4_BASE 0x4004C000UL
ebrus 0:0a673c671a56 1186 #define LPC_SSP1_BASE 0x40058000UL
ebrus 0:0a673c671a56 1187 #define LPC_GINT0_BASE 0x4005C000UL
ebrus 0:0a673c671a56 1188 #define LPC_GINT1_BASE 0x40060000UL
ebrus 0:0a673c671a56 1189 #define LPC_USART1_BASE 0x4006C000UL
ebrus 0:0a673c671a56 1190 #define LPC_USART2_BASE 0x40070000UL
ebrus 0:0a673c671a56 1191 #define LPC_USART3_BASE 0x40074000UL
ebrus 0:0a673c671a56 1192 #define LPC_USB_BASE 0x40080000UL
ebrus 0:0a673c671a56 1193 #define LPC_CRC_BASE 0x50000000UL
ebrus 0:0a673c671a56 1194 #define LPC_DMA_BASE 0x50004000UL
ebrus 0:0a673c671a56 1195 #define LPC_SCT0_BASE 0x5000C000UL
ebrus 0:0a673c671a56 1196 #define LPC_SCT1_BASE 0x5000E000UL
ebrus 0:0a673c671a56 1197 #define LPC_GPIO_PORT_BASE 0xA0000000UL
ebrus 0:0a673c671a56 1198 #define LPC_PINT_BASE 0xA0004000UL
ebrus 0:0a673c671a56 1199
ebrus 0:0a673c671a56 1200
ebrus 0:0a673c671a56 1201 /* ================================================================================ */
ebrus 0:0a673c671a56 1202 /* ================ Peripheral declaration ================ */
ebrus 0:0a673c671a56 1203 /* ================================================================================ */
ebrus 0:0a673c671a56 1204
ebrus 0:0a673c671a56 1205 #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
ebrus 0:0a673c671a56 1206 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
ebrus 0:0a673c671a56 1207 #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
ebrus 0:0a673c671a56 1208 #define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
ebrus 0:0a673c671a56 1209 #define LPC_CT16B1 ((LPC_CT16B0_Type *) LPC_CT16B1_BASE)
ebrus 0:0a673c671a56 1210 #define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
ebrus 0:0a673c671a56 1211 #define LPC_CT32B1 ((LPC_CT32B0_Type *) LPC_CT32B1_BASE)
ebrus 0:0a673c671a56 1212 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
ebrus 0:0a673c671a56 1213 #define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
ebrus 0:0a673c671a56 1214 #define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
ebrus 0:0a673c671a56 1215 #define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
ebrus 0:0a673c671a56 1216 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
ebrus 0:0a673c671a56 1217 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
ebrus 0:0a673c671a56 1218 #define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
ebrus 0:0a673c671a56 1219 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
ebrus 0:0a673c671a56 1220 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
ebrus 0:0a673c671a56 1221 #define LPC_USART4 ((LPC_USART4_Type *) LPC_USART4_BASE)
ebrus 0:0a673c671a56 1222 #define LPC_SSP1 ((LPC_SSP0_Type *) LPC_SSP1_BASE)
ebrus 0:0a673c671a56 1223 #define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
ebrus 0:0a673c671a56 1224 #define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
ebrus 0:0a673c671a56 1225 #define LPC_USART1 ((LPC_USART4_Type *) LPC_USART1_BASE)
ebrus 0:0a673c671a56 1226 #define LPC_USART2 ((LPC_USART4_Type *) LPC_USART2_BASE)
ebrus 0:0a673c671a56 1227 #define LPC_USART3 ((LPC_USART4_Type *) LPC_USART3_BASE)
ebrus 0:0a673c671a56 1228 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
ebrus 0:0a673c671a56 1229 #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
ebrus 0:0a673c671a56 1230 #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
ebrus 0:0a673c671a56 1231 #define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
ebrus 0:0a673c671a56 1232 #define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
ebrus 0:0a673c671a56 1233 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
ebrus 0:0a673c671a56 1234 #define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
ebrus 0:0a673c671a56 1235
ebrus 0:0a673c671a56 1236
ebrus 0:0a673c671a56 1237 /** @} */ /* End of group Device_Peripheral_Registers */
ebrus 0:0a673c671a56 1238 /** @} */ /* End of group LPC11U6x */
ebrus 0:0a673c671a56 1239 /** @} */ /* End of group (null) */
ebrus 0:0a673c671a56 1240
ebrus 0:0a673c671a56 1241 #ifdef __cplusplus
ebrus 0:0a673c671a56 1242 }
ebrus 0:0a673c671a56 1243 #endif
ebrus 0:0a673c671a56 1244
ebrus 0:0a673c671a56 1245
ebrus 0:0a673c671a56 1246 #endif /* LPC11U6x_H */
ebrus 0:0a673c671a56 1247