Test the set param mode
DRV8323/DRV.h@44:8040fa2fcb0d, 2018-06-11 (annotated)
- Committer:
- benkatz
- Date:
- Mon Jun 11 00:04:06 2018 +0000
- Revision:
- 44:8040fa2fcb0d
- Child:
- 45:26801179208e
new drv chip working;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
benkatz | 44:8040fa2fcb0d | 1 | #ifndef DRV_H |
benkatz | 44:8040fa2fcb0d | 2 | #define DRV_H |
benkatz | 44:8040fa2fcb0d | 3 | |
benkatz | 44:8040fa2fcb0d | 4 | /// Registers /// |
benkatz | 44:8040fa2fcb0d | 5 | #define FSR1 0x0 ///Fault Status Register 1/// |
benkatz | 44:8040fa2fcb0d | 6 | #define FSR2 0x1 ///Fault Status Register 2/// |
benkatz | 44:8040fa2fcb0d | 7 | #define DCR 0x2 ///Drive Control Register/// |
benkatz | 44:8040fa2fcb0d | 8 | #define HSR 0x3 ///Gate Drive HS Register/// |
benkatz | 44:8040fa2fcb0d | 9 | #define LSR 0x4 ///Gate Drive LS Register/// |
benkatz | 44:8040fa2fcb0d | 10 | #define OCPCR 0x5 ///OCP Control Register/// |
benkatz | 44:8040fa2fcb0d | 11 | #define CSACR 0x6 ///CSA Control Register/// |
benkatz | 44:8040fa2fcb0d | 12 | |
benkatz | 44:8040fa2fcb0d | 13 | #define PWM_MODE_6X 0x0 ///PWM Input Modes/// |
benkatz | 44:8040fa2fcb0d | 14 | #define PWM_MODE_3X 0x1 |
benkatz | 44:8040fa2fcb0d | 15 | #define PWM_MODE_1X 0x2 |
benkatz | 44:8040fa2fcb0d | 16 | #define PWM_MODE_IND 0x3 |
benkatz | 44:8040fa2fcb0d | 17 | #define CSA_GAIN_5 0x0 ///Current Sensor Gain/// |
benkatz | 44:8040fa2fcb0d | 18 | #define CSA_GAIN_10 0x1 |
benkatz | 44:8040fa2fcb0d | 19 | #define CSA_GAIN_20 0x2 |
benkatz | 44:8040fa2fcb0d | 20 | #define CSA_GAIN_40 0x3 |
benkatz | 44:8040fa2fcb0d | 21 | #define DIS_SEN_EN 0x0 ///Overcurrent Fault |
benkatz | 44:8040fa2fcb0d | 22 | #define DIS_SEN_DIS 0x1 |
benkatz | 44:8040fa2fcb0d | 23 | |
benkatz | 44:8040fa2fcb0d | 24 | class DRV832x { |
benkatz | 44:8040fa2fcb0d | 25 | public: |
benkatz | 44:8040fa2fcb0d | 26 | DRV832x(SPI *spi, DigitalOut *cs); |
benkatz | 44:8040fa2fcb0d | 27 | int read_FSR1(); |
benkatz | 44:8040fa2fcb0d | 28 | int read_FSR2(); |
benkatz | 44:8040fa2fcb0d | 29 | int read_register(int reg); |
benkatz | 44:8040fa2fcb0d | 30 | void write_register(int reg, int val); |
benkatz | 44:8040fa2fcb0d | 31 | void write_DCR(int DIS_CPUV, int DIS_GDF, int OTW_REP, int PWM_MODE, int PWM_COM, int PWM_DIR, int COAST, int BRAKE, int CLR_FLT); |
benkatz | 44:8040fa2fcb0d | 32 | void write_HSR(int LOCK, int IDRIVEP_HS, int IDRIVEN_HS); |
benkatz | 44:8040fa2fcb0d | 33 | void write_LSR(int CBC, int TDRIVE, int IDRIVEP_LS, int IDRIVEN_LS); |
benkatz | 44:8040fa2fcb0d | 34 | void write_OCPCR(int TRETRY, int DEAD_TIME, int OCP_MODE, int OCP_DEG, int VDS_LVL); |
benkatz | 44:8040fa2fcb0d | 35 | void write_CSACR(int CSA_FET, int VREF_DIV, int LS_REF, int CSA_GAIN, int DIS_SEN, int CSA_CAL_A, int CSA_CAL_B, int CSA_CAL_C, int SEN_LVL); |
benkatz | 44:8040fa2fcb0d | 36 | void enable_gd(void); |
benkatz | 44:8040fa2fcb0d | 37 | void disable_gd(void); |
benkatz | 44:8040fa2fcb0d | 38 | void print_faults(); |
benkatz | 44:8040fa2fcb0d | 39 | |
benkatz | 44:8040fa2fcb0d | 40 | private: |
benkatz | 44:8040fa2fcb0d | 41 | SPI *_spi; |
benkatz | 44:8040fa2fcb0d | 42 | DigitalOut *_cs; |
benkatz | 44:8040fa2fcb0d | 43 | uint16_t spi_write(uint16_t val); |
benkatz | 44:8040fa2fcb0d | 44 | }; |
benkatz | 44:8040fa2fcb0d | 45 | |
benkatz | 44:8040fa2fcb0d | 46 | #endif |