David Yu / Mbed 2 deprecated 4180_Fitbit_rtos

Fitbit code using RTOS

Dependencies:   mbed PulseSensor2 SCP1000 mbed-rtos 4DGL-uLCD-SE LSM9DS1_Library_cal PinDetect FatFileSystemCpp GP-20U7

USBHostLite/usbhost_lpc17xx.cpp@0:bcfec522ef98, 2020-04-21 (annotated)

Committer:
memig3
Date:
Tue Apr 21 22:52:20 2020 +0000
Revision:
0:bcfec522ef98
working pedometer code using tickers;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
memig3 0:bcfec522ef98 1 /*
memig3 0:bcfec522ef98 2 **************************************************************************************************************
memig3 0:bcfec522ef98 3 * NXP USB Host Stack
memig3 0:bcfec522ef98 4 *
memig3 0:bcfec522ef98 5 * (c) Copyright 2008, NXP SemiConductors
memig3 0:bcfec522ef98 6 * (c) Copyright 2008, OnChip Technologies LLC
memig3 0:bcfec522ef98 7 * All Rights Reserved
memig3 0:bcfec522ef98 8 *
memig3 0:bcfec522ef98 9 * www.nxp.com
memig3 0:bcfec522ef98 10 * www.onchiptech.com
memig3 0:bcfec522ef98 11 *
memig3 0:bcfec522ef98 12 * File : usbhost_lpc17xx.c
memig3 0:bcfec522ef98 13 * Programmer(s) : Ravikanth.P
memig3 0:bcfec522ef98 14 * Version :
memig3 0:bcfec522ef98 15 *
memig3 0:bcfec522ef98 16 **************************************************************************************************************
memig3 0:bcfec522ef98 17 */
memig3 0:bcfec522ef98 18
memig3 0:bcfec522ef98 19 /*
memig3 0:bcfec522ef98 20 **************************************************************************************************************
memig3 0:bcfec522ef98 21 * INCLUDE HEADER FILES
memig3 0:bcfec522ef98 22 **************************************************************************************************************
memig3 0:bcfec522ef98 23 */
memig3 0:bcfec522ef98 24
memig3 0:bcfec522ef98 25 #include "usbhost_lpc17xx.h"
memig3 0:bcfec522ef98 26
memig3 0:bcfec522ef98 27 /*
memig3 0:bcfec522ef98 28 **************************************************************************************************************
memig3 0:bcfec522ef98 29 * GLOBAL VARIABLES
memig3 0:bcfec522ef98 30 **************************************************************************************************************
memig3 0:bcfec522ef98 31 */
memig3 0:bcfec522ef98 32 int gUSBConnected;
memig3 0:bcfec522ef98 33
memig3 0:bcfec522ef98 34 volatile USB_INT32U HOST_RhscIntr = 0; /* Root Hub Status Change interrupt */
memig3 0:bcfec522ef98 35 volatile USB_INT32U HOST_WdhIntr = 0; /* Semaphore to wait until the TD is submitted */
memig3 0:bcfec522ef98 36 volatile USB_INT08U HOST_TDControlStatus = 0;
memig3 0:bcfec522ef98 37 volatile HCED *EDCtrl; /* Control endpoint descriptor structure */
memig3 0:bcfec522ef98 38 volatile HCED *EDBulkIn; /* BulkIn endpoint descriptor structure */
memig3 0:bcfec522ef98 39 volatile HCED *EDBulkOut; /* BulkOut endpoint descriptor structure */
memig3 0:bcfec522ef98 40 volatile HCTD *TDHead; /* Head transfer descriptor structure */
memig3 0:bcfec522ef98 41 volatile HCTD *TDTail; /* Tail transfer descriptor structure */
memig3 0:bcfec522ef98 42 volatile HCCA *Hcca; /* Host Controller Communications Area structure */
memig3 0:bcfec522ef98 43 USB_INT16U *TDBufNonVol; /* Identical to TDBuffer just to reduce compiler warnings */
memig3 0:bcfec522ef98 44 volatile USB_INT08U *TDBuffer; /* Current Buffer Pointer of transfer descriptor */
memig3 0:bcfec522ef98 45
memig3 0:bcfec522ef98 46 // USB host structures
memig3 0:bcfec522ef98 47 // AHB SRAM block 1
memig3 0:bcfec522ef98 48 #define HOSTBASEADDR 0x2007C000
memig3 0:bcfec522ef98 49 // reserve memory for the linker
memig3 0:bcfec522ef98 50 static USB_INT08U HostBuf[0x200] __attribute__((at(HOSTBASEADDR)));
memig3 0:bcfec522ef98 51 /*
memig3 0:bcfec522ef98 52 **************************************************************************************************************
memig3 0:bcfec522ef98 53 * DELAY IN MILLI SECONDS
memig3 0:bcfec522ef98 54 *
memig3 0:bcfec522ef98 55 * Description: This function provides a delay in milli seconds
memig3 0:bcfec522ef98 56 *
memig3 0:bcfec522ef98 57 * Arguments : delay The delay required
memig3 0:bcfec522ef98 58 *
memig3 0:bcfec522ef98 59 * Returns : None
memig3 0:bcfec522ef98 60 *
memig3 0:bcfec522ef98 61 **************************************************************************************************************
memig3 0:bcfec522ef98 62 */
memig3 0:bcfec522ef98 63
memig3 0:bcfec522ef98 64 void Host_DelayMS (USB_INT32U delay)
memig3 0:bcfec522ef98 65 {
memig3 0:bcfec522ef98 66 volatile USB_INT32U i;
memig3 0:bcfec522ef98 67
memig3 0:bcfec522ef98 68
memig3 0:bcfec522ef98 69 for (i = 0; i < delay; i++) {
memig3 0:bcfec522ef98 70 Host_DelayUS(1000);
memig3 0:bcfec522ef98 71 }
memig3 0:bcfec522ef98 72 }
memig3 0:bcfec522ef98 73
memig3 0:bcfec522ef98 74 /*
memig3 0:bcfec522ef98 75 **************************************************************************************************************
memig3 0:bcfec522ef98 76 * DELAY IN MICRO SECONDS
memig3 0:bcfec522ef98 77 *
memig3 0:bcfec522ef98 78 * Description: This function provides a delay in micro seconds
memig3 0:bcfec522ef98 79 *
memig3 0:bcfec522ef98 80 * Arguments : delay The delay required
memig3 0:bcfec522ef98 81 *
memig3 0:bcfec522ef98 82 * Returns : None
memig3 0:bcfec522ef98 83 *
memig3 0:bcfec522ef98 84 **************************************************************************************************************
memig3 0:bcfec522ef98 85 */
memig3 0:bcfec522ef98 86
memig3 0:bcfec522ef98 87 void Host_DelayUS (USB_INT32U delay)
memig3 0:bcfec522ef98 88 {
memig3 0:bcfec522ef98 89 volatile USB_INT32U i;
memig3 0:bcfec522ef98 90
memig3 0:bcfec522ef98 91
memig3 0:bcfec522ef98 92 for (i = 0; i < (4 * delay); i++) { /* This logic was tested. It gives app. 1 micro sec delay */
memig3 0:bcfec522ef98 93 ;
memig3 0:bcfec522ef98 94 }
memig3 0:bcfec522ef98 95 }
memig3 0:bcfec522ef98 96
memig3 0:bcfec522ef98 97 // bits of the USB/OTG clock control register
memig3 0:bcfec522ef98 98 #define HOST_CLK_EN (1<<0)
memig3 0:bcfec522ef98 99 #define DEV_CLK_EN (1<<1)
memig3 0:bcfec522ef98 100 #define PORTSEL_CLK_EN (1<<3)
memig3 0:bcfec522ef98 101 #define AHB_CLK_EN (1<<4)
memig3 0:bcfec522ef98 102
memig3 0:bcfec522ef98 103 // bits of the USB/OTG clock status register
memig3 0:bcfec522ef98 104 #define HOST_CLK_ON (1<<0)
memig3 0:bcfec522ef98 105 #define DEV_CLK_ON (1<<1)
memig3 0:bcfec522ef98 106 #define PORTSEL_CLK_ON (1<<3)
memig3 0:bcfec522ef98 107 #define AHB_CLK_ON (1<<4)
memig3 0:bcfec522ef98 108
memig3 0:bcfec522ef98 109 // we need host clock, OTG/portsel clock and AHB clock
memig3 0:bcfec522ef98 110 #define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
memig3 0:bcfec522ef98 111
memig3 0:bcfec522ef98 112 /*
memig3 0:bcfec522ef98 113 **************************************************************************************************************
memig3 0:bcfec522ef98 114 * INITIALIZE THE HOST CONTROLLER
memig3 0:bcfec522ef98 115 *
memig3 0:bcfec522ef98 116 * Description: This function initializes lpc17xx host controller
memig3 0:bcfec522ef98 117 *
memig3 0:bcfec522ef98 118 * Arguments : None
memig3 0:bcfec522ef98 119 *
memig3 0:bcfec522ef98 120 * Returns :
memig3 0:bcfec522ef98 121 *
memig3 0:bcfec522ef98 122 **************************************************************************************************************
memig3 0:bcfec522ef98 123 */
memig3 0:bcfec522ef98 124 void Host_Init (void)
memig3 0:bcfec522ef98 125 {
memig3 0:bcfec522ef98 126 PRINT_Log("In Host_Init\n");
memig3 0:bcfec522ef98 127 NVIC_DisableIRQ(USB_IRQn); /* Disable the USB interrupt source */
memig3 0:bcfec522ef98 128
memig3 0:bcfec522ef98 129 // turn on power for USB
memig3 0:bcfec522ef98 130 LPC_SC->PCONP |= (1UL<<31);
memig3 0:bcfec522ef98 131 // Enable USB host clock, port selection and AHB clock
memig3 0:bcfec522ef98 132 LPC_USB->USBClkCtrl |= CLOCK_MASK;
memig3 0:bcfec522ef98 133 // Wait for clocks to become available
memig3 0:bcfec522ef98 134 while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK)
memig3 0:bcfec522ef98 135 ;
memig3 0:bcfec522ef98 136
memig3 0:bcfec522ef98 137 // it seems the bits[0:1] mean the following
memig3 0:bcfec522ef98 138 // 0: U1=device, U2=host
memig3 0:bcfec522ef98 139 // 1: U1=host, U2=host
memig3 0:bcfec522ef98 140 // 2: reserved
memig3 0:bcfec522ef98 141 // 3: U1=host, U2=device
memig3 0:bcfec522ef98 142 // NB: this register is only available if OTG clock (aka "port select") is enabled!!
memig3 0:bcfec522ef98 143 // since we don't care about port 2, set just bit 0 to 1 (U1=host)
memig3 0:bcfec522ef98 144 LPC_USB->OTGStCtrl |= 1;
memig3 0:bcfec522ef98 145
memig3 0:bcfec522ef98 146 // now that we've configured the ports, we can turn off the portsel clock
memig3 0:bcfec522ef98 147 LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
memig3 0:bcfec522ef98 148
memig3 0:bcfec522ef98 149 // power pins are not connected on mbed, so we can skip them
memig3 0:bcfec522ef98 150 /* P1[18] = USB_UP_LED, 01 */
memig3 0:bcfec522ef98 151 /* P1[19] = /USB_PPWR, 10 */
memig3 0:bcfec522ef98 152 /* P1[22] = USB_PWRD, 10 */
memig3 0:bcfec522ef98 153 /* P1[27] = /USB_OVRCR, 10 */
memig3 0:bcfec522ef98 154 /*LPC_PINCON->PINSEL3 &= ~((3<<4) | (3<<6) | (3<<12) | (3<<22));
memig3 0:bcfec522ef98 155 LPC_PINCON->PINSEL3 |= ((1<<4)|(2<<6) | (2<<12) | (2<<22)); // 0x00802080
memig3 0:bcfec522ef98 156 */
memig3 0:bcfec522ef98 157
memig3 0:bcfec522ef98 158 // configure USB D+/D- pins
memig3 0:bcfec522ef98 159 /* P0[29] = USB_D+, 01 */
memig3 0:bcfec522ef98 160 /* P0[30] = USB_D-, 01 */
memig3 0:bcfec522ef98 161 LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
memig3 0:bcfec522ef98 162 LPC_PINCON->PINSEL1 |= ((1<<26)|(1<<28)); // 0x14000000
memig3 0:bcfec522ef98 163
memig3 0:bcfec522ef98 164 PRINT_Log("Initializing Host Stack\n");
memig3 0:bcfec522ef98 165
memig3 0:bcfec522ef98 166 Hcca = (volatile HCCA *)(HostBuf+0x000);
memig3 0:bcfec522ef98 167 TDHead = (volatile HCTD *)(HostBuf+0x100);
memig3 0:bcfec522ef98 168 TDTail = (volatile HCTD *)(HostBuf+0x110);
memig3 0:bcfec522ef98 169 EDCtrl = (volatile HCED *)(HostBuf+0x120);
memig3 0:bcfec522ef98 170 EDBulkIn = (volatile HCED *)(HostBuf+0x130);
memig3 0:bcfec522ef98 171 EDBulkOut = (volatile HCED *)(HostBuf+0x140);
memig3 0:bcfec522ef98 172 TDBuffer = (volatile USB_INT08U *)(HostBuf+0x150);
memig3 0:bcfec522ef98 173
memig3 0:bcfec522ef98 174 /* Initialize all the TDs, EDs and HCCA to 0 */
memig3 0:bcfec522ef98 175 Host_EDInit(EDCtrl);
memig3 0:bcfec522ef98 176 Host_EDInit(EDBulkIn);
memig3 0:bcfec522ef98 177 Host_EDInit(EDBulkOut);
memig3 0:bcfec522ef98 178 Host_TDInit(TDHead);
memig3 0:bcfec522ef98 179 Host_TDInit(TDTail);
memig3 0:bcfec522ef98 180 Host_HCCAInit(Hcca);
memig3 0:bcfec522ef98 181
memig3 0:bcfec522ef98 182 Host_DelayMS(50); /* Wait 50 ms before apply reset */
memig3 0:bcfec522ef98 183 LPC_USB->HcControl = 0; /* HARDWARE RESET */
memig3 0:bcfec522ef98 184 LPC_USB->HcControlHeadED = 0; /* Initialize Control list head to Zero */
memig3 0:bcfec522ef98 185 LPC_USB->HcBulkHeadED = 0; /* Initialize Bulk list head to Zero */
memig3 0:bcfec522ef98 186
memig3 0:bcfec522ef98 187 /* SOFTWARE RESET */
memig3 0:bcfec522ef98 188 LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
memig3 0:bcfec522ef98 189 LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL; /* Write Fm Interval and Largest Data Packet Counter */
memig3 0:bcfec522ef98 190
memig3 0:bcfec522ef98 191 /* Put HC in operational state */
memig3 0:bcfec522ef98 192 LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
memig3 0:bcfec522ef98 193 LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC; /* Set Global Power */
memig3 0:bcfec522ef98 194
memig3 0:bcfec522ef98 195 LPC_USB->HcHCCA = (USB_INT32U)Hcca;
memig3 0:bcfec522ef98 196 LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus; /* Clear Interrrupt Status */
memig3 0:bcfec522ef98 197
memig3 0:bcfec522ef98 198
memig3 0:bcfec522ef98 199 LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE |
memig3 0:bcfec522ef98 200 OR_INTR_ENABLE_WDH |
memig3 0:bcfec522ef98 201 OR_INTR_ENABLE_RHSC;
memig3 0:bcfec522ef98 202
memig3 0:bcfec522ef98 203 NVIC_SetPriority(USB_IRQn, 0); /* highest priority */
memig3 0:bcfec522ef98 204 /* Enable the USB Interrupt */
memig3 0:bcfec522ef98 205 NVIC_EnableIRQ(USB_IRQn);
memig3 0:bcfec522ef98 206 PRINT_Log("Host Initialized\n");
memig3 0:bcfec522ef98 207 }
memig3 0:bcfec522ef98 208
memig3 0:bcfec522ef98 209 /*
memig3 0:bcfec522ef98 210 **************************************************************************************************************
memig3 0:bcfec522ef98 211 * INTERRUPT SERVICE ROUTINE
memig3 0:bcfec522ef98 212 *
memig3 0:bcfec522ef98 213 * Description: This function services the interrupt caused by host controller
memig3 0:bcfec522ef98 214 *
memig3 0:bcfec522ef98 215 * Arguments : None
memig3 0:bcfec522ef98 216 *
memig3 0:bcfec522ef98 217 * Returns : None
memig3 0:bcfec522ef98 218 *
memig3 0:bcfec522ef98 219 **************************************************************************************************************
memig3 0:bcfec522ef98 220 */
memig3 0:bcfec522ef98 221
memig3 0:bcfec522ef98 222 void USB_IRQHandler (void) __irq
memig3 0:bcfec522ef98 223 {
memig3 0:bcfec522ef98 224 USB_INT32U int_status;
memig3 0:bcfec522ef98 225 USB_INT32U ie_status;
memig3 0:bcfec522ef98 226
memig3 0:bcfec522ef98 227 int_status = LPC_USB->HcInterruptStatus; /* Read Interrupt Status */
memig3 0:bcfec522ef98 228 ie_status = LPC_USB->HcInterruptEnable; /* Read Interrupt enable status */
memig3 0:bcfec522ef98 229
memig3 0:bcfec522ef98 230 if (!(int_status & ie_status)) {
memig3 0:bcfec522ef98 231 return;
memig3 0:bcfec522ef98 232 } else {
memig3 0:bcfec522ef98 233
memig3 0:bcfec522ef98 234 int_status = int_status & ie_status;
memig3 0:bcfec522ef98 235 if (int_status & OR_INTR_STATUS_RHSC) { /* Root hub status change interrupt */
memig3 0:bcfec522ef98 236 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
memig3 0:bcfec522ef98 237 if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
memig3 0:bcfec522ef98 238 /*
memig3 0:bcfec522ef98 239 * When DRWE is on, Connect Status Change
memig3 0:bcfec522ef98 240 * means a remote wakeup event.
memig3 0:bcfec522ef98 241 */
memig3 0:bcfec522ef98 242 HOST_RhscIntr = 1;// JUST SOMETHING FOR A BREAKPOINT
memig3 0:bcfec522ef98 243 }
memig3 0:bcfec522ef98 244 else {
memig3 0:bcfec522ef98 245 /*
memig3 0:bcfec522ef98 246 * When DRWE is off, Connect Status Change
memig3 0:bcfec522ef98 247 * is NOT a remote wakeup event
memig3 0:bcfec522ef98 248 */
memig3 0:bcfec522ef98 249 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
memig3 0:bcfec522ef98 250 if (!gUSBConnected) {
memig3 0:bcfec522ef98 251 HOST_TDControlStatus = 0;
memig3 0:bcfec522ef98 252 HOST_WdhIntr = 0;
memig3 0:bcfec522ef98 253 HOST_RhscIntr = 1;
memig3 0:bcfec522ef98 254 gUSBConnected = 1;
memig3 0:bcfec522ef98 255 }
memig3 0:bcfec522ef98 256 else
memig3 0:bcfec522ef98 257 PRINT_Log("Spurious status change (connected)?\n");
memig3 0:bcfec522ef98 258 } else {
memig3 0:bcfec522ef98 259 if (gUSBConnected) {
memig3 0:bcfec522ef98 260 LPC_USB->HcInterruptEnable = 0; // why do we get multiple disc. rupts???
memig3 0:bcfec522ef98 261 HOST_RhscIntr = 0;
memig3 0:bcfec522ef98 262 gUSBConnected = 0;
memig3 0:bcfec522ef98 263 }
memig3 0:bcfec522ef98 264 else
memig3 0:bcfec522ef98 265 PRINT_Log("Spurious status change (disconnected)?\n");
memig3 0:bcfec522ef98 266 }
memig3 0:bcfec522ef98 267 }
memig3 0:bcfec522ef98 268 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
memig3 0:bcfec522ef98 269 }
memig3 0:bcfec522ef98 270 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
memig3 0:bcfec522ef98 271 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
memig3 0:bcfec522ef98 272 }
memig3 0:bcfec522ef98 273 }
memig3 0:bcfec522ef98 274 if (int_status & OR_INTR_STATUS_WDH) { /* Writeback Done Head interrupt */
memig3 0:bcfec522ef98 275 HOST_WdhIntr = 1;
memig3 0:bcfec522ef98 276 HOST_TDControlStatus = (TDHead->Control >> 28) & 0xf;
memig3 0:bcfec522ef98 277 }
memig3 0:bcfec522ef98 278 LPC_USB->HcInterruptStatus = int_status; /* Clear interrupt status register */
memig3 0:bcfec522ef98 279 }
memig3 0:bcfec522ef98 280 return;
memig3 0:bcfec522ef98 281 }
memig3 0:bcfec522ef98 282
memig3 0:bcfec522ef98 283 /*
memig3 0:bcfec522ef98 284 **************************************************************************************************************
memig3 0:bcfec522ef98 285 * PROCESS TRANSFER DESCRIPTOR
memig3 0:bcfec522ef98 286 *
memig3 0:bcfec522ef98 287 * Description: This function processes the transfer descriptor
memig3 0:bcfec522ef98 288 *
memig3 0:bcfec522ef98 289 * Arguments : ed Endpoint descriptor that contains this transfer descriptor
memig3 0:bcfec522ef98 290 * token SETUP, IN, OUT
memig3 0:bcfec522ef98 291 * buffer Current Buffer Pointer of the transfer descriptor
memig3 0:bcfec522ef98 292 * buffer_len Length of the buffer
memig3 0:bcfec522ef98 293 *
memig3 0:bcfec522ef98 294 * Returns : OK if TD submission is successful
memig3 0:bcfec522ef98 295 * ERROR if TD submission fails
memig3 0:bcfec522ef98 296 *
memig3 0:bcfec522ef98 297 **************************************************************************************************************
memig3 0:bcfec522ef98 298 */
memig3 0:bcfec522ef98 299
memig3 0:bcfec522ef98 300 USB_INT32S Host_ProcessTD (volatile HCED *ed,
memig3 0:bcfec522ef98 301 volatile USB_INT32U token,
memig3 0:bcfec522ef98 302 volatile USB_INT08U *buffer,
memig3 0:bcfec522ef98 303 USB_INT32U buffer_len)
memig3 0:bcfec522ef98 304 {
memig3 0:bcfec522ef98 305 volatile USB_INT32U td_toggle;
memig3 0:bcfec522ef98 306
memig3 0:bcfec522ef98 307
memig3 0:bcfec522ef98 308 if (ed == EDCtrl) {
memig3 0:bcfec522ef98 309 if (token == TD_SETUP) {
memig3 0:bcfec522ef98 310 td_toggle = TD_TOGGLE_0;
memig3 0:bcfec522ef98 311 } else {
memig3 0:bcfec522ef98 312 td_toggle = TD_TOGGLE_1;
memig3 0:bcfec522ef98 313 }
memig3 0:bcfec522ef98 314 } else {
memig3 0:bcfec522ef98 315 td_toggle = 0;
memig3 0:bcfec522ef98 316 }
memig3 0:bcfec522ef98 317 TDHead->Control = (TD_ROUNDING |
memig3 0:bcfec522ef98 318 token |
memig3 0:bcfec522ef98 319 TD_DELAY_INT(0) |
memig3 0:bcfec522ef98 320 td_toggle |
memig3 0:bcfec522ef98 321 TD_CC);
memig3 0:bcfec522ef98 322 TDTail->Control = 0;
memig3 0:bcfec522ef98 323 TDHead->CurrBufPtr = (USB_INT32U) buffer;
memig3 0:bcfec522ef98 324 TDTail->CurrBufPtr = 0;
memig3 0:bcfec522ef98 325 TDHead->Next = (USB_INT32U) TDTail;
memig3 0:bcfec522ef98 326 TDTail->Next = 0;
memig3 0:bcfec522ef98 327 TDHead->BufEnd = (USB_INT32U)(buffer + (buffer_len - 1));
memig3 0:bcfec522ef98 328 TDTail->BufEnd = 0;
memig3 0:bcfec522ef98 329
memig3 0:bcfec522ef98 330 ed->HeadTd = (USB_INT32U)TDHead | ((ed->HeadTd) & 0x00000002);
memig3 0:bcfec522ef98 331 ed->TailTd = (USB_INT32U)TDTail;
memig3 0:bcfec522ef98 332 ed->Next = 0;
memig3 0:bcfec522ef98 333
memig3 0:bcfec522ef98 334 if (ed == EDCtrl) {
memig3 0:bcfec522ef98 335 LPC_USB->HcControlHeadED = (USB_INT32U)ed;
memig3 0:bcfec522ef98 336 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_CLF;
memig3 0:bcfec522ef98 337 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_CLE;
memig3 0:bcfec522ef98 338 } else {
memig3 0:bcfec522ef98 339 LPC_USB->HcBulkHeadED = (USB_INT32U)ed;
memig3 0:bcfec522ef98 340 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_BLF;
memig3 0:bcfec522ef98 341 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_BLE;
memig3 0:bcfec522ef98 342 }
memig3 0:bcfec522ef98 343
memig3 0:bcfec522ef98 344 Host_WDHWait();
memig3 0:bcfec522ef98 345
memig3 0:bcfec522ef98 346 // if (!(TDHead->Control & 0xF0000000)) {
memig3 0:bcfec522ef98 347 if (!HOST_TDControlStatus) {
memig3 0:bcfec522ef98 348 return (OK);
memig3 0:bcfec522ef98 349 } else {
memig3 0:bcfec522ef98 350 return (ERR_TD_FAIL);
memig3 0:bcfec522ef98 351 }
memig3 0:bcfec522ef98 352 }
memig3 0:bcfec522ef98 353
memig3 0:bcfec522ef98 354 /*
memig3 0:bcfec522ef98 355 **************************************************************************************************************
memig3 0:bcfec522ef98 356 * ENUMERATE THE DEVICE
memig3 0:bcfec522ef98 357 *
memig3 0:bcfec522ef98 358 * Description: This function is used to enumerate the device connected
memig3 0:bcfec522ef98 359 *
memig3 0:bcfec522ef98 360 * Arguments : None
memig3 0:bcfec522ef98 361 *
memig3 0:bcfec522ef98 362 * Returns : None
memig3 0:bcfec522ef98 363 *
memig3 0:bcfec522ef98 364 **************************************************************************************************************
memig3 0:bcfec522ef98 365 */
memig3 0:bcfec522ef98 366
memig3 0:bcfec522ef98 367 USB_INT32S Host_EnumDev (void)
memig3 0:bcfec522ef98 368 {
memig3 0:bcfec522ef98 369 USB_INT32S rc;
memig3 0:bcfec522ef98 370
memig3 0:bcfec522ef98 371 PRINT_Log("Connect a Mass Storage device\n");
memig3 0:bcfec522ef98 372 while (!HOST_RhscIntr)
memig3 0:bcfec522ef98 373 __WFI();
memig3 0:bcfec522ef98 374 Host_DelayMS(100); /* USB 2.0 spec says atleast 50ms delay beore port reset */
memig3 0:bcfec522ef98 375 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS; // Initiate port reset
memig3 0:bcfec522ef98 376 while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS)
memig3 0:bcfec522ef98 377 __WFI(); // Wait for port reset to complete...
memig3 0:bcfec522ef98 378 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC; // ...and clear port reset signal
memig3 0:bcfec522ef98 379 Host_DelayMS(200); /* Wait for 100 MS after port reset */
memig3 0:bcfec522ef98 380
memig3 0:bcfec522ef98 381 EDCtrl->Control = 8 << 16; /* Put max pkt size = 8 */
memig3 0:bcfec522ef98 382 /* Read first 8 bytes of device desc */
memig3 0:bcfec522ef98 383 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_DEVICE, 0, TDBuffer, 8);
memig3 0:bcfec522ef98 384 if (rc != OK) {
memig3 0:bcfec522ef98 385 PRINT_Err(rc);
memig3 0:bcfec522ef98 386 return (rc);
memig3 0:bcfec522ef98 387 }
memig3 0:bcfec522ef98 388 EDCtrl->Control = TDBuffer[7] << 16; /* Get max pkt size of endpoint 0 */
memig3 0:bcfec522ef98 389 rc = HOST_SET_ADDRESS(1); /* Set the device address to 1 */
memig3 0:bcfec522ef98 390 if (rc != OK) {
memig3 0:bcfec522ef98 391 PRINT_Err(rc);
memig3 0:bcfec522ef98 392 return (rc);
memig3 0:bcfec522ef98 393 }
memig3 0:bcfec522ef98 394 Host_DelayMS(2);
memig3 0:bcfec522ef98 395 EDCtrl->Control = (EDCtrl->Control) | 1; /* Modify control pipe with address 1 */
memig3 0:bcfec522ef98 396 /* Get the configuration descriptor */
memig3 0:bcfec522ef98 397 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, 9);
memig3 0:bcfec522ef98 398 if (rc != OK) {
memig3 0:bcfec522ef98 399 PRINT_Err(rc);
memig3 0:bcfec522ef98 400 return (rc);
memig3 0:bcfec522ef98 401 }
memig3 0:bcfec522ef98 402 /* Get the first configuration data */
memig3 0:bcfec522ef98 403 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, ReadLE16U(&TDBuffer[2]));
memig3 0:bcfec522ef98 404 if (rc != OK) {
memig3 0:bcfec522ef98 405 PRINT_Err(rc);
memig3 0:bcfec522ef98 406 return (rc);
memig3 0:bcfec522ef98 407 }
memig3 0:bcfec522ef98 408 rc = MS_ParseConfiguration(); /* Parse the configuration */
memig3 0:bcfec522ef98 409 if (rc != OK) {
memig3 0:bcfec522ef98 410 PRINT_Err(rc);
memig3 0:bcfec522ef98 411 return (rc);
memig3 0:bcfec522ef98 412 }
memig3 0:bcfec522ef98 413 rc = USBH_SET_CONFIGURATION(1); /* Select device configuration 1 */
memig3 0:bcfec522ef98 414 if (rc != OK) {
memig3 0:bcfec522ef98 415 PRINT_Err(rc);
memig3 0:bcfec522ef98 416 }
memig3 0:bcfec522ef98 417 Host_DelayMS(100); /* Some devices may require this delay */
memig3 0:bcfec522ef98 418 return (rc);
memig3 0:bcfec522ef98 419 }
memig3 0:bcfec522ef98 420
memig3 0:bcfec522ef98 421 /*
memig3 0:bcfec522ef98 422 **************************************************************************************************************
memig3 0:bcfec522ef98 423 * RECEIVE THE CONTROL INFORMATION
memig3 0:bcfec522ef98 424 *
memig3 0:bcfec522ef98 425 * Description: This function is used to receive the control information
memig3 0:bcfec522ef98 426 *
memig3 0:bcfec522ef98 427 * Arguments : bm_request_type
memig3 0:bcfec522ef98 428 * b_request
memig3 0:bcfec522ef98 429 * w_value
memig3 0:bcfec522ef98 430 * w_index
memig3 0:bcfec522ef98 431 * w_length
memig3 0:bcfec522ef98 432 * buffer
memig3 0:bcfec522ef98 433 *
memig3 0:bcfec522ef98 434 * Returns : OK if Success
memig3 0:bcfec522ef98 435 * ERROR if Failed
memig3 0:bcfec522ef98 436 *
memig3 0:bcfec522ef98 437 **************************************************************************************************************
memig3 0:bcfec522ef98 438 */
memig3 0:bcfec522ef98 439
memig3 0:bcfec522ef98 440 USB_INT32S Host_CtrlRecv ( USB_INT08U bm_request_type,
memig3 0:bcfec522ef98 441 USB_INT08U b_request,
memig3 0:bcfec522ef98 442 USB_INT16U w_value,
memig3 0:bcfec522ef98 443 USB_INT16U w_index,
memig3 0:bcfec522ef98 444 USB_INT16U w_length,
memig3 0:bcfec522ef98 445 volatile USB_INT08U *buffer)
memig3 0:bcfec522ef98 446 {
memig3 0:bcfec522ef98 447 USB_INT32S rc;
memig3 0:bcfec522ef98 448
memig3 0:bcfec522ef98 449
memig3 0:bcfec522ef98 450 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
memig3 0:bcfec522ef98 451 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
memig3 0:bcfec522ef98 452 if (rc == OK) {
memig3 0:bcfec522ef98 453 if (w_length) {
memig3 0:bcfec522ef98 454 rc = Host_ProcessTD(EDCtrl, TD_IN, TDBuffer, w_length);
memig3 0:bcfec522ef98 455 }
memig3 0:bcfec522ef98 456 if (rc == OK) {
memig3 0:bcfec522ef98 457 rc = Host_ProcessTD(EDCtrl, TD_OUT, NULL, 0);
memig3 0:bcfec522ef98 458 }
memig3 0:bcfec522ef98 459 }
memig3 0:bcfec522ef98 460 return (rc);
memig3 0:bcfec522ef98 461 }
memig3 0:bcfec522ef98 462
memig3 0:bcfec522ef98 463 /*
memig3 0:bcfec522ef98 464 **************************************************************************************************************
memig3 0:bcfec522ef98 465 * SEND THE CONTROL INFORMATION
memig3 0:bcfec522ef98 466 *
memig3 0:bcfec522ef98 467 * Description: This function is used to send the control information
memig3 0:bcfec522ef98 468 *
memig3 0:bcfec522ef98 469 * Arguments : None
memig3 0:bcfec522ef98 470 *
memig3 0:bcfec522ef98 471 * Returns : OK if Success
memig3 0:bcfec522ef98 472 * ERR_INVALID_BOOTSIG if Failed
memig3 0:bcfec522ef98 473 *
memig3 0:bcfec522ef98 474 **************************************************************************************************************
memig3 0:bcfec522ef98 475 */
memig3 0:bcfec522ef98 476
memig3 0:bcfec522ef98 477 USB_INT32S Host_CtrlSend ( USB_INT08U bm_request_type,
memig3 0:bcfec522ef98 478 USB_INT08U b_request,
memig3 0:bcfec522ef98 479 USB_INT16U w_value,
memig3 0:bcfec522ef98 480 USB_INT16U w_index,
memig3 0:bcfec522ef98 481 USB_INT16U w_length,
memig3 0:bcfec522ef98 482 volatile USB_INT08U *buffer)
memig3 0:bcfec522ef98 483 {
memig3 0:bcfec522ef98 484 USB_INT32S rc;
memig3 0:bcfec522ef98 485
memig3 0:bcfec522ef98 486
memig3 0:bcfec522ef98 487 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
memig3 0:bcfec522ef98 488
memig3 0:bcfec522ef98 489 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
memig3 0:bcfec522ef98 490 if (rc == OK) {
memig3 0:bcfec522ef98 491 if (w_length) {
memig3 0:bcfec522ef98 492 rc = Host_ProcessTD(EDCtrl, TD_OUT, TDBuffer, w_length);
memig3 0:bcfec522ef98 493 }
memig3 0:bcfec522ef98 494 if (rc == OK) {
memig3 0:bcfec522ef98 495 rc = Host_ProcessTD(EDCtrl, TD_IN, NULL, 0);
memig3 0:bcfec522ef98 496 }
memig3 0:bcfec522ef98 497 }
memig3 0:bcfec522ef98 498 return (rc);
memig3 0:bcfec522ef98 499 }
memig3 0:bcfec522ef98 500
memig3 0:bcfec522ef98 501 /*
memig3 0:bcfec522ef98 502 **************************************************************************************************************
memig3 0:bcfec522ef98 503 * FILL SETUP PACKET
memig3 0:bcfec522ef98 504 *
memig3 0:bcfec522ef98 505 * Description: This function is used to fill the setup packet
memig3 0:bcfec522ef98 506 *
memig3 0:bcfec522ef98 507 * Arguments : None
memig3 0:bcfec522ef98 508 *
memig3 0:bcfec522ef98 509 * Returns : OK if Success
memig3 0:bcfec522ef98 510 * ERR_INVALID_BOOTSIG if Failed
memig3 0:bcfec522ef98 511 *
memig3 0:bcfec522ef98 512 **************************************************************************************************************
memig3 0:bcfec522ef98 513 */
memig3 0:bcfec522ef98 514
memig3 0:bcfec522ef98 515 void Host_FillSetup (USB_INT08U bm_request_type,
memig3 0:bcfec522ef98 516 USB_INT08U b_request,
memig3 0:bcfec522ef98 517 USB_INT16U w_value,
memig3 0:bcfec522ef98 518 USB_INT16U w_index,
memig3 0:bcfec522ef98 519 USB_INT16U w_length)
memig3 0:bcfec522ef98 520 {
memig3 0:bcfec522ef98 521 int i;
memig3 0:bcfec522ef98 522 for (i=0;i<w_length;i++)
memig3 0:bcfec522ef98 523 TDBuffer[i] = 0;
memig3 0:bcfec522ef98 524
memig3 0:bcfec522ef98 525 TDBuffer[0] = bm_request_type;
memig3 0:bcfec522ef98 526 TDBuffer[1] = b_request;
memig3 0:bcfec522ef98 527 WriteLE16U(&TDBuffer[2], w_value);
memig3 0:bcfec522ef98 528 WriteLE16U(&TDBuffer[4], w_index);
memig3 0:bcfec522ef98 529 WriteLE16U(&TDBuffer[6], w_length);
memig3 0:bcfec522ef98 530 }
memig3 0:bcfec522ef98 531
memig3 0:bcfec522ef98 532
memig3 0:bcfec522ef98 533
memig3 0:bcfec522ef98 534 /*
memig3 0:bcfec522ef98 535 **************************************************************************************************************
memig3 0:bcfec522ef98 536 * INITIALIZE THE TRANSFER DESCRIPTOR
memig3 0:bcfec522ef98 537 *
memig3 0:bcfec522ef98 538 * Description: This function initializes transfer descriptor
memig3 0:bcfec522ef98 539 *
memig3 0:bcfec522ef98 540 * Arguments : Pointer to TD structure
memig3 0:bcfec522ef98 541 *
memig3 0:bcfec522ef98 542 * Returns : None
memig3 0:bcfec522ef98 543 *
memig3 0:bcfec522ef98 544 **************************************************************************************************************
memig3 0:bcfec522ef98 545 */
memig3 0:bcfec522ef98 546
memig3 0:bcfec522ef98 547 void Host_TDInit (volatile HCTD *td)
memig3 0:bcfec522ef98 548 {
memig3 0:bcfec522ef98 549
memig3 0:bcfec522ef98 550 td->Control = 0;
memig3 0:bcfec522ef98 551 td->CurrBufPtr = 0;
memig3 0:bcfec522ef98 552 td->Next = 0;
memig3 0:bcfec522ef98 553 td->BufEnd = 0;
memig3 0:bcfec522ef98 554 }
memig3 0:bcfec522ef98 555
memig3 0:bcfec522ef98 556 /*
memig3 0:bcfec522ef98 557 **************************************************************************************************************
memig3 0:bcfec522ef98 558 * INITIALIZE THE ENDPOINT DESCRIPTOR
memig3 0:bcfec522ef98 559 *
memig3 0:bcfec522ef98 560 * Description: This function initializes endpoint descriptor
memig3 0:bcfec522ef98 561 *
memig3 0:bcfec522ef98 562 * Arguments : Pointer to ED strcuture
memig3 0:bcfec522ef98 563 *
memig3 0:bcfec522ef98 564 * Returns : None
memig3 0:bcfec522ef98 565 *
memig3 0:bcfec522ef98 566 **************************************************************************************************************
memig3 0:bcfec522ef98 567 */
memig3 0:bcfec522ef98 568
memig3 0:bcfec522ef98 569 void Host_EDInit (volatile HCED *ed)
memig3 0:bcfec522ef98 570 {
memig3 0:bcfec522ef98 571
memig3 0:bcfec522ef98 572 ed->Control = 0;
memig3 0:bcfec522ef98 573 ed->TailTd = 0;
memig3 0:bcfec522ef98 574 ed->HeadTd = 0;
memig3 0:bcfec522ef98 575 ed->Next = 0;
memig3 0:bcfec522ef98 576 }
memig3 0:bcfec522ef98 577
memig3 0:bcfec522ef98 578 /*
memig3 0:bcfec522ef98 579 **************************************************************************************************************
memig3 0:bcfec522ef98 580 * INITIALIZE HOST CONTROLLER COMMUNICATIONS AREA
memig3 0:bcfec522ef98 581 *
memig3 0:bcfec522ef98 582 * Description: This function initializes host controller communications area
memig3 0:bcfec522ef98 583 *
memig3 0:bcfec522ef98 584 * Arguments : Pointer to HCCA
memig3 0:bcfec522ef98 585 *
memig3 0:bcfec522ef98 586 * Returns :
memig3 0:bcfec522ef98 587 *
memig3 0:bcfec522ef98 588 **************************************************************************************************************
memig3 0:bcfec522ef98 589 */
memig3 0:bcfec522ef98 590
memig3 0:bcfec522ef98 591 void Host_HCCAInit (volatile HCCA *hcca)
memig3 0:bcfec522ef98 592 {
memig3 0:bcfec522ef98 593 USB_INT32U i;
memig3 0:bcfec522ef98 594
memig3 0:bcfec522ef98 595
memig3 0:bcfec522ef98 596 for (i = 0; i < 32; i++) {
memig3 0:bcfec522ef98 597
memig3 0:bcfec522ef98 598 hcca->IntTable[i] = 0;
memig3 0:bcfec522ef98 599 hcca->FrameNumber = 0;
memig3 0:bcfec522ef98 600 hcca->DoneHead = 0;
memig3 0:bcfec522ef98 601 }
memig3 0:bcfec522ef98 602
memig3 0:bcfec522ef98 603 }
memig3 0:bcfec522ef98 604
memig3 0:bcfec522ef98 605 /*
memig3 0:bcfec522ef98 606 **************************************************************************************************************
memig3 0:bcfec522ef98 607 * WAIT FOR WDH INTERRUPT
memig3 0:bcfec522ef98 608 *
memig3 0:bcfec522ef98 609 * Description: This function is infinite loop which breaks when ever a WDH interrupt rises
memig3 0:bcfec522ef98 610 *
memig3 0:bcfec522ef98 611 * Arguments : None
memig3 0:bcfec522ef98 612 *
memig3 0:bcfec522ef98 613 * Returns : None
memig3 0:bcfec522ef98 614 *
memig3 0:bcfec522ef98 615 **************************************************************************************************************
memig3 0:bcfec522ef98 616 */
memig3 0:bcfec522ef98 617
memig3 0:bcfec522ef98 618 void Host_WDHWait (void)
memig3 0:bcfec522ef98 619 {
memig3 0:bcfec522ef98 620 while (!HOST_WdhIntr)
memig3 0:bcfec522ef98 621 __WFI();
memig3 0:bcfec522ef98 622
memig3 0:bcfec522ef98 623 HOST_WdhIntr = 0;
memig3 0:bcfec522ef98 624 }
memig3 0:bcfec522ef98 625
memig3 0:bcfec522ef98 626 /*
memig3 0:bcfec522ef98 627 **************************************************************************************************************
memig3 0:bcfec522ef98 628 * READ LE 32U
memig3 0:bcfec522ef98 629 *
memig3 0:bcfec522ef98 630 * Description: This function is used to read an unsigned integer from a character buffer in the platform
memig3 0:bcfec522ef98 631 * containing little endian processor
memig3 0:bcfec522ef98 632 *
memig3 0:bcfec522ef98 633 * Arguments : pmem Pointer to the character buffer
memig3 0:bcfec522ef98 634 *
memig3 0:bcfec522ef98 635 * Returns : val Unsigned integer
memig3 0:bcfec522ef98 636 *
memig3 0:bcfec522ef98 637 **************************************************************************************************************
memig3 0:bcfec522ef98 638 */
memig3 0:bcfec522ef98 639
memig3 0:bcfec522ef98 640 USB_INT32U ReadLE32U (volatile USB_INT08U *pmem)
memig3 0:bcfec522ef98 641 {
memig3 0:bcfec522ef98 642 USB_INT32U val = *(USB_INT32U*)pmem;
memig3 0:bcfec522ef98 643 #ifdef __BIG_ENDIAN
memig3 0:bcfec522ef98 644 return __REV(val);
memig3 0:bcfec522ef98 645 #else
memig3 0:bcfec522ef98 646 return val;
memig3 0:bcfec522ef98 647 #endif
memig3 0:bcfec522ef98 648 }
memig3 0:bcfec522ef98 649
memig3 0:bcfec522ef98 650 /*
memig3 0:bcfec522ef98 651 **************************************************************************************************************
memig3 0:bcfec522ef98 652 * WRITE LE 32U
memig3 0:bcfec522ef98 653 *
memig3 0:bcfec522ef98 654 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
memig3 0:bcfec522ef98 655 * containing little endian processor.
memig3 0:bcfec522ef98 656 *
memig3 0:bcfec522ef98 657 * Arguments : pmem Pointer to the charecter buffer
memig3 0:bcfec522ef98 658 * val Integer value to be placed in the charecter buffer
memig3 0:bcfec522ef98 659 *
memig3 0:bcfec522ef98 660 * Returns : None
memig3 0:bcfec522ef98 661 *
memig3 0:bcfec522ef98 662 **************************************************************************************************************
memig3 0:bcfec522ef98 663 */
memig3 0:bcfec522ef98 664
memig3 0:bcfec522ef98 665 void WriteLE32U (volatile USB_INT08U *pmem,
memig3 0:bcfec522ef98 666 USB_INT32U val)
memig3 0:bcfec522ef98 667 {
memig3 0:bcfec522ef98 668 #ifdef __BIG_ENDIAN
memig3 0:bcfec522ef98 669 *(USB_INT32U*)pmem = __REV(val);
memig3 0:bcfec522ef98 670 #else
memig3 0:bcfec522ef98 671 *(USB_INT32U*)pmem = val;
memig3 0:bcfec522ef98 672 #endif
memig3 0:bcfec522ef98 673 }
memig3 0:bcfec522ef98 674
memig3 0:bcfec522ef98 675 /*
memig3 0:bcfec522ef98 676 **************************************************************************************************************
memig3 0:bcfec522ef98 677 * READ LE 16U
memig3 0:bcfec522ef98 678 *
memig3 0:bcfec522ef98 679 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
memig3 0:bcfec522ef98 680 * containing little endian processor
memig3 0:bcfec522ef98 681 *
memig3 0:bcfec522ef98 682 * Arguments : pmem Pointer to the charecter buffer
memig3 0:bcfec522ef98 683 *
memig3 0:bcfec522ef98 684 * Returns : val Unsigned short integer
memig3 0:bcfec522ef98 685 *
memig3 0:bcfec522ef98 686 **************************************************************************************************************
memig3 0:bcfec522ef98 687 */
memig3 0:bcfec522ef98 688
memig3 0:bcfec522ef98 689 USB_INT16U ReadLE16U (volatile USB_INT08U *pmem)
memig3 0:bcfec522ef98 690 {
memig3 0:bcfec522ef98 691 USB_INT16U val = *(USB_INT16U*)pmem;
memig3 0:bcfec522ef98 692 #ifdef __BIG_ENDIAN
memig3 0:bcfec522ef98 693 return __REV16(val);
memig3 0:bcfec522ef98 694 #else
memig3 0:bcfec522ef98 695 return val;
memig3 0:bcfec522ef98 696 #endif
memig3 0:bcfec522ef98 697 }
memig3 0:bcfec522ef98 698
memig3 0:bcfec522ef98 699 /*
memig3 0:bcfec522ef98 700 **************************************************************************************************************
memig3 0:bcfec522ef98 701 * WRITE LE 16U
memig3 0:bcfec522ef98 702 *
memig3 0:bcfec522ef98 703 * Description: This function is used to write an unsigned short integer into a charecter buffer in the
memig3 0:bcfec522ef98 704 * platform containing little endian processor
memig3 0:bcfec522ef98 705 *
memig3 0:bcfec522ef98 706 * Arguments : pmem Pointer to the charecter buffer
memig3 0:bcfec522ef98 707 * val Value to be placed in the charecter buffer
memig3 0:bcfec522ef98 708 *
memig3 0:bcfec522ef98 709 * Returns : None
memig3 0:bcfec522ef98 710 *
memig3 0:bcfec522ef98 711 **************************************************************************************************************
memig3 0:bcfec522ef98 712 */
memig3 0:bcfec522ef98 713
memig3 0:bcfec522ef98 714 void WriteLE16U (volatile USB_INT08U *pmem,
memig3 0:bcfec522ef98 715 USB_INT16U val)
memig3 0:bcfec522ef98 716 {
memig3 0:bcfec522ef98 717 #ifdef __BIG_ENDIAN
memig3 0:bcfec522ef98 718 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
memig3 0:bcfec522ef98 719 #else
memig3 0:bcfec522ef98 720 *(USB_INT16U*)pmem = val;
memig3 0:bcfec522ef98 721 #endif
memig3 0:bcfec522ef98 722 }
memig3 0:bcfec522ef98 723
memig3 0:bcfec522ef98 724 /*
memig3 0:bcfec522ef98 725 **************************************************************************************************************
memig3 0:bcfec522ef98 726 * READ BE 32U
memig3 0:bcfec522ef98 727 *
memig3 0:bcfec522ef98 728 * Description: This function is used to read an unsigned integer from a charecter buffer in the platform
memig3 0:bcfec522ef98 729 * containing big endian processor
memig3 0:bcfec522ef98 730 *
memig3 0:bcfec522ef98 731 * Arguments : pmem Pointer to the charecter buffer
memig3 0:bcfec522ef98 732 *
memig3 0:bcfec522ef98 733 * Returns : val Unsigned integer
memig3 0:bcfec522ef98 734 *
memig3 0:bcfec522ef98 735 **************************************************************************************************************
memig3 0:bcfec522ef98 736 */
memig3 0:bcfec522ef98 737
memig3 0:bcfec522ef98 738 USB_INT32U ReadBE32U (volatile USB_INT08U *pmem)
memig3 0:bcfec522ef98 739 {
memig3 0:bcfec522ef98 740 USB_INT32U val = *(USB_INT32U*)pmem;
memig3 0:bcfec522ef98 741 #ifdef __BIG_ENDIAN
memig3 0:bcfec522ef98 742 return val;
memig3 0:bcfec522ef98 743 #else
memig3 0:bcfec522ef98 744 return __REV(val);
memig3 0:bcfec522ef98 745 #endif
memig3 0:bcfec522ef98 746 }
memig3 0:bcfec522ef98 747
memig3 0:bcfec522ef98 748 /*
memig3 0:bcfec522ef98 749 **************************************************************************************************************
memig3 0:bcfec522ef98 750 * WRITE BE 32U
memig3 0:bcfec522ef98 751 *
memig3 0:bcfec522ef98 752 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
memig3 0:bcfec522ef98 753 * containing big endian processor
memig3 0:bcfec522ef98 754 *
memig3 0:bcfec522ef98 755 * Arguments : pmem Pointer to the charecter buffer
memig3 0:bcfec522ef98 756 * val Value to be placed in the charecter buffer
memig3 0:bcfec522ef98 757 *
memig3 0:bcfec522ef98 758 * Returns : None
memig3 0:bcfec522ef98 759 *
memig3 0:bcfec522ef98 760 **************************************************************************************************************
memig3 0:bcfec522ef98 761 */
memig3 0:bcfec522ef98 762
memig3 0:bcfec522ef98 763 void WriteBE32U (volatile USB_INT08U *pmem,
memig3 0:bcfec522ef98 764 USB_INT32U val)
memig3 0:bcfec522ef98 765 {
memig3 0:bcfec522ef98 766 #ifdef __BIG_ENDIAN
memig3 0:bcfec522ef98 767 *(USB_INT32U*)pmem = val;
memig3 0:bcfec522ef98 768 #else
memig3 0:bcfec522ef98 769 *(USB_INT32U*)pmem = __REV(val);
memig3 0:bcfec522ef98 770 #endif
memig3 0:bcfec522ef98 771 }
memig3 0:bcfec522ef98 772
memig3 0:bcfec522ef98 773 /*
memig3 0:bcfec522ef98 774 **************************************************************************************************************
memig3 0:bcfec522ef98 775 * READ BE 16U
memig3 0:bcfec522ef98 776 *
memig3 0:bcfec522ef98 777 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
memig3 0:bcfec522ef98 778 * containing big endian processor
memig3 0:bcfec522ef98 779 *
memig3 0:bcfec522ef98 780 * Arguments : pmem Pointer to the charecter buffer
memig3 0:bcfec522ef98 781 *
memig3 0:bcfec522ef98 782 * Returns : val Unsigned short integer
memig3 0:bcfec522ef98 783 *
memig3 0:bcfec522ef98 784 **************************************************************************************************************
memig3 0:bcfec522ef98 785 */
memig3 0:bcfec522ef98 786
memig3 0:bcfec522ef98 787 USB_INT16U ReadBE16U (volatile USB_INT08U *pmem)
memig3 0:bcfec522ef98 788 {
memig3 0:bcfec522ef98 789 USB_INT16U val = *(USB_INT16U*)pmem;
memig3 0:bcfec522ef98 790 #ifdef __BIG_ENDIAN
memig3 0:bcfec522ef98 791 return val;
memig3 0:bcfec522ef98 792 #else
memig3 0:bcfec522ef98 793 return __REV16(val);
memig3 0:bcfec522ef98 794 #endif
memig3 0:bcfec522ef98 795 }
memig3 0:bcfec522ef98 796
memig3 0:bcfec522ef98 797 /*
memig3 0:bcfec522ef98 798 **************************************************************************************************************
memig3 0:bcfec522ef98 799 * WRITE BE 16U
memig3 0:bcfec522ef98 800 *
memig3 0:bcfec522ef98 801 * Description: This function is used to write an unsigned short integer into the charecter buffer in the
memig3 0:bcfec522ef98 802 * platform containing big endian processor
memig3 0:bcfec522ef98 803 *
memig3 0:bcfec522ef98 804 * Arguments : pmem Pointer to the charecter buffer
memig3 0:bcfec522ef98 805 * val Value to be placed in the charecter buffer
memig3 0:bcfec522ef98 806 *
memig3 0:bcfec522ef98 807 * Returns : None
memig3 0:bcfec522ef98 808 *
memig3 0:bcfec522ef98 809 **************************************************************************************************************
memig3 0:bcfec522ef98 810 */
memig3 0:bcfec522ef98 811
memig3 0:bcfec522ef98 812 void WriteBE16U (volatile USB_INT08U *pmem,
memig3 0:bcfec522ef98 813 USB_INT16U val)
memig3 0:bcfec522ef98 814 {
memig3 0:bcfec522ef98 815 #ifdef __BIG_ENDIAN
memig3 0:bcfec522ef98 816 *(USB_INT16U*)pmem = val;
memig3 0:bcfec522ef98 817 #else
memig3 0:bcfec522ef98 818 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
memig3 0:bcfec522ef98 819 #endif
memig3 0:bcfec522ef98 820 }