David Yu / Mbed 2 deprecated 4180_Fitbit_rtos

Fitbit code using RTOS

Dependencies:   mbed PulseSensor2 SCP1000 mbed-rtos 4DGL-uLCD-SE LSM9DS1_Library_cal PinDetect FatFileSystemCpp GP-20U7

USBHostLite/usbhost_lpc17xx.h@4:158ea0c5531c, 2020-04-22 (annotated)

Committer:
dyu2021
Date:
Wed Apr 22 17:22:42 2020 +0000
Revision:
4:158ea0c5531c
Parent:
0:bcfec522ef98 
Updated GPS distance calculation and fixed saving dates

Who changed what in which revision?

UserRevisionLine numberNew contents of line
memig3 0:bcfec522ef98 1 /*
memig3 0:bcfec522ef98 2 **************************************************************************************************************
memig3 0:bcfec522ef98 3 * NXP USB Host Stack
memig3 0:bcfec522ef98 4 *
memig3 0:bcfec522ef98 5 * (c) Copyright 2008, NXP SemiConductors
memig3 0:bcfec522ef98 6 * (c) Copyright 2008, OnChip Technologies LLC
memig3 0:bcfec522ef98 7 * All Rights Reserved
memig3 0:bcfec522ef98 8 *
memig3 0:bcfec522ef98 9 * www.nxp.com
memig3 0:bcfec522ef98 10 * www.onchiptech.com
memig3 0:bcfec522ef98 11 *
memig3 0:bcfec522ef98 12 * File : usbhost_lpc17xx.h
memig3 0:bcfec522ef98 13 * Programmer(s) : Ravikanth.P
memig3 0:bcfec522ef98 14 * Version :
memig3 0:bcfec522ef98 15 *
memig3 0:bcfec522ef98 16 **************************************************************************************************************
memig3 0:bcfec522ef98 17 */
memig3 0:bcfec522ef98 18
memig3 0:bcfec522ef98 19 #ifndef USBHOST_LPC17xx_H
memig3 0:bcfec522ef98 20 #define USBHOST_LPC17xx_H
memig3 0:bcfec522ef98 21
memig3 0:bcfec522ef98 22 /*
memig3 0:bcfec522ef98 23 **************************************************************************************************************
memig3 0:bcfec522ef98 24 * INCLUDE HEADER FILES
memig3 0:bcfec522ef98 25 **************************************************************************************************************
memig3 0:bcfec522ef98 26 */
memig3 0:bcfec522ef98 27
memig3 0:bcfec522ef98 28 #include "usbhost_inc.h"
memig3 0:bcfec522ef98 29
memig3 0:bcfec522ef98 30 /*
memig3 0:bcfec522ef98 31 **************************************************************************************************************
memig3 0:bcfec522ef98 32 * PRINT CONFIGURATION
memig3 0:bcfec522ef98 33 **************************************************************************************************************
memig3 0:bcfec522ef98 34 */
memig3 0:bcfec522ef98 35
memig3 0:bcfec522ef98 36 #define PRINT_ENABLE 1
memig3 0:bcfec522ef98 37
memig3 0:bcfec522ef98 38 #if PRINT_ENABLE
memig3 0:bcfec522ef98 39 #define PRINT_Log(...) printf(__VA_ARGS__)
memig3 0:bcfec522ef98 40 #define PRINT_Err(rc) printf("ERROR: In %s at Line %u - rc = %d\n", __FUNCTION__, __LINE__, rc)
memig3 0:bcfec522ef98 41
memig3 0:bcfec522ef98 42 #else
memig3 0:bcfec522ef98 43 #define PRINT_Log(...) do {} while(0)
memig3 0:bcfec522ef98 44 #define PRINT_Err(rc) do {} while(0)
memig3 0:bcfec522ef98 45
memig3 0:bcfec522ef98 46 #endif
memig3 0:bcfec522ef98 47
memig3 0:bcfec522ef98 48 /*
memig3 0:bcfec522ef98 49 **************************************************************************************************************
memig3 0:bcfec522ef98 50 * GENERAL DEFINITIONS
memig3 0:bcfec522ef98 51 **************************************************************************************************************
memig3 0:bcfec522ef98 52 */
memig3 0:bcfec522ef98 53
memig3 0:bcfec522ef98 54 #define DESC_LENGTH(x) x[0]
memig3 0:bcfec522ef98 55 #define DESC_TYPE(x) x[1]
memig3 0:bcfec522ef98 56
memig3 0:bcfec522ef98 57
memig3 0:bcfec522ef98 58 #define HOST_GET_DESCRIPTOR(descType, descIndex, data, length) \
memig3 0:bcfec522ef98 59 Host_CtrlRecv(USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE, GET_DESCRIPTOR, \
memig3 0:bcfec522ef98 60 (descType << 8)|(descIndex), 0, length, data)
memig3 0:bcfec522ef98 61
memig3 0:bcfec522ef98 62 #define HOST_SET_ADDRESS(new_addr) \
memig3 0:bcfec522ef98 63 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE, SET_ADDRESS, \
memig3 0:bcfec522ef98 64 new_addr, 0, 0, NULL)
memig3 0:bcfec522ef98 65
memig3 0:bcfec522ef98 66 #define USBH_SET_CONFIGURATION(configNum) \
memig3 0:bcfec522ef98 67 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE, SET_CONFIGURATION, \
memig3 0:bcfec522ef98 68 configNum, 0, 0, NULL)
memig3 0:bcfec522ef98 69
memig3 0:bcfec522ef98 70 #define USBH_SET_INTERFACE(ifNum, altNum) \
memig3 0:bcfec522ef98 71 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_INTERFACE, SET_INTERFACE, \
memig3 0:bcfec522ef98 72 altNum, ifNum, 0, NULL)
memig3 0:bcfec522ef98 73
memig3 0:bcfec522ef98 74 /*
memig3 0:bcfec522ef98 75 **************************************************************************************************************
memig3 0:bcfec522ef98 76 * OHCI OPERATIONAL REGISTER FIELD DEFINITIONS
memig3 0:bcfec522ef98 77 **************************************************************************************************************
memig3 0:bcfec522ef98 78 */
memig3 0:bcfec522ef98 79
memig3 0:bcfec522ef98 80 /* ------------------ HcControl Register --------------------- */
memig3 0:bcfec522ef98 81 #define OR_CONTROL_CLE 0x00000010
memig3 0:bcfec522ef98 82 #define OR_CONTROL_BLE 0x00000020
memig3 0:bcfec522ef98 83 #define OR_CONTROL_HCFS 0x000000C0
memig3 0:bcfec522ef98 84 #define OR_CONTROL_HC_OPER 0x00000080
memig3 0:bcfec522ef98 85 /* ----------------- HcCommandStatus Register ----------------- */
memig3 0:bcfec522ef98 86 #define OR_CMD_STATUS_HCR 0x00000001
memig3 0:bcfec522ef98 87 #define OR_CMD_STATUS_CLF 0x00000002
memig3 0:bcfec522ef98 88 #define OR_CMD_STATUS_BLF 0x00000004
memig3 0:bcfec522ef98 89 /* --------------- HcInterruptStatus Register ----------------- */
memig3 0:bcfec522ef98 90 #define OR_INTR_STATUS_WDH 0x00000002
memig3 0:bcfec522ef98 91 #define OR_INTR_STATUS_RHSC 0x00000040
memig3 0:bcfec522ef98 92 /* --------------- HcInterruptEnable Register ----------------- */
memig3 0:bcfec522ef98 93 #define OR_INTR_ENABLE_WDH 0x00000002
memig3 0:bcfec522ef98 94 #define OR_INTR_ENABLE_RHSC 0x00000040
memig3 0:bcfec522ef98 95 #define OR_INTR_ENABLE_MIE 0x80000000
memig3 0:bcfec522ef98 96 /* ---------------- HcRhDescriptorA Register ------------------ */
memig3 0:bcfec522ef98 97 #define OR_RH_STATUS_LPSC 0x00010000
memig3 0:bcfec522ef98 98 #define OR_RH_STATUS_DRWE 0x00008000
memig3 0:bcfec522ef98 99 /* -------------- HcRhPortStatus[1:NDP] Register -------------- */
memig3 0:bcfec522ef98 100 #define OR_RH_PORT_CCS 0x00000001
memig3 0:bcfec522ef98 101 #define OR_RH_PORT_PRS 0x00000010
memig3 0:bcfec522ef98 102 #define OR_RH_PORT_CSC 0x00010000
memig3 0:bcfec522ef98 103 #define OR_RH_PORT_PRSC 0x00100000
memig3 0:bcfec522ef98 104
memig3 0:bcfec522ef98 105
memig3 0:bcfec522ef98 106 /*
memig3 0:bcfec522ef98 107 **************************************************************************************************************
memig3 0:bcfec522ef98 108 * FRAME INTERVAL
memig3 0:bcfec522ef98 109 **************************************************************************************************************
memig3 0:bcfec522ef98 110 */
memig3 0:bcfec522ef98 111
memig3 0:bcfec522ef98 112 #define FI 0x2EDF /* 12000 bits per frame (-1) */
memig3 0:bcfec522ef98 113 #define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
memig3 0:bcfec522ef98 114
memig3 0:bcfec522ef98 115 /*
memig3 0:bcfec522ef98 116 **************************************************************************************************************
memig3 0:bcfec522ef98 117 * TRANSFER DESCRIPTOR CONTROL FIELDS
memig3 0:bcfec522ef98 118 **************************************************************************************************************
memig3 0:bcfec522ef98 119 */
memig3 0:bcfec522ef98 120
memig3 0:bcfec522ef98 121 #define TD_ROUNDING (USB_INT32U) (0x00040000) /* Buffer Rounding */
memig3 0:bcfec522ef98 122 #define TD_SETUP (USB_INT32U)(0) /* Direction of Setup Packet */
memig3 0:bcfec522ef98 123 #define TD_IN (USB_INT32U)(0x00100000) /* Direction In */
memig3 0:bcfec522ef98 124 #define TD_OUT (USB_INT32U)(0x00080000) /* Direction Out */
memig3 0:bcfec522ef98 125 #define TD_DELAY_INT(x) (USB_INT32U)((x) << 21) /* Delay Interrupt */
memig3 0:bcfec522ef98 126 #define TD_TOGGLE_0 (USB_INT32U)(0x02000000) /* Toggle 0 */
memig3 0:bcfec522ef98 127 #define TD_TOGGLE_1 (USB_INT32U)(0x03000000) /* Toggle 1 */
memig3 0:bcfec522ef98 128 #define TD_CC (USB_INT32U)(0xF0000000) /* Completion Code */
memig3 0:bcfec522ef98 129
memig3 0:bcfec522ef98 130 /*
memig3 0:bcfec522ef98 131 **************************************************************************************************************
memig3 0:bcfec522ef98 132 * USB STANDARD REQUEST DEFINITIONS
memig3 0:bcfec522ef98 133 **************************************************************************************************************
memig3 0:bcfec522ef98 134 */
memig3 0:bcfec522ef98 135
memig3 0:bcfec522ef98 136 #define USB_DESCRIPTOR_TYPE_DEVICE 1
memig3 0:bcfec522ef98 137 #define USB_DESCRIPTOR_TYPE_CONFIGURATION 2
memig3 0:bcfec522ef98 138 #define USB_DESCRIPTOR_TYPE_INTERFACE 4
memig3 0:bcfec522ef98 139 #define USB_DESCRIPTOR_TYPE_ENDPOINT 5
memig3 0:bcfec522ef98 140 /* ----------- Control RequestType Fields ----------- */
memig3 0:bcfec522ef98 141 #define USB_DEVICE_TO_HOST 0x80
memig3 0:bcfec522ef98 142 #define USB_HOST_TO_DEVICE 0x00
memig3 0:bcfec522ef98 143 #define USB_REQUEST_TYPE_CLASS 0x20
memig3 0:bcfec522ef98 144 #define USB_RECIPIENT_DEVICE 0x00
memig3 0:bcfec522ef98 145 #define USB_RECIPIENT_INTERFACE 0x01
memig3 0:bcfec522ef98 146 /* -------------- USB Standard Requests -------------- */
memig3 0:bcfec522ef98 147 #define SET_ADDRESS 5
memig3 0:bcfec522ef98 148 #define GET_DESCRIPTOR 6
memig3 0:bcfec522ef98 149 #define SET_CONFIGURATION 9
memig3 0:bcfec522ef98 150 #define SET_INTERFACE 11
memig3 0:bcfec522ef98 151
memig3 0:bcfec522ef98 152 /*
memig3 0:bcfec522ef98 153 **************************************************************************************************************
memig3 0:bcfec522ef98 154 * TYPE DEFINITIONS
memig3 0:bcfec522ef98 155 **************************************************************************************************************
memig3 0:bcfec522ef98 156 */
memig3 0:bcfec522ef98 157
memig3 0:bcfec522ef98 158 typedef struct hcEd { /* ----------- HostController EndPoint Descriptor ------------- */
memig3 0:bcfec522ef98 159 volatile USB_INT32U Control; /* Endpoint descriptor control */
memig3 0:bcfec522ef98 160 volatile USB_INT32U TailTd; /* Physical address of tail in Transfer descriptor list */
memig3 0:bcfec522ef98 161 volatile USB_INT32U HeadTd; /* Physcial address of head in Transfer descriptor list */
memig3 0:bcfec522ef98 162 volatile USB_INT32U Next; /* Physical address of next Endpoint descriptor */
memig3 0:bcfec522ef98 163 } HCED;
memig3 0:bcfec522ef98 164
memig3 0:bcfec522ef98 165 typedef struct hcTd { /* ------------ HostController Transfer Descriptor ------------ */
memig3 0:bcfec522ef98 166 volatile USB_INT32U Control; /* Transfer descriptor control */
memig3 0:bcfec522ef98 167 volatile USB_INT32U CurrBufPtr; /* Physical address of current buffer pointer */
memig3 0:bcfec522ef98 168 volatile USB_INT32U Next; /* Physical pointer to next Transfer Descriptor */
memig3 0:bcfec522ef98 169 volatile USB_INT32U BufEnd; /* Physical address of end of buffer */
memig3 0:bcfec522ef98 170 } HCTD;
memig3 0:bcfec522ef98 171
memig3 0:bcfec522ef98 172 typedef struct hcca { /* ----------- Host Controller Communication Area ------------ */
memig3 0:bcfec522ef98 173 volatile USB_INT32U IntTable[32]; /* Interrupt Table */
memig3 0:bcfec522ef98 174 volatile USB_INT32U FrameNumber; /* Frame Number */
memig3 0:bcfec522ef98 175 volatile USB_INT32U DoneHead; /* Done Head */
memig3 0:bcfec522ef98 176 volatile USB_INT08U Reserved[116]; /* Reserved for future use */
memig3 0:bcfec522ef98 177 volatile USB_INT08U Unknown[4]; /* Unused */
memig3 0:bcfec522ef98 178 } HCCA;
memig3 0:bcfec522ef98 179
memig3 0:bcfec522ef98 180 /*
memig3 0:bcfec522ef98 181 **************************************************************************************************************
memig3 0:bcfec522ef98 182 * EXTERN DECLARATIONS
memig3 0:bcfec522ef98 183 **************************************************************************************************************
memig3 0:bcfec522ef98 184 */
memig3 0:bcfec522ef98 185
memig3 0:bcfec522ef98 186 extern volatile HCED *EDBulkIn; /* BulkIn endpoint descriptor structure */
memig3 0:bcfec522ef98 187 extern volatile HCED *EDBulkOut; /* BulkOut endpoint descriptor structure */
memig3 0:bcfec522ef98 188 extern volatile HCTD *TDHead; /* Head transfer descriptor structure */
memig3 0:bcfec522ef98 189 extern volatile HCTD *TDTail; /* Tail transfer descriptor structure */
memig3 0:bcfec522ef98 190 extern volatile USB_INT08U *TDBuffer; /* Current Buffer Pointer of transfer descriptor */
memig3 0:bcfec522ef98 191
memig3 0:bcfec522ef98 192 /*
memig3 0:bcfec522ef98 193 **************************************************************************************************************
memig3 0:bcfec522ef98 194 * FUNCTION PROTOTYPES
memig3 0:bcfec522ef98 195 **************************************************************************************************************
memig3 0:bcfec522ef98 196 */
memig3 0:bcfec522ef98 197
memig3 0:bcfec522ef98 198 void Host_Init (void);
memig3 0:bcfec522ef98 199
memig3 0:bcfec522ef98 200 extern "C" void USB_IRQHandler(void) __irq;
memig3 0:bcfec522ef98 201
memig3 0:bcfec522ef98 202 USB_INT32S Host_EnumDev (void);
memig3 0:bcfec522ef98 203
memig3 0:bcfec522ef98 204 USB_INT32S Host_ProcessTD(volatile HCED *ed,
memig3 0:bcfec522ef98 205 volatile USB_INT32U token,
memig3 0:bcfec522ef98 206 volatile USB_INT08U *buffer,
memig3 0:bcfec522ef98 207 USB_INT32U buffer_len);
memig3 0:bcfec522ef98 208
memig3 0:bcfec522ef98 209 void Host_DelayUS ( USB_INT32U delay);
memig3 0:bcfec522ef98 210 void Host_DelayMS ( USB_INT32U delay);
memig3 0:bcfec522ef98 211
memig3 0:bcfec522ef98 212
memig3 0:bcfec522ef98 213 void Host_TDInit (volatile HCTD *td);
memig3 0:bcfec522ef98 214 void Host_EDInit (volatile HCED *ed);
memig3 0:bcfec522ef98 215 void Host_HCCAInit (volatile HCCA *hcca);
memig3 0:bcfec522ef98 216
memig3 0:bcfec522ef98 217 USB_INT32S Host_CtrlRecv ( USB_INT08U bm_request_type,
memig3 0:bcfec522ef98 218 USB_INT08U b_request,
memig3 0:bcfec522ef98 219 USB_INT16U w_value,
memig3 0:bcfec522ef98 220 USB_INT16U w_index,
memig3 0:bcfec522ef98 221 USB_INT16U w_length,
memig3 0:bcfec522ef98 222 volatile USB_INT08U *buffer);
memig3 0:bcfec522ef98 223
memig3 0:bcfec522ef98 224 USB_INT32S Host_CtrlSend ( USB_INT08U bm_request_type,
memig3 0:bcfec522ef98 225 USB_INT08U b_request,
memig3 0:bcfec522ef98 226 USB_INT16U w_value,
memig3 0:bcfec522ef98 227 USB_INT16U w_index,
memig3 0:bcfec522ef98 228 USB_INT16U w_length,
memig3 0:bcfec522ef98 229 volatile USB_INT08U *buffer);
memig3 0:bcfec522ef98 230
memig3 0:bcfec522ef98 231 void Host_FillSetup( USB_INT08U bm_request_type,
memig3 0:bcfec522ef98 232 USB_INT08U b_request,
memig3 0:bcfec522ef98 233 USB_INT16U w_value,
memig3 0:bcfec522ef98 234 USB_INT16U w_index,
memig3 0:bcfec522ef98 235 USB_INT16U w_length);
memig3 0:bcfec522ef98 236
memig3 0:bcfec522ef98 237
memig3 0:bcfec522ef98 238 void Host_WDHWait (void);
memig3 0:bcfec522ef98 239
memig3 0:bcfec522ef98 240
memig3 0:bcfec522ef98 241 USB_INT32U ReadLE32U (volatile USB_INT08U *pmem);
memig3 0:bcfec522ef98 242 void WriteLE32U (volatile USB_INT08U *pmem,
memig3 0:bcfec522ef98 243 USB_INT32U val);
memig3 0:bcfec522ef98 244 USB_INT16U ReadLE16U (volatile USB_INT08U *pmem);
memig3 0:bcfec522ef98 245 void WriteLE16U (volatile USB_INT08U *pmem,
memig3 0:bcfec522ef98 246 USB_INT16U val);
memig3 0:bcfec522ef98 247 USB_INT32U ReadBE32U (volatile USB_INT08U *pmem);
memig3 0:bcfec522ef98 248 void WriteBE32U (volatile USB_INT08U *pmem,
memig3 0:bcfec522ef98 249 USB_INT32U val);
memig3 0:bcfec522ef98 250 USB_INT16U ReadBE16U (volatile USB_INT08U *pmem);
memig3 0:bcfec522ef98 251 void WriteBE16U (volatile USB_INT08U *pmem,
memig3 0:bcfec522ef98 252 USB_INT16U val);
memig3 0:bcfec522ef98 253
memig3 0:bcfec522ef98 254 #endif