wayne roberts
sx1261/2 driver
Dependents: alarm_slave iq_sx126x sx126x_simple_TX_shield_2020a sx126x_simple_RX_shield_2020a ... more
Driver for SX1261 or SX1262
Diff: sx12xx.h
- Revision:
- 5:8b75387af4e0
- Parent:
- 4:b941bceb401d
- Child:
- 6:cd4b02a7e65d
--- a/sx12xx.h Thu Jul 05 13:38:27 2018 -0700
+++ b/sx12xx.h Thu Aug 16 14:47:55 2018 -0700
@@ -43,7 +43,8 @@
#define OPCODE_SET_LORA_SYMBOL_TIMEOUT 0xa0
#define OPCODE_GET_STATUS 0xc0
#define OPCODE_SET_FS 0xc1
-#define OPCODE_SET_TX_CONTINUOUS 0xd1
+#define OPCODE_SET_TX_CARRIER 0xd1
+#define OPCODE_SET_TX_PREAMBLE 0xd2
/***************************************************************/
#define PACKET_TYPE_GFSK 0
#define PACKET_TYPE_LORA 1
@@ -51,8 +52,8 @@
#define HEADER_TYPE_VARIABLE_LENGTH 0
#define HEADER_TYPE_FIXED_LENGTH 1
-#define CRC_OFF 0
-#define CRC_ON 0
+#define LROA_CRC_OFF 0
+#define LORA_CRC_ON 1
#define STANDARD_IQ 0
#define INVERTED_IQ 1
@@ -68,10 +69,14 @@
#define REG_ADDR_FSK_PKTCTRL1 0x6b4 // 3bit
#define REG_ADDR_FSK_PREAMBLE_TXLEN 0x6b5 // 16bit
#define REG_ADDR_FSK_SYNC_LEN 0x6b7 // 7bit
+#define REG_ADDR_FSK_PKTCTRL1A 0x6b8 // 14bit 5bits+9bits
#define REG_ADDR_FSK_PKTCTRL2 0x6ba // 8bit
#define REG_ADDR_FSK_PAYLOAD_LEN 0x6bb // 8bit
+#define REG_ADDR_FSK_CRCINIT 0x6bc // 16bit
+#define REG_ADDR_FSK_CRCPOLY 0x6be // 16bit
#define REG_ADDR_SYNCADDR 0x6c0 // 64bit fsk
#define REG_ADDR_NODEADDR 0x6cd // 8bit fsk
+#define REG_ADDR_BROADCAST 0x6ce // 8bit fsk
#define REG_ADDR_NODEADDRCOMP 0x6cf // 2bit fsk
#define REG_ADDR_LORA_TXPKTLEN 0x702 // 8bit
@@ -85,12 +90,20 @@
#define REG_ADDR_DIGFECTL 0x804 // 6bits
#define REG_ADDR_BWSEL 0x807 // 5bits
#define REG_ADDR_RANDOM 0x819 // ro
+#define REG_ADDR_PA_CTRL0 0x880 // 8bits
+#define REG_ADDR_PA_CTRL1 0x881 // 8bits
+#define REG_ADDR_DIG_CTRL 0x882 // 8bits
+#define REG_ADDR_PWR_CTRL 0x883 // 8bits
+#define REG_ADDR_I_GAIN 0x884 // 8bits integral gain in pi filter
+#define REG_ADDR_P_GAIN 0x885 // 8bits proportional gain in pi filter
#define REG_ADDR_RFFREQ 0x88b // 31bits
#define REG_ADDR_FREQ_OFFSET 0x88f // 19bits
#define REG_ADDR_ANACTRL6 0x8d7 // 6bits
#define REG_ADDR_ANACTRL7 0x8d8 // 6bits
#define REG_ADDR_ANACTRL15 0x8e1 // 7bits
-#define REG_ADDR_OCP 0x8e7
+#define REG_ADDR_PA_CTRL1B 0x8e6
+#define REG_ADDR_OCP 0x8e7 // 6bits Imax 2.5mA steps
+#define REG_ADDR_IMAX_OFFSET 0x8e8 // 5bits OCP offset
#define REG_ADDR_ 0x
/**********************************************/
@@ -221,7 +234,7 @@
typedef union {
struct {
- uint8_t bt : 2; // 0,1 0=BT1.0 1=BT0.5 2=BT0.3
+ uint8_t bt : 2; // 0,1 0=BT0.3 1=BT0.5 2=BT0.7 3=BT1.0
uint8_t double_rate : 1; // 2 double oversampling rate
uint8_t pulse_shape : 2; // 3,4 0=noFilter 1=gaussian 2=RRC
uint8_t res : 3; // 5,6,7
@@ -245,15 +258,27 @@
typedef union {
struct {
- uint8_t preamble_len_rx : 2; // 0,1 number of preamble bits detected
- uint8_t preamble_det_on : 1; // 2 enable rx-sde preamble detector
- uint8_t res : 1; // 7
+ uint8_t preamble_len_rx : 2; // 0,1 number of preamble bits detected
+ uint8_t preamble_det_on : 1; // 2 enable rx-sde preamble detector
+ uint8_t res : 5; // 7
} bits;
uint8_t octet;
} pktCtrl1_t; // at 0x6b4 fsk
typedef union {
struct {
+ uint16_t whit_init_val : 9; // 0...8 at 0x6b9
+ uint16_t infinite_seq_en : 1; // 9
+ uint16_t infinite_seq_select : 2; // 10,11
+ uint16_t cont_tx : 1; // 12
+ uint16_t sync_det_on : 1; // 13
+ uint16_t res : 2; // 14,15
+ } bits;
+ uint16_t word;
+} PktCtrl1a_t; // at 0x6b8
+
+typedef union {
+ struct {
uint8_t crc_disable : 1; // 0
uint8_t crc_len : 1; // 1 0=1byte 1=2byte
uint8_t crc_inv : 1; // 2
@@ -321,9 +346,49 @@
typedef union {
struct {
+ uint8_t reg_pa_discharge_en : 1; // 0
+ uint8_t reg_pa_boost_en : 1; // 1
+ uint8_t dac_pol : 2; // 2,3
+ } bits;
+ uint8_t octet;
+} paCtrl0_t; // at 0x880
+
+typedef union {
+ struct {
+ uint8_t boost_delay : 6; // 0,1,2,3,4,5
+ uint8_t boost_width : 2; // 6,7
+ } bits;
+ uint8_t octet;
+} paCtrl1_t; // at 0x881
+
+typedef union {
+ struct {
+ uint8_t ramp_on : 1; // 0
+ uint8_t ramp_down : 1; // 1
+ uint8_t ramp_up : 1; // 2
+ uint8_t ramp_status : 1; // 3
+ uint8_t force_dac_code_en : 1; // 4
+ uint8_t pa_mod_en : 1; // 5
+ } bits;
+ uint8_t octet;
+} DigCtrl_t; // at 0x882
+
+typedef union {
+ struct {
+ uint8_t tx_pwr : 5; // 0,1,2,3,4
+ uint8_t ramp_time : 3; // 5,6,7
+ } bits;
+ uint8_t octet;
+} PwrCtrl_t; // at 0x883
+
+
+
+
+typedef union {
+ struct {
uint8_t pa_hp_ena_ana : 1; // 0
uint8_t tx_ena_bat : 1; // 1
- uint8_t pa_dctrim_select_ana : 4; // 2,3,4,5
+ uint8_t pa_dctrim_select_ana : 4; // 2,3,4,5 paDutyCycle
uint8_t res : 2; // 6,7
} bits;
uint8_t octet;
@@ -334,7 +399,7 @@
uint8_t pa_lp_ena_ana : 1; // 0
uint8_t pa_clamp_code_bat : 3; // 1,2,3
uint8_t pa_clamp_override_bat : 1; // 4
- uint8_t pa_hp_sel_ana : 1; // 5,6,7
+ uint8_t pa_hp_sel_ana : 3; // 5,6,7 hpMax
} bits;
uint8_t octet;
} AnaCtrl7_t; // at 0x8d8
@@ -352,6 +417,17 @@
typedef union {
struct {
+ uint8_t force_ref : 1; // 0
+ uint8_t pa_voltage_lim_en : 1; // 1
+ uint8_t pa_current_lim_en : 1; // 2
+ uint8_t tx_mode_bat : 1; // 3 deviceSel 0=hipower 1=lopower take precedence over hpp_mode
+ uint8_t hp_mode : 1; // 4 hi-power submode 0=14dBm LUT, 1=20dBm LUT
+ } bits;
+ uint8_t octet;
+} PaCtrl1b_t; // at 0x8e6
+
+typedef union {
+ struct {
uint8_t spreadingFactor; // param1
uint8_t bandwidth; // param2
uint8_t codingRate; // param3
@@ -430,6 +506,7 @@
void setStandby(stby_t);
void setSleep(bool warmStart, bool rtcWakeup);
void setFS(void);
+ void setBufferBase(uint8_t txAddr, uint8_t rxAddr);
static Callback<void()> dio1_topHalf; // low latency ISR context
void service(void);