wayne roberts / Mbed OS LoRaWAN_singlechannel_endnode

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Dependencies:   SX127x sx12xx_hal TSL2561

radio/sx1272/sx1272.cpp@3:aead8f8fdc1f, 2017-05-26 (annotated)

Committer:
dudmuck
Date:
Fri May 26 11:00:03 2017 -0700
Revision:
3:aead8f8fdc1f
Child:
5:c108560af4c3
add choice of radio chip

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dudmuck 3:aead8f8fdc1f 1 /*
dudmuck 3:aead8f8fdc1f 2 / _____) _ | |
dudmuck 3:aead8f8fdc1f 3 ( (____ _____ ____ _| |_ _____ ____| |__
dudmuck 3:aead8f8fdc1f 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
dudmuck 3:aead8f8fdc1f 5 _____) ) ____| | | || |_| ____( (___| | | |
dudmuck 3:aead8f8fdc1f 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
dudmuck 3:aead8f8fdc1f 7 (C) 2015 Semtech
dudmuck 3:aead8f8fdc1f 8
dudmuck 3:aead8f8fdc1f 9 Description: Actual implementation of a SX1272 radio, inherits Radio
dudmuck 3:aead8f8fdc1f 10
dudmuck 3:aead8f8fdc1f 11 License: Revised BSD License, see LICENSE.TXT file include in the project
dudmuck 3:aead8f8fdc1f 12
dudmuck 3:aead8f8fdc1f 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
dudmuck 3:aead8f8fdc1f 14 */
dudmuck 3:aead8f8fdc1f 15 #include "sx1272.h"
dudmuck 3:aead8f8fdc1f 16 #ifdef ENABLE_SX1272
dudmuck 3:aead8f8fdc1f 17
dudmuck 3:aead8f8fdc1f 18 extern LowPowerTimer lp_timer; // from LoRaMac
dudmuck 3:aead8f8fdc1f 19
dudmuck 3:aead8f8fdc1f 20 const FskBandwidth_t SX1272::FskBandwidths[] =
dudmuck 3:aead8f8fdc1f 21 {
dudmuck 3:aead8f8fdc1f 22 { 2600 , 0x17 },
dudmuck 3:aead8f8fdc1f 23 { 3100 , 0x0F },
dudmuck 3:aead8f8fdc1f 24 { 3900 , 0x07 },
dudmuck 3:aead8f8fdc1f 25 { 5200 , 0x16 },
dudmuck 3:aead8f8fdc1f 26 { 6300 , 0x0E },
dudmuck 3:aead8f8fdc1f 27 { 7800 , 0x06 },
dudmuck 3:aead8f8fdc1f 28 { 10400 , 0x15 },
dudmuck 3:aead8f8fdc1f 29 { 12500 , 0x0D },
dudmuck 3:aead8f8fdc1f 30 { 15600 , 0x05 },
dudmuck 3:aead8f8fdc1f 31 { 20800 , 0x14 },
dudmuck 3:aead8f8fdc1f 32 { 25000 , 0x0C },
dudmuck 3:aead8f8fdc1f 33 { 31300 , 0x04 },
dudmuck 3:aead8f8fdc1f 34 { 41700 , 0x13 },
dudmuck 3:aead8f8fdc1f 35 { 50000 , 0x0B },
dudmuck 3:aead8f8fdc1f 36 { 62500 , 0x03 },
dudmuck 3:aead8f8fdc1f 37 { 83333 , 0x12 },
dudmuck 3:aead8f8fdc1f 38 { 100000, 0x0A },
dudmuck 3:aead8f8fdc1f 39 { 125000, 0x02 },
dudmuck 3:aead8f8fdc1f 40 { 166700, 0x11 },
dudmuck 3:aead8f8fdc1f 41 { 200000, 0x09 },
dudmuck 3:aead8f8fdc1f 42 { 250000, 0x01 },
dudmuck 3:aead8f8fdc1f 43 { 300000, 0x00 }, // Invalid Bandwidth
dudmuck 3:aead8f8fdc1f 44 };
dudmuck 3:aead8f8fdc1f 45
dudmuck 3:aead8f8fdc1f 46
dudmuck 3:aead8f8fdc1f 47 SX1272::SX1272( RadioEvents_t *events,
dudmuck 3:aead8f8fdc1f 48 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
dudmuck 3:aead8f8fdc1f 49 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
dudmuck 3:aead8f8fdc1f 50 : Radio( events ),
dudmuck 3:aead8f8fdc1f 51 spi( mosi, miso, sclk ),
dudmuck 3:aead8f8fdc1f 52 nss( nss ),
dudmuck 3:aead8f8fdc1f 53 reset( reset ),
dudmuck 3:aead8f8fdc1f 54 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
dudmuck 3:aead8f8fdc1f 55 isRadioActive( false )
dudmuck 3:aead8f8fdc1f 56 {
dudmuck 3:aead8f8fdc1f 57 wait_ms( 10 );
dudmuck 3:aead8f8fdc1f 58 this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE];
dudmuck 3:aead8f8fdc1f 59
dudmuck 3:aead8f8fdc1f 60 this->RadioEvents = events;
dudmuck 3:aead8f8fdc1f 61
dudmuck 3:aead8f8fdc1f 62 this->dioIrq = new DioIrqHandler[6];
dudmuck 3:aead8f8fdc1f 63
dudmuck 3:aead8f8fdc1f 64 this->dioIrq[0] = &SX1272::OnDio0Irq;
dudmuck 3:aead8f8fdc1f 65 this->dioIrq[1] = &SX1272::OnDio1Irq;
dudmuck 3:aead8f8fdc1f 66 this->dioIrq[2] = &SX1272::OnDio2Irq;
dudmuck 3:aead8f8fdc1f 67 this->dioIrq[3] = &SX1272::OnDio3Irq;
dudmuck 3:aead8f8fdc1f 68 this->dioIrq[4] = &SX1272::OnDio4Irq;
dudmuck 3:aead8f8fdc1f 69 this->dioIrq[5] = NULL;
dudmuck 3:aead8f8fdc1f 70
dudmuck 3:aead8f8fdc1f 71 this->settings.State = RF_IDLE;
dudmuck 3:aead8f8fdc1f 72 }
dudmuck 3:aead8f8fdc1f 73
dudmuck 3:aead8f8fdc1f 74 SX1272::~SX1272( )
dudmuck 3:aead8f8fdc1f 75 {
dudmuck 3:aead8f8fdc1f 76 delete this->rxtxBuffer;
dudmuck 3:aead8f8fdc1f 77 delete this->dioIrq;
dudmuck 3:aead8f8fdc1f 78 }
dudmuck 3:aead8f8fdc1f 79
dudmuck 3:aead8f8fdc1f 80 void SX1272::Init( RadioEvents_t *events )
dudmuck 3:aead8f8fdc1f 81 {
dudmuck 3:aead8f8fdc1f 82 this->RadioEvents = events;
dudmuck 3:aead8f8fdc1f 83 }
dudmuck 3:aead8f8fdc1f 84
dudmuck 3:aead8f8fdc1f 85 RadioState SX1272::GetStatus( void )
dudmuck 3:aead8f8fdc1f 86 {
dudmuck 3:aead8f8fdc1f 87 return this->settings.State;
dudmuck 3:aead8f8fdc1f 88 }
dudmuck 3:aead8f8fdc1f 89
dudmuck 3:aead8f8fdc1f 90 void SX1272::SetChannel( uint32_t freq )
dudmuck 3:aead8f8fdc1f 91 {
dudmuck 3:aead8f8fdc1f 92 this->settings.Channel = freq;
dudmuck 3:aead8f8fdc1f 93 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
dudmuck 3:aead8f8fdc1f 94 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
dudmuck 3:aead8f8fdc1f 95 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
dudmuck 3:aead8f8fdc1f 96 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
dudmuck 3:aead8f8fdc1f 97 }
dudmuck 3:aead8f8fdc1f 98
dudmuck 3:aead8f8fdc1f 99 bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
dudmuck 3:aead8f8fdc1f 100 {
dudmuck 3:aead8f8fdc1f 101 int16_t rssi = 0;
dudmuck 3:aead8f8fdc1f 102
dudmuck 3:aead8f8fdc1f 103 SetModem( modem );
dudmuck 3:aead8f8fdc1f 104
dudmuck 3:aead8f8fdc1f 105 SetChannel( freq );
dudmuck 3:aead8f8fdc1f 106
dudmuck 3:aead8f8fdc1f 107 SetOpMode( RF_OPMODE_RECEIVER );
dudmuck 3:aead8f8fdc1f 108
dudmuck 3:aead8f8fdc1f 109 wait_ms( 1 );
dudmuck 3:aead8f8fdc1f 110
dudmuck 3:aead8f8fdc1f 111 rssi = GetRssi( modem );
dudmuck 3:aead8f8fdc1f 112
dudmuck 3:aead8f8fdc1f 113 Sleep( );
dudmuck 3:aead8f8fdc1f 114
dudmuck 3:aead8f8fdc1f 115 if( rssi > rssiThresh )
dudmuck 3:aead8f8fdc1f 116 {
dudmuck 3:aead8f8fdc1f 117 return false;
dudmuck 3:aead8f8fdc1f 118 }
dudmuck 3:aead8f8fdc1f 119 return true;
dudmuck 3:aead8f8fdc1f 120 }
dudmuck 3:aead8f8fdc1f 121
dudmuck 3:aead8f8fdc1f 122 uint32_t SX1272::Random( void )
dudmuck 3:aead8f8fdc1f 123 {
dudmuck 3:aead8f8fdc1f 124 uint8_t i;
dudmuck 3:aead8f8fdc1f 125 uint32_t rnd = 0;
dudmuck 3:aead8f8fdc1f 126
dudmuck 3:aead8f8fdc1f 127 /*
dudmuck 3:aead8f8fdc1f 128 * Radio setup for random number generation
dudmuck 3:aead8f8fdc1f 129 */
dudmuck 3:aead8f8fdc1f 130 // Set LoRa modem ON
dudmuck 3:aead8f8fdc1f 131 SetModem( MODEM_LORA );
dudmuck 3:aead8f8fdc1f 132
dudmuck 3:aead8f8fdc1f 133 // Disable LoRa modem interrupts
dudmuck 3:aead8f8fdc1f 134 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
dudmuck 3:aead8f8fdc1f 135 RFLR_IRQFLAGS_RXDONE |
dudmuck 3:aead8f8fdc1f 136 RFLR_IRQFLAGS_PAYLOADCRCERROR |
dudmuck 3:aead8f8fdc1f 137 RFLR_IRQFLAGS_VALIDHEADER |
dudmuck 3:aead8f8fdc1f 138 RFLR_IRQFLAGS_TXDONE |
dudmuck 3:aead8f8fdc1f 139 RFLR_IRQFLAGS_CADDONE |
dudmuck 3:aead8f8fdc1f 140 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
dudmuck 3:aead8f8fdc1f 141 RFLR_IRQFLAGS_CADDETECTED );
dudmuck 3:aead8f8fdc1f 142
dudmuck 3:aead8f8fdc1f 143 // Set radio in continuous reception
dudmuck 3:aead8f8fdc1f 144 SetOpMode( RF_OPMODE_RECEIVER );
dudmuck 3:aead8f8fdc1f 145
dudmuck 3:aead8f8fdc1f 146 for( i = 0; i < 32; i++ )
dudmuck 3:aead8f8fdc1f 147 {
dudmuck 3:aead8f8fdc1f 148 wait_ms( 1 );
dudmuck 3:aead8f8fdc1f 149 // Unfiltered RSSI value reading. Only takes the LSB value
dudmuck 3:aead8f8fdc1f 150 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
dudmuck 3:aead8f8fdc1f 151 }
dudmuck 3:aead8f8fdc1f 152
dudmuck 3:aead8f8fdc1f 153 Sleep( );
dudmuck 3:aead8f8fdc1f 154
dudmuck 3:aead8f8fdc1f 155 return rnd;
dudmuck 3:aead8f8fdc1f 156 }
dudmuck 3:aead8f8fdc1f 157
dudmuck 3:aead8f8fdc1f 158 /*!
dudmuck 3:aead8f8fdc1f 159 * Returns the known FSK bandwidth registers value
dudmuck 3:aead8f8fdc1f 160 *
dudmuck 3:aead8f8fdc1f 161 * \param [IN] bandwidth Bandwidth value in Hz
dudmuck 3:aead8f8fdc1f 162 * \retval regValue Bandwidth register value.
dudmuck 3:aead8f8fdc1f 163 */
dudmuck 3:aead8f8fdc1f 164 uint8_t SX1272::GetFskBandwidthRegValue( uint32_t bandwidth )
dudmuck 3:aead8f8fdc1f 165 {
dudmuck 3:aead8f8fdc1f 166 uint8_t i;
dudmuck 3:aead8f8fdc1f 167
dudmuck 3:aead8f8fdc1f 168 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
dudmuck 3:aead8f8fdc1f 169 {
dudmuck 3:aead8f8fdc1f 170 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
dudmuck 3:aead8f8fdc1f 171 {
dudmuck 3:aead8f8fdc1f 172 return FskBandwidths[i].RegValue;
dudmuck 3:aead8f8fdc1f 173 }
dudmuck 3:aead8f8fdc1f 174 }
dudmuck 3:aead8f8fdc1f 175 // ERROR: Value not found
dudmuck 3:aead8f8fdc1f 176 while( 1 );
dudmuck 3:aead8f8fdc1f 177 }
dudmuck 3:aead8f8fdc1f 178
dudmuck 3:aead8f8fdc1f 179 void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
dudmuck 3:aead8f8fdc1f 180 uint32_t datarate, uint8_t coderate,
dudmuck 3:aead8f8fdc1f 181 uint32_t bandwidthAfc, uint16_t preambleLen,
dudmuck 3:aead8f8fdc1f 182 uint16_t symbTimeout, bool fixLen,
dudmuck 3:aead8f8fdc1f 183 uint8_t payloadLen,
dudmuck 3:aead8f8fdc1f 184 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
dudmuck 3:aead8f8fdc1f 185 bool iqInverted, bool rxContinuous )
dudmuck 3:aead8f8fdc1f 186 {
dudmuck 3:aead8f8fdc1f 187 SetModem( modem );
dudmuck 3:aead8f8fdc1f 188
dudmuck 3:aead8f8fdc1f 189 switch( modem )
dudmuck 3:aead8f8fdc1f 190 {
dudmuck 3:aead8f8fdc1f 191 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 192 {
dudmuck 3:aead8f8fdc1f 193 this->settings.Fsk.Bandwidth = bandwidth;
dudmuck 3:aead8f8fdc1f 194 this->settings.Fsk.Datarate = datarate;
dudmuck 3:aead8f8fdc1f 195 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
dudmuck 3:aead8f8fdc1f 196 this->settings.Fsk.FixLen = fixLen;
dudmuck 3:aead8f8fdc1f 197 this->settings.Fsk.PayloadLen = payloadLen;
dudmuck 3:aead8f8fdc1f 198 this->settings.Fsk.CrcOn = crcOn;
dudmuck 3:aead8f8fdc1f 199 this->settings.Fsk.IqInverted = iqInverted;
dudmuck 3:aead8f8fdc1f 200 this->settings.Fsk.RxContinuous = rxContinuous;
dudmuck 3:aead8f8fdc1f 201 this->settings.Fsk.PreambleLen = preambleLen;
dudmuck 3:aead8f8fdc1f 202 this->settings.Fsk.RxSingleTimeout = symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1e3;
dudmuck 3:aead8f8fdc1f 203
dudmuck 3:aead8f8fdc1f 204 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
dudmuck 3:aead8f8fdc1f 205 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
dudmuck 3:aead8f8fdc1f 206 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
dudmuck 3:aead8f8fdc1f 207
dudmuck 3:aead8f8fdc1f 208 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
dudmuck 3:aead8f8fdc1f 209 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
dudmuck 3:aead8f8fdc1f 210
dudmuck 3:aead8f8fdc1f 211 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
dudmuck 3:aead8f8fdc1f 212 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
dudmuck 3:aead8f8fdc1f 213
dudmuck 3:aead8f8fdc1f 214 if( fixLen == 1 )
dudmuck 3:aead8f8fdc1f 215 {
dudmuck 3:aead8f8fdc1f 216 Write( REG_PAYLOADLENGTH, payloadLen );
dudmuck 3:aead8f8fdc1f 217 }
dudmuck 3:aead8f8fdc1f 218 else
dudmuck 3:aead8f8fdc1f 219 {
dudmuck 3:aead8f8fdc1f 220 Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
dudmuck 3:aead8f8fdc1f 221 }
dudmuck 3:aead8f8fdc1f 222
dudmuck 3:aead8f8fdc1f 223 Write( REG_PACKETCONFIG1,
dudmuck 3:aead8f8fdc1f 224 ( Read( REG_PACKETCONFIG1 ) &
dudmuck 3:aead8f8fdc1f 225 RF_PACKETCONFIG1_CRC_MASK &
dudmuck 3:aead8f8fdc1f 226 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
dudmuck 3:aead8f8fdc1f 227 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
dudmuck 3:aead8f8fdc1f 228 ( crcOn << 4 ) );
dudmuck 3:aead8f8fdc1f 229 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
dudmuck 3:aead8f8fdc1f 230 }
dudmuck 3:aead8f8fdc1f 231 break;
dudmuck 3:aead8f8fdc1f 232 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 233 {
dudmuck 3:aead8f8fdc1f 234 this->settings.LoRa.Bandwidth = bandwidth;
dudmuck 3:aead8f8fdc1f 235 this->settings.LoRa.Datarate = datarate;
dudmuck 3:aead8f8fdc1f 236 this->settings.LoRa.Coderate = coderate;
dudmuck 3:aead8f8fdc1f 237 this->settings.LoRa.PreambleLen = preambleLen;
dudmuck 3:aead8f8fdc1f 238 this->settings.LoRa.FixLen = fixLen;
dudmuck 3:aead8f8fdc1f 239 this->settings.LoRa.PayloadLen = payloadLen;
dudmuck 3:aead8f8fdc1f 240 this->settings.LoRa.CrcOn = crcOn;
dudmuck 3:aead8f8fdc1f 241 this->settings.LoRa.FreqHopOn = freqHopOn;
dudmuck 3:aead8f8fdc1f 242 this->settings.LoRa.HopPeriod = hopPeriod;
dudmuck 3:aead8f8fdc1f 243 this->settings.LoRa.IqInverted = iqInverted;
dudmuck 3:aead8f8fdc1f 244 this->settings.LoRa.RxContinuous = rxContinuous;
dudmuck 3:aead8f8fdc1f 245
dudmuck 3:aead8f8fdc1f 246 if( datarate > 12 )
dudmuck 3:aead8f8fdc1f 247 {
dudmuck 3:aead8f8fdc1f 248 datarate = 12;
dudmuck 3:aead8f8fdc1f 249 }
dudmuck 3:aead8f8fdc1f 250 else if( datarate < 6 )
dudmuck 3:aead8f8fdc1f 251 {
dudmuck 3:aead8f8fdc1f 252 datarate = 6;
dudmuck 3:aead8f8fdc1f 253 }
dudmuck 3:aead8f8fdc1f 254
dudmuck 3:aead8f8fdc1f 255 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
dudmuck 3:aead8f8fdc1f 256 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
dudmuck 3:aead8f8fdc1f 257 {
dudmuck 3:aead8f8fdc1f 258 this->settings.LoRa.LowDatarateOptimize = 0x01;
dudmuck 3:aead8f8fdc1f 259 }
dudmuck 3:aead8f8fdc1f 260 else
dudmuck 3:aead8f8fdc1f 261 {
dudmuck 3:aead8f8fdc1f 262 this->settings.LoRa.LowDatarateOptimize = 0x00;
dudmuck 3:aead8f8fdc1f 263 }
dudmuck 3:aead8f8fdc1f 264
dudmuck 3:aead8f8fdc1f 265 Write( REG_LR_MODEMCONFIG1,
dudmuck 3:aead8f8fdc1f 266 ( Read( REG_LR_MODEMCONFIG1 ) &
dudmuck 3:aead8f8fdc1f 267 RFLR_MODEMCONFIG1_BW_MASK &
dudmuck 3:aead8f8fdc1f 268 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
dudmuck 3:aead8f8fdc1f 269 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
dudmuck 3:aead8f8fdc1f 270 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
dudmuck 3:aead8f8fdc1f 271 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
dudmuck 3:aead8f8fdc1f 272 ( bandwidth << 6 ) | ( coderate << 3 ) |
dudmuck 3:aead8f8fdc1f 273 ( fixLen << 2 ) | ( crcOn << 1 ) |
dudmuck 3:aead8f8fdc1f 274 this->settings.LoRa.LowDatarateOptimize );
dudmuck 3:aead8f8fdc1f 275
dudmuck 3:aead8f8fdc1f 276 Write( REG_LR_MODEMCONFIG2,
dudmuck 3:aead8f8fdc1f 277 ( Read( REG_LR_MODEMCONFIG2 ) &
dudmuck 3:aead8f8fdc1f 278 RFLR_MODEMCONFIG2_SF_MASK &
dudmuck 3:aead8f8fdc1f 279 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
dudmuck 3:aead8f8fdc1f 280 ( datarate << 4 ) |
dudmuck 3:aead8f8fdc1f 281 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
dudmuck 3:aead8f8fdc1f 282
dudmuck 3:aead8f8fdc1f 283 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
dudmuck 3:aead8f8fdc1f 284
dudmuck 3:aead8f8fdc1f 285 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
dudmuck 3:aead8f8fdc1f 286 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
dudmuck 3:aead8f8fdc1f 287
dudmuck 3:aead8f8fdc1f 288 if( fixLen == 1 )
dudmuck 3:aead8f8fdc1f 289 {
dudmuck 3:aead8f8fdc1f 290 Write( REG_LR_PAYLOADLENGTH, payloadLen );
dudmuck 3:aead8f8fdc1f 291 }
dudmuck 3:aead8f8fdc1f 292
dudmuck 3:aead8f8fdc1f 293 if( this->settings.LoRa.FreqHopOn == true )
dudmuck 3:aead8f8fdc1f 294 {
dudmuck 3:aead8f8fdc1f 295 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
dudmuck 3:aead8f8fdc1f 296 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
dudmuck 3:aead8f8fdc1f 297 }
dudmuck 3:aead8f8fdc1f 298
dudmuck 3:aead8f8fdc1f 299 if( datarate == 6 )
dudmuck 3:aead8f8fdc1f 300 {
dudmuck 3:aead8f8fdc1f 301 Write( REG_LR_DETECTOPTIMIZE,
dudmuck 3:aead8f8fdc1f 302 ( Read( REG_LR_DETECTOPTIMIZE ) &
dudmuck 3:aead8f8fdc1f 303 RFLR_DETECTIONOPTIMIZE_MASK ) |
dudmuck 3:aead8f8fdc1f 304 RFLR_DETECTIONOPTIMIZE_SF6 );
dudmuck 3:aead8f8fdc1f 305 Write( REG_LR_DETECTIONTHRESHOLD,
dudmuck 3:aead8f8fdc1f 306 RFLR_DETECTIONTHRESH_SF6 );
dudmuck 3:aead8f8fdc1f 307 }
dudmuck 3:aead8f8fdc1f 308 else
dudmuck 3:aead8f8fdc1f 309 {
dudmuck 3:aead8f8fdc1f 310 Write( REG_LR_DETECTOPTIMIZE,
dudmuck 3:aead8f8fdc1f 311 ( Read( REG_LR_DETECTOPTIMIZE ) &
dudmuck 3:aead8f8fdc1f 312 RFLR_DETECTIONOPTIMIZE_MASK ) |
dudmuck 3:aead8f8fdc1f 313 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
dudmuck 3:aead8f8fdc1f 314 Write( REG_LR_DETECTIONTHRESHOLD,
dudmuck 3:aead8f8fdc1f 315 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
dudmuck 3:aead8f8fdc1f 316 }
dudmuck 3:aead8f8fdc1f 317 }
dudmuck 3:aead8f8fdc1f 318 break;
dudmuck 3:aead8f8fdc1f 319 }
dudmuck 3:aead8f8fdc1f 320 }
dudmuck 3:aead8f8fdc1f 321
dudmuck 3:aead8f8fdc1f 322 void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
dudmuck 3:aead8f8fdc1f 323 uint32_t bandwidth, uint32_t datarate,
dudmuck 3:aead8f8fdc1f 324 uint8_t coderate, uint16_t preambleLen,
dudmuck 3:aead8f8fdc1f 325 bool fixLen, bool crcOn, bool freqHopOn,
dudmuck 3:aead8f8fdc1f 326 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
dudmuck 3:aead8f8fdc1f 327 {
dudmuck 3:aead8f8fdc1f 328 SetModem( modem );
dudmuck 3:aead8f8fdc1f 329
dudmuck 3:aead8f8fdc1f 330 SetRfTxPower( power );
dudmuck 3:aead8f8fdc1f 331
dudmuck 3:aead8f8fdc1f 332 switch( modem )
dudmuck 3:aead8f8fdc1f 333 {
dudmuck 3:aead8f8fdc1f 334 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 335 {
dudmuck 3:aead8f8fdc1f 336 this->settings.Fsk.Power = power;
dudmuck 3:aead8f8fdc1f 337 this->settings.Fsk.Fdev = fdev;
dudmuck 3:aead8f8fdc1f 338 this->settings.Fsk.Bandwidth = bandwidth;
dudmuck 3:aead8f8fdc1f 339 this->settings.Fsk.Datarate = datarate;
dudmuck 3:aead8f8fdc1f 340 this->settings.Fsk.PreambleLen = preambleLen;
dudmuck 3:aead8f8fdc1f 341 this->settings.Fsk.FixLen = fixLen;
dudmuck 3:aead8f8fdc1f 342 this->settings.Fsk.CrcOn = crcOn;
dudmuck 3:aead8f8fdc1f 343 this->settings.Fsk.IqInverted = iqInverted;
dudmuck 3:aead8f8fdc1f 344 this->settings.Fsk.TxTimeout = timeout;
dudmuck 3:aead8f8fdc1f 345
dudmuck 3:aead8f8fdc1f 346 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
dudmuck 3:aead8f8fdc1f 347 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
dudmuck 3:aead8f8fdc1f 348 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
dudmuck 3:aead8f8fdc1f 349
dudmuck 3:aead8f8fdc1f 350 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
dudmuck 3:aead8f8fdc1f 351 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
dudmuck 3:aead8f8fdc1f 352 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
dudmuck 3:aead8f8fdc1f 353
dudmuck 3:aead8f8fdc1f 354 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
dudmuck 3:aead8f8fdc1f 355 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
dudmuck 3:aead8f8fdc1f 356
dudmuck 3:aead8f8fdc1f 357 Write( REG_PACKETCONFIG1,
dudmuck 3:aead8f8fdc1f 358 ( Read( REG_PACKETCONFIG1 ) &
dudmuck 3:aead8f8fdc1f 359 RF_PACKETCONFIG1_CRC_MASK &
dudmuck 3:aead8f8fdc1f 360 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
dudmuck 3:aead8f8fdc1f 361 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
dudmuck 3:aead8f8fdc1f 362 ( crcOn << 4 ) );
dudmuck 3:aead8f8fdc1f 363 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
dudmuck 3:aead8f8fdc1f 364 }
dudmuck 3:aead8f8fdc1f 365 break;
dudmuck 3:aead8f8fdc1f 366 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 367 {
dudmuck 3:aead8f8fdc1f 368 this->settings.LoRa.Power = power;
dudmuck 3:aead8f8fdc1f 369 this->settings.LoRa.Bandwidth = bandwidth;
dudmuck 3:aead8f8fdc1f 370 this->settings.LoRa.Datarate = datarate;
dudmuck 3:aead8f8fdc1f 371 this->settings.LoRa.Coderate = coderate;
dudmuck 3:aead8f8fdc1f 372 this->settings.LoRa.PreambleLen = preambleLen;
dudmuck 3:aead8f8fdc1f 373 this->settings.LoRa.FixLen = fixLen;
dudmuck 3:aead8f8fdc1f 374 this->settings.LoRa.FreqHopOn = freqHopOn;
dudmuck 3:aead8f8fdc1f 375 this->settings.LoRa.HopPeriod = hopPeriod;
dudmuck 3:aead8f8fdc1f 376 this->settings.LoRa.CrcOn = crcOn;
dudmuck 3:aead8f8fdc1f 377 this->settings.LoRa.IqInverted = iqInverted;
dudmuck 3:aead8f8fdc1f 378 this->settings.LoRa.TxTimeout = timeout;
dudmuck 3:aead8f8fdc1f 379
dudmuck 3:aead8f8fdc1f 380 if( datarate > 12 )
dudmuck 3:aead8f8fdc1f 381 {
dudmuck 3:aead8f8fdc1f 382 datarate = 12;
dudmuck 3:aead8f8fdc1f 383 }
dudmuck 3:aead8f8fdc1f 384 else if( datarate < 6 )
dudmuck 3:aead8f8fdc1f 385 {
dudmuck 3:aead8f8fdc1f 386 datarate = 6;
dudmuck 3:aead8f8fdc1f 387 }
dudmuck 3:aead8f8fdc1f 388 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
dudmuck 3:aead8f8fdc1f 389 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
dudmuck 3:aead8f8fdc1f 390 {
dudmuck 3:aead8f8fdc1f 391 this->settings.LoRa.LowDatarateOptimize = 0x01;
dudmuck 3:aead8f8fdc1f 392 }
dudmuck 3:aead8f8fdc1f 393 else
dudmuck 3:aead8f8fdc1f 394 {
dudmuck 3:aead8f8fdc1f 395 this->settings.LoRa.LowDatarateOptimize = 0x00;
dudmuck 3:aead8f8fdc1f 396 }
dudmuck 3:aead8f8fdc1f 397
dudmuck 3:aead8f8fdc1f 398 if( this->settings.LoRa.FreqHopOn == true )
dudmuck 3:aead8f8fdc1f 399 {
dudmuck 3:aead8f8fdc1f 400 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
dudmuck 3:aead8f8fdc1f 401 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
dudmuck 3:aead8f8fdc1f 402 }
dudmuck 3:aead8f8fdc1f 403
dudmuck 3:aead8f8fdc1f 404 Write( REG_LR_MODEMCONFIG1,
dudmuck 3:aead8f8fdc1f 405 ( Read( REG_LR_MODEMCONFIG1 ) &
dudmuck 3:aead8f8fdc1f 406 RFLR_MODEMCONFIG1_BW_MASK &
dudmuck 3:aead8f8fdc1f 407 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
dudmuck 3:aead8f8fdc1f 408 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
dudmuck 3:aead8f8fdc1f 409 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
dudmuck 3:aead8f8fdc1f 410 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
dudmuck 3:aead8f8fdc1f 411 ( bandwidth << 6 ) | ( coderate << 3 ) |
dudmuck 3:aead8f8fdc1f 412 ( fixLen << 2 ) | ( crcOn << 1 ) |
dudmuck 3:aead8f8fdc1f 413 this->settings.LoRa.LowDatarateOptimize );
dudmuck 3:aead8f8fdc1f 414
dudmuck 3:aead8f8fdc1f 415 Write( REG_LR_MODEMCONFIG2,
dudmuck 3:aead8f8fdc1f 416 ( Read( REG_LR_MODEMCONFIG2 ) &
dudmuck 3:aead8f8fdc1f 417 RFLR_MODEMCONFIG2_SF_MASK ) |
dudmuck 3:aead8f8fdc1f 418 ( datarate << 4 ) );
dudmuck 3:aead8f8fdc1f 419
dudmuck 3:aead8f8fdc1f 420
dudmuck 3:aead8f8fdc1f 421 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
dudmuck 3:aead8f8fdc1f 422 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
dudmuck 3:aead8f8fdc1f 423
dudmuck 3:aead8f8fdc1f 424 if( datarate == 6 )
dudmuck 3:aead8f8fdc1f 425 {
dudmuck 3:aead8f8fdc1f 426 Write( REG_LR_DETECTOPTIMIZE,
dudmuck 3:aead8f8fdc1f 427 ( Read( REG_LR_DETECTOPTIMIZE ) &
dudmuck 3:aead8f8fdc1f 428 RFLR_DETECTIONOPTIMIZE_MASK ) |
dudmuck 3:aead8f8fdc1f 429 RFLR_DETECTIONOPTIMIZE_SF6 );
dudmuck 3:aead8f8fdc1f 430 Write( REG_LR_DETECTIONTHRESHOLD,
dudmuck 3:aead8f8fdc1f 431 RFLR_DETECTIONTHRESH_SF6 );
dudmuck 3:aead8f8fdc1f 432 }
dudmuck 3:aead8f8fdc1f 433 else
dudmuck 3:aead8f8fdc1f 434 {
dudmuck 3:aead8f8fdc1f 435 Write( REG_LR_DETECTOPTIMIZE,
dudmuck 3:aead8f8fdc1f 436 ( Read( REG_LR_DETECTOPTIMIZE ) &
dudmuck 3:aead8f8fdc1f 437 RFLR_DETECTIONOPTIMIZE_MASK ) |
dudmuck 3:aead8f8fdc1f 438 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
dudmuck 3:aead8f8fdc1f 439 Write( REG_LR_DETECTIONTHRESHOLD,
dudmuck 3:aead8f8fdc1f 440 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
dudmuck 3:aead8f8fdc1f 441 }
dudmuck 3:aead8f8fdc1f 442 }
dudmuck 3:aead8f8fdc1f 443 break;
dudmuck 3:aead8f8fdc1f 444 }
dudmuck 3:aead8f8fdc1f 445 }
dudmuck 3:aead8f8fdc1f 446
dudmuck 3:aead8f8fdc1f 447 uint32_t SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
dudmuck 3:aead8f8fdc1f 448 {
dudmuck 3:aead8f8fdc1f 449 uint32_t airTime = 0;
dudmuck 3:aead8f8fdc1f 450
dudmuck 3:aead8f8fdc1f 451 switch( modem )
dudmuck 3:aead8f8fdc1f 452 {
dudmuck 3:aead8f8fdc1f 453 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 454 {
dudmuck 3:aead8f8fdc1f 455 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
dudmuck 3:aead8f8fdc1f 456 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
dudmuck 3:aead8f8fdc1f 457 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
dudmuck 3:aead8f8fdc1f 458 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
dudmuck 3:aead8f8fdc1f 459 pktLen +
dudmuck 3:aead8f8fdc1f 460 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
dudmuck 3:aead8f8fdc1f 461 this->settings.Fsk.Datarate ) * 1e3 );
dudmuck 3:aead8f8fdc1f 462 }
dudmuck 3:aead8f8fdc1f 463 break;
dudmuck 3:aead8f8fdc1f 464 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 465 {
dudmuck 3:aead8f8fdc1f 466 double bw = 0.0;
dudmuck 3:aead8f8fdc1f 467 switch( this->settings.LoRa.Bandwidth )
dudmuck 3:aead8f8fdc1f 468 {
dudmuck 3:aead8f8fdc1f 469 case 0: // 125 kHz
dudmuck 3:aead8f8fdc1f 470 bw = 125e3;
dudmuck 3:aead8f8fdc1f 471 break;
dudmuck 3:aead8f8fdc1f 472 case 1: // 250 kHz
dudmuck 3:aead8f8fdc1f 473 bw = 250e3;
dudmuck 3:aead8f8fdc1f 474 break;
dudmuck 3:aead8f8fdc1f 475 case 2: // 500 kHz
dudmuck 3:aead8f8fdc1f 476 bw = 500e3;
dudmuck 3:aead8f8fdc1f 477 break;
dudmuck 3:aead8f8fdc1f 478 }
dudmuck 3:aead8f8fdc1f 479
dudmuck 3:aead8f8fdc1f 480 // Symbol rate : time for one symbol (secs)
dudmuck 3:aead8f8fdc1f 481 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
dudmuck 3:aead8f8fdc1f 482 double ts = 1 / rs;
dudmuck 3:aead8f8fdc1f 483 // time of preamble
dudmuck 3:aead8f8fdc1f 484 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
dudmuck 3:aead8f8fdc1f 485 // Symbol length of payload and time
dudmuck 3:aead8f8fdc1f 486 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
dudmuck 3:aead8f8fdc1f 487 28 + 16 * this->settings.LoRa.CrcOn -
dudmuck 3:aead8f8fdc1f 488 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
dudmuck 3:aead8f8fdc1f 489 ( double )( 4 * ( this->settings.LoRa.Datarate -
dudmuck 3:aead8f8fdc1f 490 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) *
dudmuck 3:aead8f8fdc1f 491 ( this->settings.LoRa.Coderate + 4 );
dudmuck 3:aead8f8fdc1f 492 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
dudmuck 3:aead8f8fdc1f 493 double tPayload = nPayload * ts;
dudmuck 3:aead8f8fdc1f 494 // Time on air
dudmuck 3:aead8f8fdc1f 495 double tOnAir = tPreamble + tPayload;
dudmuck 3:aead8f8fdc1f 496 // return ms secs
dudmuck 3:aead8f8fdc1f 497 airTime = floor( tOnAir * 1e3 + 0.999 );
dudmuck 3:aead8f8fdc1f 498 }
dudmuck 3:aead8f8fdc1f 499 break;
dudmuck 3:aead8f8fdc1f 500 }
dudmuck 3:aead8f8fdc1f 501 return airTime;
dudmuck 3:aead8f8fdc1f 502 }
dudmuck 3:aead8f8fdc1f 503
dudmuck 3:aead8f8fdc1f 504 void SX1272::Send( uint8_t *buffer, uint8_t size )
dudmuck 3:aead8f8fdc1f 505 {
dudmuck 3:aead8f8fdc1f 506 uint32_t txTimeout = 0;
dudmuck 3:aead8f8fdc1f 507
dudmuck 3:aead8f8fdc1f 508 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 509 {
dudmuck 3:aead8f8fdc1f 510 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 511 {
dudmuck 3:aead8f8fdc1f 512 this->settings.FskPacketHandler.NbBytes = 0;
dudmuck 3:aead8f8fdc1f 513 this->settings.FskPacketHandler.Size = size;
dudmuck 3:aead8f8fdc1f 514
dudmuck 3:aead8f8fdc1f 515 if( this->settings.Fsk.FixLen == false )
dudmuck 3:aead8f8fdc1f 516 {
dudmuck 3:aead8f8fdc1f 517 WriteFifo( ( uint8_t* )&size, 1 );
dudmuck 3:aead8f8fdc1f 518 }
dudmuck 3:aead8f8fdc1f 519 else
dudmuck 3:aead8f8fdc1f 520 {
dudmuck 3:aead8f8fdc1f 521 Write( REG_PAYLOADLENGTH, size );
dudmuck 3:aead8f8fdc1f 522 }
dudmuck 3:aead8f8fdc1f 523
dudmuck 3:aead8f8fdc1f 524 if( ( size > 0 ) && ( size <= 64 ) )
dudmuck 3:aead8f8fdc1f 525 {
dudmuck 3:aead8f8fdc1f 526 this->settings.FskPacketHandler.ChunkSize = size;
dudmuck 3:aead8f8fdc1f 527 }
dudmuck 3:aead8f8fdc1f 528 else
dudmuck 3:aead8f8fdc1f 529 {
dudmuck 3:aead8f8fdc1f 530 memcpy( rxtxBuffer, buffer, size );
dudmuck 3:aead8f8fdc1f 531 this->settings.FskPacketHandler.ChunkSize = 32;
dudmuck 3:aead8f8fdc1f 532 }
dudmuck 3:aead8f8fdc1f 533
dudmuck 3:aead8f8fdc1f 534 // Write payload buffer
dudmuck 3:aead8f8fdc1f 535 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
dudmuck 3:aead8f8fdc1f 536 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
dudmuck 3:aead8f8fdc1f 537 txTimeout = this->settings.Fsk.TxTimeout;
dudmuck 3:aead8f8fdc1f 538 }
dudmuck 3:aead8f8fdc1f 539 break;
dudmuck 3:aead8f8fdc1f 540 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 541 {
dudmuck 3:aead8f8fdc1f 542 if( this->settings.LoRa.IqInverted == true )
dudmuck 3:aead8f8fdc1f 543 {
dudmuck 3:aead8f8fdc1f 544 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
dudmuck 3:aead8f8fdc1f 545 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
dudmuck 3:aead8f8fdc1f 546 }
dudmuck 3:aead8f8fdc1f 547 else
dudmuck 3:aead8f8fdc1f 548 {
dudmuck 3:aead8f8fdc1f 549 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
dudmuck 3:aead8f8fdc1f 550 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
dudmuck 3:aead8f8fdc1f 551 }
dudmuck 3:aead8f8fdc1f 552
dudmuck 3:aead8f8fdc1f 553 this->settings.LoRaPacketHandler.Size = size;
dudmuck 3:aead8f8fdc1f 554
dudmuck 3:aead8f8fdc1f 555 // Initializes the payload size
dudmuck 3:aead8f8fdc1f 556 Write( REG_LR_PAYLOADLENGTH, size );
dudmuck 3:aead8f8fdc1f 557
dudmuck 3:aead8f8fdc1f 558 // Full buffer used for Tx
dudmuck 3:aead8f8fdc1f 559 Write( REG_LR_FIFOTXBASEADDR, 0 );
dudmuck 3:aead8f8fdc1f 560 Write( REG_LR_FIFOADDRPTR, 0 );
dudmuck 3:aead8f8fdc1f 561
dudmuck 3:aead8f8fdc1f 562 // FIFO operations can not take place in Sleep mode
dudmuck 3:aead8f8fdc1f 563 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
dudmuck 3:aead8f8fdc1f 564 {
dudmuck 3:aead8f8fdc1f 565 Standby( );
dudmuck 3:aead8f8fdc1f 566 wait_ms( 1 );
dudmuck 3:aead8f8fdc1f 567 }
dudmuck 3:aead8f8fdc1f 568 // Write payload buffer
dudmuck 3:aead8f8fdc1f 569 WriteFifo( buffer, size );
dudmuck 3:aead8f8fdc1f 570 txTimeout = this->settings.LoRa.TxTimeout;
dudmuck 3:aead8f8fdc1f 571 }
dudmuck 3:aead8f8fdc1f 572 break;
dudmuck 3:aead8f8fdc1f 573 }
dudmuck 3:aead8f8fdc1f 574
dudmuck 3:aead8f8fdc1f 575 Tx( txTimeout );
dudmuck 3:aead8f8fdc1f 576 }
dudmuck 3:aead8f8fdc1f 577
dudmuck 3:aead8f8fdc1f 578 void SX1272::Sleep( void )
dudmuck 3:aead8f8fdc1f 579 {
dudmuck 3:aead8f8fdc1f 580 txTimeoutTimer.detach( );
dudmuck 3:aead8f8fdc1f 581 rxTimeoutTimer.detach( );
dudmuck 3:aead8f8fdc1f 582
dudmuck 3:aead8f8fdc1f 583 SetOpMode( RF_OPMODE_SLEEP );
dudmuck 3:aead8f8fdc1f 584 this->settings.State = RF_IDLE;
dudmuck 3:aead8f8fdc1f 585 }
dudmuck 3:aead8f8fdc1f 586
dudmuck 3:aead8f8fdc1f 587 void SX1272::Standby( void )
dudmuck 3:aead8f8fdc1f 588 {
dudmuck 3:aead8f8fdc1f 589 txTimeoutTimer.detach( );
dudmuck 3:aead8f8fdc1f 590 rxTimeoutTimer.detach( );
dudmuck 3:aead8f8fdc1f 591
dudmuck 3:aead8f8fdc1f 592 SetOpMode( RF_OPMODE_STANDBY );
dudmuck 3:aead8f8fdc1f 593 this->settings.State = RF_IDLE;
dudmuck 3:aead8f8fdc1f 594 }
dudmuck 3:aead8f8fdc1f 595
dudmuck 3:aead8f8fdc1f 596 void SX1272::Rx( uint32_t timeout )
dudmuck 3:aead8f8fdc1f 597 {
dudmuck 3:aead8f8fdc1f 598 bool rxContinuous = false;
dudmuck 3:aead8f8fdc1f 599
dudmuck 3:aead8f8fdc1f 600 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 601 {
dudmuck 3:aead8f8fdc1f 602 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 603 {
dudmuck 3:aead8f8fdc1f 604 rxContinuous = this->settings.Fsk.RxContinuous;
dudmuck 3:aead8f8fdc1f 605
dudmuck 3:aead8f8fdc1f 606 // DIO0=PayloadReady
dudmuck 3:aead8f8fdc1f 607 // DIO1=FifoLevel
dudmuck 3:aead8f8fdc1f 608 // DIO2=SyncAddr
dudmuck 3:aead8f8fdc1f 609 // DIO3=FifoEmpty
dudmuck 3:aead8f8fdc1f 610 // DIO4=Preamble
dudmuck 3:aead8f8fdc1f 611 // DIO5=ModeReady
dudmuck 3:aead8f8fdc1f 612 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
dudmuck 3:aead8f8fdc1f 613 RF_DIOMAPPING1_DIO1_MASK &
dudmuck 3:aead8f8fdc1f 614 RF_DIOMAPPING1_DIO2_MASK ) |
dudmuck 3:aead8f8fdc1f 615 RF_DIOMAPPING1_DIO0_00 |
dudmuck 3:aead8f8fdc1f 616 RF_DIOMAPPING1_DIO1_00 |
dudmuck 3:aead8f8fdc1f 617 RF_DIOMAPPING1_DIO2_11 );
dudmuck 3:aead8f8fdc1f 618
dudmuck 3:aead8f8fdc1f 619 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
dudmuck 3:aead8f8fdc1f 620 RF_DIOMAPPING2_MAP_MASK ) |
dudmuck 3:aead8f8fdc1f 621 RF_DIOMAPPING2_DIO4_11 |
dudmuck 3:aead8f8fdc1f 622 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
dudmuck 3:aead8f8fdc1f 623
dudmuck 3:aead8f8fdc1f 624 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
dudmuck 3:aead8f8fdc1f 625
dudmuck 3:aead8f8fdc1f 626 Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT );
dudmuck 3:aead8f8fdc1f 627
dudmuck 3:aead8f8fdc1f 628 this->settings.FskPacketHandler.PreambleDetected = false;
dudmuck 3:aead8f8fdc1f 629 this->settings.FskPacketHandler.SyncWordDetected = false;
dudmuck 3:aead8f8fdc1f 630 this->settings.FskPacketHandler.NbBytes = 0;
dudmuck 3:aead8f8fdc1f 631 this->settings.FskPacketHandler.Size = 0;
dudmuck 3:aead8f8fdc1f 632 }
dudmuck 3:aead8f8fdc1f 633 break;
dudmuck 3:aead8f8fdc1f 634 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 635 {
dudmuck 3:aead8f8fdc1f 636 if( this->settings.LoRa.IqInverted == true )
dudmuck 3:aead8f8fdc1f 637 {
dudmuck 3:aead8f8fdc1f 638 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
dudmuck 3:aead8f8fdc1f 639 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
dudmuck 3:aead8f8fdc1f 640 }
dudmuck 3:aead8f8fdc1f 641 else
dudmuck 3:aead8f8fdc1f 642 {
dudmuck 3:aead8f8fdc1f 643 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
dudmuck 3:aead8f8fdc1f 644 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
dudmuck 3:aead8f8fdc1f 645 }
dudmuck 3:aead8f8fdc1f 646
dudmuck 3:aead8f8fdc1f 647 rxContinuous = this->settings.LoRa.RxContinuous;
dudmuck 3:aead8f8fdc1f 648
dudmuck 3:aead8f8fdc1f 649 if( this->settings.LoRa.FreqHopOn == true )
dudmuck 3:aead8f8fdc1f 650 {
dudmuck 3:aead8f8fdc1f 651 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
dudmuck 3:aead8f8fdc1f 652 //RFLR_IRQFLAGS_RXDONE |
dudmuck 3:aead8f8fdc1f 653 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
dudmuck 3:aead8f8fdc1f 654 RFLR_IRQFLAGS_VALIDHEADER |
dudmuck 3:aead8f8fdc1f 655 RFLR_IRQFLAGS_TXDONE |
dudmuck 3:aead8f8fdc1f 656 RFLR_IRQFLAGS_CADDONE |
dudmuck 3:aead8f8fdc1f 657 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
dudmuck 3:aead8f8fdc1f 658 RFLR_IRQFLAGS_CADDETECTED );
dudmuck 3:aead8f8fdc1f 659
dudmuck 3:aead8f8fdc1f 660 // DIO0=RxDone, DIO2=FhssChangeChannel
dudmuck 3:aead8f8fdc1f 661 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
dudmuck 3:aead8f8fdc1f 662 }
dudmuck 3:aead8f8fdc1f 663 else
dudmuck 3:aead8f8fdc1f 664 {
dudmuck 3:aead8f8fdc1f 665 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
dudmuck 3:aead8f8fdc1f 666 //RFLR_IRQFLAGS_RXDONE |
dudmuck 3:aead8f8fdc1f 667 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
dudmuck 3:aead8f8fdc1f 668 RFLR_IRQFLAGS_VALIDHEADER |
dudmuck 3:aead8f8fdc1f 669 RFLR_IRQFLAGS_TXDONE |
dudmuck 3:aead8f8fdc1f 670 RFLR_IRQFLAGS_CADDONE |
dudmuck 3:aead8f8fdc1f 671 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
dudmuck 3:aead8f8fdc1f 672 RFLR_IRQFLAGS_CADDETECTED );
dudmuck 3:aead8f8fdc1f 673
dudmuck 3:aead8f8fdc1f 674 // DIO0=RxDone
dudmuck 3:aead8f8fdc1f 675 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
dudmuck 3:aead8f8fdc1f 676 }
dudmuck 3:aead8f8fdc1f 677 Write( REG_LR_FIFORXBASEADDR, 0 );
dudmuck 3:aead8f8fdc1f 678 Write( REG_LR_FIFOADDRPTR, 0 );
dudmuck 3:aead8f8fdc1f 679 }
dudmuck 3:aead8f8fdc1f 680 break;
dudmuck 3:aead8f8fdc1f 681 }
dudmuck 3:aead8f8fdc1f 682
dudmuck 3:aead8f8fdc1f 683 memset( rxtxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
dudmuck 3:aead8f8fdc1f 684
dudmuck 3:aead8f8fdc1f 685 this->settings.State = RF_RX_RUNNING;
dudmuck 3:aead8f8fdc1f 686 if( timeout != 0 )
dudmuck 3:aead8f8fdc1f 687 {
dudmuck 3:aead8f8fdc1f 688 rxTimeoutTimer.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), timeout * 1e3 );
dudmuck 3:aead8f8fdc1f 689 }
dudmuck 3:aead8f8fdc1f 690
dudmuck 3:aead8f8fdc1f 691 if( this->settings.Modem == MODEM_FSK )
dudmuck 3:aead8f8fdc1f 692 {
dudmuck 3:aead8f8fdc1f 693 SetOpMode( RF_OPMODE_RECEIVER );
dudmuck 3:aead8f8fdc1f 694
dudmuck 3:aead8f8fdc1f 695 if( rxContinuous == false )
dudmuck 3:aead8f8fdc1f 696 {
dudmuck 3:aead8f8fdc1f 697 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ),
dudmuck 3:aead8f8fdc1f 698 this->settings.Fsk.RxSingleTimeout * 1e3 );
dudmuck 3:aead8f8fdc1f 699 }
dudmuck 3:aead8f8fdc1f 700 }
dudmuck 3:aead8f8fdc1f 701 else
dudmuck 3:aead8f8fdc1f 702 {
dudmuck 3:aead8f8fdc1f 703 if( rxContinuous == true )
dudmuck 3:aead8f8fdc1f 704 {
dudmuck 3:aead8f8fdc1f 705 SetOpMode( RFLR_OPMODE_RECEIVER );
dudmuck 3:aead8f8fdc1f 706 }
dudmuck 3:aead8f8fdc1f 707 else
dudmuck 3:aead8f8fdc1f 708 {
dudmuck 3:aead8f8fdc1f 709 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
dudmuck 3:aead8f8fdc1f 710 }
dudmuck 3:aead8f8fdc1f 711 }
dudmuck 3:aead8f8fdc1f 712 }
dudmuck 3:aead8f8fdc1f 713
dudmuck 3:aead8f8fdc1f 714 void SX1272::Tx( uint32_t timeout )
dudmuck 3:aead8f8fdc1f 715 {
dudmuck 3:aead8f8fdc1f 716
dudmuck 3:aead8f8fdc1f 717 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 718 {
dudmuck 3:aead8f8fdc1f 719 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 720 {
dudmuck 3:aead8f8fdc1f 721 // DIO0=PacketSent
dudmuck 3:aead8f8fdc1f 722 // DIO1=FifoEmpty
dudmuck 3:aead8f8fdc1f 723 // DIO2=FifoFull
dudmuck 3:aead8f8fdc1f 724 // DIO3=FifoEmpty
dudmuck 3:aead8f8fdc1f 725 // DIO4=LowBat
dudmuck 3:aead8f8fdc1f 726 // DIO5=ModeReady
dudmuck 3:aead8f8fdc1f 727 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
dudmuck 3:aead8f8fdc1f 728 RF_DIOMAPPING1_DIO1_MASK &
dudmuck 3:aead8f8fdc1f 729 RF_DIOMAPPING1_DIO2_MASK ) |
dudmuck 3:aead8f8fdc1f 730 RF_DIOMAPPING1_DIO1_01 );
dudmuck 3:aead8f8fdc1f 731
dudmuck 3:aead8f8fdc1f 732 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
dudmuck 3:aead8f8fdc1f 733 RF_DIOMAPPING2_MAP_MASK ) );
dudmuck 3:aead8f8fdc1f 734 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
dudmuck 3:aead8f8fdc1f 735 }
dudmuck 3:aead8f8fdc1f 736 break;
dudmuck 3:aead8f8fdc1f 737 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 738 {
dudmuck 3:aead8f8fdc1f 739 if( this->settings.LoRa.FreqHopOn == true )
dudmuck 3:aead8f8fdc1f 740 {
dudmuck 3:aead8f8fdc1f 741 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
dudmuck 3:aead8f8fdc1f 742 RFLR_IRQFLAGS_RXDONE |
dudmuck 3:aead8f8fdc1f 743 RFLR_IRQFLAGS_PAYLOADCRCERROR |
dudmuck 3:aead8f8fdc1f 744 RFLR_IRQFLAGS_VALIDHEADER |
dudmuck 3:aead8f8fdc1f 745 //RFLR_IRQFLAGS_TXDONE |
dudmuck 3:aead8f8fdc1f 746 RFLR_IRQFLAGS_CADDONE |
dudmuck 3:aead8f8fdc1f 747 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
dudmuck 3:aead8f8fdc1f 748 RFLR_IRQFLAGS_CADDETECTED );
dudmuck 3:aead8f8fdc1f 749
dudmuck 3:aead8f8fdc1f 750 // DIO0=TxDone, DIO2=FhssChangeChannel
dudmuck 3:aead8f8fdc1f 751 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
dudmuck 3:aead8f8fdc1f 752 }
dudmuck 3:aead8f8fdc1f 753 else
dudmuck 3:aead8f8fdc1f 754 {
dudmuck 3:aead8f8fdc1f 755 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
dudmuck 3:aead8f8fdc1f 756 RFLR_IRQFLAGS_RXDONE |
dudmuck 3:aead8f8fdc1f 757 RFLR_IRQFLAGS_PAYLOADCRCERROR |
dudmuck 3:aead8f8fdc1f 758 RFLR_IRQFLAGS_VALIDHEADER |
dudmuck 3:aead8f8fdc1f 759 //RFLR_IRQFLAGS_TXDONE |
dudmuck 3:aead8f8fdc1f 760 RFLR_IRQFLAGS_CADDONE |
dudmuck 3:aead8f8fdc1f 761 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
dudmuck 3:aead8f8fdc1f 762 RFLR_IRQFLAGS_CADDETECTED );
dudmuck 3:aead8f8fdc1f 763
dudmuck 3:aead8f8fdc1f 764 // DIO0=TxDone
dudmuck 3:aead8f8fdc1f 765 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
dudmuck 3:aead8f8fdc1f 766 }
dudmuck 3:aead8f8fdc1f 767 }
dudmuck 3:aead8f8fdc1f 768 break;
dudmuck 3:aead8f8fdc1f 769 }
dudmuck 3:aead8f8fdc1f 770
dudmuck 3:aead8f8fdc1f 771 this->settings.State = RF_TX_RUNNING;
dudmuck 3:aead8f8fdc1f 772 txTimeoutTimer.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), timeout * 1e3 );
dudmuck 3:aead8f8fdc1f 773 SetOpMode( RF_OPMODE_TRANSMITTER );
dudmuck 3:aead8f8fdc1f 774 }
dudmuck 3:aead8f8fdc1f 775
dudmuck 3:aead8f8fdc1f 776 void SX1272::StartCad( void )
dudmuck 3:aead8f8fdc1f 777 {
dudmuck 3:aead8f8fdc1f 778 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 779 {
dudmuck 3:aead8f8fdc1f 780 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 781 {
dudmuck 3:aead8f8fdc1f 782
dudmuck 3:aead8f8fdc1f 783 }
dudmuck 3:aead8f8fdc1f 784 break;
dudmuck 3:aead8f8fdc1f 785 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 786 {
dudmuck 3:aead8f8fdc1f 787 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
dudmuck 3:aead8f8fdc1f 788 RFLR_IRQFLAGS_RXDONE |
dudmuck 3:aead8f8fdc1f 789 RFLR_IRQFLAGS_PAYLOADCRCERROR |
dudmuck 3:aead8f8fdc1f 790 RFLR_IRQFLAGS_VALIDHEADER |
dudmuck 3:aead8f8fdc1f 791 RFLR_IRQFLAGS_TXDONE |
dudmuck 3:aead8f8fdc1f 792 //RFLR_IRQFLAGS_CADDONE |
dudmuck 3:aead8f8fdc1f 793 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
dudmuck 3:aead8f8fdc1f 794 //RFLR_IRQFLAGS_CADDETECTED
dudmuck 3:aead8f8fdc1f 795 );
dudmuck 3:aead8f8fdc1f 796
dudmuck 3:aead8f8fdc1f 797 // DIO3=CADDone
dudmuck 3:aead8f8fdc1f 798 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 );
dudmuck 3:aead8f8fdc1f 799
dudmuck 3:aead8f8fdc1f 800 this->settings.State = RF_CAD;
dudmuck 3:aead8f8fdc1f 801 SetOpMode( RFLR_OPMODE_CAD );
dudmuck 3:aead8f8fdc1f 802 }
dudmuck 3:aead8f8fdc1f 803 break;
dudmuck 3:aead8f8fdc1f 804 default:
dudmuck 3:aead8f8fdc1f 805 break;
dudmuck 3:aead8f8fdc1f 806 }
dudmuck 3:aead8f8fdc1f 807 }
dudmuck 3:aead8f8fdc1f 808
dudmuck 3:aead8f8fdc1f 809 void SX1272::SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time )
dudmuck 3:aead8f8fdc1f 810 {
dudmuck 3:aead8f8fdc1f 811 uint32_t timeout = ( uint32_t )( time * 1e6 );
dudmuck 3:aead8f8fdc1f 812
dudmuck 3:aead8f8fdc1f 813 SetChannel( freq );
dudmuck 3:aead8f8fdc1f 814
dudmuck 3:aead8f8fdc1f 815 SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout );
dudmuck 3:aead8f8fdc1f 816
dudmuck 3:aead8f8fdc1f 817 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) );
dudmuck 3:aead8f8fdc1f 818 // Disable radio interrupts
dudmuck 3:aead8f8fdc1f 819 Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
dudmuck 3:aead8f8fdc1f 820 Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
dudmuck 3:aead8f8fdc1f 821
dudmuck 3:aead8f8fdc1f 822 this->settings.State = RF_TX_RUNNING;
dudmuck 3:aead8f8fdc1f 823 txTimeoutTimer.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ), timeout );
dudmuck 3:aead8f8fdc1f 824 SetOpMode( RF_OPMODE_TRANSMITTER );
dudmuck 3:aead8f8fdc1f 825 }
dudmuck 3:aead8f8fdc1f 826
dudmuck 3:aead8f8fdc1f 827 int16_t SX1272::GetRssi( RadioModems_t modem )
dudmuck 3:aead8f8fdc1f 828 {
dudmuck 3:aead8f8fdc1f 829 int16_t rssi = 0;
dudmuck 3:aead8f8fdc1f 830
dudmuck 3:aead8f8fdc1f 831 switch( modem )
dudmuck 3:aead8f8fdc1f 832 {
dudmuck 3:aead8f8fdc1f 833 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 834 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
dudmuck 3:aead8f8fdc1f 835 break;
dudmuck 3:aead8f8fdc1f 836 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 837 rssi = RSSI_OFFSET + Read( REG_LR_RSSIVALUE );
dudmuck 3:aead8f8fdc1f 838 break;
dudmuck 3:aead8f8fdc1f 839 default:
dudmuck 3:aead8f8fdc1f 840 rssi = -1;
dudmuck 3:aead8f8fdc1f 841 break;
dudmuck 3:aead8f8fdc1f 842 }
dudmuck 3:aead8f8fdc1f 843 return rssi;
dudmuck 3:aead8f8fdc1f 844 }
dudmuck 3:aead8f8fdc1f 845
dudmuck 3:aead8f8fdc1f 846 void SX1272::SetOpMode( uint8_t opMode )
dudmuck 3:aead8f8fdc1f 847 {
dudmuck 3:aead8f8fdc1f 848 if( opMode == RF_OPMODE_SLEEP )
dudmuck 3:aead8f8fdc1f 849 {
dudmuck 3:aead8f8fdc1f 850 SetAntSwLowPower( true );
dudmuck 3:aead8f8fdc1f 851 }
dudmuck 3:aead8f8fdc1f 852 else
dudmuck 3:aead8f8fdc1f 853 {
dudmuck 3:aead8f8fdc1f 854 SetAntSwLowPower( false );
dudmuck 3:aead8f8fdc1f 855 SetAntSw( opMode );
dudmuck 3:aead8f8fdc1f 856 }
dudmuck 3:aead8f8fdc1f 857 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
dudmuck 3:aead8f8fdc1f 858 }
dudmuck 3:aead8f8fdc1f 859
dudmuck 3:aead8f8fdc1f 860 void SX1272::SetModem( RadioModems_t modem )
dudmuck 3:aead8f8fdc1f 861 {
dudmuck 3:aead8f8fdc1f 862 if( ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 )
dudmuck 3:aead8f8fdc1f 863 {
dudmuck 3:aead8f8fdc1f 864 this->settings.Modem = MODEM_LORA;
dudmuck 3:aead8f8fdc1f 865 }
dudmuck 3:aead8f8fdc1f 866 else
dudmuck 3:aead8f8fdc1f 867 {
dudmuck 3:aead8f8fdc1f 868 this->settings.Modem = MODEM_FSK;
dudmuck 3:aead8f8fdc1f 869 }
dudmuck 3:aead8f8fdc1f 870
dudmuck 3:aead8f8fdc1f 871 if( this->settings.Modem == modem )
dudmuck 3:aead8f8fdc1f 872 {
dudmuck 3:aead8f8fdc1f 873 return;
dudmuck 3:aead8f8fdc1f 874 }
dudmuck 3:aead8f8fdc1f 875
dudmuck 3:aead8f8fdc1f 876 this->settings.Modem = modem;
dudmuck 3:aead8f8fdc1f 877 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 878 {
dudmuck 3:aead8f8fdc1f 879 default:
dudmuck 3:aead8f8fdc1f 880 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 881 Sleep( );
dudmuck 3:aead8f8fdc1f 882 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
dudmuck 3:aead8f8fdc1f 883
dudmuck 3:aead8f8fdc1f 884 Write( REG_DIOMAPPING1, 0x00 );
dudmuck 3:aead8f8fdc1f 885 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
dudmuck 3:aead8f8fdc1f 886 break;
dudmuck 3:aead8f8fdc1f 887 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 888 Sleep( );
dudmuck 3:aead8f8fdc1f 889 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
dudmuck 3:aead8f8fdc1f 890
dudmuck 3:aead8f8fdc1f 891 Write( REG_DIOMAPPING1, 0x00 );
dudmuck 3:aead8f8fdc1f 892 Write( REG_DIOMAPPING2, 0x00 );
dudmuck 3:aead8f8fdc1f 893 break;
dudmuck 3:aead8f8fdc1f 894 }
dudmuck 3:aead8f8fdc1f 895 }
dudmuck 3:aead8f8fdc1f 896
dudmuck 3:aead8f8fdc1f 897 void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
dudmuck 3:aead8f8fdc1f 898 {
dudmuck 3:aead8f8fdc1f 899 this->SetModem( modem );
dudmuck 3:aead8f8fdc1f 900
dudmuck 3:aead8f8fdc1f 901 switch( modem )
dudmuck 3:aead8f8fdc1f 902 {
dudmuck 3:aead8f8fdc1f 903 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 904 if( this->settings.Fsk.FixLen == false )
dudmuck 3:aead8f8fdc1f 905 {
dudmuck 3:aead8f8fdc1f 906 this->Write( REG_PAYLOADLENGTH, max );
dudmuck 3:aead8f8fdc1f 907 }
dudmuck 3:aead8f8fdc1f 908 break;
dudmuck 3:aead8f8fdc1f 909 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 910 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
dudmuck 3:aead8f8fdc1f 911 break;
dudmuck 3:aead8f8fdc1f 912 }
dudmuck 3:aead8f8fdc1f 913 }
dudmuck 3:aead8f8fdc1f 914
dudmuck 3:aead8f8fdc1f 915 void SX1272::SetPublicNetwork( bool enable )
dudmuck 3:aead8f8fdc1f 916 {
dudmuck 3:aead8f8fdc1f 917 SetModem( MODEM_LORA );
dudmuck 3:aead8f8fdc1f 918 this->settings.LoRa.PublicNetwork = enable;
dudmuck 3:aead8f8fdc1f 919 if( enable == true )
dudmuck 3:aead8f8fdc1f 920 {
dudmuck 3:aead8f8fdc1f 921 // Change LoRa modem SyncWord
dudmuck 3:aead8f8fdc1f 922 Write( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD );
dudmuck 3:aead8f8fdc1f 923 }
dudmuck 3:aead8f8fdc1f 924 else
dudmuck 3:aead8f8fdc1f 925 {
dudmuck 3:aead8f8fdc1f 926 // Change LoRa modem SyncWord
dudmuck 3:aead8f8fdc1f 927 Write( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD );
dudmuck 3:aead8f8fdc1f 928 }
dudmuck 3:aead8f8fdc1f 929 }
dudmuck 3:aead8f8fdc1f 930
dudmuck 3:aead8f8fdc1f 931 void SX1272::OnTimeoutIrq( void )
dudmuck 3:aead8f8fdc1f 932 {
dudmuck 3:aead8f8fdc1f 933 switch( this->settings.State )
dudmuck 3:aead8f8fdc1f 934 {
dudmuck 3:aead8f8fdc1f 935 case RF_RX_RUNNING:
dudmuck 3:aead8f8fdc1f 936 if( this->settings.Modem == MODEM_FSK )
dudmuck 3:aead8f8fdc1f 937 {
dudmuck 3:aead8f8fdc1f 938 this->settings.FskPacketHandler.PreambleDetected = false;
dudmuck 3:aead8f8fdc1f 939 this->settings.FskPacketHandler.SyncWordDetected = false;
dudmuck 3:aead8f8fdc1f 940 this->settings.FskPacketHandler.NbBytes = 0;
dudmuck 3:aead8f8fdc1f 941 this->settings.FskPacketHandler.Size = 0;
dudmuck 3:aead8f8fdc1f 942
dudmuck 3:aead8f8fdc1f 943 // Clear Irqs
dudmuck 3:aead8f8fdc1f 944 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
dudmuck 3:aead8f8fdc1f 945 RF_IRQFLAGS1_PREAMBLEDETECT |
dudmuck 3:aead8f8fdc1f 946 RF_IRQFLAGS1_SYNCADDRESSMATCH );
dudmuck 3:aead8f8fdc1f 947 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
dudmuck 3:aead8f8fdc1f 948
dudmuck 3:aead8f8fdc1f 949 if( this->settings.Fsk.RxContinuous == true )
dudmuck 3:aead8f8fdc1f 950 {
dudmuck 3:aead8f8fdc1f 951 // Continuous mode restart Rx chain
dudmuck 3:aead8f8fdc1f 952 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
dudmuck 3:aead8f8fdc1f 953 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ),
dudmuck 3:aead8f8fdc1f 954 this->settings.Fsk.RxSingleTimeout * 1e3 );
dudmuck 3:aead8f8fdc1f 955 }
dudmuck 3:aead8f8fdc1f 956 else
dudmuck 3:aead8f8fdc1f 957 {
dudmuck 3:aead8f8fdc1f 958 this->settings.State = RF_IDLE;
dudmuck 3:aead8f8fdc1f 959 rxTimeoutSyncWord.detach( );
dudmuck 3:aead8f8fdc1f 960 }
dudmuck 3:aead8f8fdc1f 961 }
dudmuck 3:aead8f8fdc1f 962 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
dudmuck 3:aead8f8fdc1f 963 {
dudmuck 3:aead8f8fdc1f 964 this->RadioEvents->RxTimeout( );
dudmuck 3:aead8f8fdc1f 965 }
dudmuck 3:aead8f8fdc1f 966 break;
dudmuck 3:aead8f8fdc1f 967 case RF_TX_RUNNING:
dudmuck 3:aead8f8fdc1f 968 // Tx timeout shouldn't happen.
dudmuck 3:aead8f8fdc1f 969 // But it has been observed that when it happens it is a result of a corrupted SPI transfer
dudmuck 3:aead8f8fdc1f 970 // it depends on the platform design.
dudmuck 3:aead8f8fdc1f 971 //
dudmuck 3:aead8f8fdc1f 972 // The workaround is to put the radio in a known state. Thus, we re-initialize it.
dudmuck 3:aead8f8fdc1f 973
dudmuck 3:aead8f8fdc1f 974 // BEGIN WORKAROUND
dudmuck 3:aead8f8fdc1f 975
dudmuck 3:aead8f8fdc1f 976 // Reset the radio
dudmuck 3:aead8f8fdc1f 977 Reset( );
dudmuck 3:aead8f8fdc1f 978
dudmuck 3:aead8f8fdc1f 979 // Initialize radio default values
dudmuck 3:aead8f8fdc1f 980 SetOpMode( RF_OPMODE_SLEEP );
dudmuck 3:aead8f8fdc1f 981
dudmuck 3:aead8f8fdc1f 982 RadioRegistersInit( );
dudmuck 3:aead8f8fdc1f 983
dudmuck 3:aead8f8fdc1f 984 SetModem( MODEM_FSK );
dudmuck 3:aead8f8fdc1f 985
dudmuck 3:aead8f8fdc1f 986 // Restore previous network type setting.
dudmuck 3:aead8f8fdc1f 987 SetPublicNetwork( this->settings.LoRa.PublicNetwork );
dudmuck 3:aead8f8fdc1f 988 // END WORKAROUND
dudmuck 3:aead8f8fdc1f 989
dudmuck 3:aead8f8fdc1f 990 this->settings.State = RF_IDLE;
dudmuck 3:aead8f8fdc1f 991 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
dudmuck 3:aead8f8fdc1f 992 {
dudmuck 3:aead8f8fdc1f 993 this->RadioEvents->TxTimeout( );
dudmuck 3:aead8f8fdc1f 994 }
dudmuck 3:aead8f8fdc1f 995 break;
dudmuck 3:aead8f8fdc1f 996 default:
dudmuck 3:aead8f8fdc1f 997 break;
dudmuck 3:aead8f8fdc1f 998 }
dudmuck 3:aead8f8fdc1f 999 }
dudmuck 3:aead8f8fdc1f 1000
dudmuck 3:aead8f8fdc1f 1001 void SX1272::OnDio0Irq( void )
dudmuck 3:aead8f8fdc1f 1002 {
dudmuck 3:aead8f8fdc1f 1003 volatile uint8_t irqFlags = 0;
dudmuck 3:aead8f8fdc1f 1004 unsigned int now_us = lp_timer.read_us();
dudmuck 3:aead8f8fdc1f 1005
dudmuck 3:aead8f8fdc1f 1006 switch( this->settings.State )
dudmuck 3:aead8f8fdc1f 1007 {
dudmuck 3:aead8f8fdc1f 1008 case RF_RX_RUNNING:
dudmuck 3:aead8f8fdc1f 1009 //TimerStop( &RxTimeoutTimer );
dudmuck 3:aead8f8fdc1f 1010 // RxDone interrupt
dudmuck 3:aead8f8fdc1f 1011 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 1012 {
dudmuck 3:aead8f8fdc1f 1013 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 1014 if( this->settings.Fsk.CrcOn == true )
dudmuck 3:aead8f8fdc1f 1015 {
dudmuck 3:aead8f8fdc1f 1016 irqFlags = Read( REG_IRQFLAGS2 );
dudmuck 3:aead8f8fdc1f 1017 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
dudmuck 3:aead8f8fdc1f 1018 {
dudmuck 3:aead8f8fdc1f 1019 // Clear Irqs
dudmuck 3:aead8f8fdc1f 1020 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
dudmuck 3:aead8f8fdc1f 1021 RF_IRQFLAGS1_PREAMBLEDETECT |
dudmuck 3:aead8f8fdc1f 1022 RF_IRQFLAGS1_SYNCADDRESSMATCH );
dudmuck 3:aead8f8fdc1f 1023 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
dudmuck 3:aead8f8fdc1f 1024
dudmuck 3:aead8f8fdc1f 1025 rxTimeoutTimer.detach( );
dudmuck 3:aead8f8fdc1f 1026
dudmuck 3:aead8f8fdc1f 1027 if( this->settings.Fsk.RxContinuous == false )
dudmuck 3:aead8f8fdc1f 1028 {
dudmuck 3:aead8f8fdc1f 1029 rxTimeoutSyncWord.detach( );
dudmuck 3:aead8f8fdc1f 1030 this->settings.State = RF_IDLE;
dudmuck 3:aead8f8fdc1f 1031 }
dudmuck 3:aead8f8fdc1f 1032 else
dudmuck 3:aead8f8fdc1f 1033 {
dudmuck 3:aead8f8fdc1f 1034 // Continuous mode restart Rx chain
dudmuck 3:aead8f8fdc1f 1035 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
dudmuck 3:aead8f8fdc1f 1036 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ),
dudmuck 3:aead8f8fdc1f 1037 this->settings.Fsk.RxSingleTimeout * 1e3 );
dudmuck 3:aead8f8fdc1f 1038 }
dudmuck 3:aead8f8fdc1f 1039
dudmuck 3:aead8f8fdc1f 1040 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
dudmuck 3:aead8f8fdc1f 1041 {
dudmuck 3:aead8f8fdc1f 1042 this->RadioEvents->RxError( );
dudmuck 3:aead8f8fdc1f 1043 }
dudmuck 3:aead8f8fdc1f 1044 this->settings.FskPacketHandler.PreambleDetected = false;
dudmuck 3:aead8f8fdc1f 1045 this->settings.FskPacketHandler.SyncWordDetected = false;
dudmuck 3:aead8f8fdc1f 1046 this->settings.FskPacketHandler.NbBytes = 0;
dudmuck 3:aead8f8fdc1f 1047 this->settings.FskPacketHandler.Size = 0;
dudmuck 3:aead8f8fdc1f 1048 break;
dudmuck 3:aead8f8fdc1f 1049 }
dudmuck 3:aead8f8fdc1f 1050 }
dudmuck 3:aead8f8fdc1f 1051
dudmuck 3:aead8f8fdc1f 1052 // Read received packet size
dudmuck 3:aead8f8fdc1f 1053 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
dudmuck 3:aead8f8fdc1f 1054 {
dudmuck 3:aead8f8fdc1f 1055 if( this->settings.Fsk.FixLen == false )
dudmuck 3:aead8f8fdc1f 1056 {
dudmuck 3:aead8f8fdc1f 1057 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
dudmuck 3:aead8f8fdc1f 1058 }
dudmuck 3:aead8f8fdc1f 1059 else
dudmuck 3:aead8f8fdc1f 1060 {
dudmuck 3:aead8f8fdc1f 1061 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
dudmuck 3:aead8f8fdc1f 1062 }
dudmuck 3:aead8f8fdc1f 1063 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
dudmuck 3:aead8f8fdc1f 1064 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
dudmuck 3:aead8f8fdc1f 1065 }
dudmuck 3:aead8f8fdc1f 1066 else
dudmuck 3:aead8f8fdc1f 1067 {
dudmuck 3:aead8f8fdc1f 1068 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
dudmuck 3:aead8f8fdc1f 1069 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
dudmuck 3:aead8f8fdc1f 1070 }
dudmuck 3:aead8f8fdc1f 1071
dudmuck 3:aead8f8fdc1f 1072 rxTimeoutTimer.detach( );
dudmuck 3:aead8f8fdc1f 1073
dudmuck 3:aead8f8fdc1f 1074 if( this->settings.Fsk.RxContinuous == false )
dudmuck 3:aead8f8fdc1f 1075 {
dudmuck 3:aead8f8fdc1f 1076 this->settings.State = RF_IDLE;
dudmuck 3:aead8f8fdc1f 1077 rxTimeoutSyncWord.detach( );
dudmuck 3:aead8f8fdc1f 1078 }
dudmuck 3:aead8f8fdc1f 1079 else
dudmuck 3:aead8f8fdc1f 1080 {
dudmuck 3:aead8f8fdc1f 1081 // Continuous mode restart Rx chain
dudmuck 3:aead8f8fdc1f 1082 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
dudmuck 3:aead8f8fdc1f 1083 rxTimeoutSyncWord.attach_us( mbed::callback( this, &SX1272::OnTimeoutIrq ),
dudmuck 3:aead8f8fdc1f 1084 this->settings.Fsk.RxSingleTimeout * 1e3 );
dudmuck 3:aead8f8fdc1f 1085 }
dudmuck 3:aead8f8fdc1f 1086
dudmuck 3:aead8f8fdc1f 1087 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
dudmuck 3:aead8f8fdc1f 1088 {
dudmuck 3:aead8f8fdc1f 1089 this->RadioEvents->RxDone(now_us, rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
dudmuck 3:aead8f8fdc1f 1090 }
dudmuck 3:aead8f8fdc1f 1091 this->settings.FskPacketHandler.PreambleDetected = false;
dudmuck 3:aead8f8fdc1f 1092 this->settings.FskPacketHandler.SyncWordDetected = false;
dudmuck 3:aead8f8fdc1f 1093 this->settings.FskPacketHandler.NbBytes = 0;
dudmuck 3:aead8f8fdc1f 1094 this->settings.FskPacketHandler.Size = 0;
dudmuck 3:aead8f8fdc1f 1095 break;
dudmuck 3:aead8f8fdc1f 1096 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 1097 {
dudmuck 3:aead8f8fdc1f 1098 int8_t snr = 0;
dudmuck 3:aead8f8fdc1f 1099
dudmuck 3:aead8f8fdc1f 1100 // Clear Irq
dudmuck 3:aead8f8fdc1f 1101 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
dudmuck 3:aead8f8fdc1f 1102
dudmuck 3:aead8f8fdc1f 1103 irqFlags = Read( REG_LR_IRQFLAGS );
dudmuck 3:aead8f8fdc1f 1104 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
dudmuck 3:aead8f8fdc1f 1105 {
dudmuck 3:aead8f8fdc1f 1106 // Clear Irq
dudmuck 3:aead8f8fdc1f 1107 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
dudmuck 3:aead8f8fdc1f 1108
dudmuck 3:aead8f8fdc1f 1109 if( this->settings.LoRa.RxContinuous == false )
dudmuck 3:aead8f8fdc1f 1110 {
dudmuck 3:aead8f8fdc1f 1111 this->settings.State = RF_IDLE;
dudmuck 3:aead8f8fdc1f 1112 }
dudmuck 3:aead8f8fdc1f 1113 rxTimeoutTimer.detach( );
dudmuck 3:aead8f8fdc1f 1114
dudmuck 3:aead8f8fdc1f 1115 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
dudmuck 3:aead8f8fdc1f 1116 {
dudmuck 3:aead8f8fdc1f 1117 this->RadioEvents->RxError( );
dudmuck 3:aead8f8fdc1f 1118 }
dudmuck 3:aead8f8fdc1f 1119 break;
dudmuck 3:aead8f8fdc1f 1120 }
dudmuck 3:aead8f8fdc1f 1121
dudmuck 3:aead8f8fdc1f 1122 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
dudmuck 3:aead8f8fdc1f 1123 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
dudmuck 3:aead8f8fdc1f 1124 {
dudmuck 3:aead8f8fdc1f 1125 // Invert and divide by 4
dudmuck 3:aead8f8fdc1f 1126 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
dudmuck 3:aead8f8fdc1f 1127 snr = -snr;
dudmuck 3:aead8f8fdc1f 1128 }
dudmuck 3:aead8f8fdc1f 1129 else
dudmuck 3:aead8f8fdc1f 1130 {
dudmuck 3:aead8f8fdc1f 1131 // Divide by 4
dudmuck 3:aead8f8fdc1f 1132 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
dudmuck 3:aead8f8fdc1f 1133 }
dudmuck 3:aead8f8fdc1f 1134
dudmuck 3:aead8f8fdc1f 1135 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
dudmuck 3:aead8f8fdc1f 1136 if( snr < 0 )
dudmuck 3:aead8f8fdc1f 1137 {
dudmuck 3:aead8f8fdc1f 1138 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 ) +
dudmuck 3:aead8f8fdc1f 1139 snr;
dudmuck 3:aead8f8fdc1f 1140 }
dudmuck 3:aead8f8fdc1f 1141 else
dudmuck 3:aead8f8fdc1f 1142 {
dudmuck 3:aead8f8fdc1f 1143 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 );
dudmuck 3:aead8f8fdc1f 1144 }
dudmuck 3:aead8f8fdc1f 1145
dudmuck 3:aead8f8fdc1f 1146 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
dudmuck 3:aead8f8fdc1f 1147 ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size );
dudmuck 3:aead8f8fdc1f 1148
dudmuck 3:aead8f8fdc1f 1149 if( this->settings.LoRa.RxContinuous == false )
dudmuck 3:aead8f8fdc1f 1150 {
dudmuck 3:aead8f8fdc1f 1151 this->settings.State = RF_IDLE;
dudmuck 3:aead8f8fdc1f 1152 }
dudmuck 3:aead8f8fdc1f 1153 rxTimeoutTimer.detach( );
dudmuck 3:aead8f8fdc1f 1154
dudmuck 3:aead8f8fdc1f 1155 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
dudmuck 3:aead8f8fdc1f 1156 {
dudmuck 3:aead8f8fdc1f 1157 this->RadioEvents->RxDone(now_us, rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
dudmuck 3:aead8f8fdc1f 1158 }
dudmuck 3:aead8f8fdc1f 1159 }
dudmuck 3:aead8f8fdc1f 1160 break;
dudmuck 3:aead8f8fdc1f 1161 default:
dudmuck 3:aead8f8fdc1f 1162 break;
dudmuck 3:aead8f8fdc1f 1163 }
dudmuck 3:aead8f8fdc1f 1164 break;
dudmuck 3:aead8f8fdc1f 1165 case RF_TX_RUNNING:
dudmuck 3:aead8f8fdc1f 1166 txTimeoutTimer.detach( );
dudmuck 3:aead8f8fdc1f 1167 // TxDone interrupt
dudmuck 3:aead8f8fdc1f 1168 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 1169 {
dudmuck 3:aead8f8fdc1f 1170 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 1171 // Clear Irq
dudmuck 3:aead8f8fdc1f 1172 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
dudmuck 3:aead8f8fdc1f 1173 // Intentional fall through
dudmuck 3:aead8f8fdc1f 1174 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 1175 default:
dudmuck 3:aead8f8fdc1f 1176 this->settings.State = RF_IDLE;
dudmuck 3:aead8f8fdc1f 1177 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
dudmuck 3:aead8f8fdc1f 1178 {
dudmuck 3:aead8f8fdc1f 1179 this->RadioEvents->TxDone( now_us );
dudmuck 3:aead8f8fdc1f 1180 }
dudmuck 3:aead8f8fdc1f 1181 break;
dudmuck 3:aead8f8fdc1f 1182 }
dudmuck 3:aead8f8fdc1f 1183 break;
dudmuck 3:aead8f8fdc1f 1184 default:
dudmuck 3:aead8f8fdc1f 1185 break;
dudmuck 3:aead8f8fdc1f 1186 }
dudmuck 3:aead8f8fdc1f 1187 }
dudmuck 3:aead8f8fdc1f 1188
dudmuck 3:aead8f8fdc1f 1189 void SX1272::OnDio1Irq( void )
dudmuck 3:aead8f8fdc1f 1190 {
dudmuck 3:aead8f8fdc1f 1191 switch( this->settings.State )
dudmuck 3:aead8f8fdc1f 1192 {
dudmuck 3:aead8f8fdc1f 1193 case RF_RX_RUNNING:
dudmuck 3:aead8f8fdc1f 1194 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 1195 {
dudmuck 3:aead8f8fdc1f 1196 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 1197 // FifoLevel interrupt
dudmuck 3:aead8f8fdc1f 1198 // Read received packet size
dudmuck 3:aead8f8fdc1f 1199 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
dudmuck 3:aead8f8fdc1f 1200 {
dudmuck 3:aead8f8fdc1f 1201 if( this->settings.Fsk.FixLen == false )
dudmuck 3:aead8f8fdc1f 1202 {
dudmuck 3:aead8f8fdc1f 1203 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
dudmuck 3:aead8f8fdc1f 1204 }
dudmuck 3:aead8f8fdc1f 1205 else
dudmuck 3:aead8f8fdc1f 1206 {
dudmuck 3:aead8f8fdc1f 1207 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
dudmuck 3:aead8f8fdc1f 1208 }
dudmuck 3:aead8f8fdc1f 1209 }
dudmuck 3:aead8f8fdc1f 1210
dudmuck 3:aead8f8fdc1f 1211 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
dudmuck 3:aead8f8fdc1f 1212 {
dudmuck 3:aead8f8fdc1f 1213 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
dudmuck 3:aead8f8fdc1f 1214 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
dudmuck 3:aead8f8fdc1f 1215 }
dudmuck 3:aead8f8fdc1f 1216 else
dudmuck 3:aead8f8fdc1f 1217 {
dudmuck 3:aead8f8fdc1f 1218 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
dudmuck 3:aead8f8fdc1f 1219 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
dudmuck 3:aead8f8fdc1f 1220 }
dudmuck 3:aead8f8fdc1f 1221 break;
dudmuck 3:aead8f8fdc1f 1222 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 1223 // Sync time out
dudmuck 3:aead8f8fdc1f 1224 rxTimeoutTimer.detach( );
dudmuck 3:aead8f8fdc1f 1225 // Clear Irq
dudmuck 3:aead8f8fdc1f 1226 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT );
dudmuck 3:aead8f8fdc1f 1227
dudmuck 3:aead8f8fdc1f 1228 this->settings.State = RF_IDLE;
dudmuck 3:aead8f8fdc1f 1229 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
dudmuck 3:aead8f8fdc1f 1230 {
dudmuck 3:aead8f8fdc1f 1231 this->RadioEvents->RxTimeout( );
dudmuck 3:aead8f8fdc1f 1232 }
dudmuck 3:aead8f8fdc1f 1233 break;
dudmuck 3:aead8f8fdc1f 1234 default:
dudmuck 3:aead8f8fdc1f 1235 break;
dudmuck 3:aead8f8fdc1f 1236 }
dudmuck 3:aead8f8fdc1f 1237 break;
dudmuck 3:aead8f8fdc1f 1238 case RF_TX_RUNNING:
dudmuck 3:aead8f8fdc1f 1239 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 1240 {
dudmuck 3:aead8f8fdc1f 1241 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 1242 // FifoEmpty interrupt
dudmuck 3:aead8f8fdc1f 1243 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
dudmuck 3:aead8f8fdc1f 1244 {
dudmuck 3:aead8f8fdc1f 1245 WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
dudmuck 3:aead8f8fdc1f 1246 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
dudmuck 3:aead8f8fdc1f 1247 }
dudmuck 3:aead8f8fdc1f 1248 else
dudmuck 3:aead8f8fdc1f 1249 {
dudmuck 3:aead8f8fdc1f 1250 // Write the last chunk of data
dudmuck 3:aead8f8fdc1f 1251 WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
dudmuck 3:aead8f8fdc1f 1252 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
dudmuck 3:aead8f8fdc1f 1253 }
dudmuck 3:aead8f8fdc1f 1254 break;
dudmuck 3:aead8f8fdc1f 1255 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 1256 break;
dudmuck 3:aead8f8fdc1f 1257 default:
dudmuck 3:aead8f8fdc1f 1258 break;
dudmuck 3:aead8f8fdc1f 1259 }
dudmuck 3:aead8f8fdc1f 1260 break;
dudmuck 3:aead8f8fdc1f 1261 default:
dudmuck 3:aead8f8fdc1f 1262 break;
dudmuck 3:aead8f8fdc1f 1263 }
dudmuck 3:aead8f8fdc1f 1264 }
dudmuck 3:aead8f8fdc1f 1265
dudmuck 3:aead8f8fdc1f 1266 void SX1272::OnDio2Irq( void )
dudmuck 3:aead8f8fdc1f 1267 {
dudmuck 3:aead8f8fdc1f 1268 switch( this->settings.State )
dudmuck 3:aead8f8fdc1f 1269 {
dudmuck 3:aead8f8fdc1f 1270 case RF_RX_RUNNING:
dudmuck 3:aead8f8fdc1f 1271 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 1272 {
dudmuck 3:aead8f8fdc1f 1273 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 1274 // Checks if DIO4 is connected. If it is not PreambleDtected is set to true.
dudmuck 3:aead8f8fdc1f 1275 if( this->dioIrq[4] == NULL )
dudmuck 3:aead8f8fdc1f 1276 {
dudmuck 3:aead8f8fdc1f 1277 this->settings.FskPacketHandler.PreambleDetected = true;
dudmuck 3:aead8f8fdc1f 1278 }
dudmuck 3:aead8f8fdc1f 1279
dudmuck 3:aead8f8fdc1f 1280 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
dudmuck 3:aead8f8fdc1f 1281 {
dudmuck 3:aead8f8fdc1f 1282 rxTimeoutSyncWord.detach( );
dudmuck 3:aead8f8fdc1f 1283
dudmuck 3:aead8f8fdc1f 1284 this->settings.FskPacketHandler.SyncWordDetected = true;
dudmuck 3:aead8f8fdc1f 1285
dudmuck 3:aead8f8fdc1f 1286 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
dudmuck 3:aead8f8fdc1f 1287
dudmuck 3:aead8f8fdc1f 1288 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
dudmuck 3:aead8f8fdc1f 1289 ( uint16_t )Read( REG_AFCLSB ) ) *
dudmuck 3:aead8f8fdc1f 1290 ( double )FREQ_STEP;
dudmuck 3:aead8f8fdc1f 1291 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
dudmuck 3:aead8f8fdc1f 1292 }
dudmuck 3:aead8f8fdc1f 1293 break;
dudmuck 3:aead8f8fdc1f 1294 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 1295 if( this->settings.LoRa.FreqHopOn == true )
dudmuck 3:aead8f8fdc1f 1296 {
dudmuck 3:aead8f8fdc1f 1297 // Clear Irq
dudmuck 3:aead8f8fdc1f 1298 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
dudmuck 3:aead8f8fdc1f 1299
dudmuck 3:aead8f8fdc1f 1300 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
dudmuck 3:aead8f8fdc1f 1301 {
dudmuck 3:aead8f8fdc1f 1302 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
dudmuck 3:aead8f8fdc1f 1303 }
dudmuck 3:aead8f8fdc1f 1304 }
dudmuck 3:aead8f8fdc1f 1305 break;
dudmuck 3:aead8f8fdc1f 1306 default:
dudmuck 3:aead8f8fdc1f 1307 break;
dudmuck 3:aead8f8fdc1f 1308 }
dudmuck 3:aead8f8fdc1f 1309 break;
dudmuck 3:aead8f8fdc1f 1310 case RF_TX_RUNNING:
dudmuck 3:aead8f8fdc1f 1311 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 1312 {
dudmuck 3:aead8f8fdc1f 1313 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 1314 break;
dudmuck 3:aead8f8fdc1f 1315 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 1316 if( this->settings.LoRa.FreqHopOn == true )
dudmuck 3:aead8f8fdc1f 1317 {
dudmuck 3:aead8f8fdc1f 1318 // Clear Irq
dudmuck 3:aead8f8fdc1f 1319 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
dudmuck 3:aead8f8fdc1f 1320
dudmuck 3:aead8f8fdc1f 1321 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
dudmuck 3:aead8f8fdc1f 1322 {
dudmuck 3:aead8f8fdc1f 1323 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
dudmuck 3:aead8f8fdc1f 1324 }
dudmuck 3:aead8f8fdc1f 1325 }
dudmuck 3:aead8f8fdc1f 1326 break;
dudmuck 3:aead8f8fdc1f 1327 default:
dudmuck 3:aead8f8fdc1f 1328 break;
dudmuck 3:aead8f8fdc1f 1329 }
dudmuck 3:aead8f8fdc1f 1330 break;
dudmuck 3:aead8f8fdc1f 1331 default:
dudmuck 3:aead8f8fdc1f 1332 break;
dudmuck 3:aead8f8fdc1f 1333 }
dudmuck 3:aead8f8fdc1f 1334 }
dudmuck 3:aead8f8fdc1f 1335
dudmuck 3:aead8f8fdc1f 1336 void SX1272::OnDio3Irq( void )
dudmuck 3:aead8f8fdc1f 1337 {
dudmuck 3:aead8f8fdc1f 1338 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 1339 {
dudmuck 3:aead8f8fdc1f 1340 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 1341 break;
dudmuck 3:aead8f8fdc1f 1342 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 1343 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
dudmuck 3:aead8f8fdc1f 1344 {
dudmuck 3:aead8f8fdc1f 1345 // Clear Irq
dudmuck 3:aead8f8fdc1f 1346 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
dudmuck 3:aead8f8fdc1f 1347 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
dudmuck 3:aead8f8fdc1f 1348 {
dudmuck 3:aead8f8fdc1f 1349 this->RadioEvents->CadDone( true );
dudmuck 3:aead8f8fdc1f 1350 }
dudmuck 3:aead8f8fdc1f 1351 }
dudmuck 3:aead8f8fdc1f 1352 else
dudmuck 3:aead8f8fdc1f 1353 {
dudmuck 3:aead8f8fdc1f 1354 // Clear Irq
dudmuck 3:aead8f8fdc1f 1355 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
dudmuck 3:aead8f8fdc1f 1356 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
dudmuck 3:aead8f8fdc1f 1357 {
dudmuck 3:aead8f8fdc1f 1358 this->RadioEvents->CadDone( false );
dudmuck 3:aead8f8fdc1f 1359 }
dudmuck 3:aead8f8fdc1f 1360 }
dudmuck 3:aead8f8fdc1f 1361 break;
dudmuck 3:aead8f8fdc1f 1362 default:
dudmuck 3:aead8f8fdc1f 1363 break;
dudmuck 3:aead8f8fdc1f 1364 }
dudmuck 3:aead8f8fdc1f 1365 }
dudmuck 3:aead8f8fdc1f 1366
dudmuck 3:aead8f8fdc1f 1367 void SX1272::OnDio4Irq( void )
dudmuck 3:aead8f8fdc1f 1368 {
dudmuck 3:aead8f8fdc1f 1369 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 1370 {
dudmuck 3:aead8f8fdc1f 1371 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 1372 {
dudmuck 3:aead8f8fdc1f 1373 if( this->settings.FskPacketHandler.PreambleDetected == false )
dudmuck 3:aead8f8fdc1f 1374 {
dudmuck 3:aead8f8fdc1f 1375 this->settings.FskPacketHandler.PreambleDetected = true;
dudmuck 3:aead8f8fdc1f 1376 }
dudmuck 3:aead8f8fdc1f 1377 }
dudmuck 3:aead8f8fdc1f 1378 break;
dudmuck 3:aead8f8fdc1f 1379 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 1380 break;
dudmuck 3:aead8f8fdc1f 1381 default:
dudmuck 3:aead8f8fdc1f 1382 break;
dudmuck 3:aead8f8fdc1f 1383 }
dudmuck 3:aead8f8fdc1f 1384 }
dudmuck 3:aead8f8fdc1f 1385
dudmuck 3:aead8f8fdc1f 1386 void SX1272::OnDio5Irq( void )
dudmuck 3:aead8f8fdc1f 1387 {
dudmuck 3:aead8f8fdc1f 1388 switch( this->settings.Modem )
dudmuck 3:aead8f8fdc1f 1389 {
dudmuck 3:aead8f8fdc1f 1390 case MODEM_FSK:
dudmuck 3:aead8f8fdc1f 1391 break;
dudmuck 3:aead8f8fdc1f 1392 case MODEM_LORA:
dudmuck 3:aead8f8fdc1f 1393 break;
dudmuck 3:aead8f8fdc1f 1394 default:
dudmuck 3:aead8f8fdc1f 1395 break;
dudmuck 3:aead8f8fdc1f 1396 }
dudmuck 3:aead8f8fdc1f 1397 }
dudmuck 3:aead8f8fdc1f 1398 #endif /* ENABLE_SX1272 */