Diff: MACROS.h

Revision:

27:9c93ce7cb9d8

Parent:

20:59c74aaedda2

Child:

28:76793a84f9e5

diff -r 91e4dba7ebe2 -r 9c93ce7cb9d8 MACROS.h
--- a/MACROS.h	Mon Jun 10 19:06:21 2013 +0000
+++ b/MACROS.h	Thu Jul 11 13:34:53 2013 +0000
@@ -23,48 +23,69 @@
 #ifndef MODSERIAL_MACROS_H
 #define MODSERIAL_MACROS_H
 
-#define MODSERIAL_RBR  0x00
-#define MODSERIAL_THR  0x00
-#define MODSERIAL_DLL  0x00
-#define MODSERIAL_IER  0x04
-#define MODSERIAL_DML  0x04
-#define MODSERIAL_IIR  0x08
-#define MODSERIAL_FCR  0x08
-#define MODSERIAL_LCR  0x0C
-#define MODSERIAL_LSR  0x14
-#define MODSERIAL_SCR  0x1C
-#define MODSERIAL_ACR  0x20
-#define MODSERIAL_ICR  0x24
-#define MODSERIAL_FDR  0x28
-#define MODSERIAL_TER  0x30
-
-#define MODSERIAL_LSR_RDR  (1UL << 0)
-#define MODSERIAL_LSR_OE   (1UL << 1)
-#define MODSERIAL_LSR_PE   (1UL << 2)
-#define MODSERIAL_LSR_FE   (1UL << 3)
-#define MODSERIAL_LSR_BR   (1UL << 4)
-#define MODSERIAL_LSR_THRE (1UL << 5)
-#define MODSERIAL_LSR_TEMT (1UL << 6)
-#define MODSERIAL_LSR_RXFE (1UL << 7)
-
-#define MODSERIAL_FIFO_ENABLE   1
-#define MODSERIAL_FIFO_RX_RESET 2
-#define MODSERIAL_FIFO_TX_RESET 4
-
-#define _RBR    *((char *)_base+MODSERIAL_RBR)
-#define _THR    *((char *)_base+MODSERIAL_THR)
-#define _IIR    *((char *)_base+MODSERIAL_IIR)
-#define _IER    *((char *)_base+MODSERIAL_IER)
-#define _LSR    *((char *)_base+MODSERIAL_LSR)
-#define _FCR    *((char *)_base+MODSERIAL_FCR)
 
 #define MODSERIAL_TX_BUFFER_EMPTY (buffer_count[TxIrq]==0)
 #define MODSERIAL_RX_BUFFER_EMPTY (buffer_count[RxIrq]==0)
 #define MODSERIAL_TX_BUFFER_FULL  (buffer_count[TxIrq]==buffer_size[TxIrq])
 #define MODSERIAL_RX_BUFFER_FULL  (buffer_count[RxIrq]==buffer_size[RxIrq])
 
-#define MODSERIAL_THR_HAS_SPACE ((int)_LSR&MODSERIAL_LSR_THRE)
-#define MODSERIAL_TEMT_IS_EMPTY ((int)_LSR&MODSERIAL_LSR_TEMT)
-#define MODSERIAL_RBR_HAS_DATA  ((int)_LSR&MODSERIAL_LSR_RDR)
+
+#ifdef TARGET_LPC1768
+
+#define MODSERIAL_IRQ_REG ((LPC_UART_TypeDef*)_base)->IER
+#define DISABLE_TX_IRQ MODSERIAL_IRQ_REG &= ~(1UL << 1)
+#define DISABLE_RX_IRQ MODSERIAL_IRQ_REG &= ~(1UL << 0)
+#define ENABLE_TX_IRQ MODSERIAL_IRQ_REG |= (1UL << 1)
+#define ENABLE_RX_IRQ MODSERIAL_IRQ_REG |= (1UL << 0)
+
+#define RESET_TX_FIFO ((LPC_UART_TypeDef*)_base)->FCR |= (1UL<<2)
+#define RESET_RX_FIFO ((LPC_UART_TypeDef*)_base)->FCR |= (1UL<<1)
+#define ENABLE_FIFO ((LPC_UART_TypeDef*)_base)->FCR = (1UL<<0) + (1UL<<1) + (1UL<<2)
+
+#define MODSERIAL_READ_REG ((LPC_UART_TypeDef*)_base)->RBR
+#define MODSERIAL_WRITE_REG ((LPC_UART_TypeDef*)_base)->THR
+#define MODSERIAL_READABLE ((((LPC_UART_TypeDef*)_base)->LSR & (1UL<<0)) != 0)
+#define MODSERIAL_WRITABLE ((((LPC_UART_TypeDef*)_base)->LSR & (1UL<<5)) != 0)
+
 
 #endif
+
+#ifdef TARGET_LPC11U24
+
+#define MODSERIAL_IRQ_REG ((LPC_UART_TypeDef*)_base)->IER
+#define DISABLE_TX_IRQ MODSERIAL_IRQ_REG &= ~(1UL << 1)
+#define DISABLE_RX_IRQ MODSERIAL_IRQ_REG &= ~(1UL << 0)
+#define ENABLE_TX_IRQ MODSERIAL_IRQ_REG |= (1UL << 1)
+#define ENABLE_RX_IRQ MODSERIAL_IRQ_REG |= (1UL << 0)
+
+#define RESET_TX_FIFO ((LPC_UART_TypeDef*)_base)->FCR |= (1UL<<2)
+#define RESET_RX_FIFO ((LPC_UART_TypeDef*)_base)->FCR |= (1UL<<1)
+#define ENABLE_FIFO ((LPC_UART_TypeDef*)_base)->FCR = (1UL<<0) + (1UL<<1) + (1UL<<2)
+
+#define MODSERIAL_READ_REG ((LPC_UART_TypeDef*)_base)->RBR
+#define MODSERIAL_WRITE_REG ((LPC_UART_TypeDef*)_base)->THR
+#define MODSERIAL_READABLE ((((LPC_UART_TypeDef*)_base)->LSR & (1UL<<0)) != 0)
+#define MODSERIAL_WRITABLE ((((LPC_UART_TypeDef*)_base)->LSR & (1UL<<5)) != 0)
+
+#endif
+
+#ifdef TARGET_KL25Z
+
+#define MODSERIAL_IRQ_REG ((UART_Type*)_base)->C2
+#define DISABLE_TX_IRQ MODSERIAL_IRQ_REG &= ~(1UL << UART_C2_TIE_SHIFT)
+#define DISABLE_RX_IRQ MODSERIAL_IRQ_REG &= ~(1UL << UART_C2_RIE_SHIFT)
+#define ENABLE_TX_IRQ MODSERIAL_IRQ_REG |= (1UL << UART_C2_TIE_SHIFT)
+#define ENABLE_RX_IRQ MODSERIAL_IRQ_REG |= (1UL << UART_C2_RIE_SHIFT)
+
+#define RESET_TX_FIFO while(0 == 1)
+#define RESET_RX_FIFO while(0 == 1)
+#define ENABLE_FIFO while(0 == 1)
+
+#define MODSERIAL_READ_REG ((UART_Type*)_base)->D
+#define MODSERIAL_WRITE_REG ((UART_Type*)_base)->D
+#define MODSERIAL_READABLE ((((UART_Type*)_base)->S1 & (1UL<<5)) != 0)
+#define MODSERIAL_WRITABLE ((((UART_Type*)_base)->S1 & (1UL<<7)) != 0)
+
+#endif
+
+#endif