RFID-RC522 Shield
Dependents: RFID-RC522 RFID-RC522 main job ... more
MFRC522.cpp@0:332c9a37111d, 2018-09-20 (annotated)
- Committer:
- duchonic
- Date:
- Thu Sep 20 09:03:56 2018 +0000
- Revision:
- 0:332c9a37111d
first
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
duchonic | 0:332c9a37111d | 1 | /* |
duchonic | 0:332c9a37111d | 2 | * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT. |
duchonic | 0:332c9a37111d | 3 | * _Please_ see the comments in MFRC522.h - they give useful hints and background. |
duchonic | 0:332c9a37111d | 4 | * Released into the public domain. |
duchonic | 0:332c9a37111d | 5 | */ |
duchonic | 0:332c9a37111d | 6 | |
duchonic | 0:332c9a37111d | 7 | #include "MFRC522.h" |
duchonic | 0:332c9a37111d | 8 | |
duchonic | 0:332c9a37111d | 9 | static const char* const _TypeNamePICC[] = |
duchonic | 0:332c9a37111d | 10 | { |
duchonic | 0:332c9a37111d | 11 | "Unknown type", |
duchonic | 0:332c9a37111d | 12 | "PICC compliant with ISO/IEC 14443-4", |
duchonic | 0:332c9a37111d | 13 | "PICC compliant with ISO/IEC 18092 (NFC)", |
duchonic | 0:332c9a37111d | 14 | "MIFARE Mini, 320 bytes", |
duchonic | 0:332c9a37111d | 15 | "MIFARE 1KB", |
duchonic | 0:332c9a37111d | 16 | "MIFARE 4KB", |
duchonic | 0:332c9a37111d | 17 | "MIFARE Ultralight or Ultralight C", |
duchonic | 0:332c9a37111d | 18 | "MIFARE Plus", |
duchonic | 0:332c9a37111d | 19 | "MIFARE TNP3XXX", |
duchonic | 0:332c9a37111d | 20 | |
duchonic | 0:332c9a37111d | 21 | /* not complete UID */ |
duchonic | 0:332c9a37111d | 22 | "SAK indicates UID is not complete" |
duchonic | 0:332c9a37111d | 23 | }; |
duchonic | 0:332c9a37111d | 24 | |
duchonic | 0:332c9a37111d | 25 | static const char* const _ErrorMessage[] = |
duchonic | 0:332c9a37111d | 26 | { |
duchonic | 0:332c9a37111d | 27 | "Unknown error", |
duchonic | 0:332c9a37111d | 28 | "Success", |
duchonic | 0:332c9a37111d | 29 | "Error in communication", |
duchonic | 0:332c9a37111d | 30 | "Collision detected", |
duchonic | 0:332c9a37111d | 31 | "Timeout in communication", |
duchonic | 0:332c9a37111d | 32 | "A buffer is not big enough", |
duchonic | 0:332c9a37111d | 33 | "Internal error in the code, should not happen", |
duchonic | 0:332c9a37111d | 34 | "Invalid argument", |
duchonic | 0:332c9a37111d | 35 | "The CRC_A does not match", |
duchonic | 0:332c9a37111d | 36 | "A MIFARE PICC responded with NAK" |
duchonic | 0:332c9a37111d | 37 | }; |
duchonic | 0:332c9a37111d | 38 | |
duchonic | 0:332c9a37111d | 39 | #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0])) |
duchonic | 0:332c9a37111d | 40 | #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0])) |
duchonic | 0:332c9a37111d | 41 | |
duchonic | 0:332c9a37111d | 42 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 43 | // Functions for setting up the driver |
duchonic | 0:332c9a37111d | 44 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 45 | |
duchonic | 0:332c9a37111d | 46 | /** |
duchonic | 0:332c9a37111d | 47 | * Constructor. |
duchonic | 0:332c9a37111d | 48 | * Prepares the output pins. |
duchonic | 0:332c9a37111d | 49 | */ |
duchonic | 0:332c9a37111d | 50 | MFRC522::MFRC522(PinName mosi, |
duchonic | 0:332c9a37111d | 51 | PinName miso, |
duchonic | 0:332c9a37111d | 52 | PinName sclk, |
duchonic | 0:332c9a37111d | 53 | PinName cs, |
duchonic | 0:332c9a37111d | 54 | PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset) |
duchonic | 0:332c9a37111d | 55 | { |
duchonic | 0:332c9a37111d | 56 | /* Configure SPI bus */ |
duchonic | 0:332c9a37111d | 57 | m_SPI.format(8, 0); |
duchonic | 0:332c9a37111d | 58 | m_SPI.frequency(8000000); |
duchonic | 0:332c9a37111d | 59 | |
duchonic | 0:332c9a37111d | 60 | |
duchonic | 0:332c9a37111d | 61 | /* Release SPI-CS pin */ |
duchonic | 0:332c9a37111d | 62 | m_CS = 1; |
duchonic | 0:332c9a37111d | 63 | |
duchonic | 0:332c9a37111d | 64 | /* Release RESET pin */ |
duchonic | 0:332c9a37111d | 65 | m_RESET = 1; |
duchonic | 0:332c9a37111d | 66 | |
duchonic | 0:332c9a37111d | 67 | printf("rc522 Constructor\n"); |
duchonic | 0:332c9a37111d | 68 | } // End constructor |
duchonic | 0:332c9a37111d | 69 | |
duchonic | 0:332c9a37111d | 70 | |
duchonic | 0:332c9a37111d | 71 | /** |
duchonic | 0:332c9a37111d | 72 | * Destructor. |
duchonic | 0:332c9a37111d | 73 | */ |
duchonic | 0:332c9a37111d | 74 | MFRC522::~MFRC522() |
duchonic | 0:332c9a37111d | 75 | { |
duchonic | 0:332c9a37111d | 76 | printf("rc522 Destructor\n"); |
duchonic | 0:332c9a37111d | 77 | } |
duchonic | 0:332c9a37111d | 78 | |
duchonic | 0:332c9a37111d | 79 | |
duchonic | 0:332c9a37111d | 80 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 81 | // Basic interface functions for communicating with the MFRC522 |
duchonic | 0:332c9a37111d | 82 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 83 | |
duchonic | 0:332c9a37111d | 84 | /** |
duchonic | 0:332c9a37111d | 85 | * Writes a byte to the specified register in the MFRC522 chip. |
duchonic | 0:332c9a37111d | 86 | * The interface is described in the datasheet section 8.1.2. |
duchonic | 0:332c9a37111d | 87 | */ |
duchonic | 0:332c9a37111d | 88 | void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value) |
duchonic | 0:332c9a37111d | 89 | { |
duchonic | 0:332c9a37111d | 90 | m_CS = 0; /* Select SPI Chip MFRC522 */ |
duchonic | 0:332c9a37111d | 91 | |
duchonic | 0:332c9a37111d | 92 | // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3. |
duchonic | 0:332c9a37111d | 93 | (void) m_SPI.write(reg & 0x7E); |
duchonic | 0:332c9a37111d | 94 | (void) m_SPI.write(value); |
duchonic | 0:332c9a37111d | 95 | |
duchonic | 0:332c9a37111d | 96 | m_CS = 1; /* Release SPI Chip MFRC522 */ |
duchonic | 0:332c9a37111d | 97 | } // End PCD_WriteRegister() |
duchonic | 0:332c9a37111d | 98 | |
duchonic | 0:332c9a37111d | 99 | /** |
duchonic | 0:332c9a37111d | 100 | * Writes a number of bytes to the specified register in the MFRC522 chip. |
duchonic | 0:332c9a37111d | 101 | * The interface is described in the datasheet section 8.1.2. |
duchonic | 0:332c9a37111d | 102 | */ |
duchonic | 0:332c9a37111d | 103 | void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values) |
duchonic | 0:332c9a37111d | 104 | { |
duchonic | 0:332c9a37111d | 105 | m_CS = 0; /* Select SPI Chip MFRC522 */ |
duchonic | 0:332c9a37111d | 106 | |
duchonic | 0:332c9a37111d | 107 | // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3. |
duchonic | 0:332c9a37111d | 108 | (void) m_SPI.write(reg & 0x7E); |
duchonic | 0:332c9a37111d | 109 | for (uint8_t index = 0; index < count; index++) |
duchonic | 0:332c9a37111d | 110 | { |
duchonic | 0:332c9a37111d | 111 | (void) m_SPI.write(values[index]); |
duchonic | 0:332c9a37111d | 112 | } |
duchonic | 0:332c9a37111d | 113 | |
duchonic | 0:332c9a37111d | 114 | m_CS = 1; /* Release SPI Chip MFRC522 */ |
duchonic | 0:332c9a37111d | 115 | } // End PCD_WriteRegister() |
duchonic | 0:332c9a37111d | 116 | |
duchonic | 0:332c9a37111d | 117 | /** |
duchonic | 0:332c9a37111d | 118 | * Reads a byte from the specified register in the MFRC522 chip. |
duchonic | 0:332c9a37111d | 119 | * The interface is described in the datasheet section 8.1.2. |
duchonic | 0:332c9a37111d | 120 | */ |
duchonic | 0:332c9a37111d | 121 | uint8_t MFRC522::PCD_ReadRegister(uint8_t reg) |
duchonic | 0:332c9a37111d | 122 | { |
duchonic | 0:332c9a37111d | 123 | uint8_t value; |
duchonic | 0:332c9a37111d | 124 | m_CS = 0; /* Select SPI Chip MFRC522 */ |
duchonic | 0:332c9a37111d | 125 | |
duchonic | 0:332c9a37111d | 126 | // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3. |
duchonic | 0:332c9a37111d | 127 | (void) m_SPI.write(0x80 | reg); |
duchonic | 0:332c9a37111d | 128 | |
duchonic | 0:332c9a37111d | 129 | // Read the value back. Send 0 to stop reading. |
duchonic | 0:332c9a37111d | 130 | value = m_SPI.write(0); |
duchonic | 0:332c9a37111d | 131 | |
duchonic | 0:332c9a37111d | 132 | m_CS = 1; /* Release SPI Chip MFRC522 */ |
duchonic | 0:332c9a37111d | 133 | |
duchonic | 0:332c9a37111d | 134 | return value; |
duchonic | 0:332c9a37111d | 135 | } // End PCD_ReadRegister() |
duchonic | 0:332c9a37111d | 136 | |
duchonic | 0:332c9a37111d | 137 | /** |
duchonic | 0:332c9a37111d | 138 | * Reads a number of bytes from the specified register in the MFRC522 chip. |
duchonic | 0:332c9a37111d | 139 | * The interface is described in the datasheet section 8.1.2. |
duchonic | 0:332c9a37111d | 140 | */ |
duchonic | 0:332c9a37111d | 141 | void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign) |
duchonic | 0:332c9a37111d | 142 | { |
duchonic | 0:332c9a37111d | 143 | if (count == 0) { return; } |
duchonic | 0:332c9a37111d | 144 | |
duchonic | 0:332c9a37111d | 145 | uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3. |
duchonic | 0:332c9a37111d | 146 | uint8_t index = 0; // Index in values array. |
duchonic | 0:332c9a37111d | 147 | |
duchonic | 0:332c9a37111d | 148 | m_CS = 0; /* Select SPI Chip MFRC522 */ |
duchonic | 0:332c9a37111d | 149 | count--; // One read is performed outside of the loop |
duchonic | 0:332c9a37111d | 150 | (void) m_SPI.write(address); // Tell MFRC522 which address we want to read |
duchonic | 0:332c9a37111d | 151 | |
duchonic | 0:332c9a37111d | 152 | while (index < count) |
duchonic | 0:332c9a37111d | 153 | { |
duchonic | 0:332c9a37111d | 154 | if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0] |
duchonic | 0:332c9a37111d | 155 | { |
duchonic | 0:332c9a37111d | 156 | // Create bit mask for bit positions rxAlign..7 |
duchonic | 0:332c9a37111d | 157 | uint8_t mask = 0; |
duchonic | 0:332c9a37111d | 158 | for (uint8_t i = rxAlign; i <= 7; i++) |
duchonic | 0:332c9a37111d | 159 | { |
duchonic | 0:332c9a37111d | 160 | mask |= (1 << i); |
duchonic | 0:332c9a37111d | 161 | } |
duchonic | 0:332c9a37111d | 162 | |
duchonic | 0:332c9a37111d | 163 | // Read value and tell that we want to read the same address again. |
duchonic | 0:332c9a37111d | 164 | uint8_t value = m_SPI.write(address); |
duchonic | 0:332c9a37111d | 165 | |
duchonic | 0:332c9a37111d | 166 | // Apply mask to both current value of values[0] and the new data in value. |
duchonic | 0:332c9a37111d | 167 | values[0] = (values[index] & ~mask) | (value & mask); |
duchonic | 0:332c9a37111d | 168 | } |
duchonic | 0:332c9a37111d | 169 | else |
duchonic | 0:332c9a37111d | 170 | { |
duchonic | 0:332c9a37111d | 171 | // Read value and tell that we want to read the same address again. |
duchonic | 0:332c9a37111d | 172 | values[index] = m_SPI.write(address); |
duchonic | 0:332c9a37111d | 173 | } |
duchonic | 0:332c9a37111d | 174 | |
duchonic | 0:332c9a37111d | 175 | index++; |
duchonic | 0:332c9a37111d | 176 | } |
duchonic | 0:332c9a37111d | 177 | |
duchonic | 0:332c9a37111d | 178 | values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading. |
duchonic | 0:332c9a37111d | 179 | |
duchonic | 0:332c9a37111d | 180 | m_CS = 1; /* Release SPI Chip MFRC522 */ |
duchonic | 0:332c9a37111d | 181 | } // End PCD_ReadRegister() |
duchonic | 0:332c9a37111d | 182 | |
duchonic | 0:332c9a37111d | 183 | /** |
duchonic | 0:332c9a37111d | 184 | * Sets the bits given in mask in register reg. |
duchonic | 0:332c9a37111d | 185 | */ |
duchonic | 0:332c9a37111d | 186 | void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask) |
duchonic | 0:332c9a37111d | 187 | { |
duchonic | 0:332c9a37111d | 188 | uint8_t tmp = PCD_ReadRegister(reg); |
duchonic | 0:332c9a37111d | 189 | PCD_WriteRegister(reg, tmp | mask); // set bit mask |
duchonic | 0:332c9a37111d | 190 | } // End PCD_SetRegisterBitMask() |
duchonic | 0:332c9a37111d | 191 | |
duchonic | 0:332c9a37111d | 192 | /** |
duchonic | 0:332c9a37111d | 193 | * Clears the bits given in mask from register reg. |
duchonic | 0:332c9a37111d | 194 | */ |
duchonic | 0:332c9a37111d | 195 | void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask) |
duchonic | 0:332c9a37111d | 196 | { |
duchonic | 0:332c9a37111d | 197 | uint8_t tmp = PCD_ReadRegister(reg); |
duchonic | 0:332c9a37111d | 198 | PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask |
duchonic | 0:332c9a37111d | 199 | } // End PCD_ClearRegisterBitMask() |
duchonic | 0:332c9a37111d | 200 | |
duchonic | 0:332c9a37111d | 201 | |
duchonic | 0:332c9a37111d | 202 | /** |
duchonic | 0:332c9a37111d | 203 | * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A. |
duchonic | 0:332c9a37111d | 204 | */ |
duchonic | 0:332c9a37111d | 205 | uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result) |
duchonic | 0:332c9a37111d | 206 | { |
duchonic | 0:332c9a37111d | 207 | PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command. |
duchonic | 0:332c9a37111d | 208 | PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit |
duchonic | 0:332c9a37111d | 209 | PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization |
duchonic | 0:332c9a37111d | 210 | PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO |
duchonic | 0:332c9a37111d | 211 | PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation |
duchonic | 0:332c9a37111d | 212 | |
duchonic | 0:332c9a37111d | 213 | // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us. |
duchonic | 0:332c9a37111d | 214 | uint16_t i = 5000; |
duchonic | 0:332c9a37111d | 215 | uint8_t n; |
duchonic | 0:332c9a37111d | 216 | while (1) |
duchonic | 0:332c9a37111d | 217 | { |
duchonic | 0:332c9a37111d | 218 | n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved |
duchonic | 0:332c9a37111d | 219 | if (n & 0x04) |
duchonic | 0:332c9a37111d | 220 | { |
duchonic | 0:332c9a37111d | 221 | // CRCIRq bit set - calculation done |
duchonic | 0:332c9a37111d | 222 | break; |
duchonic | 0:332c9a37111d | 223 | } |
duchonic | 0:332c9a37111d | 224 | |
duchonic | 0:332c9a37111d | 225 | if (--i == 0) |
duchonic | 0:332c9a37111d | 226 | { |
duchonic | 0:332c9a37111d | 227 | // The emergency break. We will eventually terminate on this one after 89ms. |
duchonic | 0:332c9a37111d | 228 | // Communication with the MFRC522 might be down. |
duchonic | 0:332c9a37111d | 229 | return STATUS_TIMEOUT; |
duchonic | 0:332c9a37111d | 230 | } |
duchonic | 0:332c9a37111d | 231 | } |
duchonic | 0:332c9a37111d | 232 | |
duchonic | 0:332c9a37111d | 233 | // Stop calculating CRC for new content in the FIFO. |
duchonic | 0:332c9a37111d | 234 | PCD_WriteRegister(CommandReg, PCD_Idle); |
duchonic | 0:332c9a37111d | 235 | |
duchonic | 0:332c9a37111d | 236 | // Transfer the result from the registers to the result buffer |
duchonic | 0:332c9a37111d | 237 | result[0] = PCD_ReadRegister(CRCResultRegL); |
duchonic | 0:332c9a37111d | 238 | result[1] = PCD_ReadRegister(CRCResultRegH); |
duchonic | 0:332c9a37111d | 239 | return STATUS_OK; |
duchonic | 0:332c9a37111d | 240 | } // End PCD_CalculateCRC() |
duchonic | 0:332c9a37111d | 241 | |
duchonic | 0:332c9a37111d | 242 | |
duchonic | 0:332c9a37111d | 243 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 244 | // Functions for manipulating the MFRC522 |
duchonic | 0:332c9a37111d | 245 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 246 | void MFRC522::PCD_Reset_On() |
duchonic | 0:332c9a37111d | 247 | { |
duchonic | 0:332c9a37111d | 248 | m_RESET = 0; |
duchonic | 0:332c9a37111d | 249 | } |
duchonic | 0:332c9a37111d | 250 | |
duchonic | 0:332c9a37111d | 251 | void MFRC522::PCD_Reset_Off() |
duchonic | 0:332c9a37111d | 252 | { |
duchonic | 0:332c9a37111d | 253 | m_RESET = 1; |
duchonic | 0:332c9a37111d | 254 | } |
duchonic | 0:332c9a37111d | 255 | |
duchonic | 0:332c9a37111d | 256 | |
duchonic | 0:332c9a37111d | 257 | /** |
duchonic | 0:332c9a37111d | 258 | * Initializes the MFRC522 chip. |
duchonic | 0:332c9a37111d | 259 | */ |
duchonic | 0:332c9a37111d | 260 | void MFRC522::PCD_Init() |
duchonic | 0:332c9a37111d | 261 | { |
duchonic | 0:332c9a37111d | 262 | /* Reset MFRC522 */ |
duchonic | 0:332c9a37111d | 263 | m_RESET = 0; |
duchonic | 0:332c9a37111d | 264 | wait_ms(10); |
duchonic | 0:332c9a37111d | 265 | m_RESET = 1; |
duchonic | 0:332c9a37111d | 266 | |
duchonic | 0:332c9a37111d | 267 | printf("pcd_init()\n"); |
duchonic | 0:332c9a37111d | 268 | |
duchonic | 0:332c9a37111d | 269 | // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms. |
duchonic | 0:332c9a37111d | 270 | wait_ms(50); |
duchonic | 0:332c9a37111d | 271 | |
duchonic | 0:332c9a37111d | 272 | // When communicating with a PICC we need a timeout if something goes wrong. |
duchonic | 0:332c9a37111d | 273 | // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo]. |
duchonic | 0:332c9a37111d | 274 | // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg. |
duchonic | 0:332c9a37111d | 275 | PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds |
duchonic | 0:332c9a37111d | 276 | PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us. |
duchonic | 0:332c9a37111d | 277 | PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout. |
duchonic | 0:332c9a37111d | 278 | PCD_WriteRegister(TReloadRegL, 0xE8); |
duchonic | 0:332c9a37111d | 279 | |
duchonic | 0:332c9a37111d | 280 | PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting |
duchonic | 0:332c9a37111d | 281 | PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4) |
duchonic | 0:332c9a37111d | 282 | |
duchonic | 0:332c9a37111d | 283 | PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max |
duchonic | 0:332c9a37111d | 284 | |
duchonic | 0:332c9a37111d | 285 | PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset) |
duchonic | 0:332c9a37111d | 286 | |
duchonic | 0:332c9a37111d | 287 | } // End PCD_Init() |
duchonic | 0:332c9a37111d | 288 | |
duchonic | 0:332c9a37111d | 289 | /** |
duchonic | 0:332c9a37111d | 290 | * Performs a soft reset on the MFRC522 chip and waits for it to be ready again. |
duchonic | 0:332c9a37111d | 291 | */ |
duchonic | 0:332c9a37111d | 292 | void MFRC522::PCD_Reset() |
duchonic | 0:332c9a37111d | 293 | { |
duchonic | 0:332c9a37111d | 294 | PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command. |
duchonic | 0:332c9a37111d | 295 | // The datasheet does not mention how long the SoftRest command takes to complete. |
duchonic | 0:332c9a37111d | 296 | // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg) |
duchonic | 0:332c9a37111d | 297 | // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms. |
duchonic | 0:332c9a37111d | 298 | wait_ms(50); |
duchonic | 0:332c9a37111d | 299 | |
duchonic | 0:332c9a37111d | 300 | // Wait for the PowerDown bit in CommandReg to be cleared |
duchonic | 0:332c9a37111d | 301 | while (PCD_ReadRegister(CommandReg) & (1<<4)) |
duchonic | 0:332c9a37111d | 302 | { |
duchonic | 0:332c9a37111d | 303 | // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry. |
duchonic | 0:332c9a37111d | 304 | } |
duchonic | 0:332c9a37111d | 305 | } // End PCD_Reset() |
duchonic | 0:332c9a37111d | 306 | |
duchonic | 0:332c9a37111d | 307 | /** |
duchonic | 0:332c9a37111d | 308 | * Turns the antenna on by enabling pins TX1 and TX2. |
duchonic | 0:332c9a37111d | 309 | * After a reset these pins disabled. |
duchonic | 0:332c9a37111d | 310 | */ |
duchonic | 0:332c9a37111d | 311 | void MFRC522::PCD_AntennaOn() |
duchonic | 0:332c9a37111d | 312 | { |
duchonic | 0:332c9a37111d | 313 | uint8_t value = PCD_ReadRegister(TxControlReg); |
duchonic | 0:332c9a37111d | 314 | if ((value & 0x03) != 0x03) |
duchonic | 0:332c9a37111d | 315 | { |
duchonic | 0:332c9a37111d | 316 | PCD_WriteRegister(TxControlReg, value | 0x03); |
duchonic | 0:332c9a37111d | 317 | } |
duchonic | 0:332c9a37111d | 318 | } // End PCD_AntennaOn() |
duchonic | 0:332c9a37111d | 319 | |
duchonic | 0:332c9a37111d | 320 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 321 | // Functions for communicating with PICCs |
duchonic | 0:332c9a37111d | 322 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 323 | |
duchonic | 0:332c9a37111d | 324 | /** |
duchonic | 0:332c9a37111d | 325 | * Executes the Transceive command. |
duchonic | 0:332c9a37111d | 326 | * CRC validation can only be done if backData and backLen are specified. |
duchonic | 0:332c9a37111d | 327 | */ |
duchonic | 0:332c9a37111d | 328 | uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData, |
duchonic | 0:332c9a37111d | 329 | uint8_t sendLen, |
duchonic | 0:332c9a37111d | 330 | uint8_t *backData, |
duchonic | 0:332c9a37111d | 331 | uint8_t *backLen, |
duchonic | 0:332c9a37111d | 332 | uint8_t *validBits, |
duchonic | 0:332c9a37111d | 333 | uint8_t rxAlign, |
duchonic | 0:332c9a37111d | 334 | bool checkCRC) |
duchonic | 0:332c9a37111d | 335 | { |
duchonic | 0:332c9a37111d | 336 | uint8_t waitIRq = 0x30; // RxIRq and IdleIRq |
duchonic | 0:332c9a37111d | 337 | return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC); |
duchonic | 0:332c9a37111d | 338 | } // End PCD_TransceiveData() |
duchonic | 0:332c9a37111d | 339 | |
duchonic | 0:332c9a37111d | 340 | /** |
duchonic | 0:332c9a37111d | 341 | * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO. |
duchonic | 0:332c9a37111d | 342 | * CRC validation can only be done if backData and backLen are specified. |
duchonic | 0:332c9a37111d | 343 | */ |
duchonic | 0:332c9a37111d | 344 | uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command, |
duchonic | 0:332c9a37111d | 345 | uint8_t waitIRq, |
duchonic | 0:332c9a37111d | 346 | uint8_t *sendData, |
duchonic | 0:332c9a37111d | 347 | uint8_t sendLen, |
duchonic | 0:332c9a37111d | 348 | uint8_t *backData, |
duchonic | 0:332c9a37111d | 349 | uint8_t *backLen, |
duchonic | 0:332c9a37111d | 350 | uint8_t *validBits, |
duchonic | 0:332c9a37111d | 351 | uint8_t rxAlign, |
duchonic | 0:332c9a37111d | 352 | bool checkCRC) |
duchonic | 0:332c9a37111d | 353 | { |
duchonic | 0:332c9a37111d | 354 | uint8_t n, _validBits = 0; |
duchonic | 0:332c9a37111d | 355 | uint32_t i; |
duchonic | 0:332c9a37111d | 356 | |
duchonic | 0:332c9a37111d | 357 | // Prepare values for BitFramingReg |
duchonic | 0:332c9a37111d | 358 | uint8_t txLastBits = validBits ? *validBits : 0; |
duchonic | 0:332c9a37111d | 359 | uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0] |
duchonic | 0:332c9a37111d | 360 | |
duchonic | 0:332c9a37111d | 361 | PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command. |
duchonic | 0:332c9a37111d | 362 | PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits |
duchonic | 0:332c9a37111d | 363 | PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization |
duchonic | 0:332c9a37111d | 364 | PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO |
duchonic | 0:332c9a37111d | 365 | PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments |
duchonic | 0:332c9a37111d | 366 | PCD_WriteRegister(CommandReg, command); // Execute the command |
duchonic | 0:332c9a37111d | 367 | if (command == PCD_Transceive) |
duchonic | 0:332c9a37111d | 368 | { |
duchonic | 0:332c9a37111d | 369 | PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts |
duchonic | 0:332c9a37111d | 370 | } |
duchonic | 0:332c9a37111d | 371 | |
duchonic | 0:332c9a37111d | 372 | // Wait for the command to complete. |
duchonic | 0:332c9a37111d | 373 | // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting. |
duchonic | 0:332c9a37111d | 374 | // Each iteration of the do-while-loop takes 17.86us. |
duchonic | 0:332c9a37111d | 375 | i = 2000; |
duchonic | 0:332c9a37111d | 376 | while (1) |
duchonic | 0:332c9a37111d | 377 | { |
duchonic | 0:332c9a37111d | 378 | n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq |
duchonic | 0:332c9a37111d | 379 | if (n & waitIRq) |
duchonic | 0:332c9a37111d | 380 | { // One of the interrupts that signal success has been set. |
duchonic | 0:332c9a37111d | 381 | break; |
duchonic | 0:332c9a37111d | 382 | } |
duchonic | 0:332c9a37111d | 383 | |
duchonic | 0:332c9a37111d | 384 | if (n & 0x01) |
duchonic | 0:332c9a37111d | 385 | { // Timer interrupt - nothing received in 25ms |
duchonic | 0:332c9a37111d | 386 | return STATUS_TIMEOUT; |
duchonic | 0:332c9a37111d | 387 | } |
duchonic | 0:332c9a37111d | 388 | |
duchonic | 0:332c9a37111d | 389 | if (--i == 0) |
duchonic | 0:332c9a37111d | 390 | { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down. |
duchonic | 0:332c9a37111d | 391 | return STATUS_TIMEOUT; |
duchonic | 0:332c9a37111d | 392 | } |
duchonic | 0:332c9a37111d | 393 | } |
duchonic | 0:332c9a37111d | 394 | |
duchonic | 0:332c9a37111d | 395 | // Stop now if any errors except collisions were detected. |
duchonic | 0:332c9a37111d | 396 | uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr |
duchonic | 0:332c9a37111d | 397 | if (errorRegValue & 0x13) |
duchonic | 0:332c9a37111d | 398 | { // BufferOvfl ParityErr ProtocolErr |
duchonic | 0:332c9a37111d | 399 | return STATUS_ERROR; |
duchonic | 0:332c9a37111d | 400 | } |
duchonic | 0:332c9a37111d | 401 | |
duchonic | 0:332c9a37111d | 402 | // If the caller wants data back, get it from the MFRC522. |
duchonic | 0:332c9a37111d | 403 | if (backData && backLen) |
duchonic | 0:332c9a37111d | 404 | { |
duchonic | 0:332c9a37111d | 405 | n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO |
duchonic | 0:332c9a37111d | 406 | if (n > *backLen) |
duchonic | 0:332c9a37111d | 407 | { |
duchonic | 0:332c9a37111d | 408 | return STATUS_NO_ROOM; |
duchonic | 0:332c9a37111d | 409 | } |
duchonic | 0:332c9a37111d | 410 | |
duchonic | 0:332c9a37111d | 411 | *backLen = n; // Number of bytes returned |
duchonic | 0:332c9a37111d | 412 | PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO |
duchonic | 0:332c9a37111d | 413 | _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid. |
duchonic | 0:332c9a37111d | 414 | if (validBits) |
duchonic | 0:332c9a37111d | 415 | { |
duchonic | 0:332c9a37111d | 416 | *validBits = _validBits; |
duchonic | 0:332c9a37111d | 417 | } |
duchonic | 0:332c9a37111d | 418 | } |
duchonic | 0:332c9a37111d | 419 | |
duchonic | 0:332c9a37111d | 420 | // Tell about collisions |
duchonic | 0:332c9a37111d | 421 | if (errorRegValue & 0x08) |
duchonic | 0:332c9a37111d | 422 | { // CollErr |
duchonic | 0:332c9a37111d | 423 | return STATUS_COLLISION; |
duchonic | 0:332c9a37111d | 424 | } |
duchonic | 0:332c9a37111d | 425 | |
duchonic | 0:332c9a37111d | 426 | // Perform CRC_A validation if requested. |
duchonic | 0:332c9a37111d | 427 | if (backData && backLen && checkCRC) |
duchonic | 0:332c9a37111d | 428 | { |
duchonic | 0:332c9a37111d | 429 | // In this case a MIFARE Classic NAK is not OK. |
duchonic | 0:332c9a37111d | 430 | if ((*backLen == 1) && (_validBits == 4)) |
duchonic | 0:332c9a37111d | 431 | { |
duchonic | 0:332c9a37111d | 432 | return STATUS_MIFARE_NACK; |
duchonic | 0:332c9a37111d | 433 | } |
duchonic | 0:332c9a37111d | 434 | |
duchonic | 0:332c9a37111d | 435 | // We need at least the CRC_A value and all 8 bits of the last byte must be received. |
duchonic | 0:332c9a37111d | 436 | if ((*backLen < 2) || (_validBits != 0)) |
duchonic | 0:332c9a37111d | 437 | { |
duchonic | 0:332c9a37111d | 438 | return STATUS_CRC_WRONG; |
duchonic | 0:332c9a37111d | 439 | } |
duchonic | 0:332c9a37111d | 440 | |
duchonic | 0:332c9a37111d | 441 | // Verify CRC_A - do our own calculation and store the control in controlBuffer. |
duchonic | 0:332c9a37111d | 442 | uint8_t controlBuffer[2]; |
duchonic | 0:332c9a37111d | 443 | n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]); |
duchonic | 0:332c9a37111d | 444 | if (n != STATUS_OK) |
duchonic | 0:332c9a37111d | 445 | { |
duchonic | 0:332c9a37111d | 446 | return n; |
duchonic | 0:332c9a37111d | 447 | } |
duchonic | 0:332c9a37111d | 448 | |
duchonic | 0:332c9a37111d | 449 | if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1])) |
duchonic | 0:332c9a37111d | 450 | { |
duchonic | 0:332c9a37111d | 451 | return STATUS_CRC_WRONG; |
duchonic | 0:332c9a37111d | 452 | } |
duchonic | 0:332c9a37111d | 453 | } |
duchonic | 0:332c9a37111d | 454 | |
duchonic | 0:332c9a37111d | 455 | return STATUS_OK; |
duchonic | 0:332c9a37111d | 456 | } // End PCD_CommunicateWithPICC() |
duchonic | 0:332c9a37111d | 457 | |
duchonic | 0:332c9a37111d | 458 | /* |
duchonic | 0:332c9a37111d | 459 | * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame. |
duchonic | 0:332c9a37111d | 460 | * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design. |
duchonic | 0:332c9a37111d | 461 | */ |
duchonic | 0:332c9a37111d | 462 | uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize) |
duchonic | 0:332c9a37111d | 463 | { |
duchonic | 0:332c9a37111d | 464 | return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize); |
duchonic | 0:332c9a37111d | 465 | } // End PICC_RequestA() |
duchonic | 0:332c9a37111d | 466 | |
duchonic | 0:332c9a37111d | 467 | /** |
duchonic | 0:332c9a37111d | 468 | * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame. |
duchonic | 0:332c9a37111d | 469 | * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design. |
duchonic | 0:332c9a37111d | 470 | */ |
duchonic | 0:332c9a37111d | 471 | uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize) |
duchonic | 0:332c9a37111d | 472 | { |
duchonic | 0:332c9a37111d | 473 | return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize); |
duchonic | 0:332c9a37111d | 474 | } // End PICC_WakeupA() |
duchonic | 0:332c9a37111d | 475 | |
duchonic | 0:332c9a37111d | 476 | /* |
duchonic | 0:332c9a37111d | 477 | * Transmits REQA or WUPA commands. |
duchonic | 0:332c9a37111d | 478 | * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design. |
duchonic | 0:332c9a37111d | 479 | */ |
duchonic | 0:332c9a37111d | 480 | uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize) |
duchonic | 0:332c9a37111d | 481 | { |
duchonic | 0:332c9a37111d | 482 | uint8_t validBits; |
duchonic | 0:332c9a37111d | 483 | uint8_t status; |
duchonic | 0:332c9a37111d | 484 | |
duchonic | 0:332c9a37111d | 485 | if (bufferATQA == NULL || *bufferSize < 2) |
duchonic | 0:332c9a37111d | 486 | { // The ATQA response is 2 bytes long. |
duchonic | 0:332c9a37111d | 487 | return STATUS_NO_ROOM; |
duchonic | 0:332c9a37111d | 488 | } |
duchonic | 0:332c9a37111d | 489 | |
duchonic | 0:332c9a37111d | 490 | // ValuesAfterColl=1 => Bits received after collision are cleared. |
duchonic | 0:332c9a37111d | 491 | PCD_ClrRegisterBits(CollReg, 0x80); |
duchonic | 0:332c9a37111d | 492 | |
duchonic | 0:332c9a37111d | 493 | // For REQA and WUPA we need the short frame format |
duchonic | 0:332c9a37111d | 494 | // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0] |
duchonic | 0:332c9a37111d | 495 | validBits = 7; |
duchonic | 0:332c9a37111d | 496 | |
duchonic | 0:332c9a37111d | 497 | status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits); |
duchonic | 0:332c9a37111d | 498 | if (status != STATUS_OK) |
duchonic | 0:332c9a37111d | 499 | { |
duchonic | 0:332c9a37111d | 500 | return status; |
duchonic | 0:332c9a37111d | 501 | } |
duchonic | 0:332c9a37111d | 502 | |
duchonic | 0:332c9a37111d | 503 | if ((*bufferSize != 2) || (validBits != 0)) |
duchonic | 0:332c9a37111d | 504 | { // ATQA must be exactly 16 bits. |
duchonic | 0:332c9a37111d | 505 | return STATUS_ERROR; |
duchonic | 0:332c9a37111d | 506 | } |
duchonic | 0:332c9a37111d | 507 | |
duchonic | 0:332c9a37111d | 508 | return STATUS_OK; |
duchonic | 0:332c9a37111d | 509 | } // End PICC_REQA_or_WUPA() |
duchonic | 0:332c9a37111d | 510 | |
duchonic | 0:332c9a37111d | 511 | /* |
duchonic | 0:332c9a37111d | 512 | * Transmits SELECT/ANTICOLLISION commands to select a single PICC. |
duchonic | 0:332c9a37111d | 513 | */ |
duchonic | 0:332c9a37111d | 514 | uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits) |
duchonic | 0:332c9a37111d | 515 | { |
duchonic | 0:332c9a37111d | 516 | bool uidComplete; |
duchonic | 0:332c9a37111d | 517 | bool selectDone; |
duchonic | 0:332c9a37111d | 518 | bool useCascadeTag; |
duchonic | 0:332c9a37111d | 519 | uint8_t cascadeLevel = 1; |
duchonic | 0:332c9a37111d | 520 | uint8_t result; |
duchonic | 0:332c9a37111d | 521 | uint8_t count; |
duchonic | 0:332c9a37111d | 522 | uint8_t index; |
duchonic | 0:332c9a37111d | 523 | uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level. |
duchonic | 0:332c9a37111d | 524 | uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level. |
duchonic | 0:332c9a37111d | 525 | uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A |
duchonic | 0:332c9a37111d | 526 | uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO. |
duchonic | 0:332c9a37111d | 527 | uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received. |
duchonic | 0:332c9a37111d | 528 | uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte. |
duchonic | 0:332c9a37111d | 529 | uint8_t *responseBuffer; |
duchonic | 0:332c9a37111d | 530 | uint8_t responseLength; |
duchonic | 0:332c9a37111d | 531 | |
duchonic | 0:332c9a37111d | 532 | // Description of buffer structure: |
duchonic | 0:332c9a37111d | 533 | // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3 |
duchonic | 0:332c9a37111d | 534 | // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits. |
duchonic | 0:332c9a37111d | 535 | // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag. |
duchonic | 0:332c9a37111d | 536 | // Byte 3: UID-data |
duchonic | 0:332c9a37111d | 537 | // Byte 4: UID-data |
duchonic | 0:332c9a37111d | 538 | // Byte 5: UID-data |
duchonic | 0:332c9a37111d | 539 | // Byte 6: BCC Block Check Character - XOR of bytes 2-5 |
duchonic | 0:332c9a37111d | 540 | // Byte 7: CRC_A |
duchonic | 0:332c9a37111d | 541 | // Byte 8: CRC_A |
duchonic | 0:332c9a37111d | 542 | // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level. |
duchonic | 0:332c9a37111d | 543 | // |
duchonic | 0:332c9a37111d | 544 | // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels) |
duchonic | 0:332c9a37111d | 545 | // UID size Cascade level Byte2 Byte3 Byte4 Byte5 |
duchonic | 0:332c9a37111d | 546 | // ======== ============= ===== ===== ===== ===== |
duchonic | 0:332c9a37111d | 547 | // 4 bytes 1 uid0 uid1 uid2 uid3 |
duchonic | 0:332c9a37111d | 548 | // 7 bytes 1 CT uid0 uid1 uid2 |
duchonic | 0:332c9a37111d | 549 | // 2 uid3 uid4 uid5 uid6 |
duchonic | 0:332c9a37111d | 550 | // 10 bytes 1 CT uid0 uid1 uid2 |
duchonic | 0:332c9a37111d | 551 | // 2 CT uid3 uid4 uid5 |
duchonic | 0:332c9a37111d | 552 | // 3 uid6 uid7 uid8 uid9 |
duchonic | 0:332c9a37111d | 553 | |
duchonic | 0:332c9a37111d | 554 | // Sanity checks |
duchonic | 0:332c9a37111d | 555 | if (validBits > 80) |
duchonic | 0:332c9a37111d | 556 | { |
duchonic | 0:332c9a37111d | 557 | return STATUS_INVALID; |
duchonic | 0:332c9a37111d | 558 | } |
duchonic | 0:332c9a37111d | 559 | |
duchonic | 0:332c9a37111d | 560 | // Prepare MFRC522 |
duchonic | 0:332c9a37111d | 561 | // ValuesAfterColl=1 => Bits received after collision are cleared. |
duchonic | 0:332c9a37111d | 562 | PCD_ClrRegisterBits(CollReg, 0x80); |
duchonic | 0:332c9a37111d | 563 | |
duchonic | 0:332c9a37111d | 564 | // Repeat Cascade Level loop until we have a complete UID. |
duchonic | 0:332c9a37111d | 565 | uidComplete = false; |
duchonic | 0:332c9a37111d | 566 | while ( ! uidComplete) |
duchonic | 0:332c9a37111d | 567 | { |
duchonic | 0:332c9a37111d | 568 | // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2. |
duchonic | 0:332c9a37111d | 569 | switch (cascadeLevel) |
duchonic | 0:332c9a37111d | 570 | { |
duchonic | 0:332c9a37111d | 571 | case 1: |
duchonic | 0:332c9a37111d | 572 | buffer[0] = PICC_CMD_SEL_CL1; |
duchonic | 0:332c9a37111d | 573 | uidIndex = 0; |
duchonic | 0:332c9a37111d | 574 | useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes |
duchonic | 0:332c9a37111d | 575 | break; |
duchonic | 0:332c9a37111d | 576 | |
duchonic | 0:332c9a37111d | 577 | case 2: |
duchonic | 0:332c9a37111d | 578 | buffer[0] = PICC_CMD_SEL_CL2; |
duchonic | 0:332c9a37111d | 579 | uidIndex = 3; |
duchonic | 0:332c9a37111d | 580 | useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes |
duchonic | 0:332c9a37111d | 581 | break; |
duchonic | 0:332c9a37111d | 582 | |
duchonic | 0:332c9a37111d | 583 | case 3: |
duchonic | 0:332c9a37111d | 584 | buffer[0] = PICC_CMD_SEL_CL3; |
duchonic | 0:332c9a37111d | 585 | uidIndex = 6; |
duchonic | 0:332c9a37111d | 586 | useCascadeTag = false; // Never used in CL3. |
duchonic | 0:332c9a37111d | 587 | break; |
duchonic | 0:332c9a37111d | 588 | |
duchonic | 0:332c9a37111d | 589 | default: |
duchonic | 0:332c9a37111d | 590 | return STATUS_INTERNAL_ERROR; |
duchonic | 0:332c9a37111d | 591 | //break; |
duchonic | 0:332c9a37111d | 592 | } |
duchonic | 0:332c9a37111d | 593 | |
duchonic | 0:332c9a37111d | 594 | // How many UID bits are known in this Cascade Level? |
duchonic | 0:332c9a37111d | 595 | if(validBits > (8 * uidIndex)) |
duchonic | 0:332c9a37111d | 596 | { |
duchonic | 0:332c9a37111d | 597 | currentLevelKnownBits = validBits - (8 * uidIndex); |
duchonic | 0:332c9a37111d | 598 | } |
duchonic | 0:332c9a37111d | 599 | else |
duchonic | 0:332c9a37111d | 600 | { |
duchonic | 0:332c9a37111d | 601 | currentLevelKnownBits = 0; |
duchonic | 0:332c9a37111d | 602 | } |
duchonic | 0:332c9a37111d | 603 | |
duchonic | 0:332c9a37111d | 604 | // Copy the known bits from uid->uidByte[] to buffer[] |
duchonic | 0:332c9a37111d | 605 | index = 2; // destination index in buffer[] |
duchonic | 0:332c9a37111d | 606 | if (useCascadeTag) |
duchonic | 0:332c9a37111d | 607 | { |
duchonic | 0:332c9a37111d | 608 | buffer[index++] = PICC_CMD_CT; |
duchonic | 0:332c9a37111d | 609 | } |
duchonic | 0:332c9a37111d | 610 | |
duchonic | 0:332c9a37111d | 611 | uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level. |
duchonic | 0:332c9a37111d | 612 | if (bytesToCopy) |
duchonic | 0:332c9a37111d | 613 | { |
duchonic | 0:332c9a37111d | 614 | // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag |
duchonic | 0:332c9a37111d | 615 | uint8_t maxBytes = useCascadeTag ? 3 : 4; |
duchonic | 0:332c9a37111d | 616 | if (bytesToCopy > maxBytes) |
duchonic | 0:332c9a37111d | 617 | { |
duchonic | 0:332c9a37111d | 618 | bytesToCopy = maxBytes; |
duchonic | 0:332c9a37111d | 619 | } |
duchonic | 0:332c9a37111d | 620 | |
duchonic | 0:332c9a37111d | 621 | for (count = 0; count < bytesToCopy; count++) |
duchonic | 0:332c9a37111d | 622 | { |
duchonic | 0:332c9a37111d | 623 | buffer[index++] = uid->uidByte[uidIndex + count]; |
duchonic | 0:332c9a37111d | 624 | } |
duchonic | 0:332c9a37111d | 625 | } |
duchonic | 0:332c9a37111d | 626 | |
duchonic | 0:332c9a37111d | 627 | // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits |
duchonic | 0:332c9a37111d | 628 | if (useCascadeTag) |
duchonic | 0:332c9a37111d | 629 | { |
duchonic | 0:332c9a37111d | 630 | currentLevelKnownBits += 8; |
duchonic | 0:332c9a37111d | 631 | } |
duchonic | 0:332c9a37111d | 632 | |
duchonic | 0:332c9a37111d | 633 | // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations. |
duchonic | 0:332c9a37111d | 634 | selectDone = false; |
duchonic | 0:332c9a37111d | 635 | while ( ! selectDone) |
duchonic | 0:332c9a37111d | 636 | { |
duchonic | 0:332c9a37111d | 637 | // Find out how many bits and bytes to send and receive. |
duchonic | 0:332c9a37111d | 638 | if (currentLevelKnownBits >= 32) |
duchonic | 0:332c9a37111d | 639 | { // All UID bits in this Cascade Level are known. This is a SELECT. |
duchonic | 0:332c9a37111d | 640 | //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC); |
duchonic | 0:332c9a37111d | 641 | buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes |
duchonic | 0:332c9a37111d | 642 | |
duchonic | 0:332c9a37111d | 643 | // Calulate BCC - Block Check Character |
duchonic | 0:332c9a37111d | 644 | buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5]; |
duchonic | 0:332c9a37111d | 645 | |
duchonic | 0:332c9a37111d | 646 | // Calculate CRC_A |
duchonic | 0:332c9a37111d | 647 | result = PCD_CalculateCRC(buffer, 7, &buffer[7]); |
duchonic | 0:332c9a37111d | 648 | if (result != STATUS_OK) |
duchonic | 0:332c9a37111d | 649 | { |
duchonic | 0:332c9a37111d | 650 | return result; |
duchonic | 0:332c9a37111d | 651 | } |
duchonic | 0:332c9a37111d | 652 | |
duchonic | 0:332c9a37111d | 653 | txLastBits = 0; // 0 => All 8 bits are valid. |
duchonic | 0:332c9a37111d | 654 | bufferUsed = 9; |
duchonic | 0:332c9a37111d | 655 | |
duchonic | 0:332c9a37111d | 656 | // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx) |
duchonic | 0:332c9a37111d | 657 | responseBuffer = &buffer[6]; |
duchonic | 0:332c9a37111d | 658 | responseLength = 3; |
duchonic | 0:332c9a37111d | 659 | } |
duchonic | 0:332c9a37111d | 660 | else |
duchonic | 0:332c9a37111d | 661 | { // This is an ANTICOLLISION. |
duchonic | 0:332c9a37111d | 662 | //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC); |
duchonic | 0:332c9a37111d | 663 | txLastBits = currentLevelKnownBits % 8; |
duchonic | 0:332c9a37111d | 664 | count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part. |
duchonic | 0:332c9a37111d | 665 | index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs |
duchonic | 0:332c9a37111d | 666 | buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits |
duchonic | 0:332c9a37111d | 667 | bufferUsed = index + (txLastBits ? 1 : 0); |
duchonic | 0:332c9a37111d | 668 | |
duchonic | 0:332c9a37111d | 669 | // Store response in the unused part of buffer |
duchonic | 0:332c9a37111d | 670 | responseBuffer = &buffer[index]; |
duchonic | 0:332c9a37111d | 671 | responseLength = sizeof(buffer) - index; |
duchonic | 0:332c9a37111d | 672 | } |
duchonic | 0:332c9a37111d | 673 | |
duchonic | 0:332c9a37111d | 674 | // Set bit adjustments |
duchonic | 0:332c9a37111d | 675 | rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read. |
duchonic | 0:332c9a37111d | 676 | PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0] |
duchonic | 0:332c9a37111d | 677 | |
duchonic | 0:332c9a37111d | 678 | // Transmit the buffer and receive the response. |
duchonic | 0:332c9a37111d | 679 | result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign); |
duchonic | 0:332c9a37111d | 680 | if (result == STATUS_COLLISION) |
duchonic | 0:332c9a37111d | 681 | { // More than one PICC in the field => collision. |
duchonic | 0:332c9a37111d | 682 | result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0] |
duchonic | 0:332c9a37111d | 683 | if (result & 0x20) |
duchonic | 0:332c9a37111d | 684 | { // CollPosNotValid |
duchonic | 0:332c9a37111d | 685 | return STATUS_COLLISION; // Without a valid collision position we cannot continue |
duchonic | 0:332c9a37111d | 686 | } |
duchonic | 0:332c9a37111d | 687 | |
duchonic | 0:332c9a37111d | 688 | uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32. |
duchonic | 0:332c9a37111d | 689 | if (collisionPos == 0) |
duchonic | 0:332c9a37111d | 690 | { |
duchonic | 0:332c9a37111d | 691 | collisionPos = 32; |
duchonic | 0:332c9a37111d | 692 | } |
duchonic | 0:332c9a37111d | 693 | |
duchonic | 0:332c9a37111d | 694 | if (collisionPos <= currentLevelKnownBits) |
duchonic | 0:332c9a37111d | 695 | { // No progress - should not happen |
duchonic | 0:332c9a37111d | 696 | return STATUS_INTERNAL_ERROR; |
duchonic | 0:332c9a37111d | 697 | } |
duchonic | 0:332c9a37111d | 698 | |
duchonic | 0:332c9a37111d | 699 | // Choose the PICC with the bit set. |
duchonic | 0:332c9a37111d | 700 | currentLevelKnownBits = collisionPos; |
duchonic | 0:332c9a37111d | 701 | count = (currentLevelKnownBits - 1) % 8; // The bit to modify |
duchonic | 0:332c9a37111d | 702 | index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0. |
duchonic | 0:332c9a37111d | 703 | buffer[index] |= (1 << count); |
duchonic | 0:332c9a37111d | 704 | } |
duchonic | 0:332c9a37111d | 705 | else if (result != STATUS_OK) |
duchonic | 0:332c9a37111d | 706 | { |
duchonic | 0:332c9a37111d | 707 | return result; |
duchonic | 0:332c9a37111d | 708 | } |
duchonic | 0:332c9a37111d | 709 | else |
duchonic | 0:332c9a37111d | 710 | { // STATUS_OK |
duchonic | 0:332c9a37111d | 711 | if (currentLevelKnownBits >= 32) |
duchonic | 0:332c9a37111d | 712 | { // This was a SELECT. |
duchonic | 0:332c9a37111d | 713 | selectDone = true; // No more anticollision |
duchonic | 0:332c9a37111d | 714 | // We continue below outside the while. |
duchonic | 0:332c9a37111d | 715 | } |
duchonic | 0:332c9a37111d | 716 | else |
duchonic | 0:332c9a37111d | 717 | { // This was an ANTICOLLISION. |
duchonic | 0:332c9a37111d | 718 | // We now have all 32 bits of the UID in this Cascade Level |
duchonic | 0:332c9a37111d | 719 | currentLevelKnownBits = 32; |
duchonic | 0:332c9a37111d | 720 | // Run loop again to do the SELECT. |
duchonic | 0:332c9a37111d | 721 | } |
duchonic | 0:332c9a37111d | 722 | } |
duchonic | 0:332c9a37111d | 723 | } // End of while ( ! selectDone) |
duchonic | 0:332c9a37111d | 724 | |
duchonic | 0:332c9a37111d | 725 | // We do not check the CBB - it was constructed by us above. |
duchonic | 0:332c9a37111d | 726 | |
duchonic | 0:332c9a37111d | 727 | // Copy the found UID bytes from buffer[] to uid->uidByte[] |
duchonic | 0:332c9a37111d | 728 | index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[] |
duchonic | 0:332c9a37111d | 729 | bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4; |
duchonic | 0:332c9a37111d | 730 | for (count = 0; count < bytesToCopy; count++) |
duchonic | 0:332c9a37111d | 731 | { |
duchonic | 0:332c9a37111d | 732 | uid->uidByte[uidIndex + count] = buffer[index++]; |
duchonic | 0:332c9a37111d | 733 | } |
duchonic | 0:332c9a37111d | 734 | |
duchonic | 0:332c9a37111d | 735 | // Check response SAK (Select Acknowledge) |
duchonic | 0:332c9a37111d | 736 | if (responseLength != 3 || txLastBits != 0) |
duchonic | 0:332c9a37111d | 737 | { // SAK must be exactly 24 bits (1 byte + CRC_A). |
duchonic | 0:332c9a37111d | 738 | return STATUS_ERROR; |
duchonic | 0:332c9a37111d | 739 | } |
duchonic | 0:332c9a37111d | 740 | |
duchonic | 0:332c9a37111d | 741 | // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore. |
duchonic | 0:332c9a37111d | 742 | result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]); |
duchonic | 0:332c9a37111d | 743 | if (result != STATUS_OK) |
duchonic | 0:332c9a37111d | 744 | { |
duchonic | 0:332c9a37111d | 745 | return result; |
duchonic | 0:332c9a37111d | 746 | } |
duchonic | 0:332c9a37111d | 747 | |
duchonic | 0:332c9a37111d | 748 | if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2])) |
duchonic | 0:332c9a37111d | 749 | { |
duchonic | 0:332c9a37111d | 750 | return STATUS_CRC_WRONG; |
duchonic | 0:332c9a37111d | 751 | } |
duchonic | 0:332c9a37111d | 752 | |
duchonic | 0:332c9a37111d | 753 | if (responseBuffer[0] & 0x04) |
duchonic | 0:332c9a37111d | 754 | { // Cascade bit set - UID not complete yes |
duchonic | 0:332c9a37111d | 755 | cascadeLevel++; |
duchonic | 0:332c9a37111d | 756 | } |
duchonic | 0:332c9a37111d | 757 | else |
duchonic | 0:332c9a37111d | 758 | { |
duchonic | 0:332c9a37111d | 759 | uidComplete = true; |
duchonic | 0:332c9a37111d | 760 | uid->sak = responseBuffer[0]; |
duchonic | 0:332c9a37111d | 761 | } |
duchonic | 0:332c9a37111d | 762 | } // End of while ( ! uidComplete) |
duchonic | 0:332c9a37111d | 763 | |
duchonic | 0:332c9a37111d | 764 | // Set correct uid->size |
duchonic | 0:332c9a37111d | 765 | uid->size = 3 * cascadeLevel + 1; |
duchonic | 0:332c9a37111d | 766 | |
duchonic | 0:332c9a37111d | 767 | return STATUS_OK; |
duchonic | 0:332c9a37111d | 768 | } // End PICC_Select() |
duchonic | 0:332c9a37111d | 769 | |
duchonic | 0:332c9a37111d | 770 | /* |
duchonic | 0:332c9a37111d | 771 | * Instructs a PICC in state ACTIVE(*) to go to state HALT. |
duchonic | 0:332c9a37111d | 772 | */ |
duchonic | 0:332c9a37111d | 773 | uint8_t MFRC522::PICC_HaltA() |
duchonic | 0:332c9a37111d | 774 | { |
duchonic | 0:332c9a37111d | 775 | uint8_t result; |
duchonic | 0:332c9a37111d | 776 | uint8_t buffer[4]; |
duchonic | 0:332c9a37111d | 777 | |
duchonic | 0:332c9a37111d | 778 | // Build command buffer |
duchonic | 0:332c9a37111d | 779 | buffer[0] = PICC_CMD_HLTA; |
duchonic | 0:332c9a37111d | 780 | buffer[1] = 0; |
duchonic | 0:332c9a37111d | 781 | |
duchonic | 0:332c9a37111d | 782 | // Calculate CRC_A |
duchonic | 0:332c9a37111d | 783 | result = PCD_CalculateCRC(buffer, 2, &buffer[2]); |
duchonic | 0:332c9a37111d | 784 | if (result == STATUS_OK) |
duchonic | 0:332c9a37111d | 785 | { |
duchonic | 0:332c9a37111d | 786 | // Send the command. |
duchonic | 0:332c9a37111d | 787 | // The standard says: |
duchonic | 0:332c9a37111d | 788 | // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the |
duchonic | 0:332c9a37111d | 789 | // HLTA command, this response shall be interpreted as 'not acknowledge'. |
duchonic | 0:332c9a37111d | 790 | // We interpret that this way: Only STATUS_TIMEOUT is an success. |
duchonic | 0:332c9a37111d | 791 | result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0); |
duchonic | 0:332c9a37111d | 792 | if (result == STATUS_TIMEOUT) |
duchonic | 0:332c9a37111d | 793 | { |
duchonic | 0:332c9a37111d | 794 | result = STATUS_OK; |
duchonic | 0:332c9a37111d | 795 | } |
duchonic | 0:332c9a37111d | 796 | else if (result == STATUS_OK) |
duchonic | 0:332c9a37111d | 797 | { // That is ironically NOT ok in this case ;-) |
duchonic | 0:332c9a37111d | 798 | result = STATUS_ERROR; |
duchonic | 0:332c9a37111d | 799 | } |
duchonic | 0:332c9a37111d | 800 | } |
duchonic | 0:332c9a37111d | 801 | |
duchonic | 0:332c9a37111d | 802 | return result; |
duchonic | 0:332c9a37111d | 803 | } // End PICC_HaltA() |
duchonic | 0:332c9a37111d | 804 | |
duchonic | 0:332c9a37111d | 805 | |
duchonic | 0:332c9a37111d | 806 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 807 | // Functions for communicating with MIFARE PICCs |
duchonic | 0:332c9a37111d | 808 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 809 | |
duchonic | 0:332c9a37111d | 810 | /* |
duchonic | 0:332c9a37111d | 811 | * Executes the MFRC522 MFAuthent command. |
duchonic | 0:332c9a37111d | 812 | */ |
duchonic | 0:332c9a37111d | 813 | uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid) |
duchonic | 0:332c9a37111d | 814 | { |
duchonic | 0:332c9a37111d | 815 | uint8_t i, waitIRq = 0x10; // IdleIRq |
duchonic | 0:332c9a37111d | 816 | |
duchonic | 0:332c9a37111d | 817 | // Build command buffer |
duchonic | 0:332c9a37111d | 818 | uint8_t sendData[12]; |
duchonic | 0:332c9a37111d | 819 | sendData[0] = command; |
duchonic | 0:332c9a37111d | 820 | sendData[1] = blockAddr; |
duchonic | 0:332c9a37111d | 821 | |
duchonic | 0:332c9a37111d | 822 | for (i = 0; i < MF_KEY_SIZE; i++) |
duchonic | 0:332c9a37111d | 823 | { // 6 key bytes |
duchonic | 0:332c9a37111d | 824 | sendData[2+i] = key->keyByte[i]; |
duchonic | 0:332c9a37111d | 825 | } |
duchonic | 0:332c9a37111d | 826 | |
duchonic | 0:332c9a37111d | 827 | for (i = 0; i < 4; i++) |
duchonic | 0:332c9a37111d | 828 | { // The first 4 bytes of the UID |
duchonic | 0:332c9a37111d | 829 | sendData[8+i] = uid->uidByte[i]; |
duchonic | 0:332c9a37111d | 830 | } |
duchonic | 0:332c9a37111d | 831 | |
duchonic | 0:332c9a37111d | 832 | // Start the authentication. |
duchonic | 0:332c9a37111d | 833 | return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData)); |
duchonic | 0:332c9a37111d | 834 | } // End PCD_Authenticate() |
duchonic | 0:332c9a37111d | 835 | |
duchonic | 0:332c9a37111d | 836 | /* |
duchonic | 0:332c9a37111d | 837 | * Used to exit the PCD from its authenticated state. |
duchonic | 0:332c9a37111d | 838 | * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start. |
duchonic | 0:332c9a37111d | 839 | */ |
duchonic | 0:332c9a37111d | 840 | void MFRC522::PCD_StopCrypto1() |
duchonic | 0:332c9a37111d | 841 | { |
duchonic | 0:332c9a37111d | 842 | // Clear MFCrypto1On bit |
duchonic | 0:332c9a37111d | 843 | PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0] |
duchonic | 0:332c9a37111d | 844 | } // End PCD_StopCrypto1() |
duchonic | 0:332c9a37111d | 845 | |
duchonic | 0:332c9a37111d | 846 | /* |
duchonic | 0:332c9a37111d | 847 | * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC. |
duchonic | 0:332c9a37111d | 848 | */ |
duchonic | 0:332c9a37111d | 849 | uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize) |
duchonic | 0:332c9a37111d | 850 | { |
duchonic | 0:332c9a37111d | 851 | uint8_t result = STATUS_NO_ROOM; |
duchonic | 0:332c9a37111d | 852 | |
duchonic | 0:332c9a37111d | 853 | // Sanity check |
duchonic | 0:332c9a37111d | 854 | if ((buffer == NULL) || (*bufferSize < 18)) |
duchonic | 0:332c9a37111d | 855 | { |
duchonic | 0:332c9a37111d | 856 | return result; |
duchonic | 0:332c9a37111d | 857 | } |
duchonic | 0:332c9a37111d | 858 | |
duchonic | 0:332c9a37111d | 859 | // Build command buffer |
duchonic | 0:332c9a37111d | 860 | buffer[0] = PICC_CMD_MF_READ; |
duchonic | 0:332c9a37111d | 861 | buffer[1] = blockAddr; |
duchonic | 0:332c9a37111d | 862 | |
duchonic | 0:332c9a37111d | 863 | // Calculate CRC_A |
duchonic | 0:332c9a37111d | 864 | result = PCD_CalculateCRC(buffer, 2, &buffer[2]); |
duchonic | 0:332c9a37111d | 865 | if (result != STATUS_OK) |
duchonic | 0:332c9a37111d | 866 | { |
duchonic | 0:332c9a37111d | 867 | return result; |
duchonic | 0:332c9a37111d | 868 | } |
duchonic | 0:332c9a37111d | 869 | |
duchonic | 0:332c9a37111d | 870 | // Transmit the buffer and receive the response, validate CRC_A. |
duchonic | 0:332c9a37111d | 871 | return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true); |
duchonic | 0:332c9a37111d | 872 | } // End MIFARE_Read() |
duchonic | 0:332c9a37111d | 873 | |
duchonic | 0:332c9a37111d | 874 | /* |
duchonic | 0:332c9a37111d | 875 | * Writes 16 bytes to the active PICC. |
duchonic | 0:332c9a37111d | 876 | */ |
duchonic | 0:332c9a37111d | 877 | uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize) |
duchonic | 0:332c9a37111d | 878 | { |
duchonic | 0:332c9a37111d | 879 | uint8_t result; |
duchonic | 0:332c9a37111d | 880 | |
duchonic | 0:332c9a37111d | 881 | // Sanity check |
duchonic | 0:332c9a37111d | 882 | if (buffer == NULL || bufferSize < 16) |
duchonic | 0:332c9a37111d | 883 | { |
duchonic | 0:332c9a37111d | 884 | return STATUS_INVALID; |
duchonic | 0:332c9a37111d | 885 | } |
duchonic | 0:332c9a37111d | 886 | |
duchonic | 0:332c9a37111d | 887 | // Mifare Classic protocol requires two communications to perform a write. |
duchonic | 0:332c9a37111d | 888 | // Step 1: Tell the PICC we want to write to block blockAddr. |
duchonic | 0:332c9a37111d | 889 | uint8_t cmdBuffer[2]; |
duchonic | 0:332c9a37111d | 890 | cmdBuffer[0] = PICC_CMD_MF_WRITE; |
duchonic | 0:332c9a37111d | 891 | cmdBuffer[1] = blockAddr; |
duchonic | 0:332c9a37111d | 892 | // Adds CRC_A and checks that the response is MF_ACK. |
duchonic | 0:332c9a37111d | 893 | result = PCD_MIFARE_Transceive(cmdBuffer, 2); |
duchonic | 0:332c9a37111d | 894 | if (result != STATUS_OK) |
duchonic | 0:332c9a37111d | 895 | { |
duchonic | 0:332c9a37111d | 896 | return result; |
duchonic | 0:332c9a37111d | 897 | } |
duchonic | 0:332c9a37111d | 898 | |
duchonic | 0:332c9a37111d | 899 | // Step 2: Transfer the data |
duchonic | 0:332c9a37111d | 900 | // Adds CRC_A and checks that the response is MF_ACK. |
duchonic | 0:332c9a37111d | 901 | result = PCD_MIFARE_Transceive(buffer, bufferSize); |
duchonic | 0:332c9a37111d | 902 | if (result != STATUS_OK) |
duchonic | 0:332c9a37111d | 903 | { |
duchonic | 0:332c9a37111d | 904 | return result; |
duchonic | 0:332c9a37111d | 905 | } |
duchonic | 0:332c9a37111d | 906 | |
duchonic | 0:332c9a37111d | 907 | return STATUS_OK; |
duchonic | 0:332c9a37111d | 908 | } // End MIFARE_Write() |
duchonic | 0:332c9a37111d | 909 | |
duchonic | 0:332c9a37111d | 910 | /* |
duchonic | 0:332c9a37111d | 911 | * Writes a 4 byte page to the active MIFARE Ultralight PICC. |
duchonic | 0:332c9a37111d | 912 | */ |
duchonic | 0:332c9a37111d | 913 | uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize) |
duchonic | 0:332c9a37111d | 914 | { |
duchonic | 0:332c9a37111d | 915 | uint8_t result; |
duchonic | 0:332c9a37111d | 916 | |
duchonic | 0:332c9a37111d | 917 | // Sanity check |
duchonic | 0:332c9a37111d | 918 | if (buffer == NULL || bufferSize < 4) |
duchonic | 0:332c9a37111d | 919 | { |
duchonic | 0:332c9a37111d | 920 | return STATUS_INVALID; |
duchonic | 0:332c9a37111d | 921 | } |
duchonic | 0:332c9a37111d | 922 | |
duchonic | 0:332c9a37111d | 923 | // Build commmand buffer |
duchonic | 0:332c9a37111d | 924 | uint8_t cmdBuffer[6]; |
duchonic | 0:332c9a37111d | 925 | cmdBuffer[0] = PICC_CMD_UL_WRITE; |
duchonic | 0:332c9a37111d | 926 | cmdBuffer[1] = page; |
duchonic | 0:332c9a37111d | 927 | memcpy(&cmdBuffer[2], buffer, 4); |
duchonic | 0:332c9a37111d | 928 | |
duchonic | 0:332c9a37111d | 929 | // Perform the write |
duchonic | 0:332c9a37111d | 930 | result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK. |
duchonic | 0:332c9a37111d | 931 | if (result != STATUS_OK) |
duchonic | 0:332c9a37111d | 932 | { |
duchonic | 0:332c9a37111d | 933 | return result; |
duchonic | 0:332c9a37111d | 934 | } |
duchonic | 0:332c9a37111d | 935 | |
duchonic | 0:332c9a37111d | 936 | return STATUS_OK; |
duchonic | 0:332c9a37111d | 937 | } // End MIFARE_Ultralight_Write() |
duchonic | 0:332c9a37111d | 938 | |
duchonic | 0:332c9a37111d | 939 | /* |
duchonic | 0:332c9a37111d | 940 | * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory. |
duchonic | 0:332c9a37111d | 941 | */ |
duchonic | 0:332c9a37111d | 942 | uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta) |
duchonic | 0:332c9a37111d | 943 | { |
duchonic | 0:332c9a37111d | 944 | return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta); |
duchonic | 0:332c9a37111d | 945 | } // End MIFARE_Decrement() |
duchonic | 0:332c9a37111d | 946 | |
duchonic | 0:332c9a37111d | 947 | /* |
duchonic | 0:332c9a37111d | 948 | * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory. |
duchonic | 0:332c9a37111d | 949 | */ |
duchonic | 0:332c9a37111d | 950 | uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta) |
duchonic | 0:332c9a37111d | 951 | { |
duchonic | 0:332c9a37111d | 952 | return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta); |
duchonic | 0:332c9a37111d | 953 | } // End MIFARE_Increment() |
duchonic | 0:332c9a37111d | 954 | |
duchonic | 0:332c9a37111d | 955 | /** |
duchonic | 0:332c9a37111d | 956 | * MIFARE Restore copies the value of the addressed block into a volatile memory. |
duchonic | 0:332c9a37111d | 957 | */ |
duchonic | 0:332c9a37111d | 958 | uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr) |
duchonic | 0:332c9a37111d | 959 | { |
duchonic | 0:332c9a37111d | 960 | // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2. |
duchonic | 0:332c9a37111d | 961 | // Doing only a single step does not work, so I chose to transfer 0L in step two. |
duchonic | 0:332c9a37111d | 962 | return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L); |
duchonic | 0:332c9a37111d | 963 | } // End MIFARE_Restore() |
duchonic | 0:332c9a37111d | 964 | |
duchonic | 0:332c9a37111d | 965 | /* |
duchonic | 0:332c9a37111d | 966 | * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore. |
duchonic | 0:332c9a37111d | 967 | */ |
duchonic | 0:332c9a37111d | 968 | uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data) |
duchonic | 0:332c9a37111d | 969 | { |
duchonic | 0:332c9a37111d | 970 | uint8_t result; |
duchonic | 0:332c9a37111d | 971 | uint8_t cmdBuffer[2]; // We only need room for 2 bytes. |
duchonic | 0:332c9a37111d | 972 | |
duchonic | 0:332c9a37111d | 973 | // Step 1: Tell the PICC the command and block address |
duchonic | 0:332c9a37111d | 974 | cmdBuffer[0] = command; |
duchonic | 0:332c9a37111d | 975 | cmdBuffer[1] = blockAddr; |
duchonic | 0:332c9a37111d | 976 | |
duchonic | 0:332c9a37111d | 977 | // Adds CRC_A and checks that the response is MF_ACK. |
duchonic | 0:332c9a37111d | 978 | result = PCD_MIFARE_Transceive(cmdBuffer, 2); |
duchonic | 0:332c9a37111d | 979 | if (result != STATUS_OK) |
duchonic | 0:332c9a37111d | 980 | { |
duchonic | 0:332c9a37111d | 981 | return result; |
duchonic | 0:332c9a37111d | 982 | } |
duchonic | 0:332c9a37111d | 983 | |
duchonic | 0:332c9a37111d | 984 | // Step 2: Transfer the data |
duchonic | 0:332c9a37111d | 985 | // Adds CRC_A and accept timeout as success. |
duchonic | 0:332c9a37111d | 986 | result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true); |
duchonic | 0:332c9a37111d | 987 | if (result != STATUS_OK) |
duchonic | 0:332c9a37111d | 988 | { |
duchonic | 0:332c9a37111d | 989 | return result; |
duchonic | 0:332c9a37111d | 990 | } |
duchonic | 0:332c9a37111d | 991 | |
duchonic | 0:332c9a37111d | 992 | return STATUS_OK; |
duchonic | 0:332c9a37111d | 993 | } // End MIFARE_TwoStepHelper() |
duchonic | 0:332c9a37111d | 994 | |
duchonic | 0:332c9a37111d | 995 | /* |
duchonic | 0:332c9a37111d | 996 | * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block. |
duchonic | 0:332c9a37111d | 997 | */ |
duchonic | 0:332c9a37111d | 998 | uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr) |
duchonic | 0:332c9a37111d | 999 | { |
duchonic | 0:332c9a37111d | 1000 | uint8_t cmdBuffer[2]; // We only need room for 2 bytes. |
duchonic | 0:332c9a37111d | 1001 | |
duchonic | 0:332c9a37111d | 1002 | // Tell the PICC we want to transfer the result into block blockAddr. |
duchonic | 0:332c9a37111d | 1003 | cmdBuffer[0] = PICC_CMD_MF_TRANSFER; |
duchonic | 0:332c9a37111d | 1004 | cmdBuffer[1] = blockAddr; |
duchonic | 0:332c9a37111d | 1005 | |
duchonic | 0:332c9a37111d | 1006 | // Adds CRC_A and checks that the response is MF_ACK. |
duchonic | 0:332c9a37111d | 1007 | return PCD_MIFARE_Transceive(cmdBuffer, 2); |
duchonic | 0:332c9a37111d | 1008 | } // End MIFARE_Transfer() |
duchonic | 0:332c9a37111d | 1009 | |
duchonic | 0:332c9a37111d | 1010 | |
duchonic | 0:332c9a37111d | 1011 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 1012 | // Support functions |
duchonic | 0:332c9a37111d | 1013 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 1014 | |
duchonic | 0:332c9a37111d | 1015 | /* |
duchonic | 0:332c9a37111d | 1016 | * Wrapper for MIFARE protocol communication. |
duchonic | 0:332c9a37111d | 1017 | * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout. |
duchonic | 0:332c9a37111d | 1018 | */ |
duchonic | 0:332c9a37111d | 1019 | uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout) |
duchonic | 0:332c9a37111d | 1020 | { |
duchonic | 0:332c9a37111d | 1021 | uint8_t result; |
duchonic | 0:332c9a37111d | 1022 | uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A. |
duchonic | 0:332c9a37111d | 1023 | |
duchonic | 0:332c9a37111d | 1024 | // Sanity check |
duchonic | 0:332c9a37111d | 1025 | if (sendData == NULL || sendLen > 16) |
duchonic | 0:332c9a37111d | 1026 | { |
duchonic | 0:332c9a37111d | 1027 | return STATUS_INVALID; |
duchonic | 0:332c9a37111d | 1028 | } |
duchonic | 0:332c9a37111d | 1029 | |
duchonic | 0:332c9a37111d | 1030 | // Copy sendData[] to cmdBuffer[] and add CRC_A |
duchonic | 0:332c9a37111d | 1031 | memcpy(cmdBuffer, sendData, sendLen); |
duchonic | 0:332c9a37111d | 1032 | result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]); |
duchonic | 0:332c9a37111d | 1033 | if (result != STATUS_OK) |
duchonic | 0:332c9a37111d | 1034 | { |
duchonic | 0:332c9a37111d | 1035 | return result; |
duchonic | 0:332c9a37111d | 1036 | } |
duchonic | 0:332c9a37111d | 1037 | |
duchonic | 0:332c9a37111d | 1038 | sendLen += 2; |
duchonic | 0:332c9a37111d | 1039 | |
duchonic | 0:332c9a37111d | 1040 | // Transceive the data, store the reply in cmdBuffer[] |
duchonic | 0:332c9a37111d | 1041 | uint8_t waitIRq = 0x30; // RxIRq and IdleIRq |
duchonic | 0:332c9a37111d | 1042 | uint8_t cmdBufferSize = sizeof(cmdBuffer); |
duchonic | 0:332c9a37111d | 1043 | uint8_t validBits = 0; |
duchonic | 0:332c9a37111d | 1044 | result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits); |
duchonic | 0:332c9a37111d | 1045 | if (acceptTimeout && result == STATUS_TIMEOUT) |
duchonic | 0:332c9a37111d | 1046 | { |
duchonic | 0:332c9a37111d | 1047 | return STATUS_OK; |
duchonic | 0:332c9a37111d | 1048 | } |
duchonic | 0:332c9a37111d | 1049 | |
duchonic | 0:332c9a37111d | 1050 | if (result != STATUS_OK) |
duchonic | 0:332c9a37111d | 1051 | { |
duchonic | 0:332c9a37111d | 1052 | return result; |
duchonic | 0:332c9a37111d | 1053 | } |
duchonic | 0:332c9a37111d | 1054 | |
duchonic | 0:332c9a37111d | 1055 | // The PICC must reply with a 4 bit ACK |
duchonic | 0:332c9a37111d | 1056 | if (cmdBufferSize != 1 || validBits != 4) |
duchonic | 0:332c9a37111d | 1057 | { |
duchonic | 0:332c9a37111d | 1058 | return STATUS_ERROR; |
duchonic | 0:332c9a37111d | 1059 | } |
duchonic | 0:332c9a37111d | 1060 | |
duchonic | 0:332c9a37111d | 1061 | if (cmdBuffer[0] != MF_ACK) |
duchonic | 0:332c9a37111d | 1062 | { |
duchonic | 0:332c9a37111d | 1063 | return STATUS_MIFARE_NACK; |
duchonic | 0:332c9a37111d | 1064 | } |
duchonic | 0:332c9a37111d | 1065 | |
duchonic | 0:332c9a37111d | 1066 | return STATUS_OK; |
duchonic | 0:332c9a37111d | 1067 | } // End PCD_MIFARE_Transceive() |
duchonic | 0:332c9a37111d | 1068 | |
duchonic | 0:332c9a37111d | 1069 | |
duchonic | 0:332c9a37111d | 1070 | /* |
duchonic | 0:332c9a37111d | 1071 | * Translates the SAK (Select Acknowledge) to a PICC type. |
duchonic | 0:332c9a37111d | 1072 | */ |
duchonic | 0:332c9a37111d | 1073 | uint8_t MFRC522::PICC_GetType(uint8_t sak) |
duchonic | 0:332c9a37111d | 1074 | { |
duchonic | 0:332c9a37111d | 1075 | uint8_t retType = PICC_TYPE_UNKNOWN; |
duchonic | 0:332c9a37111d | 1076 | |
duchonic | 0:332c9a37111d | 1077 | if (sak & 0x04) |
duchonic | 0:332c9a37111d | 1078 | { // UID not complete |
duchonic | 0:332c9a37111d | 1079 | retType = PICC_TYPE_NOT_COMPLETE; |
duchonic | 0:332c9a37111d | 1080 | } |
duchonic | 0:332c9a37111d | 1081 | else |
duchonic | 0:332c9a37111d | 1082 | { |
duchonic | 0:332c9a37111d | 1083 | switch (sak) |
duchonic | 0:332c9a37111d | 1084 | { |
duchonic | 0:332c9a37111d | 1085 | case 0x09: retType = PICC_TYPE_MIFARE_MINI; break; |
duchonic | 0:332c9a37111d | 1086 | case 0x08: retType = PICC_TYPE_MIFARE_1K; break; |
duchonic | 0:332c9a37111d | 1087 | case 0x18: retType = PICC_TYPE_MIFARE_4K; break; |
duchonic | 0:332c9a37111d | 1088 | case 0x00: retType = PICC_TYPE_MIFARE_UL; break; |
duchonic | 0:332c9a37111d | 1089 | case 0x10: |
duchonic | 0:332c9a37111d | 1090 | case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break; |
duchonic | 0:332c9a37111d | 1091 | case 0x01: retType = PICC_TYPE_TNP3XXX; break; |
duchonic | 0:332c9a37111d | 1092 | default: |
duchonic | 0:332c9a37111d | 1093 | if (sak & 0x20) |
duchonic | 0:332c9a37111d | 1094 | { |
duchonic | 0:332c9a37111d | 1095 | retType = PICC_TYPE_ISO_14443_4; |
duchonic | 0:332c9a37111d | 1096 | } |
duchonic | 0:332c9a37111d | 1097 | else if (sak & 0x40) |
duchonic | 0:332c9a37111d | 1098 | { |
duchonic | 0:332c9a37111d | 1099 | retType = PICC_TYPE_ISO_18092; |
duchonic | 0:332c9a37111d | 1100 | } |
duchonic | 0:332c9a37111d | 1101 | break; |
duchonic | 0:332c9a37111d | 1102 | } |
duchonic | 0:332c9a37111d | 1103 | } |
duchonic | 0:332c9a37111d | 1104 | |
duchonic | 0:332c9a37111d | 1105 | return (retType); |
duchonic | 0:332c9a37111d | 1106 | } // End PICC_GetType() |
duchonic | 0:332c9a37111d | 1107 | |
duchonic | 0:332c9a37111d | 1108 | /* |
duchonic | 0:332c9a37111d | 1109 | * Returns a string pointer to the PICC type name. |
duchonic | 0:332c9a37111d | 1110 | */ |
duchonic | 0:332c9a37111d | 1111 | char* MFRC522::PICC_GetTypeName(uint8_t piccType) |
duchonic | 0:332c9a37111d | 1112 | { |
duchonic | 0:332c9a37111d | 1113 | if(piccType == PICC_TYPE_NOT_COMPLETE) |
duchonic | 0:332c9a37111d | 1114 | { |
duchonic | 0:332c9a37111d | 1115 | piccType = MFRC522_MaxPICCs - 1; |
duchonic | 0:332c9a37111d | 1116 | } |
duchonic | 0:332c9a37111d | 1117 | |
duchonic | 0:332c9a37111d | 1118 | return((char *) _TypeNamePICC[piccType]); |
duchonic | 0:332c9a37111d | 1119 | } // End PICC_GetTypeName() |
duchonic | 0:332c9a37111d | 1120 | |
duchonic | 0:332c9a37111d | 1121 | /* |
duchonic | 0:332c9a37111d | 1122 | * Returns a string pointer to a status code name. |
duchonic | 0:332c9a37111d | 1123 | */ |
duchonic | 0:332c9a37111d | 1124 | char* MFRC522::GetStatusCodeName(uint8_t code) |
duchonic | 0:332c9a37111d | 1125 | { |
duchonic | 0:332c9a37111d | 1126 | return((char *) _ErrorMessage[code]); |
duchonic | 0:332c9a37111d | 1127 | } // End GetStatusCodeName() |
duchonic | 0:332c9a37111d | 1128 | |
duchonic | 0:332c9a37111d | 1129 | /* |
duchonic | 0:332c9a37111d | 1130 | * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1). |
duchonic | 0:332c9a37111d | 1131 | */ |
duchonic | 0:332c9a37111d | 1132 | void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer, |
duchonic | 0:332c9a37111d | 1133 | uint8_t g0, |
duchonic | 0:332c9a37111d | 1134 | uint8_t g1, |
duchonic | 0:332c9a37111d | 1135 | uint8_t g2, |
duchonic | 0:332c9a37111d | 1136 | uint8_t g3) |
duchonic | 0:332c9a37111d | 1137 | { |
duchonic | 0:332c9a37111d | 1138 | uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2); |
duchonic | 0:332c9a37111d | 1139 | uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1); |
duchonic | 0:332c9a37111d | 1140 | uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0); |
duchonic | 0:332c9a37111d | 1141 | |
duchonic | 0:332c9a37111d | 1142 | accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF); |
duchonic | 0:332c9a37111d | 1143 | accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF); |
duchonic | 0:332c9a37111d | 1144 | accessBitBuffer[2] = c3 << 4 | c2; |
duchonic | 0:332c9a37111d | 1145 | } // End MIFARE_SetAccessBits() |
duchonic | 0:332c9a37111d | 1146 | |
duchonic | 0:332c9a37111d | 1147 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 1148 | // Convenience functions - does not add extra functionality |
duchonic | 0:332c9a37111d | 1149 | ///////////////////////////////////////////////////////////////////////////////////// |
duchonic | 0:332c9a37111d | 1150 | |
duchonic | 0:332c9a37111d | 1151 | /* |
duchonic | 0:332c9a37111d | 1152 | * Returns true if a PICC responds to PICC_CMD_REQA. |
duchonic | 0:332c9a37111d | 1153 | * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored. |
duchonic | 0:332c9a37111d | 1154 | */ |
duchonic | 0:332c9a37111d | 1155 | bool MFRC522::PICC_IsNewCardPresent(void) |
duchonic | 0:332c9a37111d | 1156 | { |
duchonic | 0:332c9a37111d | 1157 | uint8_t bufferATQA[2]; |
duchonic | 0:332c9a37111d | 1158 | uint8_t bufferSize = sizeof(bufferATQA); |
duchonic | 0:332c9a37111d | 1159 | uint8_t result = PICC_RequestA(bufferATQA, &bufferSize); |
duchonic | 0:332c9a37111d | 1160 | return ((result == STATUS_OK) || (result == STATUS_COLLISION)); |
duchonic | 0:332c9a37111d | 1161 | } // End PICC_IsNewCardPresent() |
duchonic | 0:332c9a37111d | 1162 | |
duchonic | 0:332c9a37111d | 1163 | /* |
duchonic | 0:332c9a37111d | 1164 | * Simple wrapper around PICC_Select. |
duchonic | 0:332c9a37111d | 1165 | */ |
duchonic | 0:332c9a37111d | 1166 | bool MFRC522::PICC_ReadCardSerial(void) |
duchonic | 0:332c9a37111d | 1167 | { |
duchonic | 0:332c9a37111d | 1168 | uint8_t result = PICC_Select(&uid); |
duchonic | 0:332c9a37111d | 1169 | return (result == STATUS_OK); |
duchonic | 0:332c9a37111d | 1170 | } // End PICC_ReadCardSerial() |