David Mort / SSEL_spi

CLASS for automated serial 'chip select' implimentation utilizing mbed LPC1768 Timer2 hardware and it's inturrupt features.

SSEL_spi.cpp@0:9fa30f3069ae, 2014-03-22 (annotated)

Committer:
dtmort
Date:
Sat Mar 22 18:57:17 2014 +0000
Revision:
0:9fa30f3069ae
Initial commit 2014.03.22

Who changed what in which revision?

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dtmort 0:9fa30f3069ae 1 /* Class SSEL_spi, Copyright 2014, David T. Mort (http://mbed.org/users/dtmort/)
dtmort 0:9fa30f3069ae 2
dtmort 0:9fa30f3069ae 3 Licensed under the Apache License, Version 2.0 (the "License");
dtmort 0:9fa30f3069ae 4 you may not use this file except in compliance with the License.
dtmort 0:9fa30f3069ae 5 You may obtain a copy of the License at
dtmort 0:9fa30f3069ae 6
dtmort 0:9fa30f3069ae 7 http://www.apache.org/licenses/LICENSE-2.0
dtmort 0:9fa30f3069ae 8
dtmort 0:9fa30f3069ae 9 Unless required by applicable law or agreed to in writing, software
dtmort 0:9fa30f3069ae 10 distributed under the License is distributed on an "AS IS" BASIS,
dtmort 0:9fa30f3069ae 11 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
dtmort 0:9fa30f3069ae 12 See the License for the specific language governing permissions and
dtmort 0:9fa30f3069ae 13 limitations under the License.
dtmort 0:9fa30f3069ae 14 */
dtmort 0:9fa30f3069ae 15 #include "SSEL_spi.h"
dtmort 0:9fa30f3069ae 16 #include "mbed.h"
dtmort 0:9fa30f3069ae 17
dtmort 0:9fa30f3069ae 18 SSEL_spi::SSEL_spi(uint32_t frame, int mode){
dtmort 0:9fa30f3069ae 19 //hardwire SPI sclk to p30 so Counter2 can trigger p8 SSEL from serial clock counts
dtmort 0:9fa30f3069ae 20 //Setup Timer/Counter2 ********************************************************************************
dtmort 0:9fa30f3069ae 21 LPC_SC->PCONP |= 0x00400000; //Timer/COUNTER2 turn power on bit 22, Table 46
dtmort 0:9fa30f3069ae 22 LPC_PINCON->PINSEL0 |= 0x00003300; //Timer/COUNTER2: (9:8)CAP2.0 on p30, (13:12)MAT2.0 on p8(SSEL), Table 79
dtmort 0:9fa30f3069ae 23 switch (mode){
dtmort 0:9fa30f3069ae 24 case 1:
dtmort 0:9fa30f3069ae 25 case 2:
dtmort 0:9fa30f3069ae 26 LPC_TIM2->CTCR= 2; //increment on falling edge of CAP2.0 input, Table 428
dtmort 0:9fa30f3069ae 27 break;
dtmort 0:9fa30f3069ae 28 case 0:
dtmort 0:9fa30f3069ae 29 case 3:
dtmort 0:9fa30f3069ae 30 LPC_TIM2->CTCR= 1; //increment on rising edge of CAP2.0 input, Table 428
dtmort 0:9fa30f3069ae 31 }
dtmort 0:9fa30f3069ae 32 LPC_TIM2->MCR = 3; //reset TC on match to MR0 (bit 1) & interrupt (bit 0), Table 429
dtmort 0:9fa30f3069ae 33 LPC_TIM2->EMR = 48; //set bits 5:4 for toggle function, clear bit 0 MAT2.0(SSEL), Table 431/432
dtmort 0:9fa30f3069ae 34
dtmort 0:9fa30f3069ae 35 NVIC_EnableIRQ(TIMER2_IRQn); //this method enables timer2 interrupt at run time
dtmort 0:9fa30f3069ae 36
dtmort 0:9fa30f3069ae 37 LPC_TIM2->TCR = 3UL; //1:0 reset TC/PC & enable counter, clear bit 1 to begin counting, Table 427
dtmort 0:9fa30f3069ae 38 LPC_TIM2->MR0 = frame; //clock bit counter load, see 21.6.7
dtmort 0:9fa30f3069ae 39 LPC_TIM2->TCR &= ~2UL; //clear bit 1 to enable counting
dtmort 0:9fa30f3069ae 40 }
dtmort 0:9fa30f3069ae 41
dtmort 0:9fa30f3069ae 42 void SSEL_spi::active(bool cs){
dtmort 0:9fa30f3069ae 43 LPC_TIM2->EMR = 48+cs; //set or clear bit 0 of MAT2.0(SSEL) pin 8 output, Table 431/432
dtmort 0:9fa30f3069ae 44 }
dtmort 0:9fa30f3069ae 45
dtmort 0:9fa30f3069ae 46 // ISR routine ****************************************************************************************
dtmort 0:9fa30f3069ae 47 extern "C" void TIMER2_IRQHandler (void){
dtmort 0:9fa30f3069ae 48 if((LPC_TIM2->IR & 0x01)==0x01){ //if MR0 interrupt, proceed, Table 426
dtmort 0:9fa30f3069ae 49 LPC_TIM2->IR = 1UL; //clear MR0 interrupt flag by writing 1, writing 0 has no effect
dtmort 0:9fa30f3069ae 50 LPC_TIM2->EMR ^= 1UL; //toggle bit:0 to reset SSEL back to active state, Table 431
dtmort 0:9fa30f3069ae 51 }
dtmort 0:9fa30f3069ae 52 }