Mo El-Sharkawy / Mbed 2 deprecated 00_mcr20_wireless_uart

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Dependencies:   fsl_phy_mcr20a fsl_smac mbed-rtos mbed

Fork of mcr20_wireless_uart by samuel belete

RF_Drivers_Freescale/driverRFPhy.c@8:e4c9f2b7a9d2, 2015-03-05 (annotated)

Committer:
sam_grove
Date:
Thu Mar 05 20:40:54 2015 +0000
Revision:
8:e4c9f2b7a9d2
Parent:
RF_Drivers_FSL/driverRFPhy.c@5:69f1634cd40b
Child:
9:904334e768eb
rename directories;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FSL\B36402 5:69f1634cd40b 1 /*
FSL\B36402 5:69f1634cd40b 2 * driverRFPhy.c
FSL\B36402 5:69f1634cd40b 3 *
FSL\B36402 5:69f1634cd40b 4 * Created on: 14 July 2014
FSL\B36402 5:69f1634cd40b 5 * Author: mBed team
FSL\B36402 5:69f1634cd40b 6 */
FSL\B36402 5:69f1634cd40b 7 #include "arm_hal_interrupt.h"
FSL\B36402 5:69f1634cd40b 8 #include "arm_hal_phy.h"
FSL\B36402 5:69f1634cd40b 9 #include "driverRFPhy.h"
FSL\B36402 5:69f1634cd40b 10 #include "driverAtmelRFInterface.h"
FSL\B36402 5:69f1634cd40b 11 #include <string.h>
FSL\B36402 5:69f1634cd40b 12
FSL\B36402 5:69f1634cd40b 13 #include <stdio.h>
FSL\B36402 5:69f1634cd40b 14
FSL\B36402 5:69f1634cd40b 15 #include "options.h"
FSL\B36402 5:69f1634cd40b 16
FSL\B36402 5:69f1634cd40b 17 /*RF receive buffer*/
FSL\B36402 5:69f1634cd40b 18 static uint8_t rf_buffer[RF_BUFFER_SIZE];
FSL\B36402 5:69f1634cd40b 19 /*RF ACK receive buffer*/
FSL\B36402 5:69f1634cd40b 20 static uint8_t ack_rx_buf[5];
FSL\B36402 5:69f1634cd40b 21 /*ACK wait duration changes depending on data rate*/
FSL\B36402 5:69f1634cd40b 22 static uint16_t rf_ack_wait_duration = RF_ACK_WAIT_TIMEOUT;
FSL\B36402 5:69f1634cd40b 23
FSL\B36402 5:69f1634cd40b 24 static uint8_t radio_tx_power = 0x07;
FSL\B36402 5:69f1634cd40b 25 static uint8_t rf_channel;
FSL\B36402 5:69f1634cd40b 26 static uint8_t rf_tuned = 1;
FSL\B36402 5:69f1634cd40b 27 static uint8_t radio_rpc_value = 0xef;
FSL\B36402 5:69f1634cd40b 28 static uint8_t rf_use_front_end = 0;
FSL\B36402 5:69f1634cd40b 29 static uint8_t rf_use_antenna_diversity = 0;
FSL\B36402 5:69f1634cd40b 30 static uint8_t rf_csd_port = 0;
FSL\B36402 5:69f1634cd40b 31 static uint8_t rf_csd_pin = 0;
FSL\B36402 5:69f1634cd40b 32 static uint8_t rf_cps_port = 0;
FSL\B36402 5:69f1634cd40b 33 static uint8_t rf_cps_pin = 0;
FSL\B36402 5:69f1634cd40b 34 static uint8_t tx_sequence = 0xff;
FSL\B36402 5:69f1634cd40b 35 static uint8_t need_ack = 0;
FSL\B36402 5:69f1634cd40b 36 static uint8_t rf_rx_mode = 0;
FSL\B36402 5:69f1634cd40b 37 static uint8_t rf_flags = 0;
FSL\B36402 5:69f1634cd40b 38 static uint8_t rf_rnd_rssi = 0;
FSL\B36402 5:69f1634cd40b 39 static int8_t rf_radio_driver_id = -1;
FSL\B36402 5:69f1634cd40b 40 static phy_device_driver_s device_driver;
FSL\B36402 5:69f1634cd40b 41 static uint8_t atmel_MAC[8];
FSL\B36402 5:69f1634cd40b 42 static phy_device_channel_info_s channel_info;
FSL\B36402 5:69f1634cd40b 43 static uint8_t mac_tx_handle = 0;
FSL\B36402 5:69f1634cd40b 44
FSL\B36402 5:69f1634cd40b 45 /*
FSL\B36402 5:69f1634cd40b 46 * \brief Function sets given RF flag on.
FSL\B36402 5:69f1634cd40b 47 *
FSL\B36402 5:69f1634cd40b 48 * \param x Given RF flag
FSL\B36402 5:69f1634cd40b 49 *
FSL\B36402 5:69f1634cd40b 50 * \return none
FSL\B36402 5:69f1634cd40b 51 */
FSL\B36402 5:69f1634cd40b 52 void rf_flags_set(uint8_t x)
FSL\B36402 5:69f1634cd40b 53 {
FSL\B36402 5:69f1634cd40b 54 rf_flags |= x;
FSL\B36402 5:69f1634cd40b 55 }
FSL\B36402 5:69f1634cd40b 56
FSL\B36402 5:69f1634cd40b 57 /*
FSL\B36402 5:69f1634cd40b 58 * \brief Function clears given RF flag on.
FSL\B36402 5:69f1634cd40b 59 *
FSL\B36402 5:69f1634cd40b 60 * \param x Given RF flag
FSL\B36402 5:69f1634cd40b 61 *
FSL\B36402 5:69f1634cd40b 62 * \return none
FSL\B36402 5:69f1634cd40b 63 */
FSL\B36402 5:69f1634cd40b 64 void rf_flags_clear(uint8_t x)
FSL\B36402 5:69f1634cd40b 65 {
FSL\B36402 5:69f1634cd40b 66 rf_flags &= ~x;
FSL\B36402 5:69f1634cd40b 67 }
FSL\B36402 5:69f1634cd40b 68
FSL\B36402 5:69f1634cd40b 69 /*
FSL\B36402 5:69f1634cd40b 70 * \brief Function checks if given RF flag is on.
FSL\B36402 5:69f1634cd40b 71 *
FSL\B36402 5:69f1634cd40b 72 * \param x Given RF flag
FSL\B36402 5:69f1634cd40b 73 *
FSL\B36402 5:69f1634cd40b 74 * \return states of the given flags
FSL\B36402 5:69f1634cd40b 75 */
FSL\B36402 5:69f1634cd40b 76 uint8_t rf_flags_check(uint8_t x)
FSL\B36402 5:69f1634cd40b 77 {
FSL\B36402 5:69f1634cd40b 78 return (rf_flags & x);
FSL\B36402 5:69f1634cd40b 79 }
FSL\B36402 5:69f1634cd40b 80
FSL\B36402 5:69f1634cd40b 81 /*
FSL\B36402 5:69f1634cd40b 82 * \brief Function clears all RF flags.
FSL\B36402 5:69f1634cd40b 83 *
FSL\B36402 5:69f1634cd40b 84 * \param none
FSL\B36402 5:69f1634cd40b 85 *
FSL\B36402 5:69f1634cd40b 86 * \return none
FSL\B36402 5:69f1634cd40b 87 */
FSL\B36402 5:69f1634cd40b 88 void rf_flags_reset(void)
FSL\B36402 5:69f1634cd40b 89 {
FSL\B36402 5:69f1634cd40b 90 rf_flags = 0;
FSL\B36402 5:69f1634cd40b 91 }
FSL\B36402 5:69f1634cd40b 92
FSL\B36402 5:69f1634cd40b 93 /*
FSL\B36402 5:69f1634cd40b 94 * \brief Function sets CPS and CSD pins of the Front end.
FSL\B36402 5:69f1634cd40b 95 *
FSL\B36402 5:69f1634cd40b 96 * \param none
FSL\B36402 5:69f1634cd40b 97 *
FSL\B36402 5:69f1634cd40b 98 * \return none
FSL\B36402 5:69f1634cd40b 99 */
FSL\B36402 5:69f1634cd40b 100 void rf_front_end_rx_lna(void)
FSL\B36402 5:69f1634cd40b 101 {
FSL\B36402 5:69f1634cd40b 102 /* not supported in this version */
FSL\B36402 5:69f1634cd40b 103 }
FSL\B36402 5:69f1634cd40b 104
FSL\B36402 5:69f1634cd40b 105 /*
FSL\B36402 5:69f1634cd40b 106 * \brief Function clears CPS and CSD pins of the Front end.
FSL\B36402 5:69f1634cd40b 107 *
FSL\B36402 5:69f1634cd40b 108 * \param none
FSL\B36402 5:69f1634cd40b 109 *
FSL\B36402 5:69f1634cd40b 110 * \return none
FSL\B36402 5:69f1634cd40b 111 */
FSL\B36402 5:69f1634cd40b 112 void rf_front_end_sleep(void)
FSL\B36402 5:69f1634cd40b 113 {
FSL\B36402 5:69f1634cd40b 114 /* not supported in this version */
FSL\B36402 5:69f1634cd40b 115 }
FSL\B36402 5:69f1634cd40b 116
FSL\B36402 5:69f1634cd40b 117 /*
FSL\B36402 5:69f1634cd40b 118 * \brief Function initialises and registers the RF driver.
FSL\B36402 5:69f1634cd40b 119 *
FSL\B36402 5:69f1634cd40b 120 * \param none
FSL\B36402 5:69f1634cd40b 121 *
FSL\B36402 5:69f1634cd40b 122 * \return rf_radio_driver_id Driver ID given by NET library
FSL\B36402 5:69f1634cd40b 123 */
FSL\B36402 5:69f1634cd40b 124 int8_t rf_device_register(void)
FSL\B36402 5:69f1634cd40b 125 {
FSL\B36402 5:69f1634cd40b 126 rf_init();
FSL\B36402 5:69f1634cd40b 127 /*Set pointer to MAC address*/
FSL\B36402 5:69f1634cd40b 128 device_driver.PHY_MAC = atmel_MAC;
FSL\B36402 5:69f1634cd40b 129 device_driver.driver_description = "ATMEL_MAC";
FSL\B36402 5:69f1634cd40b 130 #if PHY_LINK_15_4_2_4GHZ_TYPE
FSL\B36402 5:69f1634cd40b 131 /*Number of channels in PHY*/
FSL\B36402 5:69f1634cd40b 132 channel_info.channel_count = 16;
FSL\B36402 5:69f1634cd40b 133 /*Channel mask 26-11*/
FSL\B36402 5:69f1634cd40b 134 channel_info.channel_mask = 0x07FFF800;
FSL\B36402 5:69f1634cd40b 135 /*Type of RF PHY is SubGHz*/
FSL\B36402 5:69f1634cd40b 136 device_driver.link_type = PHY_LINK_15_4_2_4GHZ_TYPE;
FSL\B36402 5:69f1634cd40b 137 device_driver.link_channel_info = &channel_info;
FSL\B36402 5:69f1634cd40b 138 #else
FSL\B36402 5:69f1634cd40b 139 /*Number of channels in PHY*/
FSL\B36402 5:69f1634cd40b 140 channel_info.channel_count = 11;
FSL\B36402 5:69f1634cd40b 141 /*Channel mask 0-10*/
FSL\B36402 5:69f1634cd40b 142 channel_info.channel_mask = 0x000007ff;
FSL\B36402 5:69f1634cd40b 143 /*Type of RF PHY is SubGHz*/
FSL\B36402 5:69f1634cd40b 144 device_driver.link_type = PHY_LINK_15_4_SUBGHZ_TYPE;
FSL\B36402 5:69f1634cd40b 145 device_driver.link_channel_info = &channel_info;
FSL\B36402 5:69f1634cd40b 146 #endif
FSL\B36402 5:69f1634cd40b 147 /*Maximum size of payload is 127*/
FSL\B36402 5:69f1634cd40b 148 device_driver.phy_MTU = 127;
FSL\B36402 5:69f1634cd40b 149 /*No header in PHY*/
FSL\B36402 5:69f1634cd40b 150 device_driver.phy_header_length = 0;
FSL\B36402 5:69f1634cd40b 151 /*No tail in PHY*/
FSL\B36402 5:69f1634cd40b 152 device_driver.phy_tail_length = 0;
FSL\B36402 5:69f1634cd40b 153 /*Set address write function*/
FSL\B36402 5:69f1634cd40b 154 device_driver.phy_xx_address_write = &rf_address_write;
FSL\B36402 5:69f1634cd40b 155 /*Set RF extension function*/
FSL\B36402 5:69f1634cd40b 156 device_driver.phy_xx_extension = &rf_extension;
FSL\B36402 5:69f1634cd40b 157 /*Set RF state control function*/
FSL\B36402 5:69f1634cd40b 158 device_driver.phy_xx_state_control = &rf_interface_state_control;
FSL\B36402 5:69f1634cd40b 159 /*Set transmit function*/
FSL\B36402 5:69f1634cd40b 160 device_driver.phy_xx_tx = &rf_start_cca;
FSL\B36402 5:69f1634cd40b 161 printf("RF Device Registration...");
FSL\B36402 5:69f1634cd40b 162 /*Register device driver*/
FSL\B36402 5:69f1634cd40b 163 rf_radio_driver_id = arm_net_phy_register(&device_driver);
FSL\B36402 5:69f1634cd40b 164 printf("OK\r\n");
FSL\B36402 5:69f1634cd40b 165 return rf_radio_driver_id;
FSL\B36402 5:69f1634cd40b 166 }
FSL\B36402 5:69f1634cd40b 167
FSL\B36402 5:69f1634cd40b 168 /*
FSL\B36402 5:69f1634cd40b 169 * \brief Function returns the generated 8-bit random value for seeding Pseudo-random generator. This value was generated by reading noise from RF channel in RF initialisation.
FSL\B36402 5:69f1634cd40b 170 *
FSL\B36402 5:69f1634cd40b 171 * \param none
FSL\B36402 5:69f1634cd40b 172 *
FSL\B36402 5:69f1634cd40b 173 * \return random RSSI value
FSL\B36402 5:69f1634cd40b 174 */
FSL\B36402 5:69f1634cd40b 175 int8_t rf_read_random(void)
FSL\B36402 5:69f1634cd40b 176 {
FSL\B36402 5:69f1634cd40b 177 return rf_rnd_rssi;
FSL\B36402 5:69f1634cd40b 178 }
FSL\B36402 5:69f1634cd40b 179
FSL\B36402 5:69f1634cd40b 180 /*
FSL\B36402 5:69f1634cd40b 181 * \brief Function is a call back for ACK wait timeout.
FSL\B36402 5:69f1634cd40b 182 *
FSL\B36402 5:69f1634cd40b 183 * \param none
FSL\B36402 5:69f1634cd40b 184 *
FSL\B36402 5:69f1634cd40b 185 * \return none
FSL\B36402 5:69f1634cd40b 186 */
FSL\B36402 5:69f1634cd40b 187 void rf_ack_wait_timer_interrupt(void)
FSL\B36402 5:69f1634cd40b 188 {
FSL\B36402 5:69f1634cd40b 189 arm_enter_critical();
FSL\B36402 5:69f1634cd40b 190 /*Force PLL state*/
FSL\B36402 5:69f1634cd40b 191 rf_if_change_trx_state(FORCE_PLL_ON);
FSL\B36402 5:69f1634cd40b 192 rf_poll_trx_state_change(PLL_ON);
FSL\B36402 5:69f1634cd40b 193 /*Start receiver in RX_AACK_ON state*/
FSL\B36402 5:69f1634cd40b 194 rf_rx_mode = 0;
FSL\B36402 5:69f1634cd40b 195 rf_flags_clear(RFF_RX);
FSL\B36402 5:69f1634cd40b 196 rf_receive();
FSL\B36402 5:69f1634cd40b 197 arm_exit_critical();
FSL\B36402 5:69f1634cd40b 198 }
FSL\B36402 5:69f1634cd40b 199
FSL\B36402 5:69f1634cd40b 200 /*
FSL\B36402 5:69f1634cd40b 201 * \brief Function is a call back for calibration interval timer.
FSL\B36402 5:69f1634cd40b 202 *
FSL\B36402 5:69f1634cd40b 203 * \param none
FSL\B36402 5:69f1634cd40b 204 *
FSL\B36402 5:69f1634cd40b 205 * \return none
FSL\B36402 5:69f1634cd40b 206 */
FSL\B36402 5:69f1634cd40b 207 void rf_calibration_timer_interrupt(void)
FSL\B36402 5:69f1634cd40b 208 {
FSL\B36402 5:69f1634cd40b 209 /*Calibrate RF*/
FSL\B36402 5:69f1634cd40b 210 rf_calibration_cb();
FSL\B36402 5:69f1634cd40b 211 /*Start new calibration timeout*/
FSL\B36402 5:69f1634cd40b 212 rf_calibration_timer_start(RF_CALIBRATION_INTERVAL);
FSL\B36402 5:69f1634cd40b 213 }
FSL\B36402 5:69f1634cd40b 214
FSL\B36402 5:69f1634cd40b 215 /*
FSL\B36402 5:69f1634cd40b 216 * \brief Function initialises the RF timer for ACK wait and calibration.
FSL\B36402 5:69f1634cd40b 217 *
FSL\B36402 5:69f1634cd40b 218 * \param none
FSL\B36402 5:69f1634cd40b 219 *
FSL\B36402 5:69f1634cd40b 220 * \return none
FSL\B36402 5:69f1634cd40b 221 */
FSL\B36402 5:69f1634cd40b 222 void rf_timer_init(void)
FSL\B36402 5:69f1634cd40b 223 {
FSL\B36402 5:69f1634cd40b 224 rf_if_timer_init();
FSL\B36402 5:69f1634cd40b 225 }
FSL\B36402 5:69f1634cd40b 226
FSL\B36402 5:69f1634cd40b 227 /*
FSL\B36402 5:69f1634cd40b 228 * \brief Function starts the ACK wait timeout.
FSL\B36402 5:69f1634cd40b 229 *
FSL\B36402 5:69f1634cd40b 230 * \param slots Given slots, resolution 50us
FSL\B36402 5:69f1634cd40b 231 *
FSL\B36402 5:69f1634cd40b 232 * \return none
FSL\B36402 5:69f1634cd40b 233 */
FSL\B36402 5:69f1634cd40b 234 void rf_ack_wait_timer_start(uint16_t slots)
FSL\B36402 5:69f1634cd40b 235 {
FSL\B36402 5:69f1634cd40b 236 rf_if_ack_wait_timer_start(slots);
FSL\B36402 5:69f1634cd40b 237 }
FSL\B36402 5:69f1634cd40b 238
FSL\B36402 5:69f1634cd40b 239 /*
FSL\B36402 5:69f1634cd40b 240 * \brief Function starts the calibration interval.
FSL\B36402 5:69f1634cd40b 241 *
FSL\B36402 5:69f1634cd40b 242 * \param slots Given slots, resolution 50us
FSL\B36402 5:69f1634cd40b 243 *
FSL\B36402 5:69f1634cd40b 244 * \return none
FSL\B36402 5:69f1634cd40b 245 */
FSL\B36402 5:69f1634cd40b 246 void rf_calibration_timer_start(uint32_t slots)
FSL\B36402 5:69f1634cd40b 247 {
FSL\B36402 5:69f1634cd40b 248 rf_if_calibration_timer_start(slots);
FSL\B36402 5:69f1634cd40b 249 }
FSL\B36402 5:69f1634cd40b 250
FSL\B36402 5:69f1634cd40b 251 /*
FSL\B36402 5:69f1634cd40b 252 * \brief Function stops the ACK wait timeout.
FSL\B36402 5:69f1634cd40b 253 *
FSL\B36402 5:69f1634cd40b 254 * \param none
FSL\B36402 5:69f1634cd40b 255 *
FSL\B36402 5:69f1634cd40b 256 * \return none
FSL\B36402 5:69f1634cd40b 257 */
FSL\B36402 5:69f1634cd40b 258 void rf_ack_wait_timer_stop(void)
FSL\B36402 5:69f1634cd40b 259 {
FSL\B36402 5:69f1634cd40b 260 rf_if_ack_wait_timer_stop();
FSL\B36402 5:69f1634cd40b 261 }
FSL\B36402 5:69f1634cd40b 262
FSL\B36402 5:69f1634cd40b 263 /*
FSL\B36402 5:69f1634cd40b 264 * \brief Function reads the MAC address array.
FSL\B36402 5:69f1634cd40b 265 *
FSL\B36402 5:69f1634cd40b 266 * \param ptr Pointer to read array
FSL\B36402 5:69f1634cd40b 267 *
FSL\B36402 5:69f1634cd40b 268 * \return none
FSL\B36402 5:69f1634cd40b 269 */
FSL\B36402 5:69f1634cd40b 270 void rf_read_mac_address(uint8_t *ptr)
FSL\B36402 5:69f1634cd40b 271 {
FSL\B36402 5:69f1634cd40b 272 memcpy(ptr, atmel_MAC, 8);
FSL\B36402 5:69f1634cd40b 273 }
FSL\B36402 5:69f1634cd40b 274
FSL\B36402 5:69f1634cd40b 275 /*
FSL\B36402 5:69f1634cd40b 276 * \brief Function sets the MAC address array.
FSL\B36402 5:69f1634cd40b 277 *
FSL\B36402 5:69f1634cd40b 278 * \param ptr Pointer to given MAC address array
FSL\B36402 5:69f1634cd40b 279 *
FSL\B36402 5:69f1634cd40b 280 * \return none
FSL\B36402 5:69f1634cd40b 281 */
FSL\B36402 5:69f1634cd40b 282 void rf_set_mac_address(const uint8_t *ptr)
FSL\B36402 5:69f1634cd40b 283 {
FSL\B36402 5:69f1634cd40b 284 memcpy(atmel_MAC,ptr,8);
FSL\B36402 5:69f1634cd40b 285 }
FSL\B36402 5:69f1634cd40b 286
FSL\B36402 5:69f1634cd40b 287 /*
FSL\B36402 5:69f1634cd40b 288 * \brief Function writes various RF settings in startup.
FSL\B36402 5:69f1634cd40b 289 *
FSL\B36402 5:69f1634cd40b 290 * \param none
FSL\B36402 5:69f1634cd40b 291 *
FSL\B36402 5:69f1634cd40b 292 * \return none
FSL\B36402 5:69f1634cd40b 293 */
FSL\B36402 5:69f1634cd40b 294 void rf_write_settings(void)
FSL\B36402 5:69f1634cd40b 295 {
FSL\B36402 5:69f1634cd40b 296 int i, j = 0;
FSL\B36402 5:69f1634cd40b 297
FSL\B36402 5:69f1634cd40b 298 arm_enter_critical();
FSL\B36402 5:69f1634cd40b 299
FSL\B36402 5:69f1634cd40b 300 //printf("RF Write Settings: 1\r\n");
FSL\B36402 5:69f1634cd40b 301 rf_if_write_rf_settings();
FSL\B36402 5:69f1634cd40b 302
FSL\B36402 5:69f1634cd40b 303 //printf("RF Write Settings: 2\r\n");
FSL\B36402 5:69f1634cd40b 304 /*Set output power*/
FSL\B36402 5:69f1634cd40b 305 rf_if_write_set_tx_power_register(radio_tx_power);
FSL\B36402 5:69f1634cd40b 306
FSL\B36402 5:69f1634cd40b 307 //printf("RF Write Settings: 3\r\n");
FSL\B36402 5:69f1634cd40b 308 /*Set RPC register*/
FSL\B36402 5:69f1634cd40b 309 rf_if_write_set_trx_rpc_register(radio_rpc_value);
FSL\B36402 5:69f1634cd40b 310
FSL\B36402 5:69f1634cd40b 311 //printf("RF Write Settings: 4\r\n");
FSL\B36402 5:69f1634cd40b 312 /*Initialise Front end*/
FSL\B36402 5:69f1634cd40b 313 if(rf_use_front_end)
FSL\B36402 5:69f1634cd40b 314 {
FSL\B36402 5:69f1634cd40b 315 printf("RF Front End used\r\n");
FSL\B36402 5:69f1634cd40b 316 rf_if_enable_pa_ext();
FSL\B36402 5:69f1634cd40b 317 /* not supported in this version */
FSL\B36402 5:69f1634cd40b 318 }
FSL\B36402 5:69f1634cd40b 319
FSL\B36402 5:69f1634cd40b 320 //printf("RF Write Settings: 5\r\n");
FSL\B36402 5:69f1634cd40b 321 /*Initialise Antenna Diversity*/
FSL\B36402 5:69f1634cd40b 322 if(rf_use_antenna_diversity) {
FSL\B36402 5:69f1634cd40b 323 printf("RF Antenna diversity\r\n");
FSL\B36402 5:69f1634cd40b 324 rf_if_write_antenna_diversity_settings();
FSL\B36402 5:69f1634cd40b 325 }
FSL\B36402 5:69f1634cd40b 326
FSL\B36402 5:69f1634cd40b 327 printf("RF Write Settings: 7\r\n");
FSL\B36402 5:69f1634cd40b 328 arm_exit_critical();
FSL\B36402 5:69f1634cd40b 329 printf("RF Write Settings End\r\n");
FSL\B36402 5:69f1634cd40b 330 }
FSL\B36402 5:69f1634cd40b 331
FSL\B36402 5:69f1634cd40b 332 /*
FSL\B36402 5:69f1634cd40b 333 * \brief Function writes 16-bit address in RF address filter.
FSL\B36402 5:69f1634cd40b 334 *
FSL\B36402 5:69f1634cd40b 335 * \param short_address Given short address
FSL\B36402 5:69f1634cd40b 336 *
FSL\B36402 5:69f1634cd40b 337 * \return none
FSL\B36402 5:69f1634cd40b 338 */
FSL\B36402 5:69f1634cd40b 339 void rf_set_short_adr(uint8_t * short_address)
FSL\B36402 5:69f1634cd40b 340 {
FSL\B36402 5:69f1634cd40b 341 uint8_t rf_off_flag = 0;
FSL\B36402 5:69f1634cd40b 342 arm_enter_critical();
FSL\B36402 5:69f1634cd40b 343 /*Wake up RF if sleeping*/
FSL\B36402 5:69f1634cd40b 344 if(rf_if_read_trx_state() == 0x00 || rf_if_read_trx_state() == 0x1F)
FSL\B36402 5:69f1634cd40b 345 {
FSL\B36402 5:69f1634cd40b 346 rf_if_disable_slptr();
FSL\B36402 5:69f1634cd40b 347 rf_off_flag = 1;
FSL\B36402 5:69f1634cd40b 348 rf_poll_trx_state_change(TRX_OFF);
FSL\B36402 5:69f1634cd40b 349 }
FSL\B36402 5:69f1634cd40b 350 /*Write address filter registers*/
FSL\B36402 5:69f1634cd40b 351 rf_if_write_short_addr_registers(short_address);
FSL\B36402 5:69f1634cd40b 352 /*RF back to sleep*/
FSL\B36402 5:69f1634cd40b 353 if(rf_off_flag)
FSL\B36402 5:69f1634cd40b 354 rf_if_enable_slptr();
FSL\B36402 5:69f1634cd40b 355 arm_exit_critical();
FSL\B36402 5:69f1634cd40b 356 }
FSL\B36402 5:69f1634cd40b 357
FSL\B36402 5:69f1634cd40b 358 /*
FSL\B36402 5:69f1634cd40b 359 * \brief Function writes PAN Id in RF PAN Id filter.
FSL\B36402 5:69f1634cd40b 360 *
FSL\B36402 5:69f1634cd40b 361 * \param pan_id Given PAN Id
FSL\B36402 5:69f1634cd40b 362 *
FSL\B36402 5:69f1634cd40b 363 * \return none
FSL\B36402 5:69f1634cd40b 364 */
FSL\B36402 5:69f1634cd40b 365 void rf_set_pan_id(uint8_t *pan_id)
FSL\B36402 5:69f1634cd40b 366 {
FSL\B36402 5:69f1634cd40b 367 uint8_t rf_off_flag = 0;
FSL\B36402 5:69f1634cd40b 368
FSL\B36402 5:69f1634cd40b 369 arm_enter_critical();
FSL\B36402 5:69f1634cd40b 370 /*Wake up RF if sleeping*/
FSL\B36402 5:69f1634cd40b 371 if(rf_if_read_trx_state() == 0x00 || rf_if_read_trx_state() == 0x1F)
FSL\B36402 5:69f1634cd40b 372 {
FSL\B36402 5:69f1634cd40b 373 rf_if_disable_slptr();
FSL\B36402 5:69f1634cd40b 374 rf_off_flag = 1;
FSL\B36402 5:69f1634cd40b 375 rf_poll_trx_state_change(TRX_OFF);
FSL\B36402 5:69f1634cd40b 376 }
FSL\B36402 5:69f1634cd40b 377 /*Write address filter registers*/
FSL\B36402 5:69f1634cd40b 378 rf_if_write_pan_id_registers(pan_id);
FSL\B36402 5:69f1634cd40b 379 /*RF back to sleep*/
FSL\B36402 5:69f1634cd40b 380 if(rf_off_flag)
FSL\B36402 5:69f1634cd40b 381 rf_if_enable_slptr();
FSL\B36402 5:69f1634cd40b 382 arm_exit_critical();
FSL\B36402 5:69f1634cd40b 383 }
FSL\B36402 5:69f1634cd40b 384
FSL\B36402 5:69f1634cd40b 385 /*
FSL\B36402 5:69f1634cd40b 386 * \brief Function writes 64-bit address in RF address filter.
FSL\B36402 5:69f1634cd40b 387 *
FSL\B36402 5:69f1634cd40b 388 * \param address Given 64-bit address
FSL\B36402 5:69f1634cd40b 389 *
FSL\B36402 5:69f1634cd40b 390 * \return none
FSL\B36402 5:69f1634cd40b 391 */
FSL\B36402 5:69f1634cd40b 392 void rf_set_address(uint8_t *address)
FSL\B36402 5:69f1634cd40b 393 {
FSL\B36402 5:69f1634cd40b 394 uint8_t rf_off_flag = 0;
FSL\B36402 5:69f1634cd40b 395
FSL\B36402 5:69f1634cd40b 396 arm_enter_critical();
FSL\B36402 5:69f1634cd40b 397 /*Wake up RF if sleeping*/
FSL\B36402 5:69f1634cd40b 398 if(rf_if_read_trx_state() == 0x00 || rf_if_read_trx_state() == 0x1F)
FSL\B36402 5:69f1634cd40b 399 {
FSL\B36402 5:69f1634cd40b 400 rf_if_disable_slptr();
FSL\B36402 5:69f1634cd40b 401 rf_off_flag = 1;
FSL\B36402 5:69f1634cd40b 402 rf_poll_trx_state_change(TRX_OFF);
FSL\B36402 5:69f1634cd40b 403 }
FSL\B36402 5:69f1634cd40b 404 /*Write address filter registers*/
FSL\B36402 5:69f1634cd40b 405 rf_if_write_ieee_addr_registers(address);
FSL\B36402 5:69f1634cd40b 406 /*RF back to sleep*/
FSL\B36402 5:69f1634cd40b 407 if(rf_off_flag)
FSL\B36402 5:69f1634cd40b 408 rf_if_enable_slptr();
FSL\B36402 5:69f1634cd40b 409
FSL\B36402 5:69f1634cd40b 410 arm_exit_critical();
FSL\B36402 5:69f1634cd40b 411 }
FSL\B36402 5:69f1634cd40b 412
FSL\B36402 5:69f1634cd40b 413 /*
FSL\B36402 5:69f1634cd40b 414 * \brief Function sets the RF channel.
FSL\B36402 5:69f1634cd40b 415 *
FSL\B36402 5:69f1634cd40b 416 * \param ch New channel
FSL\B36402 5:69f1634cd40b 417 *
FSL\B36402 5:69f1634cd40b 418 * \return none
FSL\B36402 5:69f1634cd40b 419 */
FSL\B36402 5:69f1634cd40b 420 void rf_channel_set(uint8_t ch)
FSL\B36402 5:69f1634cd40b 421 {
FSL\B36402 5:69f1634cd40b 422 arm_enter_critical();
FSL\B36402 5:69f1634cd40b 423 rf_channel = ch;
FSL\B36402 5:69f1634cd40b 424 if(ch < 0x1f)
FSL\B36402 5:69f1634cd40b 425 rf_if_set_channel_register(ch);
FSL\B36402 5:69f1634cd40b 426 arm_exit_critical();
FSL\B36402 5:69f1634cd40b 427 }
FSL\B36402 5:69f1634cd40b 428
FSL\B36402 5:69f1634cd40b 429
FSL\B36402 5:69f1634cd40b 430 /*
FSL\B36402 5:69f1634cd40b 431 * \brief Function initialises the radio driver and resets the radio.
FSL\B36402 5:69f1634cd40b 432 *
FSL\B36402 5:69f1634cd40b 433 * \param none
FSL\B36402 5:69f1634cd40b 434 *
FSL\B36402 5:69f1634cd40b 435 * \return none
FSL\B36402 5:69f1634cd40b 436 */
FSL\B36402 5:69f1634cd40b 437 void rf_init(void)
FSL\B36402 5:69f1634cd40b 438 {
FSL\B36402 5:69f1634cd40b 439 printf("RF Init Start\r\n");
FSL\B36402 5:69f1634cd40b 440 /*Initialise timers*/
FSL\B36402 5:69f1634cd40b 441 rf_timer_init(); //TODO
FSL\B36402 5:69f1634cd40b 442 rf_channel = RF_DEFAULT_CHANNEL;
FSL\B36402 5:69f1634cd40b 443 printf("RF Reset\r\n");
FSL\B36402 5:69f1634cd40b 444 /*Reset RF module*/
FSL\B36402 5:69f1634cd40b 445 rf_if_reset_radio();
FSL\B36402 5:69f1634cd40b 446 printf("RF Write Settings\r\n");
FSL\B36402 5:69f1634cd40b 447 /*Write RF settings*/
FSL\B36402 5:69f1634cd40b 448 rf_write_settings();
FSL\B36402 5:69f1634cd40b 449 printf("RF Init PHY Mode\r\n");
FSL\B36402 5:69f1634cd40b 450 /*Initialise PHY mode*/
FSL\B36402 5:69f1634cd40b 451 rf_init_phy_mode();
FSL\B36402 5:69f1634cd40b 452 /*Clear RF flags*/
FSL\B36402 5:69f1634cd40b 453 rf_flags_reset();
FSL\B36402 5:69f1634cd40b 454 /*Set RF in TRX OFF state*/
FSL\B36402 5:69f1634cd40b 455 rf_if_change_trx_state(TRX_OFF);
FSL\B36402 5:69f1634cd40b 456 /*Set RF in PLL_ON state*/
FSL\B36402 5:69f1634cd40b 457 rf_if_change_trx_state(PLL_ON);
FSL\B36402 5:69f1634cd40b 458 /*Start receiver*/
FSL\B36402 5:69f1634cd40b 459 rf_receive();
FSL\B36402 5:69f1634cd40b 460 /*Read random variable. This will be used when seeding pseudo-random generator*/
FSL\B36402 5:69f1634cd40b 461 rf_rnd_rssi = rf_if_read_rnd();
FSL\B36402 5:69f1634cd40b 462 /*Start RF calibration timer*/
FSL\B36402 5:69f1634cd40b 463 rf_calibration_timer_start(RF_CALIBRATION_INTERVAL); //ACA!
FSL\B36402 5:69f1634cd40b 464 printf("RF Init End\r\n");
FSL\B36402 5:69f1634cd40b 465 }
FSL\B36402 5:69f1634cd40b 466
FSL\B36402 5:69f1634cd40b 467 /**
FSL\B36402 5:69f1634cd40b 468 * \brief Function gets called when MAC is setting radio off.
FSL\B36402 5:69f1634cd40b 469 *
FSL\B36402 5:69f1634cd40b 470 * \param none
FSL\B36402 5:69f1634cd40b 471 *
FSL\B36402 5:69f1634cd40b 472 * \return none
FSL\B36402 5:69f1634cd40b 473 */
FSL\B36402 5:69f1634cd40b 474 void rf_off(void)
FSL\B36402 5:69f1634cd40b 475 {
FSL\B36402 5:69f1634cd40b 476 if(rf_flags_check(RFF_ON))
FSL\B36402 5:69f1634cd40b 477 {
FSL\B36402 5:69f1634cd40b 478 rf_cca_abort();
FSL\B36402 5:69f1634cd40b 479 uint16_t while_counter = 0;
FSL\B36402 5:69f1634cd40b 480 /*Wait while receiving*/
FSL\B36402 5:69f1634cd40b 481 while(rf_if_read_trx_state() == BUSY_RX_AACK || rf_if_read_trx_state() == BUSY_RX)
FSL\B36402 5:69f1634cd40b 482 {
FSL\B36402 5:69f1634cd40b 483 while_counter++;
FSL\B36402 5:69f1634cd40b 484 if(while_counter == 0xffff)
FSL\B36402 5:69f1634cd40b 485 break;
FSL\B36402 5:69f1634cd40b 486 }
FSL\B36402 5:69f1634cd40b 487 /*RF state change: RX_AACK_ON->PLL_ON->TRX_OFF->SLEEP*/
FSL\B36402 5:69f1634cd40b 488 if(rf_if_read_trx_state() == RX_AACK_ON)
FSL\B36402 5:69f1634cd40b 489 {
FSL\B36402 5:69f1634cd40b 490 rf_if_change_trx_state(PLL_ON);
FSL\B36402 5:69f1634cd40b 491 }
FSL\B36402 5:69f1634cd40b 492 rf_if_change_trx_state(TRX_OFF);
FSL\B36402 5:69f1634cd40b 493 rf_if_enable_slptr();
FSL\B36402 5:69f1634cd40b 494 rf_flags_clear(~RFF_ON);
FSL\B36402 5:69f1634cd40b 495 /*Front end in sleep*/
FSL\B36402 5:69f1634cd40b 496 if(rf_use_front_end)
FSL\B36402 5:69f1634cd40b 497 {
FSL\B36402 5:69f1634cd40b 498 rf_if_disable_pa_ext();
FSL\B36402 5:69f1634cd40b 499 rf_front_end_sleep();
FSL\B36402 5:69f1634cd40b 500 }
FSL\B36402 5:69f1634cd40b 501 /*Disable Antenna Diversity*/
FSL\B36402 5:69f1634cd40b 502 if(rf_use_antenna_diversity)
FSL\B36402 5:69f1634cd40b 503 rf_if_disable_ant_div();
FSL\B36402 5:69f1634cd40b 504 }
FSL\B36402 5:69f1634cd40b 505 }
FSL\B36402 5:69f1634cd40b 506
FSL\B36402 5:69f1634cd40b 507 /*
FSL\B36402 5:69f1634cd40b 508 * \brief Function polls the RF state until it has changed to desired state.
FSL\B36402 5:69f1634cd40b 509 *
FSL\B36402 5:69f1634cd40b 510 * \param trx_state RF state
FSL\B36402 5:69f1634cd40b 511 *
FSL\B36402 5:69f1634cd40b 512 * \return none
FSL\B36402 5:69f1634cd40b 513 */
FSL\B36402 5:69f1634cd40b 514 void rf_poll_trx_state_change(rf_trx_states_t trx_state)
FSL\B36402 5:69f1634cd40b 515 {
FSL\B36402 5:69f1634cd40b 516 uint16_t while_counter = 0;
FSL\B36402 5:69f1634cd40b 517 arm_enter_critical();
FSL\B36402 5:69f1634cd40b 518
FSL\B36402 5:69f1634cd40b 519 if(trx_state != RF_TX_START)
FSL\B36402 5:69f1634cd40b 520 {
FSL\B36402 5:69f1634cd40b 521 if(trx_state == FORCE_PLL_ON)
FSL\B36402 5:69f1634cd40b 522 trx_state = PLL_ON;
FSL\B36402 5:69f1634cd40b 523 else if(trx_state == FORCE_TRX_OFF)
FSL\B36402 5:69f1634cd40b 524 trx_state = TRX_OFF;
FSL\B36402 5:69f1634cd40b 525
FSL\B36402 5:69f1634cd40b 526 while(rf_if_read_trx_state() != trx_state)
FSL\B36402 5:69f1634cd40b 527 {
FSL\B36402 5:69f1634cd40b 528 while_counter++;
FSL\B36402 5:69f1634cd40b 529 if(while_counter == 0x1ff)
FSL\B36402 5:69f1634cd40b 530 break;
FSL\B36402 5:69f1634cd40b 531 }
FSL\B36402 5:69f1634cd40b 532 }
FSL\B36402 5:69f1634cd40b 533 arm_exit_critical();
FSL\B36402 5:69f1634cd40b 534 }
FSL\B36402 5:69f1634cd40b 535
FSL\B36402 5:69f1634cd40b 536 /*
FSL\B36402 5:69f1634cd40b 537 * \brief Function starts the CCA process before starting data transmission and copies the data to RF TX FIFO.
FSL\B36402 5:69f1634cd40b 538 *
FSL\B36402 5:69f1634cd40b 539 * \param data_ptr Pointer to TX data
FSL\B36402 5:69f1634cd40b 540 * \param data_length Length of the TX data
FSL\B36402 5:69f1634cd40b 541 * \param tx_handle Handle to transmission
FSL\B36402 5:69f1634cd40b 542 * \return 0 Success
FSL\B36402 5:69f1634cd40b 543 * \return -1 Busy
FSL\B36402 5:69f1634cd40b 544 */
FSL\B36402 5:69f1634cd40b 545 int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle)
FSL\B36402 5:69f1634cd40b 546 {
FSL\B36402 5:69f1634cd40b 547 /*Check if transmitter is busy*/
FSL\B36402 5:69f1634cd40b 548 if((rf_if_read_trx_state() == BUSY_RX_AACK) || (rf_if_read_trx_state() == BUSY_RX))
FSL\B36402 5:69f1634cd40b 549 {
FSL\B36402 5:69f1634cd40b 550 /*Return busy*/
FSL\B36402 5:69f1634cd40b 551 return -1;
FSL\B36402 5:69f1634cd40b 552 }
FSL\B36402 5:69f1634cd40b 553 else
FSL\B36402 5:69f1634cd40b 554 {
FSL\B36402 5:69f1634cd40b 555 arm_enter_critical();
FSL\B36402 5:69f1634cd40b 556 /*Check if transmitted data needs to be acked*/
FSL\B36402 5:69f1634cd40b 557 if(*data_ptr & 0x20)
FSL\B36402 5:69f1634cd40b 558 need_ack = 1;
FSL\B36402 5:69f1634cd40b 559 else
FSL\B36402 5:69f1634cd40b 560 need_ack = 0;
FSL\B36402 5:69f1634cd40b 561 /*Store the sequence number for ACK handling*/
FSL\B36402 5:69f1634cd40b 562 tx_sequence = *(data_ptr + 2);
FSL\B36402 5:69f1634cd40b 563 /*Set radio in RX state to read channel*/
FSL\B36402 5:69f1634cd40b 564 rf_receive();
FSL\B36402 5:69f1634cd40b 565 /*Write TX FIFO*/
FSL\B36402 5:69f1634cd40b 566 rf_if_write_frame_buffer(data_ptr, (uint8_t)data_length);
FSL\B36402 5:69f1634cd40b 567 rf_flags_set(RFF_CCA);
FSL\B36402 5:69f1634cd40b 568 /*Start CCA process*/
FSL\B36402 5:69f1634cd40b 569 rf_if_enable_cca_ed_done_interrupt();
FSL\B36402 5:69f1634cd40b 570 rf_if_start_cca_process();
FSL\B36402 5:69f1634cd40b 571 /*Store TX handle*/
FSL\B36402 5:69f1634cd40b 572 mac_tx_handle = tx_handle;
FSL\B36402 5:69f1634cd40b 573 arm_exit_critical();
FSL\B36402 5:69f1634cd40b 574 }
FSL\B36402 5:69f1634cd40b 575
FSL\B36402 5:69f1634cd40b 576 /*Return success*/
FSL\B36402 5:69f1634cd40b 577 return 0;
FSL\B36402 5:69f1634cd40b 578 }
FSL\B36402 5:69f1634cd40b 579
FSL\B36402 5:69f1634cd40b 580 /*
FSL\B36402 5:69f1634cd40b 581 * \brief Function aborts CCA process.
FSL\B36402 5:69f1634cd40b 582 *
FSL\B36402 5:69f1634cd40b 583 * \param none
FSL\B36402 5:69f1634cd40b 584 *
FSL\B36402 5:69f1634cd40b 585 * \return none
FSL\B36402 5:69f1634cd40b 586 */
FSL\B36402 5:69f1634cd40b 587 void rf_cca_abort(void)
FSL\B36402 5:69f1634cd40b 588 {
FSL\B36402 5:69f1634cd40b 589 /*Clear RFF_CCA RF flag*/
FSL\B36402 5:69f1634cd40b 590 rf_flags_clear(RFF_CCA);
FSL\B36402 5:69f1634cd40b 591 }
FSL\B36402 5:69f1634cd40b 592
FSL\B36402 5:69f1634cd40b 593
FSL\B36402 5:69f1634cd40b 594
FSL\B36402 5:69f1634cd40b 595 /*
FSL\B36402 5:69f1634cd40b 596 * \brief Function starts the transmission of the frame.
FSL\B36402 5:69f1634cd40b 597 *
FSL\B36402 5:69f1634cd40b 598 * \param none
FSL\B36402 5:69f1634cd40b 599 *
FSL\B36402 5:69f1634cd40b 600 * \return none
FSL\B36402 5:69f1634cd40b 601 */
FSL\B36402 5:69f1634cd40b 602 void rf_start_tx(void)
FSL\B36402 5:69f1634cd40b 603 {
FSL\B36402 5:69f1634cd40b 604 /*Only start transmitting from RX state*/
FSL\B36402 5:69f1634cd40b 605 uint8_t trx_state = rf_if_read_trx_state();
FSL\B36402 5:69f1634cd40b 606 if((trx_state != RX_AACK_ON) && (trx_state != RX_ON))
FSL\B36402 5:69f1634cd40b 607 {
FSL\B36402 5:69f1634cd40b 608 arm_net_phy_tx_done(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 1);
FSL\B36402 5:69f1634cd40b 609 }
FSL\B36402 5:69f1634cd40b 610 else
FSL\B36402 5:69f1634cd40b 611 {
FSL\B36402 5:69f1634cd40b 612 /*RF state change: ->PLL_ON->RF_TX_START*/
FSL\B36402 5:69f1634cd40b 613 rf_if_change_trx_state(FORCE_PLL_ON);
FSL\B36402 5:69f1634cd40b 614 rf_flags_clear(RFF_RX);
FSL\B36402 5:69f1634cd40b 615 rf_if_enable_tx_end_interrupt();
FSL\B36402 5:69f1634cd40b 616 rf_flags_set(RFF_TX);
FSL\B36402 5:69f1634cd40b 617 rf_if_change_trx_state(RF_TX_START);
FSL\B36402 5:69f1634cd40b 618 }
FSL\B36402 5:69f1634cd40b 619 }
FSL\B36402 5:69f1634cd40b 620
FSL\B36402 5:69f1634cd40b 621 /*
FSL\B36402 5:69f1634cd40b 622 * \brief Function sets the RF in RX state.
FSL\B36402 5:69f1634cd40b 623 *
FSL\B36402 5:69f1634cd40b 624 * \param none
FSL\B36402 5:69f1634cd40b 625 *
FSL\B36402 5:69f1634cd40b 626 * \return none
FSL\B36402 5:69f1634cd40b 627 */
FSL\B36402 5:69f1634cd40b 628 void rf_receive(void)
FSL\B36402 5:69f1634cd40b 629 {
FSL\B36402 5:69f1634cd40b 630 uint16_t while_counter = 0;
FSL\B36402 5:69f1634cd40b 631 if(rf_flags_check(RFF_ON) == 0)
FSL\B36402 5:69f1634cd40b 632 {
FSL\B36402 5:69f1634cd40b 633 rf_on();
FSL\B36402 5:69f1634cd40b 634 }
FSL\B36402 5:69f1634cd40b 635 /*If not yet in RX state set it*/
FSL\B36402 5:69f1634cd40b 636 if(rf_flags_check(RFF_RX) == 0)
FSL\B36402 5:69f1634cd40b 637 {
FSL\B36402 5:69f1634cd40b 638 arm_enter_critical();
FSL\B36402 5:69f1634cd40b 639 /*Wait while receiving data*/
FSL\B36402 5:69f1634cd40b 640 while((rf_if_read_trx_state() == BUSY_RX) || (rf_if_read_trx_state() == BUSY_RX_AACK))
FSL\B36402 5:69f1634cd40b 641 {
FSL\B36402 5:69f1634cd40b 642 while_counter++;
FSL\B36402 5:69f1634cd40b 643 if(while_counter == 0xffff)
FSL\B36402 5:69f1634cd40b 644 {
FSL\B36402 5:69f1634cd40b 645 break;
FSL\B36402 5:69f1634cd40b 646 }
FSL\B36402 5:69f1634cd40b 647 }
FSL\B36402 5:69f1634cd40b 648 /*Wake up from sleep state*/
FSL\B36402 5:69f1634cd40b 649 if(rf_if_read_trx_state() == 0x00 || rf_if_read_trx_state() == 0x1f)
FSL\B36402 5:69f1634cd40b 650 {
FSL\B36402 5:69f1634cd40b 651 rf_if_disable_slptr();
FSL\B36402 5:69f1634cd40b 652 rf_poll_trx_state_change(TRX_OFF);
FSL\B36402 5:69f1634cd40b 653 }
FSL\B36402 5:69f1634cd40b 654
FSL\B36402 5:69f1634cd40b 655 rf_if_change_trx_state(PLL_ON);
FSL\B36402 5:69f1634cd40b 656 /*ACK is always received in RX_ON state to bypass address filters*/
FSL\B36402 5:69f1634cd40b 657 if(rf_rx_mode)
FSL\B36402 5:69f1634cd40b 658 {
FSL\B36402 5:69f1634cd40b 659 rf_rx_mode = 0;
FSL\B36402 5:69f1634cd40b 660 rf_if_change_trx_state(RX_ON);
FSL\B36402 5:69f1634cd40b 661 }
FSL\B36402 5:69f1634cd40b 662 else
FSL\B36402 5:69f1634cd40b 663 {
FSL\B36402 5:69f1634cd40b 664 rf_if_change_trx_state(RX_AACK_ON);
FSL\B36402 5:69f1634cd40b 665 /*If calibration timer was unable to calibrate the RF, run calibration now*/
FSL\B36402 5:69f1634cd40b 666 if(!rf_tuned)
FSL\B36402 5:69f1634cd40b 667 {
FSL\B36402 5:69f1634cd40b 668 /*Start calibration. This can be done in states TRX_OFF, PLL_ON or in any receive state*/
FSL\B36402 5:69f1634cd40b 669 rf_if_calibration();
FSL\B36402 5:69f1634cd40b 670 /*RF is tuned now*/
FSL\B36402 5:69f1634cd40b 671 rf_tuned = 1;
FSL\B36402 5:69f1634cd40b 672 }
FSL\B36402 5:69f1634cd40b 673 }
FSL\B36402 5:69f1634cd40b 674 rf_channel_set(rf_channel);
FSL\B36402 5:69f1634cd40b 675 rf_flags_set(RFF_RX);
FSL\B36402 5:69f1634cd40b 676 rf_if_enable_rx_end_interrupt();
FSL\B36402 5:69f1634cd40b 677 /*Enable LNA if Front end used*/
FSL\B36402 5:69f1634cd40b 678 if(rf_use_front_end)
FSL\B36402 5:69f1634cd40b 679 rf_front_end_rx_lna();
FSL\B36402 5:69f1634cd40b 680 arm_exit_critical();
FSL\B36402 5:69f1634cd40b 681 }
FSL\B36402 5:69f1634cd40b 682 /*Stop the running CCA process*/
FSL\B36402 5:69f1634cd40b 683 if(rf_flags_check(RFF_CCA))
FSL\B36402 5:69f1634cd40b 684 rf_cca_abort();
FSL\B36402 5:69f1634cd40b 685 }
FSL\B36402 5:69f1634cd40b 686
FSL\B36402 5:69f1634cd40b 687 /*
FSL\B36402 5:69f1634cd40b 688 * \brief Function calibrates the radio.
FSL\B36402 5:69f1634cd40b 689 *
FSL\B36402 5:69f1634cd40b 690 * \param none
FSL\B36402 5:69f1634cd40b 691 *
FSL\B36402 5:69f1634cd40b 692 * \return none
FSL\B36402 5:69f1634cd40b 693 */
FSL\B36402 5:69f1634cd40b 694 void rf_calibration_cb(void)
FSL\B36402 5:69f1634cd40b 695 {
FSL\B36402 5:69f1634cd40b 696 /*clear tuned flag to start tuning in rf_receive*/
FSL\B36402 5:69f1634cd40b 697 rf_tuned = 0;
FSL\B36402 5:69f1634cd40b 698 /*If RF is in default receive state, start calibration*/
FSL\B36402 5:69f1634cd40b 699 if(rf_if_read_trx_state() == RX_AACK_ON)
FSL\B36402 5:69f1634cd40b 700 {
FSL\B36402 5:69f1634cd40b 701 arm_enter_critical();
FSL\B36402 5:69f1634cd40b 702 /*Set RF in PLL_ON state*/
FSL\B36402 5:69f1634cd40b 703 rf_if_change_trx_state(PLL_ON);
FSL\B36402 5:69f1634cd40b 704 /*Set RF in TRX_OFF state to start PLL tuning*/
FSL\B36402 5:69f1634cd40b 705 rf_if_change_trx_state(TRX_OFF);
FSL\B36402 5:69f1634cd40b 706 /*Set RF in RX_ON state to calibrate*/
FSL\B36402 5:69f1634cd40b 707 rf_if_change_trx_state(RX_ON);
FSL\B36402 5:69f1634cd40b 708 /*Calibrate FTN*/
FSL\B36402 5:69f1634cd40b 709 rf_if_calibration();
FSL\B36402 5:69f1634cd40b 710 /*RF is tuned now*/
FSL\B36402 5:69f1634cd40b 711 rf_tuned = 1;
FSL\B36402 5:69f1634cd40b 712 /*Back to default receive state*/
FSL\B36402 5:69f1634cd40b 713 rf_flags_clear(RFF_RX);
FSL\B36402 5:69f1634cd40b 714 rf_receive();
FSL\B36402 5:69f1634cd40b 715 arm_exit_critical();
FSL\B36402 5:69f1634cd40b 716 }
FSL\B36402 5:69f1634cd40b 717 }
FSL\B36402 5:69f1634cd40b 718
FSL\B36402 5:69f1634cd40b 719 /*
FSL\B36402 5:69f1634cd40b 720 * \brief Function sets RF_ON flag when radio is powered.
FSL\B36402 5:69f1634cd40b 721 *
FSL\B36402 5:69f1634cd40b 722 * \param none
FSL\B36402 5:69f1634cd40b 723 *
FSL\B36402 5:69f1634cd40b 724 * \return none
FSL\B36402 5:69f1634cd40b 725 */
FSL\B36402 5:69f1634cd40b 726 void rf_on(void)
FSL\B36402 5:69f1634cd40b 727 {
FSL\B36402 5:69f1634cd40b 728 /*Set RFF_ON flag*/
FSL\B36402 5:69f1634cd40b 729 if(rf_flags_check(RFF_ON) == 0)
FSL\B36402 5:69f1634cd40b 730 {
FSL\B36402 5:69f1634cd40b 731 rf_flags_set(RFF_ON);
FSL\B36402 5:69f1634cd40b 732 /*Wake up Front end*/
FSL\B36402 5:69f1634cd40b 733 if(rf_use_front_end)
FSL\B36402 5:69f1634cd40b 734 {
FSL\B36402 5:69f1634cd40b 735 /*Set PA_EXT_EN to enable controlling of external front end*/
FSL\B36402 5:69f1634cd40b 736 rf_if_enable_pa_ext();
FSL\B36402 5:69f1634cd40b 737 rf_front_end_rx_lna();
FSL\B36402 5:69f1634cd40b 738 }
FSL\B36402 5:69f1634cd40b 739 /*Enable Antenna diversity*/
FSL\B36402 5:69f1634cd40b 740 if(rf_use_antenna_diversity)
FSL\B36402 5:69f1634cd40b 741 /*Set ANT_EXT_SW_EN to enable controlling of antenna diversity*/
FSL\B36402 5:69f1634cd40b 742 rf_if_enable_ant_div();
FSL\B36402 5:69f1634cd40b 743 }
FSL\B36402 5:69f1634cd40b 744 }
FSL\B36402 5:69f1634cd40b 745
FSL\B36402 5:69f1634cd40b 746 /*
FSL\B36402 5:69f1634cd40b 747 * \brief Function handles the received ACK frame.
FSL\B36402 5:69f1634cd40b 748 *
FSL\B36402 5:69f1634cd40b 749 * \param seq_number Sequence number of received ACK
FSL\B36402 5:69f1634cd40b 750 * \param data_pending Pending bit state in received ACK
FSL\B36402 5:69f1634cd40b 751 *
FSL\B36402 5:69f1634cd40b 752 * \return none
FSL\B36402 5:69f1634cd40b 753 */
FSL\B36402 5:69f1634cd40b 754 void rf_handle_ack(uint8_t seq_number, uint8_t data_pending)
FSL\B36402 5:69f1634cd40b 755 {
FSL\B36402 5:69f1634cd40b 756 phy_link_tx_status_e phy_status;
FSL\B36402 5:69f1634cd40b 757 arm_enter_critical();
FSL\B36402 5:69f1634cd40b 758 /*Received ACK sequence must be equal with transmitted packet sequence*/
FSL\B36402 5:69f1634cd40b 759 if(tx_sequence == seq_number)
FSL\B36402 5:69f1634cd40b 760 {
FSL\B36402 5:69f1634cd40b 761 rf_ack_wait_timer_stop();
FSL\B36402 5:69f1634cd40b 762 /*When data pending bit in ACK frame is set, inform NET library*/
FSL\B36402 5:69f1634cd40b 763 if(data_pending)
FSL\B36402 5:69f1634cd40b 764 phy_status = PHY_LINK_TX_DONE_PENDING;
FSL\B36402 5:69f1634cd40b 765 else
FSL\B36402 5:69f1634cd40b 766 phy_status = PHY_LINK_TX_DONE;
FSL\B36402 5:69f1634cd40b 767 /*Call PHY TX Done API*/
FSL\B36402 5:69f1634cd40b 768 arm_net_phy_tx_done(rf_radio_driver_id, mac_tx_handle,phy_status, 1, 1);
FSL\B36402 5:69f1634cd40b 769 }
FSL\B36402 5:69f1634cd40b 770 arm_exit_critical();
FSL\B36402 5:69f1634cd40b 771 }
FSL\B36402 5:69f1634cd40b 772
FSL\B36402 5:69f1634cd40b 773 /*
FSL\B36402 5:69f1634cd40b 774 * \brief Function is a call back for RX end interrupt.
FSL\B36402 5:69f1634cd40b 775 *
FSL\B36402 5:69f1634cd40b 776 * \param none
FSL\B36402 5:69f1634cd40b 777 *
FSL\B36402 5:69f1634cd40b 778 * \return none
FSL\B36402 5:69f1634cd40b 779 */
FSL\B36402 5:69f1634cd40b 780 void rf_handle_rx_end(void)
FSL\B36402 5:69f1634cd40b 781 {
FSL\B36402 5:69f1634cd40b 782 uint8_t rf_lqi;
FSL\B36402 5:69f1634cd40b 783
FSL\B36402 5:69f1634cd40b 784 /*Frame received interrupt*/
FSL\B36402 5:69f1634cd40b 785 if(rf_flags_check(RFF_RX))
FSL\B36402 5:69f1634cd40b 786 {
FSL\B36402 5:69f1634cd40b 787 /*Check CRC_valid bit*/
FSL\B36402 5:69f1634cd40b 788 if(rf_if_check_crc())
FSL\B36402 5:69f1634cd40b 789 {
FSL\B36402 5:69f1634cd40b 790 uint8_t *rf_rx_ptr;
FSL\B36402 5:69f1634cd40b 791 uint8_t receiving_ack = 0;
FSL\B36402 5:69f1634cd40b 792 /*Read length*/
FSL\B36402 5:69f1634cd40b 793 uint8_t len = rf_if_read_received_frame_length();
FSL\B36402 5:69f1634cd40b 794 /*Not ACK frame*/
FSL\B36402 5:69f1634cd40b 795 if(len > 5)
FSL\B36402 5:69f1634cd40b 796 {
FSL\B36402 5:69f1634cd40b 797 rf_rx_ptr = rf_buffer;
FSL\B36402 5:69f1634cd40b 798 }
FSL\B36402 5:69f1634cd40b 799 /*ACK received*/
FSL\B36402 5:69f1634cd40b 800 else
FSL\B36402 5:69f1634cd40b 801 {
FSL\B36402 5:69f1634cd40b 802 /*Read ACK in static ACK buffer*/
FSL\B36402 5:69f1634cd40b 803 receiving_ack = 1;
FSL\B36402 5:69f1634cd40b 804 rf_rx_ptr = ack_rx_buf;
FSL\B36402 5:69f1634cd40b 805 }
FSL\B36402 5:69f1634cd40b 806 /*Check the length is valid*/
FSL\B36402 5:69f1634cd40b 807 if(len > 1 && len < RF_BUFFER_SIZE)
FSL\B36402 5:69f1634cd40b 808 {
FSL\B36402 5:69f1634cd40b 809 /*Read received packet*/
FSL\B36402 5:69f1634cd40b 810 rf_if_read_packet(rf_rx_ptr, len);
FSL\B36402 5:69f1634cd40b 811 /*Get LQI*/
FSL\B36402 5:69f1634cd40b 812 rf_lqi = rf_if_read_lqi();
FSL\B36402 5:69f1634cd40b 813 /*Handle received ACK*/
FSL\B36402 5:69f1634cd40b 814 if(receiving_ack && ((ack_rx_buf[0] & 0x07) == 0x02))
FSL\B36402 5:69f1634cd40b 815 {
FSL\B36402 5:69f1634cd40b 816 uint8_t pending = 0;
FSL\B36402 5:69f1634cd40b 817 /*Check if data is pending*/
FSL\B36402 5:69f1634cd40b 818 if ((ack_rx_buf[0] & 0x10))
FSL\B36402 5:69f1634cd40b 819 {
FSL\B36402 5:69f1634cd40b 820 pending=1;
FSL\B36402 5:69f1634cd40b 821 }
FSL\B36402 5:69f1634cd40b 822 /*Send sequence number in ACK handler*/
FSL\B36402 5:69f1634cd40b 823 rf_handle_ack(ack_rx_buf[2], pending);
FSL\B36402 5:69f1634cd40b 824 }
FSL\B36402 5:69f1634cd40b 825 /*Handle received data*/
FSL\B36402 5:69f1634cd40b 826 else if(rf_if_read_trx_state() != RX_ON && rf_if_read_trx_state() != BUSY_RX)
FSL\B36402 5:69f1634cd40b 827 {
FSL\B36402 5:69f1634cd40b 828 arm_net_phy_rx(rf_buffer,len - 2, rf_lqi, rf_radio_driver_id);
FSL\B36402 5:69f1634cd40b 829 }
FSL\B36402 5:69f1634cd40b 830 }
FSL\B36402 5:69f1634cd40b 831 }
FSL\B36402 5:69f1634cd40b 832 }
FSL\B36402 5:69f1634cd40b 833 /*Start receiver*/
FSL\B36402 5:69f1634cd40b 834 rf_flags_clear(RFF_RX);
FSL\B36402 5:69f1634cd40b 835 rf_receive();
FSL\B36402 5:69f1634cd40b 836 }
FSL\B36402 5:69f1634cd40b 837
FSL\B36402 5:69f1634cd40b 838 /*
FSL\B36402 5:69f1634cd40b 839 * \brief Function is called when MAC is shutting down the radio.
FSL\B36402 5:69f1634cd40b 840 *
FSL\B36402 5:69f1634cd40b 841 * \param none
FSL\B36402 5:69f1634cd40b 842 *
FSL\B36402 5:69f1634cd40b 843 * \return none
FSL\B36402 5:69f1634cd40b 844 */
FSL\B36402 5:69f1634cd40b 845 void rf_shutdown(void)
FSL\B36402 5:69f1634cd40b 846 {
FSL\B36402 5:69f1634cd40b 847 /*Call RF OFF*/
FSL\B36402 5:69f1634cd40b 848 rf_off();
FSL\B36402 5:69f1634cd40b 849 /*Clear RF flags*/
FSL\B36402 5:69f1634cd40b 850 rf_flags_reset();
FSL\B36402 5:69f1634cd40b 851 }
FSL\B36402 5:69f1634cd40b 852
FSL\B36402 5:69f1634cd40b 853 /*
FSL\B36402 5:69f1634cd40b 854 * \brief Function is a call back for TX end interrupt.
FSL\B36402 5:69f1634cd40b 855 *
FSL\B36402 5:69f1634cd40b 856 * \param none
FSL\B36402 5:69f1634cd40b 857 *
FSL\B36402 5:69f1634cd40b 858 * \return none
FSL\B36402 5:69f1634cd40b 859 */
FSL\B36402 5:69f1634cd40b 860 void rf_handle_tx_end(void)
FSL\B36402 5:69f1634cd40b 861 {
FSL\B36402 5:69f1634cd40b 862 phy_link_tx_status_e phy_status = PHY_LINK_TX_SUCCESS;
FSL\B36402 5:69f1634cd40b 863
FSL\B36402 5:69f1634cd40b 864 rf_rx_mode = 0;
FSL\B36402 5:69f1634cd40b 865 /*If ACK is needed for this transmission*/
FSL\B36402 5:69f1634cd40b 866 if(need_ack && rf_flags_check(RFF_TX))
FSL\B36402 5:69f1634cd40b 867 {
FSL\B36402 5:69f1634cd40b 868 rf_ack_wait_timer_start(rf_ack_wait_duration);
FSL\B36402 5:69f1634cd40b 869 rf_rx_mode = 1;
FSL\B36402 5:69f1634cd40b 870 }
FSL\B36402 5:69f1634cd40b 871 rf_flags_clear(RFF_RX);
FSL\B36402 5:69f1634cd40b 872 /*Start receiver*/
FSL\B36402 5:69f1634cd40b 873 rf_receive();
FSL\B36402 5:69f1634cd40b 874
FSL\B36402 5:69f1634cd40b 875 /*Call PHY TX Done API*/
FSL\B36402 5:69f1634cd40b 876 arm_net_phy_tx_done(rf_radio_driver_id, mac_tx_handle, phy_status, 1, 1);
FSL\B36402 5:69f1634cd40b 877 }
FSL\B36402 5:69f1634cd40b 878
FSL\B36402 5:69f1634cd40b 879 /*
FSL\B36402 5:69f1634cd40b 880 * \brief Function is a call back for CCA ED done interrupt.
FSL\B36402 5:69f1634cd40b 881 *
FSL\B36402 5:69f1634cd40b 882 * \param none
FSL\B36402 5:69f1634cd40b 883 *
FSL\B36402 5:69f1634cd40b 884 * \return none
FSL\B36402 5:69f1634cd40b 885 */
FSL\B36402 5:69f1634cd40b 886 void rf_handle_cca_ed_done(void)
FSL\B36402 5:69f1634cd40b 887 {
FSL\B36402 5:69f1634cd40b 888 rf_flags_clear(RFF_CCA);
FSL\B36402 5:69f1634cd40b 889 /*Check the result of CCA process*/
FSL\B36402 5:69f1634cd40b 890 if(rf_if_check_cca())
FSL\B36402 5:69f1634cd40b 891 {
FSL\B36402 5:69f1634cd40b 892 rf_start_tx();
FSL\B36402 5:69f1634cd40b 893 }
FSL\B36402 5:69f1634cd40b 894 else
FSL\B36402 5:69f1634cd40b 895 {
FSL\B36402 5:69f1634cd40b 896 /*Send CCA fail notification*/
FSL\B36402 5:69f1634cd40b 897 arm_net_phy_tx_done(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 1);
FSL\B36402 5:69f1634cd40b 898 }
FSL\B36402 5:69f1634cd40b 899 }
FSL\B36402 5:69f1634cd40b 900
FSL\B36402 5:69f1634cd40b 901 /*
FSL\B36402 5:69f1634cd40b 902 * \brief Function sets the TX power variable.
FSL\B36402 5:69f1634cd40b 903 *
FSL\B36402 5:69f1634cd40b 904 * \param power TX power setting
FSL\B36402 5:69f1634cd40b 905 *
FSL\B36402 5:69f1634cd40b 906 * \return 0 Success
FSL\B36402 5:69f1634cd40b 907 * \return -1 Fail
FSL\B36402 5:69f1634cd40b 908 */
FSL\B36402 5:69f1634cd40b 909 int8_t rf_tx_power_set(uint8_t power)
FSL\B36402 5:69f1634cd40b 910 {
FSL\B36402 5:69f1634cd40b 911 int8_t ret_val = -1;
FSL\B36402 5:69f1634cd40b 912 if(power < 16)
FSL\B36402 5:69f1634cd40b 913 {
FSL\B36402 5:69f1634cd40b 914 radio_tx_power = power;
FSL\B36402 5:69f1634cd40b 915 ret_val = 0;
FSL\B36402 5:69f1634cd40b 916 }
FSL\B36402 5:69f1634cd40b 917 return ret_val;
FSL\B36402 5:69f1634cd40b 918 }
FSL\B36402 5:69f1634cd40b 919
FSL\B36402 5:69f1634cd40b 920 /*
FSL\B36402 5:69f1634cd40b 921 * \brief Function returns the TX power variable.
FSL\B36402 5:69f1634cd40b 922 *
FSL\B36402 5:69f1634cd40b 923 * \param none
FSL\B36402 5:69f1634cd40b 924 *
FSL\B36402 5:69f1634cd40b 925 * \return radio_tx_power TX power variable
FSL\B36402 5:69f1634cd40b 926 */
FSL\B36402 5:69f1634cd40b 927 uint8_t rf_tx_power_get(void)
FSL\B36402 5:69f1634cd40b 928 {
FSL\B36402 5:69f1634cd40b 929 return radio_tx_power;
FSL\B36402 5:69f1634cd40b 930 }
FSL\B36402 5:69f1634cd40b 931
FSL\B36402 5:69f1634cd40b 932 /*
FSL\B36402 5:69f1634cd40b 933 * \brief Function sets the RF RPC variable.
FSL\B36402 5:69f1634cd40b 934 *
FSL\B36402 5:69f1634cd40b 935 * \param rpc_value RPC setting
FSL\B36402 5:69f1634cd40b 936 *
FSL\B36402 5:69f1634cd40b 937 * \return 0 Success
FSL\B36402 5:69f1634cd40b 938 */
FSL\B36402 5:69f1634cd40b 939 int8_t rf_rpc_set(uint8_t rpc_value)
FSL\B36402 5:69f1634cd40b 940 {
FSL\B36402 5:69f1634cd40b 941 int8_t ret_val = -1;
FSL\B36402 5:69f1634cd40b 942 radio_rpc_value = rpc_value;
FSL\B36402 5:69f1634cd40b 943 ret_val = 0;
FSL\B36402 5:69f1634cd40b 944 return ret_val;
FSL\B36402 5:69f1634cd40b 945 }
FSL\B36402 5:69f1634cd40b 946
FSL\B36402 5:69f1634cd40b 947 /*
FSL\B36402 5:69f1634cd40b 948 * \brief Function enables the usage of Front end.
FSL\B36402 5:69f1634cd40b 949 *
FSL\B36402 5:69f1634cd40b 950 * \param none
FSL\B36402 5:69f1634cd40b 951 *
FSL\B36402 5:69f1634cd40b 952 * \return 0 Success
FSL\B36402 5:69f1634cd40b 953 */
FSL\B36402 5:69f1634cd40b 954 int8_t rf_enable_pa(void)
FSL\B36402 5:69f1634cd40b 955 {
FSL\B36402 5:69f1634cd40b 956 int8_t ret_val = 0;
FSL\B36402 5:69f1634cd40b 957 rf_use_front_end = 1;
FSL\B36402 5:69f1634cd40b 958 return ret_val;
FSL\B36402 5:69f1634cd40b 959 }
FSL\B36402 5:69f1634cd40b 960
FSL\B36402 5:69f1634cd40b 961 /*
FSL\B36402 5:69f1634cd40b 962 * \brief Function enables the usage of Antenna diversity.
FSL\B36402 5:69f1634cd40b 963 *
FSL\B36402 5:69f1634cd40b 964 * \param none
FSL\B36402 5:69f1634cd40b 965 *
FSL\B36402 5:69f1634cd40b 966 * \return 0 Success
FSL\B36402 5:69f1634cd40b 967 */
FSL\B36402 5:69f1634cd40b 968 int8_t rf_enable_antenna_diversity(void)
FSL\B36402 5:69f1634cd40b 969 {
FSL\B36402 5:69f1634cd40b 970 int8_t ret_val = 0;
FSL\B36402 5:69f1634cd40b 971 rf_use_antenna_diversity = 1;
FSL\B36402 5:69f1634cd40b 972 return ret_val;
FSL\B36402 5:69f1634cd40b 973 }
FSL\B36402 5:69f1634cd40b 974
FSL\B36402 5:69f1634cd40b 975 /*
FSL\B36402 5:69f1634cd40b 976 * \brief Function defines the CSD pin of the Front end.
FSL\B36402 5:69f1634cd40b 977 *
FSL\B36402 5:69f1634cd40b 978 * \param port CSD port
FSL\B36402 5:69f1634cd40b 979 * \param port CSD pin
FSL\B36402 5:69f1634cd40b 980 *
FSL\B36402 5:69f1634cd40b 981 * \return 0 Success
FSL\B36402 5:69f1634cd40b 982 */
FSL\B36402 5:69f1634cd40b 983 int8_t rf_set_csd_pin(uint8_t port, uint8_t pin)
FSL\B36402 5:69f1634cd40b 984 {
FSL\B36402 5:69f1634cd40b 985 int8_t ret_val = -1;
FSL\B36402 5:69f1634cd40b 986
FSL\B36402 5:69f1634cd40b 987 rf_csd_port = port;
FSL\B36402 5:69f1634cd40b 988 rf_csd_pin = pin;
FSL\B36402 5:69f1634cd40b 989 ret_val = 0;
FSL\B36402 5:69f1634cd40b 990
FSL\B36402 5:69f1634cd40b 991 return ret_val;
FSL\B36402 5:69f1634cd40b 992 }
FSL\B36402 5:69f1634cd40b 993
FSL\B36402 5:69f1634cd40b 994 /*
FSL\B36402 5:69f1634cd40b 995 * \brief Function defines the CPS pin of the Front end.
FSL\B36402 5:69f1634cd40b 996 *
FSL\B36402 5:69f1634cd40b 997 * \param port CPS port
FSL\B36402 5:69f1634cd40b 998 * \param port CPS pin
FSL\B36402 5:69f1634cd40b 999 *
FSL\B36402 5:69f1634cd40b 1000 * \return 0 Success
FSL\B36402 5:69f1634cd40b 1001 */
FSL\B36402 5:69f1634cd40b 1002 int8_t rf_set_cps_pin(uint8_t port, uint8_t pin)
FSL\B36402 5:69f1634cd40b 1003 {
FSL\B36402 5:69f1634cd40b 1004 int8_t ret_val = -1;
FSL\B36402 5:69f1634cd40b 1005
FSL\B36402 5:69f1634cd40b 1006 rf_cps_port = port;
FSL\B36402 5:69f1634cd40b 1007 rf_cps_pin = pin;
FSL\B36402 5:69f1634cd40b 1008 ret_val = 0;
FSL\B36402 5:69f1634cd40b 1009
FSL\B36402 5:69f1634cd40b 1010 return ret_val;
FSL\B36402 5:69f1634cd40b 1011 }
FSL\B36402 5:69f1634cd40b 1012
FSL\B36402 5:69f1634cd40b 1013 /*
FSL\B36402 5:69f1634cd40b 1014 * \brief Function gives the control of RF states to MAC.
FSL\B36402 5:69f1634cd40b 1015 *
FSL\B36402 5:69f1634cd40b 1016 * \param new_state RF state
FSL\B36402 5:69f1634cd40b 1017 * \param rf_channel RF channel
FSL\B36402 5:69f1634cd40b 1018 *
FSL\B36402 5:69f1634cd40b 1019 * \return 0 Success
FSL\B36402 5:69f1634cd40b 1020 */
FSL\B36402 5:69f1634cd40b 1021 static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel)
FSL\B36402 5:69f1634cd40b 1022 {
FSL\B36402 5:69f1634cd40b 1023 int8_t ret_val = 0;
FSL\B36402 5:69f1634cd40b 1024 switch (new_state)
FSL\B36402 5:69f1634cd40b 1025 {
FSL\B36402 5:69f1634cd40b 1026 /*Reset PHY driver and set to idle*/
FSL\B36402 5:69f1634cd40b 1027 case PHY_INTERFACE_RESET:
FSL\B36402 5:69f1634cd40b 1028 break;
FSL\B36402 5:69f1634cd40b 1029 /*Disable PHY Interface driver*/
FSL\B36402 5:69f1634cd40b 1030 case PHY_INTERFACE_DOWN:
FSL\B36402 5:69f1634cd40b 1031 rf_shutdown();
FSL\B36402 5:69f1634cd40b 1032 break;
FSL\B36402 5:69f1634cd40b 1033 /*Enable PHY Interface driver*/
FSL\B36402 5:69f1634cd40b 1034 case PHY_INTERFACE_UP:
FSL\B36402 5:69f1634cd40b 1035 rf_channel_set(rf_channel);
FSL\B36402 5:69f1634cd40b 1036 rf_receive();
FSL\B36402 5:69f1634cd40b 1037 break;
FSL\B36402 5:69f1634cd40b 1038 /*Enable wireless interface ED scan mode*/
FSL\B36402 5:69f1634cd40b 1039 case PHY_INTERFACE_RX_ENERGY_STATE:
FSL\B36402 5:69f1634cd40b 1040 break;
FSL\B36402 5:69f1634cd40b 1041 }
FSL\B36402 5:69f1634cd40b 1042 return ret_val;
FSL\B36402 5:69f1634cd40b 1043 }
FSL\B36402 5:69f1634cd40b 1044
FSL\B36402 5:69f1634cd40b 1045 /*
FSL\B36402 5:69f1634cd40b 1046 * \brief Function controls the ACK pending, channel setting and energy detection.
FSL\B36402 5:69f1634cd40b 1047 *
FSL\B36402 5:69f1634cd40b 1048 * \param extension_type Type of control
FSL\B36402 5:69f1634cd40b 1049 * \param data_ptr Data from NET library
FSL\B36402 5:69f1634cd40b 1050 *
FSL\B36402 5:69f1634cd40b 1051 * \return 0 Success
FSL\B36402 5:69f1634cd40b 1052 */
FSL\B36402 5:69f1634cd40b 1053 static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr)
FSL\B36402 5:69f1634cd40b 1054 {
FSL\B36402 5:69f1634cd40b 1055 switch (extension_type)
FSL\B36402 5:69f1634cd40b 1056 {
FSL\B36402 5:69f1634cd40b 1057 /*Control MAC pending bit for Indirect data transmission*/
FSL\B36402 5:69f1634cd40b 1058 case PHY_EXTENSION_CTRL_PENDING_BIT:
FSL\B36402 5:69f1634cd40b 1059 if(*data_ptr)
FSL\B36402 5:69f1634cd40b 1060 {
FSL\B36402 5:69f1634cd40b 1061 rf_if_ack_pending_ctrl(1);
FSL\B36402 5:69f1634cd40b 1062 }
FSL\B36402 5:69f1634cd40b 1063 else
FSL\B36402 5:69f1634cd40b 1064 {
FSL\B36402 5:69f1634cd40b 1065 rf_if_ack_pending_ctrl(0);
FSL\B36402 5:69f1634cd40b 1066 }
FSL\B36402 5:69f1634cd40b 1067 break;
FSL\B36402 5:69f1634cd40b 1068 /*Return frame pending status*/
FSL\B36402 5:69f1634cd40b 1069 case PHY_EXTENSION_READ_LAST_ACK_PENDING_STATUS:
FSL\B36402 5:69f1634cd40b 1070 *data_ptr = rf_if_last_acked_pending();
FSL\B36402 5:69f1634cd40b 1071 break;
FSL\B36402 5:69f1634cd40b 1072 /*Set channel*/
FSL\B36402 5:69f1634cd40b 1073 case PHY_EXTENSION_SET_CHANNEL:
FSL\B36402 5:69f1634cd40b 1074 break;
FSL\B36402 5:69f1634cd40b 1075 /*Read energy on the channel*/
FSL\B36402 5:69f1634cd40b 1076 case PHY_EXTENSION_READ_CHANNEL_ENERGY:
FSL\B36402 5:69f1634cd40b 1077 break;
FSL\B36402 5:69f1634cd40b 1078 /*Read status of the link*/
FSL\B36402 5:69f1634cd40b 1079 case PHY_EXTENSION_READ_LINK_STATUS:
FSL\B36402 5:69f1634cd40b 1080 break;
FSL\B36402 5:69f1634cd40b 1081 }
FSL\B36402 5:69f1634cd40b 1082 return 0;
FSL\B36402 5:69f1634cd40b 1083 }
FSL\B36402 5:69f1634cd40b 1084
FSL\B36402 5:69f1634cd40b 1085 /*
FSL\B36402 5:69f1634cd40b 1086 * \brief Function sets the addresses to RF address filters.
FSL\B36402 5:69f1634cd40b 1087 *
FSL\B36402 5:69f1634cd40b 1088 * \param address_type Type of address
FSL\B36402 5:69f1634cd40b 1089 * \param address_ptr Pointer to given address
FSL\B36402 5:69f1634cd40b 1090 *
FSL\B36402 5:69f1634cd40b 1091 * \return 0 Success
FSL\B36402 5:69f1634cd40b 1092 */
FSL\B36402 5:69f1634cd40b 1093 static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr)
FSL\B36402 5:69f1634cd40b 1094 {
FSL\B36402 5:69f1634cd40b 1095 int8_t ret_val = 0;
FSL\B36402 5:69f1634cd40b 1096 switch (address_type)
FSL\B36402 5:69f1634cd40b 1097 {
FSL\B36402 5:69f1634cd40b 1098 /*Set 48-bit address*/
FSL\B36402 5:69f1634cd40b 1099 case PHY_MAC_48BIT:
FSL\B36402 5:69f1634cd40b 1100 break;
FSL\B36402 5:69f1634cd40b 1101 /*Set 64-bit address*/
FSL\B36402 5:69f1634cd40b 1102 case PHY_MAC_64BIT:
FSL\B36402 5:69f1634cd40b 1103 rf_set_address(address_ptr);
FSL\B36402 5:69f1634cd40b 1104 break;
FSL\B36402 5:69f1634cd40b 1105 /*Set 16-bit address*/
FSL\B36402 5:69f1634cd40b 1106 case PHY_MAC_16BIT:
FSL\B36402 5:69f1634cd40b 1107 rf_set_short_adr(address_ptr);
FSL\B36402 5:69f1634cd40b 1108 break;
FSL\B36402 5:69f1634cd40b 1109 /*Set PAN Id*/
FSL\B36402 5:69f1634cd40b 1110 case PHY_MAC_PANID:
FSL\B36402 5:69f1634cd40b 1111 rf_set_pan_id(address_ptr);
FSL\B36402 5:69f1634cd40b 1112 break;
FSL\B36402 5:69f1634cd40b 1113 }
FSL\B36402 5:69f1634cd40b 1114 return ret_val;
FSL\B36402 5:69f1634cd40b 1115 }
FSL\B36402 5:69f1634cd40b 1116
FSL\B36402 5:69f1634cd40b 1117 /*
FSL\B36402 5:69f1634cd40b 1118 * \brief Function initialises the ACK wait time and returns the used PHY mode.
FSL\B36402 5:69f1634cd40b 1119 *
FSL\B36402 5:69f1634cd40b 1120 * \param none
FSL\B36402 5:69f1634cd40b 1121 *
FSL\B36402 5:69f1634cd40b 1122 * \return tmp Used PHY mode
FSL\B36402 5:69f1634cd40b 1123 */
FSL\B36402 5:69f1634cd40b 1124 uint8_t rf_init_phy_mode(void)
FSL\B36402 5:69f1634cd40b 1125 {
FSL\B36402 5:69f1634cd40b 1126 uint8_t tmp;
FSL\B36402 5:69f1634cd40b 1127 /*Read used PHY Mode*/
FSL\B36402 5:69f1634cd40b 1128 tmp = rf_if_read_register(TRX_CTRL_2);
FSL\B36402 5:69f1634cd40b 1129 /*Set ACK wait time for used data rate*/
FSL\B36402 5:69f1634cd40b 1130 if((tmp & 0x1f) == 0x00)
FSL\B36402 5:69f1634cd40b 1131 {
FSL\B36402 5:69f1634cd40b 1132 rf_ack_wait_duration = 938;
FSL\B36402 5:69f1634cd40b 1133 tmp = BPSK_20;
FSL\B36402 5:69f1634cd40b 1134 }
FSL\B36402 5:69f1634cd40b 1135 else if((tmp & 0x1f) == 0x04)
FSL\B36402 5:69f1634cd40b 1136 {
FSL\B36402 5:69f1634cd40b 1137 rf_ack_wait_duration = 469;
FSL\B36402 5:69f1634cd40b 1138 tmp = BPSK_40;
FSL\B36402 5:69f1634cd40b 1139 }
FSL\B36402 5:69f1634cd40b 1140 else if((tmp & 0x1f) == 0x14)
FSL\B36402 5:69f1634cd40b 1141 {
FSL\B36402 5:69f1634cd40b 1142 rf_ack_wait_duration = 469;
FSL\B36402 5:69f1634cd40b 1143 tmp = BPSK_40_ALT;
FSL\B36402 5:69f1634cd40b 1144 }
FSL\B36402 5:69f1634cd40b 1145 else if((tmp & 0x1f) == 0x08)
FSL\B36402 5:69f1634cd40b 1146 {
FSL\B36402 5:69f1634cd40b 1147 rf_ack_wait_duration = 100;
FSL\B36402 5:69f1634cd40b 1148 tmp = OQPSK_SIN_RC_100;
FSL\B36402 5:69f1634cd40b 1149 }
FSL\B36402 5:69f1634cd40b 1150 else if((tmp & 0x1f) == 0x09)
FSL\B36402 5:69f1634cd40b 1151 {
FSL\B36402 5:69f1634cd40b 1152 rf_ack_wait_duration = 50;
FSL\B36402 5:69f1634cd40b 1153 tmp = OQPSK_SIN_RC_200;
FSL\B36402 5:69f1634cd40b 1154 }
FSL\B36402 5:69f1634cd40b 1155 else if((tmp & 0x1f) == 0x18)
FSL\B36402 5:69f1634cd40b 1156 {
FSL\B36402 5:69f1634cd40b 1157 rf_ack_wait_duration = 100;
FSL\B36402 5:69f1634cd40b 1158 tmp = OQPSK_RC_100;
FSL\B36402 5:69f1634cd40b 1159 }
FSL\B36402 5:69f1634cd40b 1160 else if((tmp & 0x1f) == 0x19)
FSL\B36402 5:69f1634cd40b 1161 {
FSL\B36402 5:69f1634cd40b 1162 rf_ack_wait_duration = 50;
FSL\B36402 5:69f1634cd40b 1163 tmp = OQPSK_RC_200;
FSL\B36402 5:69f1634cd40b 1164 }
FSL\B36402 5:69f1634cd40b 1165 else if((tmp & 0x1f) == 0x0c)
FSL\B36402 5:69f1634cd40b 1166 {
FSL\B36402 5:69f1634cd40b 1167 rf_ack_wait_duration = 50;
FSL\B36402 5:69f1634cd40b 1168 tmp = OQPSK_SIN_250;
FSL\B36402 5:69f1634cd40b 1169 }
FSL\B36402 5:69f1634cd40b 1170 else if((tmp & 0x1f) == 0x0d)
FSL\B36402 5:69f1634cd40b 1171 {
FSL\B36402 5:69f1634cd40b 1172 rf_ack_wait_duration = 25;
FSL\B36402 5:69f1634cd40b 1173 tmp = OQPSK_SIN_500;
FSL\B36402 5:69f1634cd40b 1174 }
FSL\B36402 5:69f1634cd40b 1175 else if((tmp & 0x1f) == 0x0f)
FSL\B36402 5:69f1634cd40b 1176 {
FSL\B36402 5:69f1634cd40b 1177 rf_ack_wait_duration = 25;
FSL\B36402 5:69f1634cd40b 1178 tmp = OQPSK_SIN_500_ALT;
FSL\B36402 5:69f1634cd40b 1179 }
FSL\B36402 5:69f1634cd40b 1180 else if((tmp & 0x1f) == 0x1c)
FSL\B36402 5:69f1634cd40b 1181 {
FSL\B36402 5:69f1634cd40b 1182 rf_ack_wait_duration = 50;
FSL\B36402 5:69f1634cd40b 1183 tmp = OQPSK_RC_250;
FSL\B36402 5:69f1634cd40b 1184 }
FSL\B36402 5:69f1634cd40b 1185 else if((tmp & 0x1f) == 0x1d)
FSL\B36402 5:69f1634cd40b 1186 {
FSL\B36402 5:69f1634cd40b 1187 rf_ack_wait_duration = 25;
FSL\B36402 5:69f1634cd40b 1188 tmp = OQPSK_RC_500;
FSL\B36402 5:69f1634cd40b 1189 }
FSL\B36402 5:69f1634cd40b 1190 else if((tmp & 0x1f) == 0x1f)
FSL\B36402 5:69f1634cd40b 1191 {
FSL\B36402 5:69f1634cd40b 1192 rf_ack_wait_duration = 25;
FSL\B36402 5:69f1634cd40b 1193 tmp = OQPSK_RC_500_ALT;
FSL\B36402 5:69f1634cd40b 1194 }
FSL\B36402 5:69f1634cd40b 1195 else if((tmp & 0x3f) == 0x2A)
FSL\B36402 5:69f1634cd40b 1196 {
FSL\B36402 5:69f1634cd40b 1197 rf_ack_wait_duration = 25;
FSL\B36402 5:69f1634cd40b 1198 tmp = OQPSK_SIN_RC_400_SCR_ON;
FSL\B36402 5:69f1634cd40b 1199 }
FSL\B36402 5:69f1634cd40b 1200 else if((tmp & 0x3f) == 0x0A)
FSL\B36402 5:69f1634cd40b 1201 {
FSL\B36402 5:69f1634cd40b 1202 rf_ack_wait_duration = 25;
FSL\B36402 5:69f1634cd40b 1203 tmp = OQPSK_SIN_RC_400_SCR_OFF;
FSL\B36402 5:69f1634cd40b 1204 }
FSL\B36402 5:69f1634cd40b 1205 else if((tmp & 0x3f) == 0x3A)
FSL\B36402 5:69f1634cd40b 1206 {
FSL\B36402 5:69f1634cd40b 1207 rf_ack_wait_duration = 25;
FSL\B36402 5:69f1634cd40b 1208 tmp = OQPSK_RC_400_SCR_ON;
FSL\B36402 5:69f1634cd40b 1209 }
FSL\B36402 5:69f1634cd40b 1210 else if((tmp & 0x3f) == 0x1A)
FSL\B36402 5:69f1634cd40b 1211 {
FSL\B36402 5:69f1634cd40b 1212 rf_ack_wait_duration = 25;
FSL\B36402 5:69f1634cd40b 1213 tmp = OQPSK_RC_400_SCR_OFF;
FSL\B36402 5:69f1634cd40b 1214 }
FSL\B36402 5:69f1634cd40b 1215 else if((tmp & 0x3f) == 0x2E)
FSL\B36402 5:69f1634cd40b 1216 {
FSL\B36402 5:69f1634cd40b 1217 rf_ack_wait_duration = 13;
FSL\B36402 5:69f1634cd40b 1218 tmp = OQPSK_SIN_1000_SCR_ON;
FSL\B36402 5:69f1634cd40b 1219 }
FSL\B36402 5:69f1634cd40b 1220 else if((tmp & 0x3f) == 0x0E)
FSL\B36402 5:69f1634cd40b 1221 {
FSL\B36402 5:69f1634cd40b 1222 rf_ack_wait_duration = 13;
FSL\B36402 5:69f1634cd40b 1223 tmp = OQPSK_SIN_1000_SCR_OFF;
FSL\B36402 5:69f1634cd40b 1224 }
FSL\B36402 5:69f1634cd40b 1225 else if((tmp & 0x3f) == 0x3E)
FSL\B36402 5:69f1634cd40b 1226 {
FSL\B36402 5:69f1634cd40b 1227 rf_ack_wait_duration = 13;
FSL\B36402 5:69f1634cd40b 1228 tmp = OQPSK_RC_1000_SCR_ON;
FSL\B36402 5:69f1634cd40b 1229 }
FSL\B36402 5:69f1634cd40b 1230 else if((tmp & 0x3f) == 0x1E)
FSL\B36402 5:69f1634cd40b 1231 {
FSL\B36402 5:69f1634cd40b 1232 rf_ack_wait_duration = 13;
FSL\B36402 5:69f1634cd40b 1233 tmp = OQPSK_RC_1000_SCR_OFF;
FSL\B36402 5:69f1634cd40b 1234 }
FSL\B36402 5:69f1634cd40b 1235 return tmp;
FSL\B36402 5:69f1634cd40b 1236 }
FSL\B36402 5:69f1634cd40b 1237