Dongha Shin / Mbed OS lab07-pc-esp-115200

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main.cpp@0:0d96af962118, 2022-05-22 (annotated)

Committer:
dshin
Date:
Sun May 22 19:23:55 2022 +0000
Revision:
0:0d96af962118
pc-esp-115200

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dshin 0:0d96af962118 1 // ======================================================================
dshin 0:0d96af962118 2
dshin 0:0d96af962118 3 #include "mbed.h"
dshin 0:0d96af962118 4
dshin 0:0d96af962118 5 RawSerial PC(USBTX, USBRX); // PC = (USBTX=TX, USBRX=RX)
dshin 0:0d96af962118 6 RawSerial ESP(D1, D0); // ESP = (D1=TX, D0=RX)
dshin 0:0d96af962118 7
dshin 0:0d96af962118 8 /// ======================================================================
dshin 0:0d96af962118 9 // ISR for redirecting PC RX to ESP TX
dshin 0:0d96af962118 10
dshin 0:0d96af962118 11 void ISR_PC_to_ESP()
dshin 0:0d96af962118 12 {
dshin 0:0d96af962118 13 while(PC.readable()) {
dshin 0:0d96af962118 14 ESP.putc(PC.getc());
dshin 0:0d96af962118 15 }
dshin 0:0d96af962118 16 }
dshin 0:0d96af962118 17
dshin 0:0d96af962118 18 // ======================================================================
dshin 0:0d96af962118 19 // ISR for redirecting ESP RX to PC TX
dshin 0:0d96af962118 20
dshin 0:0d96af962118 21 void ISR_ESP_to_PC()
dshin 0:0d96af962118 22 {
dshin 0:0d96af962118 23 while(ESP.readable()) {
dshin 0:0d96af962118 24 PC.putc(ESP.getc());
dshin 0:0d96af962118 25 }
dshin 0:0d96af962118 26 }
dshin 0:0d96af962118 27
dshin 0:0d96af962118 28 // ======================================================================
dshin 0:0d96af962118 29 // Main thread
dshin 0:0d96af962118 30
dshin 0:0d96af962118 31 int main()
dshin 0:0d96af962118 32 {
dshin 0:0d96af962118 33 PC.baud(115200);
dshin 0:0d96af962118 34 ESP.baud(115200);
dshin 0:0d96af962118 35
dshin 0:0d96af962118 36 PC.attach(&ISR_PC_to_ESP, Serial::RxIrq);
dshin 0:0d96af962118 37 ESP.attach(&ISR_ESP_to_PC, Serial::RxIrq);
dshin 0:0d96af962118 38
dshin 0:0d96af962118 39 while(1) {
dshin 0:0d96af962118 40 sleep();
dshin 0:0d96af962118 41 }
dshin 0:0d96af962118 42 }
dshin 0:0d96af962118 43
dshin 0:0d96af962118 44 // ======================================================================