Peter Drescher / mbed-F401

mbed library with additional peripherals for ST F401 board

Fork of mbed-src by mbed official

This mbed LIB has additional peripherals for ST F401 board

  • UART2 : PA_3 rx, PA_2 tx
  • UART3 : PC_7 rx, PC_6 tx
  • I2C2 : PB_3 SDA, PB_10 SCL
  • I2C3 : PB_4 SDA, PA_8 SCL

targets/cmsis/TARGET_NORDIC/TARGET_NRF51822/nrf51.h@85:e1a8e879a6a9, 2014-02-07 (annotated)

Committer:
mbed_official
Date:
Fri Feb 07 18:00:11 2014 +0000
Revision:
85:e1a8e879a6a9
Child:
104:a6a92e2e5a92
Synchronized with git revision 4b2b368a6a3b1f0fd33d99917981c67436c4aebe



Full URL: https://github.com/mbedmicro/mbed/commit/4b2b368a6a3b1f0fd33d99917981c67436c4aebe/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 85:e1a8e879a6a9 1 /* mbed Microcontroller Library
mbed_official 85:e1a8e879a6a9 2
mbed_official 85:e1a8e879a6a9 3 * Copyright (c) 2006-2013 ARM Limited
mbed_official 85:e1a8e879a6a9 4 *
mbed_official 85:e1a8e879a6a9 5 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 85:e1a8e879a6a9 6 * you may not use this file except in compliance with the License.
mbed_official 85:e1a8e879a6a9 7 * You may obtain a copy of the License at
mbed_official 85:e1a8e879a6a9 8 *
mbed_official 85:e1a8e879a6a9 9 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 85:e1a8e879a6a9 10 *
mbed_official 85:e1a8e879a6a9 11 * Unless required by applicable law or agreed to in writing, software
mbed_official 85:e1a8e879a6a9 12 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 85:e1a8e879a6a9 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 85:e1a8e879a6a9 14 * See the License for the specific language governing permissions and
mbed_official 85:e1a8e879a6a9 15 * limitations under the License.
mbed_official 85:e1a8e879a6a9 16 */
mbed_official 85:e1a8e879a6a9 17
mbed_official 85:e1a8e879a6a9 18
mbed_official 85:e1a8e879a6a9 19
mbed_official 85:e1a8e879a6a9 20 /** @addtogroup Nordic Semiconductor
mbed_official 85:e1a8e879a6a9 21 * @{
mbed_official 85:e1a8e879a6a9 22 */
mbed_official 85:e1a8e879a6a9 23
mbed_official 85:e1a8e879a6a9 24 /** @addtogroup nRF51
mbed_official 85:e1a8e879a6a9 25 * @{
mbed_official 85:e1a8e879a6a9 26 */
mbed_official 85:e1a8e879a6a9 27
mbed_official 85:e1a8e879a6a9 28 #ifndef NRF51_H
mbed_official 85:e1a8e879a6a9 29 #define NRF51_H
mbed_official 85:e1a8e879a6a9 30
mbed_official 85:e1a8e879a6a9 31 #ifdef __cplusplus
mbed_official 85:e1a8e879a6a9 32 extern "C" {
mbed_official 85:e1a8e879a6a9 33 #endif
mbed_official 85:e1a8e879a6a9 34
mbed_official 85:e1a8e879a6a9 35
mbed_official 85:e1a8e879a6a9 36 /* ------------------------- Interrupt Number Definition ------------------------ */
mbed_official 85:e1a8e879a6a9 37
mbed_official 85:e1a8e879a6a9 38 typedef enum {
mbed_official 85:e1a8e879a6a9 39 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
mbed_official 85:e1a8e879a6a9 40 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
mbed_official 85:e1a8e879a6a9 41 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
mbed_official 85:e1a8e879a6a9 42 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
mbed_official 85:e1a8e879a6a9 43 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
mbed_official 85:e1a8e879a6a9 44 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
mbed_official 85:e1a8e879a6a9 45 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
mbed_official 85:e1a8e879a6a9 46 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
mbed_official 85:e1a8e879a6a9 47 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
mbed_official 85:e1a8e879a6a9 48 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
mbed_official 85:e1a8e879a6a9 49 RADIO_IRQn = 1, /*!< 1 RADIO */
mbed_official 85:e1a8e879a6a9 50 UART0_IRQn = 2, /*!< 2 UART0 */
mbed_official 85:e1a8e879a6a9 51 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
mbed_official 85:e1a8e879a6a9 52 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
mbed_official 85:e1a8e879a6a9 53 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
mbed_official 85:e1a8e879a6a9 54 ADC_IRQn = 7, /*!< 7 ADC */
mbed_official 85:e1a8e879a6a9 55 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
mbed_official 85:e1a8e879a6a9 56 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
mbed_official 85:e1a8e879a6a9 57 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
mbed_official 85:e1a8e879a6a9 58 RTC0_IRQn = 11, /*!< 11 RTC0 */
mbed_official 85:e1a8e879a6a9 59 TEMP_IRQn = 12, /*!< 12 TEMP */
mbed_official 85:e1a8e879a6a9 60 RNG_IRQn = 13, /*!< 13 RNG */
mbed_official 85:e1a8e879a6a9 61 ECB_IRQn = 14, /*!< 14 ECB */
mbed_official 85:e1a8e879a6a9 62 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
mbed_official 85:e1a8e879a6a9 63 WDT_IRQn = 16, /*!< 16 WDT */
mbed_official 85:e1a8e879a6a9 64 RTC1_IRQn = 17, /*!< 17 RTC1 */
mbed_official 85:e1a8e879a6a9 65 QDEC_IRQn = 18, /*!< 18 QDEC */
mbed_official 85:e1a8e879a6a9 66 LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */
mbed_official 85:e1a8e879a6a9 67 SWI0_IRQn = 20, /*!< 20 SWI0 */
mbed_official 85:e1a8e879a6a9 68 SWI1_IRQn = 21, /*!< 21 SWI1 */
mbed_official 85:e1a8e879a6a9 69 SWI2_IRQn = 22, /*!< 22 SWI2 */
mbed_official 85:e1a8e879a6a9 70 SWI3_IRQn = 23, /*!< 23 SWI3 */
mbed_official 85:e1a8e879a6a9 71 SWI4_IRQn = 24, /*!< 24 SWI4 */
mbed_official 85:e1a8e879a6a9 72 SWI5_IRQn = 25 /*!< 25 SWI5 */
mbed_official 85:e1a8e879a6a9 73 } IRQn_Type;
mbed_official 85:e1a8e879a6a9 74
mbed_official 85:e1a8e879a6a9 75
mbed_official 85:e1a8e879a6a9 76 /** @addtogroup Configuration_of_CMSIS
mbed_official 85:e1a8e879a6a9 77 * @{
mbed_official 85:e1a8e879a6a9 78 */
mbed_official 85:e1a8e879a6a9 79
mbed_official 85:e1a8e879a6a9 80
mbed_official 85:e1a8e879a6a9 81 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 82 /* ================ Processor and Core Peripheral Section ================ */
mbed_official 85:e1a8e879a6a9 83 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 84
mbed_official 85:e1a8e879a6a9 85 /* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */
mbed_official 85:e1a8e879a6a9 86 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
mbed_official 85:e1a8e879a6a9 87 #define __MPU_PRESENT 0 /*!< MPU present or not */
mbed_official 85:e1a8e879a6a9 88 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
mbed_official 85:e1a8e879a6a9 89 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 85:e1a8e879a6a9 90 /** @} */ /* End of group Configuration_of_CMSIS */
mbed_official 85:e1a8e879a6a9 91
mbed_official 85:e1a8e879a6a9 92 #include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
mbed_official 85:e1a8e879a6a9 93 #include "system_nrf51822.h" /*!< nRF51 System */
mbed_official 85:e1a8e879a6a9 94
mbed_official 85:e1a8e879a6a9 95
mbed_official 85:e1a8e879a6a9 96 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 97 /* ================ Device Specific Peripheral Section ================ */
mbed_official 85:e1a8e879a6a9 98 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 99
mbed_official 85:e1a8e879a6a9 100
mbed_official 85:e1a8e879a6a9 101 /** @addtogroup Device_Peripheral_Registers
mbed_official 85:e1a8e879a6a9 102 * @{
mbed_official 85:e1a8e879a6a9 103 */
mbed_official 85:e1a8e879a6a9 104
mbed_official 85:e1a8e879a6a9 105
mbed_official 85:e1a8e879a6a9 106 /* ------------------- Start of section using anonymous unions ------------------ */
mbed_official 85:e1a8e879a6a9 107 #if defined(__CC_ARM)
mbed_official 85:e1a8e879a6a9 108 #pragma push
mbed_official 85:e1a8e879a6a9 109 #pragma anon_unions
mbed_official 85:e1a8e879a6a9 110 #elif defined(__ICCARM__)
mbed_official 85:e1a8e879a6a9 111 #pragma language=extended
mbed_official 85:e1a8e879a6a9 112 #elif defined(__GNUC__)
mbed_official 85:e1a8e879a6a9 113 /* anonymous unions are enabled by default */
mbed_official 85:e1a8e879a6a9 114 #elif defined(__TMS470__)
mbed_official 85:e1a8e879a6a9 115 /* anonymous unions are enabled by default */
mbed_official 85:e1a8e879a6a9 116 #elif defined(__TASKING__)
mbed_official 85:e1a8e879a6a9 117 #pragma warning 586
mbed_official 85:e1a8e879a6a9 118 #else
mbed_official 85:e1a8e879a6a9 119 #warning Not supported compiler type
mbed_official 85:e1a8e879a6a9 120 #endif
mbed_official 85:e1a8e879a6a9 121
mbed_official 85:e1a8e879a6a9 122
mbed_official 85:e1a8e879a6a9 123 typedef struct {
mbed_official 85:e1a8e879a6a9 124 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
mbed_official 85:e1a8e879a6a9 125 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
mbed_official 85:e1a8e879a6a9 126 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
mbed_official 85:e1a8e879a6a9 127 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
mbed_official 85:e1a8e879a6a9 128 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
mbed_official 85:e1a8e879a6a9 129 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
mbed_official 85:e1a8e879a6a9 130 } AMLI_RAMPRI_Type;
mbed_official 85:e1a8e879a6a9 131
mbed_official 85:e1a8e879a6a9 132 typedef struct {
mbed_official 85:e1a8e879a6a9 133 __O uint32_t EN; /*!< Enable channel group. */
mbed_official 85:e1a8e879a6a9 134 __O uint32_t DIS; /*!< Disable channel group. */
mbed_official 85:e1a8e879a6a9 135 } PPI_TASKS_CHG_Type;
mbed_official 85:e1a8e879a6a9 136
mbed_official 85:e1a8e879a6a9 137 typedef struct {
mbed_official 85:e1a8e879a6a9 138 __IO uint32_t EEP; /*!< Channel event end-point. */
mbed_official 85:e1a8e879a6a9 139 __IO uint32_t TEP; /*!< Channel task end-point. */
mbed_official 85:e1a8e879a6a9 140 } PPI_CH_Type;
mbed_official 85:e1a8e879a6a9 141
mbed_official 85:e1a8e879a6a9 142
mbed_official 85:e1a8e879a6a9 143 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 144 /* ================ POWER ================ */
mbed_official 85:e1a8e879a6a9 145 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 146
mbed_official 85:e1a8e879a6a9 147
mbed_official 85:e1a8e879a6a9 148 /**
mbed_official 85:e1a8e879a6a9 149 * @brief Power Control. (POWER)
mbed_official 85:e1a8e879a6a9 150 */
mbed_official 85:e1a8e879a6a9 151
mbed_official 85:e1a8e879a6a9 152 typedef struct { /*!< POWER Structure */
mbed_official 85:e1a8e879a6a9 153 __I uint32_t RESERVED0[30];
mbed_official 85:e1a8e879a6a9 154 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
mbed_official 85:e1a8e879a6a9 155 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
mbed_official 85:e1a8e879a6a9 156 __I uint32_t RESERVED1[34];
mbed_official 85:e1a8e879a6a9 157 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
mbed_official 85:e1a8e879a6a9 158 __I uint32_t RESERVED2[126];
mbed_official 85:e1a8e879a6a9 159 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 160 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 161 __I uint32_t RESERVED3[61];
mbed_official 85:e1a8e879a6a9 162 __IO uint32_t RESETREAS; /*!< Reset reason. */
mbed_official 85:e1a8e879a6a9 163 __I uint32_t RESERVED4[63];
mbed_official 85:e1a8e879a6a9 164 __O uint32_t SYSTEMOFF; /*!< System off register. */
mbed_official 85:e1a8e879a6a9 165 __I uint32_t RESERVED5[3];
mbed_official 85:e1a8e879a6a9 166 __IO uint32_t POFCON; /*!< Power failure configuration. */
mbed_official 85:e1a8e879a6a9 167 __I uint32_t RESERVED6[2];
mbed_official 85:e1a8e879a6a9 168 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
mbed_official 85:e1a8e879a6a9 169 register. */
mbed_official 85:e1a8e879a6a9 170 __I uint32_t RESERVED7;
mbed_official 85:e1a8e879a6a9 171 __IO uint32_t RAMON; /*!< Ram on/off. */
mbed_official 85:e1a8e879a6a9 172 __I uint32_t RESERVED8[7];
mbed_official 85:e1a8e879a6a9 173 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
mbed_official 85:e1a8e879a6a9 174 is a retained register. */
mbed_official 85:e1a8e879a6a9 175 __I uint32_t RESERVED9[12];
mbed_official 85:e1a8e879a6a9 176 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
mbed_official 85:e1a8e879a6a9 177 } NRF_POWER_Type;
mbed_official 85:e1a8e879a6a9 178
mbed_official 85:e1a8e879a6a9 179
mbed_official 85:e1a8e879a6a9 180 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 181 /* ================ CLOCK ================ */
mbed_official 85:e1a8e879a6a9 182 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 183
mbed_official 85:e1a8e879a6a9 184
mbed_official 85:e1a8e879a6a9 185 /**
mbed_official 85:e1a8e879a6a9 186 * @brief Clock control. (CLOCK)
mbed_official 85:e1a8e879a6a9 187 */
mbed_official 85:e1a8e879a6a9 188
mbed_official 85:e1a8e879a6a9 189 typedef struct { /*!< CLOCK Structure */
mbed_official 85:e1a8e879a6a9 190 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
mbed_official 85:e1a8e879a6a9 191 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
mbed_official 85:e1a8e879a6a9 192 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
mbed_official 85:e1a8e879a6a9 193 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
mbed_official 85:e1a8e879a6a9 194 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
mbed_official 85:e1a8e879a6a9 195 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
mbed_official 85:e1a8e879a6a9 196 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
mbed_official 85:e1a8e879a6a9 197 __I uint32_t RESERVED0[57];
mbed_official 85:e1a8e879a6a9 198 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
mbed_official 85:e1a8e879a6a9 199 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
mbed_official 85:e1a8e879a6a9 200 __I uint32_t RESERVED1;
mbed_official 85:e1a8e879a6a9 201 __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */
mbed_official 85:e1a8e879a6a9 202 __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */
mbed_official 85:e1a8e879a6a9 203 __I uint32_t RESERVED2[124];
mbed_official 85:e1a8e879a6a9 204 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 205 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 206 __I uint32_t RESERVED3[64];
mbed_official 85:e1a8e879a6a9 207 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
mbed_official 85:e1a8e879a6a9 208 __I uint32_t RESERVED4[2];
mbed_official 85:e1a8e879a6a9 209 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
mbed_official 85:e1a8e879a6a9 210 __I uint32_t RESERVED5[63];
mbed_official 85:e1a8e879a6a9 211 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
mbed_official 85:e1a8e879a6a9 212 __I uint32_t RESERVED6[7];
mbed_official 85:e1a8e879a6a9 213 __IO uint32_t CTIV; /*!< Calibration timer interval. */
mbed_official 85:e1a8e879a6a9 214 __I uint32_t RESERVED7[5];
mbed_official 85:e1a8e879a6a9 215 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
mbed_official 85:e1a8e879a6a9 216 } NRF_CLOCK_Type;
mbed_official 85:e1a8e879a6a9 217
mbed_official 85:e1a8e879a6a9 218
mbed_official 85:e1a8e879a6a9 219 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 220 /* ================ MPU ================ */
mbed_official 85:e1a8e879a6a9 221 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 222
mbed_official 85:e1a8e879a6a9 223
mbed_official 85:e1a8e879a6a9 224 /**
mbed_official 85:e1a8e879a6a9 225 * @brief Memory Protection Unit. (MPU)
mbed_official 85:e1a8e879a6a9 226 */
mbed_official 85:e1a8e879a6a9 227
mbed_official 85:e1a8e879a6a9 228 typedef struct { /*!< MPU Structure */
mbed_official 85:e1a8e879a6a9 229 __I uint32_t RESERVED0[330];
mbed_official 85:e1a8e879a6a9 230 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
mbed_official 85:e1a8e879a6a9 231 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
mbed_official 85:e1a8e879a6a9 232 __I uint32_t RESERVED1[52];
mbed_official 85:e1a8e879a6a9 233 __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */
mbed_official 85:e1a8e879a6a9 234 __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */
mbed_official 85:e1a8e879a6a9 235 __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */
mbed_official 85:e1a8e879a6a9 236 } NRF_MPU_Type;
mbed_official 85:e1a8e879a6a9 237
mbed_official 85:e1a8e879a6a9 238
mbed_official 85:e1a8e879a6a9 239 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 240 /* ================ PU ================ */
mbed_official 85:e1a8e879a6a9 241 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 242
mbed_official 85:e1a8e879a6a9 243
mbed_official 85:e1a8e879a6a9 244 /**
mbed_official 85:e1a8e879a6a9 245 * @brief Patch unit. (PU)
mbed_official 85:e1a8e879a6a9 246 */
mbed_official 85:e1a8e879a6a9 247
mbed_official 85:e1a8e879a6a9 248 typedef struct { /*!< PU Structure */
mbed_official 85:e1a8e879a6a9 249 __I uint32_t RESERVED0[448];
mbed_official 85:e1a8e879a6a9 250 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
mbed_official 85:e1a8e879a6a9 251 __I uint32_t RESERVED1[24];
mbed_official 85:e1a8e879a6a9 252 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
mbed_official 85:e1a8e879a6a9 253 __I uint32_t RESERVED2[24];
mbed_official 85:e1a8e879a6a9 254 __IO uint32_t PATCHEN; /*!< Patch enable register. */
mbed_official 85:e1a8e879a6a9 255 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
mbed_official 85:e1a8e879a6a9 256 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
mbed_official 85:e1a8e879a6a9 257 } NRF_PU_Type;
mbed_official 85:e1a8e879a6a9 258
mbed_official 85:e1a8e879a6a9 259
mbed_official 85:e1a8e879a6a9 260 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 261 /* ================ AMLI ================ */
mbed_official 85:e1a8e879a6a9 262 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 263
mbed_official 85:e1a8e879a6a9 264
mbed_official 85:e1a8e879a6a9 265 /**
mbed_official 85:e1a8e879a6a9 266 * @brief AHB Multi-Layer Interface. (AMLI)
mbed_official 85:e1a8e879a6a9 267 */
mbed_official 85:e1a8e879a6a9 268
mbed_official 85:e1a8e879a6a9 269 typedef struct { /*!< AMLI Structure */
mbed_official 85:e1a8e879a6a9 270 __I uint32_t RESERVED0[896];
mbed_official 85:e1a8e879a6a9 271 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
mbed_official 85:e1a8e879a6a9 272 } NRF_AMLI_Type;
mbed_official 85:e1a8e879a6a9 273
mbed_official 85:e1a8e879a6a9 274
mbed_official 85:e1a8e879a6a9 275 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 276 /* ================ RADIO ================ */
mbed_official 85:e1a8e879a6a9 277 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 278
mbed_official 85:e1a8e879a6a9 279
mbed_official 85:e1a8e879a6a9 280 /**
mbed_official 85:e1a8e879a6a9 281 * @brief The radio. (RADIO)
mbed_official 85:e1a8e879a6a9 282 */
mbed_official 85:e1a8e879a6a9 283
mbed_official 85:e1a8e879a6a9 284 typedef struct { /*!< RADIO Structure */
mbed_official 85:e1a8e879a6a9 285 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
mbed_official 85:e1a8e879a6a9 286 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
mbed_official 85:e1a8e879a6a9 287 __O uint32_t TASKS_START; /*!< Start radio. */
mbed_official 85:e1a8e879a6a9 288 __O uint32_t TASKS_STOP; /*!< Stop radio. */
mbed_official 85:e1a8e879a6a9 289 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
mbed_official 85:e1a8e879a6a9 290 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
mbed_official 85:e1a8e879a6a9 291 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
mbed_official 85:e1a8e879a6a9 292 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
mbed_official 85:e1a8e879a6a9 293 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
mbed_official 85:e1a8e879a6a9 294 __I uint32_t RESERVED0[55];
mbed_official 85:e1a8e879a6a9 295 __IO uint32_t EVENTS_READY; /*!< Ready event. */
mbed_official 85:e1a8e879a6a9 296 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
mbed_official 85:e1a8e879a6a9 297 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
mbed_official 85:e1a8e879a6a9 298 __IO uint32_t EVENTS_END; /*!< End event. */
mbed_official 85:e1a8e879a6a9 299 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
mbed_official 85:e1a8e879a6a9 300 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
mbed_official 85:e1a8e879a6a9 301 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
mbed_official 85:e1a8e879a6a9 302 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
mbed_official 85:e1a8e879a6a9 303 sample is ready for readout at the RSSISAMPLE register. */
mbed_official 85:e1a8e879a6a9 304 __I uint32_t RESERVED1[2];
mbed_official 85:e1a8e879a6a9 305 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
mbed_official 85:e1a8e879a6a9 306 __I uint32_t RESERVED2[53];
mbed_official 85:e1a8e879a6a9 307 __IO uint32_t SHORTS; /*!< Shortcut for the radio. */
mbed_official 85:e1a8e879a6a9 308 __I uint32_t RESERVED3[64];
mbed_official 85:e1a8e879a6a9 309 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 310 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 311 __I uint32_t RESERVED4[61];
mbed_official 85:e1a8e879a6a9 312 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
mbed_official 85:e1a8e879a6a9 313 __I uint32_t RESERVED5;
mbed_official 85:e1a8e879a6a9 314 __I uint32_t RXMATCH; /*!< Received address. */
mbed_official 85:e1a8e879a6a9 315 __I uint32_t RXCRC; /*!< Received CRC. */
mbed_official 85:e1a8e879a6a9 316 __IO uint32_t DAI; /*!< Device address match index. */
mbed_official 85:e1a8e879a6a9 317 __I uint32_t RESERVED6[60];
mbed_official 85:e1a8e879a6a9 318 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 319 __IO uint32_t FREQUENCY; /*!< Frequency. */
mbed_official 85:e1a8e879a6a9 320 __IO uint32_t TXPOWER; /*!< Output power. */
mbed_official 85:e1a8e879a6a9 321 __IO uint32_t MODE; /*!< Data rate and modulation. */
mbed_official 85:e1a8e879a6a9 322 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
mbed_official 85:e1a8e879a6a9 323 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
mbed_official 85:e1a8e879a6a9 324 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 325 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 326 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
mbed_official 85:e1a8e879a6a9 327 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
mbed_official 85:e1a8e879a6a9 328 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
mbed_official 85:e1a8e879a6a9 329 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
mbed_official 85:e1a8e879a6a9 330 __IO uint32_t CRCCNF; /*!< CRC configuration. */
mbed_official 85:e1a8e879a6a9 331 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
mbed_official 85:e1a8e879a6a9 332 __IO uint32_t CRCINIT; /*!< CRC initial value. */
mbed_official 85:e1a8e879a6a9 333 __IO uint32_t TEST; /*!< Test features enable register. */
mbed_official 85:e1a8e879a6a9 334 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
mbed_official 85:e1a8e879a6a9 335 __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */
mbed_official 85:e1a8e879a6a9 336 __I uint32_t RESERVED7;
mbed_official 85:e1a8e879a6a9 337 __I uint32_t STATE; /*!< Current radio state. */
mbed_official 85:e1a8e879a6a9 338 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
mbed_official 85:e1a8e879a6a9 339 __I uint32_t RESERVED8[2];
mbed_official 85:e1a8e879a6a9 340 __IO uint32_t BCC; /*!< Bit counter compare. */
mbed_official 85:e1a8e879a6a9 341 __I uint32_t RESERVED9[39];
mbed_official 85:e1a8e879a6a9 342 __IO uint32_t DAB[8]; /*!< Device address base segment. */
mbed_official 85:e1a8e879a6a9 343 __IO uint32_t DAP[8]; /*!< Device address prefix. */
mbed_official 85:e1a8e879a6a9 344 __IO uint32_t DACNF; /*!< Device address match configuration. */
mbed_official 85:e1a8e879a6a9 345 __I uint32_t RESERVED10[56];
mbed_official 85:e1a8e879a6a9 346 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
mbed_official 85:e1a8e879a6a9 347 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
mbed_official 85:e1a8e879a6a9 348 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
mbed_official 85:e1a8e879a6a9 349 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
mbed_official 85:e1a8e879a6a9 350 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
mbed_official 85:e1a8e879a6a9 351 __I uint32_t RESERVED11[561];
mbed_official 85:e1a8e879a6a9 352 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 353 } NRF_RADIO_Type;
mbed_official 85:e1a8e879a6a9 354
mbed_official 85:e1a8e879a6a9 355
mbed_official 85:e1a8e879a6a9 356 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 357 /* ================ UART ================ */
mbed_official 85:e1a8e879a6a9 358 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 359
mbed_official 85:e1a8e879a6a9 360
mbed_official 85:e1a8e879a6a9 361 /**
mbed_official 85:e1a8e879a6a9 362 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
mbed_official 85:e1a8e879a6a9 363 */
mbed_official 85:e1a8e879a6a9 364
mbed_official 85:e1a8e879a6a9 365 typedef struct { /*!< UART Structure */
mbed_official 85:e1a8e879a6a9 366 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
mbed_official 85:e1a8e879a6a9 367 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
mbed_official 85:e1a8e879a6a9 368 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
mbed_official 85:e1a8e879a6a9 369 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
mbed_official 85:e1a8e879a6a9 370 __I uint32_t RESERVED0[3];
mbed_official 85:e1a8e879a6a9 371 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
mbed_official 85:e1a8e879a6a9 372 __I uint32_t RESERVED1[56];
mbed_official 85:e1a8e879a6a9 373 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
mbed_official 85:e1a8e879a6a9 374 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
mbed_official 85:e1a8e879a6a9 375 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
mbed_official 85:e1a8e879a6a9 376 __I uint32_t RESERVED2[4];
mbed_official 85:e1a8e879a6a9 377 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
mbed_official 85:e1a8e879a6a9 378 __I uint32_t RESERVED3;
mbed_official 85:e1a8e879a6a9 379 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
mbed_official 85:e1a8e879a6a9 380 __I uint32_t RESERVED4[7];
mbed_official 85:e1a8e879a6a9 381 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
mbed_official 85:e1a8e879a6a9 382 __I uint32_t RESERVED5[46];
mbed_official 85:e1a8e879a6a9 383 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
mbed_official 85:e1a8e879a6a9 384 __I uint32_t RESERVED6[64];
mbed_official 85:e1a8e879a6a9 385 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 386 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 387 __I uint32_t RESERVED7[93];
mbed_official 85:e1a8e879a6a9 388 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
mbed_official 85:e1a8e879a6a9 389 __I uint32_t RESERVED8[31];
mbed_official 85:e1a8e879a6a9 390 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
mbed_official 85:e1a8e879a6a9 391 __I uint32_t RESERVED9;
mbed_official 85:e1a8e879a6a9 392 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
mbed_official 85:e1a8e879a6a9 393 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
mbed_official 85:e1a8e879a6a9 394 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
mbed_official 85:e1a8e879a6a9 395 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
mbed_official 85:e1a8e879a6a9 396 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
mbed_official 85:e1a8e879a6a9 397 Once read the character is consummed. If read when no character
mbed_official 85:e1a8e879a6a9 398 available, the UART will stop working. */
mbed_official 85:e1a8e879a6a9 399 __O uint32_t TXD; /*!< TXD register. */
mbed_official 85:e1a8e879a6a9 400 __I uint32_t RESERVED10;
mbed_official 85:e1a8e879a6a9 401 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
mbed_official 85:e1a8e879a6a9 402 __I uint32_t RESERVED11[17];
mbed_official 85:e1a8e879a6a9 403 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
mbed_official 85:e1a8e879a6a9 404 __I uint32_t RESERVED12[675];
mbed_official 85:e1a8e879a6a9 405 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 406 } NRF_UART_Type;
mbed_official 85:e1a8e879a6a9 407
mbed_official 85:e1a8e879a6a9 408
mbed_official 85:e1a8e879a6a9 409 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 410 /* ================ SPI ================ */
mbed_official 85:e1a8e879a6a9 411 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 412
mbed_official 85:e1a8e879a6a9 413
mbed_official 85:e1a8e879a6a9 414 /**
mbed_official 85:e1a8e879a6a9 415 * @brief SPI master 0. (SPI)
mbed_official 85:e1a8e879a6a9 416 */
mbed_official 85:e1a8e879a6a9 417
mbed_official 85:e1a8e879a6a9 418 typedef struct { /*!< SPI Structure */
mbed_official 85:e1a8e879a6a9 419 __I uint32_t RESERVED0[66];
mbed_official 85:e1a8e879a6a9 420 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
mbed_official 85:e1a8e879a6a9 421 __I uint32_t RESERVED1[126];
mbed_official 85:e1a8e879a6a9 422 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 423 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 424 __I uint32_t RESERVED2[125];
mbed_official 85:e1a8e879a6a9 425 __IO uint32_t ENABLE; /*!< Enable SPI. */
mbed_official 85:e1a8e879a6a9 426 __I uint32_t RESERVED3;
mbed_official 85:e1a8e879a6a9 427 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
mbed_official 85:e1a8e879a6a9 428 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
mbed_official 85:e1a8e879a6a9 429 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
mbed_official 85:e1a8e879a6a9 430 __I uint32_t RESERVED4;
mbed_official 85:e1a8e879a6a9 431 __IO uint32_t RXD; /*!< RX data. */
mbed_official 85:e1a8e879a6a9 432 __IO uint32_t TXD; /*!< TX data. */
mbed_official 85:e1a8e879a6a9 433 __I uint32_t RESERVED5;
mbed_official 85:e1a8e879a6a9 434 __IO uint32_t FREQUENCY; /*!< SPI frequency */
mbed_official 85:e1a8e879a6a9 435 __I uint32_t RESERVED6[11];
mbed_official 85:e1a8e879a6a9 436 __IO uint32_t CONFIG; /*!< Configuration register. */
mbed_official 85:e1a8e879a6a9 437 __I uint32_t RESERVED7[681];
mbed_official 85:e1a8e879a6a9 438 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 439 } NRF_SPI_Type;
mbed_official 85:e1a8e879a6a9 440
mbed_official 85:e1a8e879a6a9 441
mbed_official 85:e1a8e879a6a9 442 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 443 /* ================ TWI ================ */
mbed_official 85:e1a8e879a6a9 444 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 445
mbed_official 85:e1a8e879a6a9 446
mbed_official 85:e1a8e879a6a9 447 /**
mbed_official 85:e1a8e879a6a9 448 * @brief Two-wire interface master 0. (TWI)
mbed_official 85:e1a8e879a6a9 449 */
mbed_official 85:e1a8e879a6a9 450
mbed_official 85:e1a8e879a6a9 451 typedef struct { /*!< TWI Structure */
mbed_official 85:e1a8e879a6a9 452 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
mbed_official 85:e1a8e879a6a9 453 __I uint32_t RESERVED0;
mbed_official 85:e1a8e879a6a9 454 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
mbed_official 85:e1a8e879a6a9 455 __I uint32_t RESERVED1[2];
mbed_official 85:e1a8e879a6a9 456 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
mbed_official 85:e1a8e879a6a9 457 __I uint32_t RESERVED2;
mbed_official 85:e1a8e879a6a9 458 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
mbed_official 85:e1a8e879a6a9 459 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
mbed_official 85:e1a8e879a6a9 460 __I uint32_t RESERVED3[56];
mbed_official 85:e1a8e879a6a9 461 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
mbed_official 85:e1a8e879a6a9 462 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
mbed_official 85:e1a8e879a6a9 463 __I uint32_t RESERVED4[4];
mbed_official 85:e1a8e879a6a9 464 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
mbed_official 85:e1a8e879a6a9 465 __I uint32_t RESERVED5;
mbed_official 85:e1a8e879a6a9 466 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
mbed_official 85:e1a8e879a6a9 467 __I uint32_t RESERVED6[4];
mbed_official 85:e1a8e879a6a9 468 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
mbed_official 85:e1a8e879a6a9 469 __I uint32_t RESERVED7[49];
mbed_official 85:e1a8e879a6a9 470 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
mbed_official 85:e1a8e879a6a9 471 __I uint32_t RESERVED8[64];
mbed_official 85:e1a8e879a6a9 472 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 473 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 474 __I uint32_t RESERVED9[110];
mbed_official 85:e1a8e879a6a9 475 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
mbed_official 85:e1a8e879a6a9 476 __I uint32_t RESERVED10[14];
mbed_official 85:e1a8e879a6a9 477 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
mbed_official 85:e1a8e879a6a9 478 __I uint32_t RESERVED11;
mbed_official 85:e1a8e879a6a9 479 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
mbed_official 85:e1a8e879a6a9 480 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
mbed_official 85:e1a8e879a6a9 481 __I uint32_t RESERVED12[2];
mbed_official 85:e1a8e879a6a9 482 __IO uint32_t RXD; /*!< RX data register. */
mbed_official 85:e1a8e879a6a9 483 __IO uint32_t TXD; /*!< TX data register. */
mbed_official 85:e1a8e879a6a9 484 __I uint32_t RESERVED13;
mbed_official 85:e1a8e879a6a9 485 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
mbed_official 85:e1a8e879a6a9 486 __I uint32_t RESERVED14[24];
mbed_official 85:e1a8e879a6a9 487 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
mbed_official 85:e1a8e879a6a9 488 __I uint32_t RESERVED15[668];
mbed_official 85:e1a8e879a6a9 489 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 490 } NRF_TWI_Type;
mbed_official 85:e1a8e879a6a9 491
mbed_official 85:e1a8e879a6a9 492
mbed_official 85:e1a8e879a6a9 493 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 494 /* ================ SPIS ================ */
mbed_official 85:e1a8e879a6a9 495 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 496
mbed_official 85:e1a8e879a6a9 497
mbed_official 85:e1a8e879a6a9 498 /**
mbed_official 85:e1a8e879a6a9 499 * @brief SPI slave 1. (SPIS)
mbed_official 85:e1a8e879a6a9 500 */
mbed_official 85:e1a8e879a6a9 501
mbed_official 85:e1a8e879a6a9 502 typedef struct { /*!< SPIS Structure */
mbed_official 85:e1a8e879a6a9 503 __I uint32_t RESERVED0[9];
mbed_official 85:e1a8e879a6a9 504 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
mbed_official 85:e1a8e879a6a9 505 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
mbed_official 85:e1a8e879a6a9 506 __I uint32_t RESERVED1[54];
mbed_official 85:e1a8e879a6a9 507 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
mbed_official 85:e1a8e879a6a9 508 __I uint32_t RESERVED2[8];
mbed_official 85:e1a8e879a6a9 509 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
mbed_official 85:e1a8e879a6a9 510 __I uint32_t RESERVED3[53];
mbed_official 85:e1a8e879a6a9 511 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
mbed_official 85:e1a8e879a6a9 512 __I uint32_t RESERVED4[64];
mbed_official 85:e1a8e879a6a9 513 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 514 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 515 __I uint32_t RESERVED5[61];
mbed_official 85:e1a8e879a6a9 516 __I uint32_t SEMSTAT; /*!< Semaphore status. */
mbed_official 85:e1a8e879a6a9 517 __I uint32_t RESERVED6[15];
mbed_official 85:e1a8e879a6a9 518 __IO uint32_t STATUS; /*!< Status from last transaction. */
mbed_official 85:e1a8e879a6a9 519 __I uint32_t RESERVED7[47];
mbed_official 85:e1a8e879a6a9 520 __IO uint32_t ENABLE; /*!< Enable SPIS. */
mbed_official 85:e1a8e879a6a9 521 __I uint32_t RESERVED8;
mbed_official 85:e1a8e879a6a9 522 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
mbed_official 85:e1a8e879a6a9 523 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
mbed_official 85:e1a8e879a6a9 524 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
mbed_official 85:e1a8e879a6a9 525 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
mbed_official 85:e1a8e879a6a9 526 __I uint32_t RESERVED9[7];
mbed_official 85:e1a8e879a6a9 527 __IO uint32_t RXDPTR; /*!< RX data pointer. */
mbed_official 85:e1a8e879a6a9 528 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
mbed_official 85:e1a8e879a6a9 529 __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
mbed_official 85:e1a8e879a6a9 530 __I uint32_t RESERVED10;
mbed_official 85:e1a8e879a6a9 531 __IO uint32_t TXDPTR; /*!< TX data pointer. */
mbed_official 85:e1a8e879a6a9 532 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
mbed_official 85:e1a8e879a6a9 533 __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
mbed_official 85:e1a8e879a6a9 534 __I uint32_t RESERVED11;
mbed_official 85:e1a8e879a6a9 535 __IO uint32_t CONFIG; /*!< Configuration register. */
mbed_official 85:e1a8e879a6a9 536 __I uint32_t RESERVED12;
mbed_official 85:e1a8e879a6a9 537 __IO uint32_t DEF; /*!< Default character. */
mbed_official 85:e1a8e879a6a9 538 __I uint32_t RESERVED13[24];
mbed_official 85:e1a8e879a6a9 539 __IO uint32_t ORC; /*!< Over-read character. */
mbed_official 85:e1a8e879a6a9 540 __I uint32_t RESERVED14[654];
mbed_official 85:e1a8e879a6a9 541 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 542 } NRF_SPIS_Type;
mbed_official 85:e1a8e879a6a9 543
mbed_official 85:e1a8e879a6a9 544
mbed_official 85:e1a8e879a6a9 545 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 546 /* ================ GPIOTE ================ */
mbed_official 85:e1a8e879a6a9 547 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 548
mbed_official 85:e1a8e879a6a9 549
mbed_official 85:e1a8e879a6a9 550 /**
mbed_official 85:e1a8e879a6a9 551 * @brief GPIO tasks and events. (GPIOTE)
mbed_official 85:e1a8e879a6a9 552 */
mbed_official 85:e1a8e879a6a9 553
mbed_official 85:e1a8e879a6a9 554 typedef struct { /*!< GPIOTE Structure */
mbed_official 85:e1a8e879a6a9 555 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
mbed_official 85:e1a8e879a6a9 556 __I uint32_t RESERVED0[60];
mbed_official 85:e1a8e879a6a9 557 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
mbed_official 85:e1a8e879a6a9 558 __I uint32_t RESERVED1[27];
mbed_official 85:e1a8e879a6a9 559 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
mbed_official 85:e1a8e879a6a9 560 __I uint32_t RESERVED2[97];
mbed_official 85:e1a8e879a6a9 561 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 562 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 563 __I uint32_t RESERVED3[129];
mbed_official 85:e1a8e879a6a9 564 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
mbed_official 85:e1a8e879a6a9 565 __I uint32_t RESERVED4[695];
mbed_official 85:e1a8e879a6a9 566 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 567 } NRF_GPIOTE_Type;
mbed_official 85:e1a8e879a6a9 568
mbed_official 85:e1a8e879a6a9 569
mbed_official 85:e1a8e879a6a9 570 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 571 /* ================ ADC ================ */
mbed_official 85:e1a8e879a6a9 572 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 573
mbed_official 85:e1a8e879a6a9 574
mbed_official 85:e1a8e879a6a9 575 /**
mbed_official 85:e1a8e879a6a9 576 * @brief Analog to digital converter. (ADC)
mbed_official 85:e1a8e879a6a9 577 */
mbed_official 85:e1a8e879a6a9 578
mbed_official 85:e1a8e879a6a9 579 typedef struct { /*!< ADC Structure */
mbed_official 85:e1a8e879a6a9 580 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
mbed_official 85:e1a8e879a6a9 581 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
mbed_official 85:e1a8e879a6a9 582 __I uint32_t RESERVED0[62];
mbed_official 85:e1a8e879a6a9 583 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
mbed_official 85:e1a8e879a6a9 584 __I uint32_t RESERVED1[128];
mbed_official 85:e1a8e879a6a9 585 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 586 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 587 __I uint32_t RESERVED2[61];
mbed_official 85:e1a8e879a6a9 588 __I uint32_t BUSY; /*!< ADC busy register. */
mbed_official 85:e1a8e879a6a9 589 __I uint32_t RESERVED3[63];
mbed_official 85:e1a8e879a6a9 590 __IO uint32_t ENABLE; /*!< ADC enable. */
mbed_official 85:e1a8e879a6a9 591 __IO uint32_t CONFIG; /*!< ADC configuration register. */
mbed_official 85:e1a8e879a6a9 592 __I uint32_t RESULT; /*!< Result of ADC conversion. */
mbed_official 85:e1a8e879a6a9 593 __I uint32_t RESERVED4[700];
mbed_official 85:e1a8e879a6a9 594 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 595 } NRF_ADC_Type;
mbed_official 85:e1a8e879a6a9 596
mbed_official 85:e1a8e879a6a9 597
mbed_official 85:e1a8e879a6a9 598 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 599 /* ================ TIMER ================ */
mbed_official 85:e1a8e879a6a9 600 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 601
mbed_official 85:e1a8e879a6a9 602
mbed_official 85:e1a8e879a6a9 603 /**
mbed_official 85:e1a8e879a6a9 604 * @brief Timer 0. (TIMER)
mbed_official 85:e1a8e879a6a9 605 */
mbed_official 85:e1a8e879a6a9 606
mbed_official 85:e1a8e879a6a9 607 typedef struct { /*!< TIMER Structure */
mbed_official 85:e1a8e879a6a9 608 __O uint32_t TASKS_START; /*!< Start Timer. */
mbed_official 85:e1a8e879a6a9 609 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
mbed_official 85:e1a8e879a6a9 610 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
mbed_official 85:e1a8e879a6a9 611 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
mbed_official 85:e1a8e879a6a9 612 __I uint32_t RESERVED0[12];
mbed_official 85:e1a8e879a6a9 613 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
mbed_official 85:e1a8e879a6a9 614 __I uint32_t RESERVED1[60];
mbed_official 85:e1a8e879a6a9 615 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
mbed_official 85:e1a8e879a6a9 616 __I uint32_t RESERVED2[44];
mbed_official 85:e1a8e879a6a9 617 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
mbed_official 85:e1a8e879a6a9 618 __I uint32_t RESERVED3[64];
mbed_official 85:e1a8e879a6a9 619 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 620 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 621 __I uint32_t RESERVED4[126];
mbed_official 85:e1a8e879a6a9 622 __IO uint32_t MODE; /*!< Timer Mode selection. */
mbed_official 85:e1a8e879a6a9 623 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
mbed_official 85:e1a8e879a6a9 624 __I uint32_t RESERVED5;
mbed_official 85:e1a8e879a6a9 625 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
mbed_official 85:e1a8e879a6a9 626 clock frequency is divided by 2^SCALE. */
mbed_official 85:e1a8e879a6a9 627 __I uint32_t RESERVED6[11];
mbed_official 85:e1a8e879a6a9 628 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
mbed_official 85:e1a8e879a6a9 629 __I uint32_t RESERVED7[683];
mbed_official 85:e1a8e879a6a9 630 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 631 } NRF_TIMER_Type;
mbed_official 85:e1a8e879a6a9 632
mbed_official 85:e1a8e879a6a9 633
mbed_official 85:e1a8e879a6a9 634 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 635 /* ================ RTC ================ */
mbed_official 85:e1a8e879a6a9 636 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 637
mbed_official 85:e1a8e879a6a9 638
mbed_official 85:e1a8e879a6a9 639 /**
mbed_official 85:e1a8e879a6a9 640 * @brief Real time counter 0. (RTC)
mbed_official 85:e1a8e879a6a9 641 */
mbed_official 85:e1a8e879a6a9 642
mbed_official 85:e1a8e879a6a9 643 typedef struct { /*!< RTC Structure */
mbed_official 85:e1a8e879a6a9 644 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
mbed_official 85:e1a8e879a6a9 645 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
mbed_official 85:e1a8e879a6a9 646 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
mbed_official 85:e1a8e879a6a9 647 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
mbed_official 85:e1a8e879a6a9 648 __I uint32_t RESERVED0[60];
mbed_official 85:e1a8e879a6a9 649 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
mbed_official 85:e1a8e879a6a9 650 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
mbed_official 85:e1a8e879a6a9 651 __I uint32_t RESERVED1[14];
mbed_official 85:e1a8e879a6a9 652 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
mbed_official 85:e1a8e879a6a9 653 __I uint32_t RESERVED2[109];
mbed_official 85:e1a8e879a6a9 654 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 655 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 656 __I uint32_t RESERVED3[13];
mbed_official 85:e1a8e879a6a9 657 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
mbed_official 85:e1a8e879a6a9 658 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
mbed_official 85:e1a8e879a6a9 659 the value of EVTEN. */
mbed_official 85:e1a8e879a6a9 660 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
mbed_official 85:e1a8e879a6a9 661 gives the value of EVTEN. */
mbed_official 85:e1a8e879a6a9 662 __I uint32_t RESERVED4[110];
mbed_official 85:e1a8e879a6a9 663 __IO uint32_t COUNTER; /*!< Current COUNTER value. */
mbed_official 85:e1a8e879a6a9 664 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
mbed_official 85:e1a8e879a6a9 665 Must be written when RTC is STOPed. */
mbed_official 85:e1a8e879a6a9 666 __I uint32_t RESERVED5[13];
mbed_official 85:e1a8e879a6a9 667 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
mbed_official 85:e1a8e879a6a9 668 __I uint32_t RESERVED6[683];
mbed_official 85:e1a8e879a6a9 669 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 670 } NRF_RTC_Type;
mbed_official 85:e1a8e879a6a9 671
mbed_official 85:e1a8e879a6a9 672
mbed_official 85:e1a8e879a6a9 673 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 674 /* ================ TEMP ================ */
mbed_official 85:e1a8e879a6a9 675 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 676
mbed_official 85:e1a8e879a6a9 677
mbed_official 85:e1a8e879a6a9 678 /**
mbed_official 85:e1a8e879a6a9 679 * @brief Temperature Sensor. (TEMP)
mbed_official 85:e1a8e879a6a9 680 */
mbed_official 85:e1a8e879a6a9 681
mbed_official 85:e1a8e879a6a9 682 typedef struct { /*!< TEMP Structure */
mbed_official 85:e1a8e879a6a9 683 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
mbed_official 85:e1a8e879a6a9 684 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
mbed_official 85:e1a8e879a6a9 685 __I uint32_t RESERVED0[62];
mbed_official 85:e1a8e879a6a9 686 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
mbed_official 85:e1a8e879a6a9 687 __I uint32_t RESERVED1[128];
mbed_official 85:e1a8e879a6a9 688 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 689 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 690 __I uint32_t RESERVED2[127];
mbed_official 85:e1a8e879a6a9 691 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
mbed_official 85:e1a8e879a6a9 692 __I uint32_t RESERVED3[700];
mbed_official 85:e1a8e879a6a9 693 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 694 } NRF_TEMP_Type;
mbed_official 85:e1a8e879a6a9 695
mbed_official 85:e1a8e879a6a9 696
mbed_official 85:e1a8e879a6a9 697 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 698 /* ================ RNG ================ */
mbed_official 85:e1a8e879a6a9 699 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 700
mbed_official 85:e1a8e879a6a9 701
mbed_official 85:e1a8e879a6a9 702 /**
mbed_official 85:e1a8e879a6a9 703 * @brief Random Number Generator. (RNG)
mbed_official 85:e1a8e879a6a9 704 */
mbed_official 85:e1a8e879a6a9 705
mbed_official 85:e1a8e879a6a9 706 typedef struct { /*!< RNG Structure */
mbed_official 85:e1a8e879a6a9 707 __O uint32_t TASKS_START; /*!< Start the random number generator. */
mbed_official 85:e1a8e879a6a9 708 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
mbed_official 85:e1a8e879a6a9 709 __I uint32_t RESERVED0[62];
mbed_official 85:e1a8e879a6a9 710 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
mbed_official 85:e1a8e879a6a9 711 __I uint32_t RESERVED1[63];
mbed_official 85:e1a8e879a6a9 712 __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */
mbed_official 85:e1a8e879a6a9 713 __I uint32_t RESERVED2[64];
mbed_official 85:e1a8e879a6a9 714 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
mbed_official 85:e1a8e879a6a9 715 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
mbed_official 85:e1a8e879a6a9 716 __I uint32_t RESERVED3[126];
mbed_official 85:e1a8e879a6a9 717 __IO uint32_t CONFIG; /*!< Configuration register. */
mbed_official 85:e1a8e879a6a9 718 __I uint32_t VALUE; /*!< RNG random number. */
mbed_official 85:e1a8e879a6a9 719 __I uint32_t RESERVED4[700];
mbed_official 85:e1a8e879a6a9 720 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 721 } NRF_RNG_Type;
mbed_official 85:e1a8e879a6a9 722
mbed_official 85:e1a8e879a6a9 723
mbed_official 85:e1a8e879a6a9 724 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 725 /* ================ ECB ================ */
mbed_official 85:e1a8e879a6a9 726 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 727
mbed_official 85:e1a8e879a6a9 728
mbed_official 85:e1a8e879a6a9 729 /**
mbed_official 85:e1a8e879a6a9 730 * @brief AES ECB Mode Encryption. (ECB)
mbed_official 85:e1a8e879a6a9 731 */
mbed_official 85:e1a8e879a6a9 732
mbed_official 85:e1a8e879a6a9 733 typedef struct { /*!< ECB Structure */
mbed_official 85:e1a8e879a6a9 734 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
mbed_official 85:e1a8e879a6a9 735 will not initiate a new encryption and the ERRORECB event will
mbed_official 85:e1a8e879a6a9 736 be triggered. */
mbed_official 85:e1a8e879a6a9 737 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
mbed_official 85:e1a8e879a6a9 738 this will will trigger the ERRORECB event. */
mbed_official 85:e1a8e879a6a9 739 __I uint32_t RESERVED0[62];
mbed_official 85:e1a8e879a6a9 740 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
mbed_official 85:e1a8e879a6a9 741 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
mbed_official 85:e1a8e879a6a9 742 error. */
mbed_official 85:e1a8e879a6a9 743 __I uint32_t RESERVED1[127];
mbed_official 85:e1a8e879a6a9 744 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 745 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 746 __I uint32_t RESERVED2[126];
mbed_official 85:e1a8e879a6a9 747 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
mbed_official 85:e1a8e879a6a9 748 __I uint32_t RESERVED3[701];
mbed_official 85:e1a8e879a6a9 749 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 750 } NRF_ECB_Type;
mbed_official 85:e1a8e879a6a9 751
mbed_official 85:e1a8e879a6a9 752
mbed_official 85:e1a8e879a6a9 753 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 754 /* ================ AAR ================ */
mbed_official 85:e1a8e879a6a9 755 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 756
mbed_official 85:e1a8e879a6a9 757
mbed_official 85:e1a8e879a6a9 758 /**
mbed_official 85:e1a8e879a6a9 759 * @brief Accelerated Address Resolver. (AAR)
mbed_official 85:e1a8e879a6a9 760 */
mbed_official 85:e1a8e879a6a9 761
mbed_official 85:e1a8e879a6a9 762 typedef struct { /*!< AAR Structure */
mbed_official 85:e1a8e879a6a9 763 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
mbed_official 85:e1a8e879a6a9 764 data structure. */
mbed_official 85:e1a8e879a6a9 765 __I uint32_t RESERVED0;
mbed_official 85:e1a8e879a6a9 766 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
mbed_official 85:e1a8e879a6a9 767 __I uint32_t RESERVED1[61];
mbed_official 85:e1a8e879a6a9 768 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
mbed_official 85:e1a8e879a6a9 769 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
mbed_official 85:e1a8e879a6a9 770 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
mbed_official 85:e1a8e879a6a9 771 __I uint32_t RESERVED2[126];
mbed_official 85:e1a8e879a6a9 772 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 773 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 774 __I uint32_t RESERVED3[61];
mbed_official 85:e1a8e879a6a9 775 __I uint32_t STATUS; /*!< Resolution status. */
mbed_official 85:e1a8e879a6a9 776 __I uint32_t RESERVED4[63];
mbed_official 85:e1a8e879a6a9 777 __IO uint32_t ENABLE; /*!< Enable AAR. */
mbed_official 85:e1a8e879a6a9 778 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
mbed_official 85:e1a8e879a6a9 779 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
mbed_official 85:e1a8e879a6a9 780 __I uint32_t RESERVED5;
mbed_official 85:e1a8e879a6a9 781 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
mbed_official 85:e1a8e879a6a9 782 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
mbed_official 85:e1a8e879a6a9 783 resolution. A minimum of 3 bytes must be reserved. */
mbed_official 85:e1a8e879a6a9 784 __I uint32_t RESERVED6[697];
mbed_official 85:e1a8e879a6a9 785 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 786 } NRF_AAR_Type;
mbed_official 85:e1a8e879a6a9 787
mbed_official 85:e1a8e879a6a9 788
mbed_official 85:e1a8e879a6a9 789 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 790 /* ================ CCM ================ */
mbed_official 85:e1a8e879a6a9 791 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 792
mbed_official 85:e1a8e879a6a9 793
mbed_official 85:e1a8e879a6a9 794 /**
mbed_official 85:e1a8e879a6a9 795 * @brief AES CCM Mode Encryption. (CCM)
mbed_official 85:e1a8e879a6a9 796 */
mbed_official 85:e1a8e879a6a9 797
mbed_official 85:e1a8e879a6a9 798 typedef struct { /*!< CCM Structure */
mbed_official 85:e1a8e879a6a9 799 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
mbed_official 85:e1a8e879a6a9 800 itself when completed. */
mbed_official 85:e1a8e879a6a9 801 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
mbed_official 85:e1a8e879a6a9 802 completed. */
mbed_official 85:e1a8e879a6a9 803 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
mbed_official 85:e1a8e879a6a9 804 __I uint32_t RESERVED0[61];
mbed_official 85:e1a8e879a6a9 805 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
mbed_official 85:e1a8e879a6a9 806 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
mbed_official 85:e1a8e879a6a9 807 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
mbed_official 85:e1a8e879a6a9 808 __I uint32_t RESERVED1[61];
mbed_official 85:e1a8e879a6a9 809 __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */
mbed_official 85:e1a8e879a6a9 810 __I uint32_t RESERVED2[64];
mbed_official 85:e1a8e879a6a9 811 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 812 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 813 __I uint32_t RESERVED3[61];
mbed_official 85:e1a8e879a6a9 814 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
mbed_official 85:e1a8e879a6a9 815 __I uint32_t RESERVED4[63];
mbed_official 85:e1a8e879a6a9 816 __IO uint32_t ENABLE; /*!< CCM enable. */
mbed_official 85:e1a8e879a6a9 817 __IO uint32_t MODE; /*!< Operation mode. */
mbed_official 85:e1a8e879a6a9 818 __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */
mbed_official 85:e1a8e879a6a9 819 __IO uint32_t INPTR; /*!< Pointer to input packet. */
mbed_official 85:e1a8e879a6a9 820 __IO uint32_t OUTPTR; /*!< Pointer to output packet. */
mbed_official 85:e1a8e879a6a9 821 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
mbed_official 85:e1a8e879a6a9 822 resolution. A minimum of 43 bytes must be reserved. */
mbed_official 85:e1a8e879a6a9 823 __I uint32_t RESERVED5[697];
mbed_official 85:e1a8e879a6a9 824 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 825 } NRF_CCM_Type;
mbed_official 85:e1a8e879a6a9 826
mbed_official 85:e1a8e879a6a9 827
mbed_official 85:e1a8e879a6a9 828 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 829 /* ================ WDT ================ */
mbed_official 85:e1a8e879a6a9 830 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 831
mbed_official 85:e1a8e879a6a9 832
mbed_official 85:e1a8e879a6a9 833 /**
mbed_official 85:e1a8e879a6a9 834 * @brief Watchdog Timer. (WDT)
mbed_official 85:e1a8e879a6a9 835 */
mbed_official 85:e1a8e879a6a9 836
mbed_official 85:e1a8e879a6a9 837 typedef struct { /*!< WDT Structure */
mbed_official 85:e1a8e879a6a9 838 __O uint32_t TASKS_START; /*!< Start the watchdog. */
mbed_official 85:e1a8e879a6a9 839 __I uint32_t RESERVED0[63];
mbed_official 85:e1a8e879a6a9 840 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
mbed_official 85:e1a8e879a6a9 841 __I uint32_t RESERVED1[128];
mbed_official 85:e1a8e879a6a9 842 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 843 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 844 __I uint32_t RESERVED2[61];
mbed_official 85:e1a8e879a6a9 845 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
mbed_official 85:e1a8e879a6a9 846 __I uint32_t REQSTATUS; /*!< Request status. */
mbed_official 85:e1a8e879a6a9 847 __I uint32_t RESERVED3[63];
mbed_official 85:e1a8e879a6a9 848 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
mbed_official 85:e1a8e879a6a9 849 __IO uint32_t RREN; /*!< Reload request enable. */
mbed_official 85:e1a8e879a6a9 850 __IO uint32_t CONFIG; /*!< Configuration register. */
mbed_official 85:e1a8e879a6a9 851 __I uint32_t RESERVED4[60];
mbed_official 85:e1a8e879a6a9 852 __O uint32_t RR[8]; /*!< Reload requests registers. */
mbed_official 85:e1a8e879a6a9 853 __I uint32_t RESERVED5[631];
mbed_official 85:e1a8e879a6a9 854 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 855 } NRF_WDT_Type;
mbed_official 85:e1a8e879a6a9 856
mbed_official 85:e1a8e879a6a9 857
mbed_official 85:e1a8e879a6a9 858 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 859 /* ================ QDEC ================ */
mbed_official 85:e1a8e879a6a9 860 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 861
mbed_official 85:e1a8e879a6a9 862
mbed_official 85:e1a8e879a6a9 863 /**
mbed_official 85:e1a8e879a6a9 864 * @brief Rotary decoder. (QDEC)
mbed_official 85:e1a8e879a6a9 865 */
mbed_official 85:e1a8e879a6a9 866
mbed_official 85:e1a8e879a6a9 867 typedef struct { /*!< QDEC Structure */
mbed_official 85:e1a8e879a6a9 868 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
mbed_official 85:e1a8e879a6a9 869 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
mbed_official 85:e1a8e879a6a9 870 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
mbed_official 85:e1a8e879a6a9 871 and clears the ACC registers. */
mbed_official 85:e1a8e879a6a9 872 __I uint32_t RESERVED0[61];
mbed_official 85:e1a8e879a6a9 873 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
mbed_official 85:e1a8e879a6a9 874 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
mbed_official 85:e1a8e879a6a9 875 ACC register different than zero. */
mbed_official 85:e1a8e879a6a9 876 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
mbed_official 85:e1a8e879a6a9 877 __I uint32_t RESERVED1[61];
mbed_official 85:e1a8e879a6a9 878 __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */
mbed_official 85:e1a8e879a6a9 879 __I uint32_t RESERVED2[64];
mbed_official 85:e1a8e879a6a9 880 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 881 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 882 __I uint32_t RESERVED3[125];
mbed_official 85:e1a8e879a6a9 883 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
mbed_official 85:e1a8e879a6a9 884 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
mbed_official 85:e1a8e879a6a9 885 __IO uint32_t SAMPLEPER; /*!< Sample period. */
mbed_official 85:e1a8e879a6a9 886 __I int32_t SAMPLE; /*!< Motion sample value. */
mbed_official 85:e1a8e879a6a9 887 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
mbed_official 85:e1a8e879a6a9 888 __I int32_t ACC; /*!< Accumulated valid transitions register. */
mbed_official 85:e1a8e879a6a9 889 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
mbed_official 85:e1a8e879a6a9 890 task. */
mbed_official 85:e1a8e879a6a9 891 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
mbed_official 85:e1a8e879a6a9 892 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
mbed_official 85:e1a8e879a6a9 893 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
mbed_official 85:e1a8e879a6a9 894 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
mbed_official 85:e1a8e879a6a9 895 __I uint32_t RESERVED4[5];
mbed_official 85:e1a8e879a6a9 896 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
mbed_official 85:e1a8e879a6a9 897 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
mbed_official 85:e1a8e879a6a9 898 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
mbed_official 85:e1a8e879a6a9 899 task. */
mbed_official 85:e1a8e879a6a9 900 __I uint32_t RESERVED5[684];
mbed_official 85:e1a8e879a6a9 901 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 902 } NRF_QDEC_Type;
mbed_official 85:e1a8e879a6a9 903
mbed_official 85:e1a8e879a6a9 904
mbed_official 85:e1a8e879a6a9 905 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 906 /* ================ LPCOMP ================ */
mbed_official 85:e1a8e879a6a9 907 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 908
mbed_official 85:e1a8e879a6a9 909
mbed_official 85:e1a8e879a6a9 910 /**
mbed_official 85:e1a8e879a6a9 911 * @brief Wakeup Comparator. (LPCOMP)
mbed_official 85:e1a8e879a6a9 912 */
mbed_official 85:e1a8e879a6a9 913
mbed_official 85:e1a8e879a6a9 914 typedef struct { /*!< LPCOMP Structure */
mbed_official 85:e1a8e879a6a9 915 __O uint32_t TASKS_START; /*!< Start the comparator. */
mbed_official 85:e1a8e879a6a9 916 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
mbed_official 85:e1a8e879a6a9 917 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
mbed_official 85:e1a8e879a6a9 918 __I uint32_t RESERVED0[61];
mbed_official 85:e1a8e879a6a9 919 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
mbed_official 85:e1a8e879a6a9 920 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
mbed_official 85:e1a8e879a6a9 921 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
mbed_official 85:e1a8e879a6a9 922 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
mbed_official 85:e1a8e879a6a9 923 __I uint32_t RESERVED1[60];
mbed_official 85:e1a8e879a6a9 924 __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */
mbed_official 85:e1a8e879a6a9 925 __I uint32_t RESERVED2[64];
mbed_official 85:e1a8e879a6a9 926 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 927 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 928 __I uint32_t RESERVED3[61];
mbed_official 85:e1a8e879a6a9 929 __I uint32_t RESULT; /*!< Result of last compare. */
mbed_official 85:e1a8e879a6a9 930 __I uint32_t RESERVED4[63];
mbed_official 85:e1a8e879a6a9 931 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
mbed_official 85:e1a8e879a6a9 932 __IO uint32_t PSEL; /*!< Input pin select. */
mbed_official 85:e1a8e879a6a9 933 __IO uint32_t REFSEL; /*!< Reference select. */
mbed_official 85:e1a8e879a6a9 934 __IO uint32_t EXTREFSEL; /*!< External reference select. */
mbed_official 85:e1a8e879a6a9 935 __I uint32_t RESERVED5[4];
mbed_official 85:e1a8e879a6a9 936 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
mbed_official 85:e1a8e879a6a9 937 __I uint32_t RESERVED6[694];
mbed_official 85:e1a8e879a6a9 938 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 939 } NRF_LPCOMP_Type;
mbed_official 85:e1a8e879a6a9 940
mbed_official 85:e1a8e879a6a9 941
mbed_official 85:e1a8e879a6a9 942 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 943 /* ================ COMP ================ */
mbed_official 85:e1a8e879a6a9 944 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 945
mbed_official 85:e1a8e879a6a9 946
mbed_official 85:e1a8e879a6a9 947 /**
mbed_official 85:e1a8e879a6a9 948 * @brief Comparator. (COMP)
mbed_official 85:e1a8e879a6a9 949 */
mbed_official 85:e1a8e879a6a9 950
mbed_official 85:e1a8e879a6a9 951 typedef struct { /*!< COMP Structure */
mbed_official 85:e1a8e879a6a9 952 __O uint32_t TASKS_START; /*!< Start the comparator. */
mbed_official 85:e1a8e879a6a9 953 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
mbed_official 85:e1a8e879a6a9 954 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
mbed_official 85:e1a8e879a6a9 955 __I uint32_t RESERVED0[61];
mbed_official 85:e1a8e879a6a9 956 __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */
mbed_official 85:e1a8e879a6a9 957 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
mbed_official 85:e1a8e879a6a9 958 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
mbed_official 85:e1a8e879a6a9 959 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
mbed_official 85:e1a8e879a6a9 960 __I uint32_t RESERVED1[60];
mbed_official 85:e1a8e879a6a9 961 __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */
mbed_official 85:e1a8e879a6a9 962 __I uint32_t RESERVED2[64];
mbed_official 85:e1a8e879a6a9 963 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 964 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 965 __I uint32_t RESERVED3[61];
mbed_official 85:e1a8e879a6a9 966 __I uint32_t RESULT; /*!< Compare result. */
mbed_official 85:e1a8e879a6a9 967 __I uint32_t RESERVED4[63];
mbed_official 85:e1a8e879a6a9 968 __IO uint32_t ENABLE; /*!< Enable the COMP. */
mbed_official 85:e1a8e879a6a9 969 __IO uint32_t PSEL; /*!< Input pin select. */
mbed_official 85:e1a8e879a6a9 970 __IO uint32_t REFSEL; /*!< Reference select. */
mbed_official 85:e1a8e879a6a9 971 __IO uint32_t EXTREFSEL; /*!< External reference select. */
mbed_official 85:e1a8e879a6a9 972 __I uint32_t RESERVED5[8];
mbed_official 85:e1a8e879a6a9 973 __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */
mbed_official 85:e1a8e879a6a9 974 __IO uint32_t MODE; /*!< Mode configuration. */
mbed_official 85:e1a8e879a6a9 975 __I uint32_t RESERVED6[689];
mbed_official 85:e1a8e879a6a9 976 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 977 } NRF_COMP_Type;
mbed_official 85:e1a8e879a6a9 978
mbed_official 85:e1a8e879a6a9 979
mbed_official 85:e1a8e879a6a9 980 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 981 /* ================ SWI ================ */
mbed_official 85:e1a8e879a6a9 982 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 983
mbed_official 85:e1a8e879a6a9 984
mbed_official 85:e1a8e879a6a9 985 /**
mbed_official 85:e1a8e879a6a9 986 * @brief SW Interrupts. (SWI)
mbed_official 85:e1a8e879a6a9 987 */
mbed_official 85:e1a8e879a6a9 988
mbed_official 85:e1a8e879a6a9 989 typedef struct { /*!< SWI Structure */
mbed_official 85:e1a8e879a6a9 990 __I uint32_t UNUSED; /*!< Unused. */
mbed_official 85:e1a8e879a6a9 991 } NRF_SWI_Type;
mbed_official 85:e1a8e879a6a9 992
mbed_official 85:e1a8e879a6a9 993
mbed_official 85:e1a8e879a6a9 994 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 995 /* ================ NVMC ================ */
mbed_official 85:e1a8e879a6a9 996 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 997
mbed_official 85:e1a8e879a6a9 998
mbed_official 85:e1a8e879a6a9 999 /**
mbed_official 85:e1a8e879a6a9 1000 * @brief Non Volatile Memory Controller. (NVMC)
mbed_official 85:e1a8e879a6a9 1001 */
mbed_official 85:e1a8e879a6a9 1002
mbed_official 85:e1a8e879a6a9 1003 typedef struct { /*!< NVMC Structure */
mbed_official 85:e1a8e879a6a9 1004 __I uint32_t RESERVED0[256];
mbed_official 85:e1a8e879a6a9 1005 __I uint32_t READY; /*!< Ready flag. */
mbed_official 85:e1a8e879a6a9 1006 __I uint32_t RESERVED1[64];
mbed_official 85:e1a8e879a6a9 1007 __IO uint32_t CONFIG; /*!< Configuration register. */
mbed_official 85:e1a8e879a6a9 1008 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
mbed_official 85:e1a8e879a6a9 1009 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
mbed_official 85:e1a8e879a6a9 1010 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
mbed_official 85:e1a8e879a6a9 1011 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
mbed_official 85:e1a8e879a6a9 1012 } NRF_NVMC_Type;
mbed_official 85:e1a8e879a6a9 1013
mbed_official 85:e1a8e879a6a9 1014
mbed_official 85:e1a8e879a6a9 1015 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1016 /* ================ PPI ================ */
mbed_official 85:e1a8e879a6a9 1017 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1018
mbed_official 85:e1a8e879a6a9 1019
mbed_official 85:e1a8e879a6a9 1020 /**
mbed_official 85:e1a8e879a6a9 1021 * @brief PPI controller. (PPI)
mbed_official 85:e1a8e879a6a9 1022 */
mbed_official 85:e1a8e879a6a9 1023
mbed_official 85:e1a8e879a6a9 1024 typedef struct { /*!< PPI Structure */
mbed_official 85:e1a8e879a6a9 1025 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
mbed_official 85:e1a8e879a6a9 1026 __I uint32_t RESERVED0[312];
mbed_official 85:e1a8e879a6a9 1027 __IO uint32_t CHEN; /*!< Channel enable. */
mbed_official 85:e1a8e879a6a9 1028 __IO uint32_t CHENSET; /*!< Channel enable set. */
mbed_official 85:e1a8e879a6a9 1029 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
mbed_official 85:e1a8e879a6a9 1030 __I uint32_t RESERVED1;
mbed_official 85:e1a8e879a6a9 1031 PPI_CH_Type CH[16]; /*!< PPI Channel. */
mbed_official 85:e1a8e879a6a9 1032 __I uint32_t RESERVED2[156];
mbed_official 85:e1a8e879a6a9 1033 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
mbed_official 85:e1a8e879a6a9 1034 } NRF_PPI_Type;
mbed_official 85:e1a8e879a6a9 1035
mbed_official 85:e1a8e879a6a9 1036
mbed_official 85:e1a8e879a6a9 1037 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1038 /* ================ FICR ================ */
mbed_official 85:e1a8e879a6a9 1039 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1040
mbed_official 85:e1a8e879a6a9 1041
mbed_official 85:e1a8e879a6a9 1042 /**
mbed_official 85:e1a8e879a6a9 1043 * @brief Factory Information Configuration. (FICR)
mbed_official 85:e1a8e879a6a9 1044 */
mbed_official 85:e1a8e879a6a9 1045
mbed_official 85:e1a8e879a6a9 1046 typedef struct { /*!< FICR Structure */
mbed_official 85:e1a8e879a6a9 1047 __I uint32_t RESERVED0[4];
mbed_official 85:e1a8e879a6a9 1048 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
mbed_official 85:e1a8e879a6a9 1049 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
mbed_official 85:e1a8e879a6a9 1050 __I uint32_t RESERVED1[4];
mbed_official 85:e1a8e879a6a9 1051 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
mbed_official 85:e1a8e879a6a9 1052 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
mbed_official 85:e1a8e879a6a9 1053 __I uint32_t RESERVED2;
mbed_official 85:e1a8e879a6a9 1054 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
mbed_official 85:e1a8e879a6a9 1055 __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */
mbed_official 85:e1a8e879a6a9 1056 __I uint32_t RESERVED3[5];
mbed_official 85:e1a8e879a6a9 1057 __I uint32_t CONFIGID; /*!< Configuration identifier. */
mbed_official 85:e1a8e879a6a9 1058 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
mbed_official 85:e1a8e879a6a9 1059 __I uint32_t RESERVED4[6];
mbed_official 85:e1a8e879a6a9 1060 __I uint32_t ER[4]; /*!< Encryption root. */
mbed_official 85:e1a8e879a6a9 1061 __I uint32_t IR[4]; /*!< Identity root. */
mbed_official 85:e1a8e879a6a9 1062 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
mbed_official 85:e1a8e879a6a9 1063 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
mbed_official 85:e1a8e879a6a9 1064 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
mbed_official 85:e1a8e879a6a9 1065 __I uint32_t RESERVED5[15];
mbed_official 85:e1a8e879a6a9 1066 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
mbed_official 85:e1a8e879a6a9 1067 mode. */
mbed_official 85:e1a8e879a6a9 1068 } NRF_FICR_Type;
mbed_official 85:e1a8e879a6a9 1069
mbed_official 85:e1a8e879a6a9 1070
mbed_official 85:e1a8e879a6a9 1071 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1072 /* ================ UICR ================ */
mbed_official 85:e1a8e879a6a9 1073 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1074
mbed_official 85:e1a8e879a6a9 1075
mbed_official 85:e1a8e879a6a9 1076 /**
mbed_official 85:e1a8e879a6a9 1077 * @brief User Information Configuration. (UICR)
mbed_official 85:e1a8e879a6a9 1078 */
mbed_official 85:e1a8e879a6a9 1079
mbed_official 85:e1a8e879a6a9 1080 typedef struct { /*!< UICR Structure */
mbed_official 85:e1a8e879a6a9 1081 __IO uint32_t CLENR0; /*!< Length of code region 0. */
mbed_official 85:e1a8e879a6a9 1082 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
mbed_official 85:e1a8e879a6a9 1083 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
mbed_official 85:e1a8e879a6a9 1084 __I uint32_t RESERVED0;
mbed_official 85:e1a8e879a6a9 1085 __I uint32_t FWID; /*!< Firmware ID. */
mbed_official 85:e1a8e879a6a9 1086 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
mbed_official 85:e1a8e879a6a9 1087 } NRF_UICR_Type;
mbed_official 85:e1a8e879a6a9 1088
mbed_official 85:e1a8e879a6a9 1089
mbed_official 85:e1a8e879a6a9 1090 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1091 /* ================ GPIO ================ */
mbed_official 85:e1a8e879a6a9 1092 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1093
mbed_official 85:e1a8e879a6a9 1094
mbed_official 85:e1a8e879a6a9 1095 /**
mbed_official 85:e1a8e879a6a9 1096 * @brief General purpose input and output. (GPIO)
mbed_official 85:e1a8e879a6a9 1097 */
mbed_official 85:e1a8e879a6a9 1098
mbed_official 85:e1a8e879a6a9 1099 typedef struct { /*!< GPIO Structure */
mbed_official 85:e1a8e879a6a9 1100 __I uint32_t RESERVED0[321];
mbed_official 85:e1a8e879a6a9 1101 __IO uint32_t OUT; /*!< Write GPIO port. */
mbed_official 85:e1a8e879a6a9 1102 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
mbed_official 85:e1a8e879a6a9 1103 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
mbed_official 85:e1a8e879a6a9 1104 __I uint32_t IN; /*!< Read GPIO port. */
mbed_official 85:e1a8e879a6a9 1105 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
mbed_official 85:e1a8e879a6a9 1106 __IO uint32_t DIRSET; /*!< DIR set register. */
mbed_official 85:e1a8e879a6a9 1107 __IO uint32_t DIRCLR; /*!< DIR clear register. */
mbed_official 85:e1a8e879a6a9 1108 __I uint32_t RESERVED1[120];
mbed_official 85:e1a8e879a6a9 1109 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
mbed_official 85:e1a8e879a6a9 1110 } NRF_GPIO_Type;
mbed_official 85:e1a8e879a6a9 1111
mbed_official 85:e1a8e879a6a9 1112
mbed_official 85:e1a8e879a6a9 1113 /* -------------------- End of section using anonymous unions ------------------- */
mbed_official 85:e1a8e879a6a9 1114 #if defined(__CC_ARM)
mbed_official 85:e1a8e879a6a9 1115 #pragma pop
mbed_official 85:e1a8e879a6a9 1116 #elif defined(__ICCARM__)
mbed_official 85:e1a8e879a6a9 1117 /* leave anonymous unions enabled */
mbed_official 85:e1a8e879a6a9 1118 #elif defined(__GNUC__)
mbed_official 85:e1a8e879a6a9 1119 /* anonymous unions are enabled by default */
mbed_official 85:e1a8e879a6a9 1120 #elif defined(__TMS470__)
mbed_official 85:e1a8e879a6a9 1121 /* anonymous unions are enabled by default */
mbed_official 85:e1a8e879a6a9 1122 #elif defined(__TASKING__)
mbed_official 85:e1a8e879a6a9 1123 #pragma warning restore
mbed_official 85:e1a8e879a6a9 1124 #else
mbed_official 85:e1a8e879a6a9 1125 #warning Not supported compiler type
mbed_official 85:e1a8e879a6a9 1126 #endif
mbed_official 85:e1a8e879a6a9 1127
mbed_official 85:e1a8e879a6a9 1128
mbed_official 85:e1a8e879a6a9 1129
mbed_official 85:e1a8e879a6a9 1130
mbed_official 85:e1a8e879a6a9 1131 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1132 /* ================ Peripheral memory map ================ */
mbed_official 85:e1a8e879a6a9 1133 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1134
mbed_official 85:e1a8e879a6a9 1135 #define NRF_POWER_BASE 0x40000000UL
mbed_official 85:e1a8e879a6a9 1136 #define NRF_CLOCK_BASE 0x40000000UL
mbed_official 85:e1a8e879a6a9 1137 #define NRF_MPU_BASE 0x40000000UL
mbed_official 85:e1a8e879a6a9 1138 #define NRF_PU_BASE 0x40000000UL
mbed_official 85:e1a8e879a6a9 1139 #define NRF_AMLI_BASE 0x40000000UL
mbed_official 85:e1a8e879a6a9 1140 #define NRF_RADIO_BASE 0x40001000UL
mbed_official 85:e1a8e879a6a9 1141 #define NRF_UART0_BASE 0x40002000UL
mbed_official 85:e1a8e879a6a9 1142 #define NRF_SPI0_BASE 0x40003000UL
mbed_official 85:e1a8e879a6a9 1143 #define NRF_TWI0_BASE 0x40003000UL
mbed_official 85:e1a8e879a6a9 1144 #define NRF_SPI1_BASE 0x40004000UL
mbed_official 85:e1a8e879a6a9 1145 #define NRF_TWI1_BASE 0x40004000UL
mbed_official 85:e1a8e879a6a9 1146 #define NRF_SPIS1_BASE 0x40004000UL
mbed_official 85:e1a8e879a6a9 1147 #define NRF_GPIOTE_BASE 0x40006000UL
mbed_official 85:e1a8e879a6a9 1148 #define NRF_ADC_BASE 0x40007000UL
mbed_official 85:e1a8e879a6a9 1149 #define NRF_TIMER0_BASE 0x40008000UL
mbed_official 85:e1a8e879a6a9 1150 #define NRF_TIMER1_BASE 0x40009000UL
mbed_official 85:e1a8e879a6a9 1151 #define NRF_TIMER2_BASE 0x4000A000UL
mbed_official 85:e1a8e879a6a9 1152 #define NRF_RTC0_BASE 0x4000B000UL
mbed_official 85:e1a8e879a6a9 1153 #define NRF_TEMP_BASE 0x4000C000UL
mbed_official 85:e1a8e879a6a9 1154 #define NRF_RNG_BASE 0x4000D000UL
mbed_official 85:e1a8e879a6a9 1155 #define NRF_ECB_BASE 0x4000E000UL
mbed_official 85:e1a8e879a6a9 1156 #define NRF_AAR_BASE 0x4000F000UL
mbed_official 85:e1a8e879a6a9 1157 #define NRF_CCM_BASE 0x4000F000UL
mbed_official 85:e1a8e879a6a9 1158 #define NRF_WDT_BASE 0x40010000UL
mbed_official 85:e1a8e879a6a9 1159 #define NRF_RTC1_BASE 0x40011000UL
mbed_official 85:e1a8e879a6a9 1160 #define NRF_QDEC_BASE 0x40012000UL
mbed_official 85:e1a8e879a6a9 1161 #define NRF_LPCOMP_BASE 0x40013000UL
mbed_official 85:e1a8e879a6a9 1162 #define NRF_COMP_BASE 0x40013000UL
mbed_official 85:e1a8e879a6a9 1163 #define NRF_SWI_BASE 0x40014000UL
mbed_official 85:e1a8e879a6a9 1164 #define NRF_NVMC_BASE 0x4001E000UL
mbed_official 85:e1a8e879a6a9 1165 #define NRF_PPI_BASE 0x4001F000UL
mbed_official 85:e1a8e879a6a9 1166 #define NRF_FICR_BASE 0x10000000UL
mbed_official 85:e1a8e879a6a9 1167 #define NRF_UICR_BASE 0x10001000UL
mbed_official 85:e1a8e879a6a9 1168 #define NRF_GPIO_BASE 0x50000000UL
mbed_official 85:e1a8e879a6a9 1169
mbed_official 85:e1a8e879a6a9 1170
mbed_official 85:e1a8e879a6a9 1171 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1172 /* ================ Peripheral declaration ================ */
mbed_official 85:e1a8e879a6a9 1173 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1174
mbed_official 85:e1a8e879a6a9 1175 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
mbed_official 85:e1a8e879a6a9 1176 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
mbed_official 85:e1a8e879a6a9 1177 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
mbed_official 85:e1a8e879a6a9 1178 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
mbed_official 85:e1a8e879a6a9 1179 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
mbed_official 85:e1a8e879a6a9 1180 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
mbed_official 85:e1a8e879a6a9 1181 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
mbed_official 85:e1a8e879a6a9 1182 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
mbed_official 85:e1a8e879a6a9 1183 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
mbed_official 85:e1a8e879a6a9 1184 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
mbed_official 85:e1a8e879a6a9 1185 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
mbed_official 85:e1a8e879a6a9 1186 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
mbed_official 85:e1a8e879a6a9 1187 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
mbed_official 85:e1a8e879a6a9 1188 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
mbed_official 85:e1a8e879a6a9 1189 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
mbed_official 85:e1a8e879a6a9 1190 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
mbed_official 85:e1a8e879a6a9 1191 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
mbed_official 85:e1a8e879a6a9 1192 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
mbed_official 85:e1a8e879a6a9 1193 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
mbed_official 85:e1a8e879a6a9 1194 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
mbed_official 85:e1a8e879a6a9 1195 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
mbed_official 85:e1a8e879a6a9 1196 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
mbed_official 85:e1a8e879a6a9 1197 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
mbed_official 85:e1a8e879a6a9 1198 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
mbed_official 85:e1a8e879a6a9 1199 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
mbed_official 85:e1a8e879a6a9 1200 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
mbed_official 85:e1a8e879a6a9 1201 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
mbed_official 85:e1a8e879a6a9 1202 #define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
mbed_official 85:e1a8e879a6a9 1203 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
mbed_official 85:e1a8e879a6a9 1204 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
mbed_official 85:e1a8e879a6a9 1205 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
mbed_official 85:e1a8e879a6a9 1206 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
mbed_official 85:e1a8e879a6a9 1207 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
mbed_official 85:e1a8e879a6a9 1208 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
mbed_official 85:e1a8e879a6a9 1209
mbed_official 85:e1a8e879a6a9 1210
mbed_official 85:e1a8e879a6a9 1211 /** @} */ /* End of group Device_Peripheral_Registers */
mbed_official 85:e1a8e879a6a9 1212 /** @} */ /* End of group nRF51 */
mbed_official 85:e1a8e879a6a9 1213 /** @} */ /* End of group Nordic Semiconductor */
mbed_official 85:e1a8e879a6a9 1214
mbed_official 85:e1a8e879a6a9 1215 #ifdef __cplusplus
mbed_official 85:e1a8e879a6a9 1216 }
mbed_official 85:e1a8e879a6a9 1217 #endif
mbed_official 85:e1a8e879a6a9 1218
mbed_official 85:e1a8e879a6a9 1219
mbed_official 85:e1a8e879a6a9 1220 #endif /* nRF51_H */
mbed_official 85:e1a8e879a6a9 1221