Peter Drescher / EALib

The wait in mci_WaitForEvent will delay all card transactions.

Dependencies:   FATFileSystem

Fork of EALib by EmbeddedArtists AB

LcdController.cpp@4:b32cf4ef45c5, 2013-10-18 (annotated)

Committer:
embeddedartists
Date:
Fri Oct 18 12:48:58 2013 +0200
Revision:
4:b32cf4ef45c5
Parent:
0:0fdadbc3d852 
Added AR1021 touch controller

Added MMA7455 accelerometer

Who changed what in which revision?

UserRevisionLine numberNew contents of line
embeddedartists 4:b32cf4ef45c5 1
embeddedartists 4:b32cf4ef45c5 2 /******************************************************************************
embeddedartists 4:b32cf4ef45c5 3 * Includes
embeddedartists 4:b32cf4ef45c5 4 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 5
embeddedartists 0:0fdadbc3d852 6 #include "mbed.h"
embeddedartists 0:0fdadbc3d852 7 #include "LcdController.h"
embeddedartists 0:0fdadbc3d852 8
embeddedartists 4:b32cf4ef45c5 9 /******************************************************************************
embeddedartists 4:b32cf4ef45c5 10 * Defines and typedefs
embeddedartists 4:b32cf4ef45c5 11 *****************************************************************************/
embeddedartists 4:b32cf4ef45c5 12
embeddedartists 0:0fdadbc3d852 13 #undef _SBF
embeddedartists 0:0fdadbc3d852 14 #define _SBF(p,v) (((uint32_t)(v)) << (p))
embeddedartists 0:0fdadbc3d852 15
embeddedartists 0:0fdadbc3d852 16 #undef _BITMASK
embeddedartists 0:0fdadbc3d852 17 #define _BITMASK(field_width) (_BIT(field_width) - 1)
embeddedartists 0:0fdadbc3d852 18
embeddedartists 0:0fdadbc3d852 19 #undef _BIT
embeddedartists 0:0fdadbc3d852 20 #define _BIT(p) (((uint32_t)(1)) << (p))
embeddedartists 0:0fdadbc3d852 21
embeddedartists 0:0fdadbc3d852 22 /***********************************************************************
embeddedartists 0:0fdadbc3d852 23 * Color LCD controller horizontal axis plane control register definitions
embeddedartists 0:0fdadbc3d852 24 **********************************************************************/
embeddedartists 0:0fdadbc3d852 25
embeddedartists 0:0fdadbc3d852 26 /* LCD controller horizontal axis plane control register pixels per line */
embeddedartists 0:0fdadbc3d852 27 #define CLCDC_LCDTIMING0_PPL_WIDTH 6
embeddedartists 0:0fdadbc3d852 28 #define CLCDC_LCDTIMING0_PPL(n) _SBF(2, (((n) / 16) - 1) & _BITMASK(CLCDC_LCDTIMING0_PPL_WIDTH))
embeddedartists 0:0fdadbc3d852 29 /* LCD controller horizontal axis plane control register HSYNC pulse width */
embeddedartists 0:0fdadbc3d852 30 #define CLCDC_LCDTIMING0_HSW_WIDTH 8
embeddedartists 0:0fdadbc3d852 31 #define CLCDC_LCDTIMING0_HSW(n) _SBF(8, ((n) - 1) & _BITMASK(CLCDC_LCDTIMING0_HSW_WIDTH))
embeddedartists 0:0fdadbc3d852 32 /* LCD controller horizontal axis plane control register horizontal front porch */
embeddedartists 0:0fdadbc3d852 33 #define CLCDC_LCDTIMING0_HFP_WIDTH 8
embeddedartists 0:0fdadbc3d852 34 #define CLCDC_LCDTIMING0_HFP(n) _SBF(16, ((n) - 1) & _BITMASK(CLCDC_LCDTIMING0_HFP_WIDTH))
embeddedartists 0:0fdadbc3d852 35 /* LCD controller horizontal axis plane control register horizontal back porch */
embeddedartists 0:0fdadbc3d852 36 #define CLCDC_LCDTIMING0_HBP_WIDTH 8
embeddedartists 0:0fdadbc3d852 37 #define CLCDC_LCDTIMING0_HBP(n) _SBF(24, ((n) - 1) & _BITMASK(CLCDC_LCDTIMING0_HBP_WIDTH))
embeddedartists 0:0fdadbc3d852 38
embeddedartists 0:0fdadbc3d852 39 /***********************************************************************
embeddedartists 0:0fdadbc3d852 40 * Color LCD controller vertical axis plane control register definitions
embeddedartists 0:0fdadbc3d852 41 **********************************************************************/
embeddedartists 0:0fdadbc3d852 42
embeddedartists 0:0fdadbc3d852 43 /* LCD controller vertical axis plane control register lines per panel */
embeddedartists 0:0fdadbc3d852 44 #define CLCDC_LCDTIMING1_LPP_WIDTH 10
embeddedartists 0:0fdadbc3d852 45 #define CLCDC_LCDTIMING1_LPP(n) _SBF(0, ((n) - 1) & _BITMASK(CLCDC_LCDTIMING1_LPP_WIDTH))
embeddedartists 0:0fdadbc3d852 46 /* LCD controller vertical axis plane control register VSYNC pulse width */
embeddedartists 0:0fdadbc3d852 47 #define CLCDC_LCDTIMING1_VSW_WIDTH 6
embeddedartists 0:0fdadbc3d852 48 #define CLCDC_LCDTIMING1_VSW(n) _SBF(10, ((n) - 1) & _BITMASK(CLCDC_LCDTIMING1_VSW_WIDTH))
embeddedartists 0:0fdadbc3d852 49 /* LCD controller vertical axis plane control register vertical front porch */
embeddedartists 0:0fdadbc3d852 50 #define CLCDC_LCDTIMING1_VFP_WIDTH 8
embeddedartists 0:0fdadbc3d852 51 #define CLCDC_LCDTIMING1_VFP(n) _SBF(16, (n) & _BITMASK(CLCDC_LCDTIMING1_VFP_WIDTH))
embeddedartists 0:0fdadbc3d852 52 /* LCD controller vertical axis plane control register vertical back porch */
embeddedartists 0:0fdadbc3d852 53 #define CLCDC_LCDTIMING1_VBP_WIDTH 8
embeddedartists 0:0fdadbc3d852 54 #define CLCDC_LCDTIMING1_VBP(n) _SBF(24, (n) & _BITMASK(CLCDC_LCDTIMING1_VBP_WIDTH))
embeddedartists 0:0fdadbc3d852 55
embeddedartists 0:0fdadbc3d852 56 /***********************************************************************
embeddedartists 0:0fdadbc3d852 57 * Color LCD controller clock and signal polarity control register definitions
embeddedartists 0:0fdadbc3d852 58 **********************************************************************/
embeddedartists 0:0fdadbc3d852 59
embeddedartists 0:0fdadbc3d852 60 /* LCD controller clock and signal polarity control register panel clock divisor low*/
embeddedartists 0:0fdadbc3d852 61 #define CLCDC_LCDTIMING2_PCD_LO_WIDTH 5
embeddedartists 0:0fdadbc3d852 62 #define CLCDC_LCDTIMING2_PCD_LO(n) _SBF(0, ((n) - 2) & _BITMASK(CLCDC_LCDTIMING2_PCD_LO_WIDTH))
embeddedartists 0:0fdadbc3d852 63 /* LCD controller clock and signal polarity control register clock select */
embeddedartists 0:0fdadbc3d852 64 #define CLCDC_LCDTIMING2_CLKSEL _BIT(5)
embeddedartists 0:0fdadbc3d852 65 /* LCD controller clock and signal polarity control register AC bias pin frequency */
embeddedartists 0:0fdadbc3d852 66 #define CLCDC_LCDTIMING2_ACB_WIDTH 5
embeddedartists 0:0fdadbc3d852 67 #define CLCDC_LCDTIMING2_ACB(n) _SBF(6, ((n) - 1) & _BITMASK(CLCDC_LCDTIMING2_ACB_WIDTH))
embeddedartists 0:0fdadbc3d852 68 /* LCD controller clock and signal polarity control register invert VSYNC */
embeddedartists 0:0fdadbc3d852 69 #define CLCDC_LCDTIMING2_IVS _BIT(11)
embeddedartists 0:0fdadbc3d852 70 /* LCD controller clock and signal polarity control register invert HSYNC */
embeddedartists 0:0fdadbc3d852 71 #define CLCDC_LCDTIMING2_IHS _BIT(12)
embeddedartists 0:0fdadbc3d852 72 /* LCD controller clock and signal polarity control register invert plane clock */
embeddedartists 0:0fdadbc3d852 73 #define CLCDC_LCDTIMING2_IPC _BIT(13)
embeddedartists 0:0fdadbc3d852 74 /* LCD controller clock and signal polarity control register invert output enable */
embeddedartists 0:0fdadbc3d852 75 #define CLCDC_LCDTIMING2_IOE _BIT(14)
embeddedartists 0:0fdadbc3d852 76 /* LCD controller clock and signal polarity control register clocks per line */
embeddedartists 0:0fdadbc3d852 77 #define CLCDC_LCDTIMING2_CPL_WIDTH 10
embeddedartists 0:0fdadbc3d852 78 #define CLCDC_LCDTIMING2_CPL(n) _SBF(16, (n) & _BITMASK(CLCDC_LCDTIMING2_CPL_WIDTH))
embeddedartists 0:0fdadbc3d852 79 /* LCD controller clock and signal polarity control register bypass pixel clock divider */
embeddedartists 0:0fdadbc3d852 80 #define CLCDC_LCDTIMING2_BCD _BIT(26)
embeddedartists 0:0fdadbc3d852 81 /* LCD controller clock and signal polarity control register panel clock divisor high*/
embeddedartists 0:0fdadbc3d852 82 #define CLCDC_LCDTIMING2_PCD_HI_WIDTH 5
embeddedartists 0:0fdadbc3d852 83 #define CLCDC_LCDTIMING2_PCD_HI(n) _SBF((27 - CLCDC_LCDTIMING2_PCD_LO_WIDTH), ((n) - 2) & _SBF(CLCDC_LCDTIMING2_PCD_LO_WIDTH, _BITMASK(CLCDC_LCDTIMING2_PCD_HI_WIDTH)))
embeddedartists 0:0fdadbc3d852 84
embeddedartists 0:0fdadbc3d852 85
embeddedartists 0:0fdadbc3d852 86 /***********************************************************************
embeddedartists 0:0fdadbc3d852 87 * Color LCD controller control register definitions
embeddedartists 0:0fdadbc3d852 88 **********************************************************************/
embeddedartists 0:0fdadbc3d852 89
embeddedartists 0:0fdadbc3d852 90 /* LCD control enable bit */
embeddedartists 0:0fdadbc3d852 91 #define CLCDC_LCDCTRL_ENABLE (1<<0)
embeddedartists 0:0fdadbc3d852 92 /* LCD control 1 bit per pixel bit field */
embeddedartists 0:0fdadbc3d852 93 #define CLCDC_LCDCTRL_BPP1 (0 << 1)
embeddedartists 0:0fdadbc3d852 94 /* LCD control 2 bits per pixel bit field */
embeddedartists 0:0fdadbc3d852 95 #define CLCDC_LCDCTRL_BPP2 (1 << 1)
embeddedartists 0:0fdadbc3d852 96 /* LCD control 4 bits per pixel bit field */
embeddedartists 0:0fdadbc3d852 97 #define CLCDC_LCDCTRL_BPP4 (2 << 1)
embeddedartists 0:0fdadbc3d852 98 /* LCD control 8 bits per pixel bit field */
embeddedartists 0:0fdadbc3d852 99 #define CLCDC_LCDCTRL_BPP8 (3 << 1)
embeddedartists 0:0fdadbc3d852 100 /* LCD control 16 bits per pixel bit field */
embeddedartists 0:0fdadbc3d852 101 #define CLCDC_LCDCTRL_BPP16 (4 << 1)
embeddedartists 0:0fdadbc3d852 102 /* LCD control 24 bits per pixel bit field */
embeddedartists 0:0fdadbc3d852 103 #define CLCDC_LCDCTRL_BPP24 (5 << 1)
embeddedartists 0:0fdadbc3d852 104 /* LCD control 16 bits (5:6:5 mode) per pixel bit field */
embeddedartists 0:0fdadbc3d852 105 #define CLCDC_LCDCTRL_BPP16_565_MODE (6 << 1)
embeddedartists 0:0fdadbc3d852 106 /* LCD control 12 bits (4:4:4 mode) per pixel bit field */
embeddedartists 0:0fdadbc3d852 107 #define CLCDC_LCDCTRL_BPP12_444_MODE (7 << 1)
embeddedartists 0:0fdadbc3d852 108 /* LCD control mono select bit */
embeddedartists 0:0fdadbc3d852 109 #define CLCDC_LCDCTRL_BW_COLOR (0 << 4)
embeddedartists 0:0fdadbc3d852 110 #define CLCDC_LCDCTRL_BW_MONO (1 << 4)
embeddedartists 0:0fdadbc3d852 111 /* LCD controler TFT select bit */
embeddedartists 0:0fdadbc3d852 112 #define CLCDC_LCDCTRL_TFT (1 << 5)
embeddedartists 0:0fdadbc3d852 113 /* LCD control monochrome LCD has 4-bit/8-bit select bit */
embeddedartists 0:0fdadbc3d852 114 #define CLCDC_LCDCTRL_MON8 (1 << 6)
embeddedartists 0:0fdadbc3d852 115 /* LCD control dual panel select bit */
embeddedartists 0:0fdadbc3d852 116 #define CLCDC_LCDCTRL_DUAL (1 << 7)
embeddedartists 0:0fdadbc3d852 117 /* LCD control RGB or BGR format select bit */
embeddedartists 0:0fdadbc3d852 118 #define CLCDC_LCDCTRL_RGB (0 << 8)
embeddedartists 0:0fdadbc3d852 119 #define CLCDC_LCDCTRL_BGR (1 << 8)
embeddedartists 0:0fdadbc3d852 120 /* LCD control big-endian byte order select bit */
embeddedartists 0:0fdadbc3d852 121 #define CLCDC_LCDCTRL_BEBO (1 << 9)
embeddedartists 0:0fdadbc3d852 122 /* LCD control big-endian pixel order within a byte select bit */
embeddedartists 0:0fdadbc3d852 123 #define CLCDC_LCDCTRL_BEPO (1 << 10)
embeddedartists 0:0fdadbc3d852 124 /* LCD control power enable bit */
embeddedartists 0:0fdadbc3d852 125 #define CLCDC_LCDCTRL_PWR (1 << 11)
embeddedartists 0:0fdadbc3d852 126 /* LCD control VCOMP interrupt is start of VSYNC */
embeddedartists 0:0fdadbc3d852 127 #define CLCDC_LCDCTRL_VCOMP_VS (0 << 12)
embeddedartists 0:0fdadbc3d852 128 /* LCD control VCOMP interrupt is start of back porch */
embeddedartists 0:0fdadbc3d852 129 #define CLCDC_LCDCTRL_VCOMP_BP (1 << 12)
embeddedartists 0:0fdadbc3d852 130 /* LCD control VCOMP interrupt is start of active video */
embeddedartists 0:0fdadbc3d852 131 #define CLCDC_LCDCTRL_VCOMP_AV (2 << 12)
embeddedartists 0:0fdadbc3d852 132 /* LCD control VCOMP interrupt is start of front porch */
embeddedartists 0:0fdadbc3d852 133 #define CLCDC_LCDCTRL_VCOMP_FP (3 << 12)
embeddedartists 0:0fdadbc3d852 134 /* LCD control watermark level is 8 or more words free bit */
embeddedartists 0:0fdadbc3d852 135 #define CLCDC_LCDCTRL_WATERMARK (1 << 16)
embeddedartists 0:0fdadbc3d852 136
embeddedartists 0:0fdadbc3d852 137
embeddedartists 0:0fdadbc3d852 138
embeddedartists 0:0fdadbc3d852 139 bool LcdController::_lcdControllerUsed = false;
embeddedartists 0:0fdadbc3d852 140
embeddedartists 0:0fdadbc3d852 141 LcdController::LcdController() {
embeddedartists 0:0fdadbc3d852 142 _opened = false;
embeddedartists 0:0fdadbc3d852 143 }
embeddedartists 0:0fdadbc3d852 144
embeddedartists 0:0fdadbc3d852 145 int LcdController::open(LcdController::Config* cfg) {
embeddedartists 0:0fdadbc3d852 146 if (_lcdControllerUsed) return 1;
embeddedartists 0:0fdadbc3d852 147 if (cfg == NULL) return 1;
embeddedartists 0:0fdadbc3d852 148
embeddedartists 0:0fdadbc3d852 149 // enable power for LCD controller
embeddedartists 0:0fdadbc3d852 150 LPC_SC->PCONP |= 0x00000001;
embeddedartists 0:0fdadbc3d852 151
embeddedartists 0:0fdadbc3d852 152 pinConfig();
embeddedartists 0:0fdadbc3d852 153 init(cfg);
embeddedartists 0:0fdadbc3d852 154
embeddedartists 0:0fdadbc3d852 155 // only one instance at a time is allowed to be used
embeddedartists 0:0fdadbc3d852 156 _lcdControllerUsed = true;
embeddedartists 0:0fdadbc3d852 157 _opened = true;
embeddedartists 0:0fdadbc3d852 158
embeddedartists 0:0fdadbc3d852 159 return 0;
embeddedartists 0:0fdadbc3d852 160 }
embeddedartists 0:0fdadbc3d852 161
embeddedartists 0:0fdadbc3d852 162 int LcdController::close() {
embeddedartists 0:0fdadbc3d852 163
embeddedartists 0:0fdadbc3d852 164 if (!_opened) return 1;
embeddedartists 0:0fdadbc3d852 165
embeddedartists 0:0fdadbc3d852 166 if (_lcdControllerUsed) {
embeddedartists 0:0fdadbc3d852 167
embeddedartists 0:0fdadbc3d852 168 // disable power for LCD controller
embeddedartists 0:0fdadbc3d852 169 LPC_SC->PCONP &= ~(0x00000001);
embeddedartists 0:0fdadbc3d852 170
embeddedartists 0:0fdadbc3d852 171 _lcdControllerUsed = false;
embeddedartists 0:0fdadbc3d852 172 _opened = false;
embeddedartists 0:0fdadbc3d852 173 }
embeddedartists 0:0fdadbc3d852 174
embeddedartists 0:0fdadbc3d852 175
embeddedartists 0:0fdadbc3d852 176 return 0;
embeddedartists 0:0fdadbc3d852 177 }
embeddedartists 0:0fdadbc3d852 178
embeddedartists 0:0fdadbc3d852 179 int LcdController::setFrameBuffer(uint32_t address) {
embeddedartists 0:0fdadbc3d852 180 if (!_opened) return 1;
embeddedartists 0:0fdadbc3d852 181
embeddedartists 0:0fdadbc3d852 182 LPC_LCD->UPBASE = address;
embeddedartists 0:0fdadbc3d852 183
embeddedartists 0:0fdadbc3d852 184 return 0;
embeddedartists 0:0fdadbc3d852 185 }
embeddedartists 0:0fdadbc3d852 186
embeddedartists 0:0fdadbc3d852 187 int LcdController::setPower(bool on) {
embeddedartists 0:0fdadbc3d852 188 if (!_opened) return 1;
embeddedartists 0:0fdadbc3d852 189
embeddedartists 0:0fdadbc3d852 190 if (on) {
embeddedartists 0:0fdadbc3d852 191 LPC_LCD->CTRL |= CLCDC_LCDCTRL_ENABLE;
embeddedartists 0:0fdadbc3d852 192 LPC_LCD->CTRL |= CLCDC_LCDCTRL_PWR;
embeddedartists 0:0fdadbc3d852 193 }
embeddedartists 0:0fdadbc3d852 194 else {
embeddedartists 0:0fdadbc3d852 195 LPC_LCD->CTRL &= ~CLCDC_LCDCTRL_PWR;
embeddedartists 0:0fdadbc3d852 196 LPC_LCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
embeddedartists 0:0fdadbc3d852 197 }
embeddedartists 0:0fdadbc3d852 198
embeddedartists 0:0fdadbc3d852 199 return 0;
embeddedartists 0:0fdadbc3d852 200 }
embeddedartists 0:0fdadbc3d852 201
embeddedartists 0:0fdadbc3d852 202 void LcdController::init(LcdController::Config* cfg) {
embeddedartists 0:0fdadbc3d852 203 uint32_t tmp, i;
embeddedartists 0:0fdadbc3d852 204
embeddedartists 0:0fdadbc3d852 205 // Disable the display in case it is on
embeddedartists 0:0fdadbc3d852 206 LPC_LCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
embeddedartists 0:0fdadbc3d852 207
embeddedartists 0:0fdadbc3d852 208 // Generate the horizontal axis plane control word
embeddedartists 0:0fdadbc3d852 209 tmp = (CLCDC_LCDTIMING0_PPL(cfg->width) |
embeddedartists 0:0fdadbc3d852 210 CLCDC_LCDTIMING0_HSW(cfg->hsync) |
embeddedartists 0:0fdadbc3d852 211 CLCDC_LCDTIMING0_HFP(cfg->horizontalFrontPorch) |
embeddedartists 0:0fdadbc3d852 212 CLCDC_LCDTIMING0_HBP(cfg->horizontalBackPorch));
embeddedartists 0:0fdadbc3d852 213 LPC_LCD->TIMH = tmp;
embeddedartists 0:0fdadbc3d852 214
embeddedartists 0:0fdadbc3d852 215 // Generate the vertical axis plane control word
embeddedartists 0:0fdadbc3d852 216 tmp = (CLCDC_LCDTIMING1_LPP(cfg->height) |
embeddedartists 0:0fdadbc3d852 217 CLCDC_LCDTIMING1_VSW(cfg->vsync) |
embeddedartists 0:0fdadbc3d852 218 CLCDC_LCDTIMING1_VFP(cfg->verticalFrontPorch) |
embeddedartists 0:0fdadbc3d852 219 CLCDC_LCDTIMING1_VBP(cfg->verticalBackPorch));
embeddedartists 0:0fdadbc3d852 220 LPC_LCD->TIMV = tmp;
embeddedartists 0:0fdadbc3d852 221
embeddedartists 0:0fdadbc3d852 222 // Generate the clock and signal polarity control word
embeddedartists 0:0fdadbc3d852 223 if(cfg->acBias != 0)
embeddedartists 0:0fdadbc3d852 224 {
embeddedartists 0:0fdadbc3d852 225 /* STN panel has AC bias value */
embeddedartists 0:0fdadbc3d852 226 tmp = CLCDC_LCDTIMING2_ACB(cfg->acBias);
embeddedartists 0:0fdadbc3d852 227 }
embeddedartists 0:0fdadbc3d852 228 else
embeddedartists 0:0fdadbc3d852 229 {
embeddedartists 0:0fdadbc3d852 230 tmp = 0;
embeddedartists 0:0fdadbc3d852 231 }
embeddedartists 0:0fdadbc3d852 232
embeddedartists 0:0fdadbc3d852 233 if (cfg->invertOutputEnable)
embeddedartists 0:0fdadbc3d852 234 {
embeddedartists 0:0fdadbc3d852 235 tmp |= CLCDC_LCDTIMING2_IOE;
embeddedartists 0:0fdadbc3d852 236 }
embeddedartists 0:0fdadbc3d852 237
embeddedartists 0:0fdadbc3d852 238 if (cfg->invertPanelClock)
embeddedartists 0:0fdadbc3d852 239 {
embeddedartists 0:0fdadbc3d852 240 tmp |= CLCDC_LCDTIMING2_IPC;
embeddedartists 0:0fdadbc3d852 241 }
embeddedartists 0:0fdadbc3d852 242
embeddedartists 0:0fdadbc3d852 243 if (cfg->invertHsync)
embeddedartists 0:0fdadbc3d852 244 {
embeddedartists 0:0fdadbc3d852 245 tmp |= CLCDC_LCDTIMING2_IHS;
embeddedartists 0:0fdadbc3d852 246 }
embeddedartists 0:0fdadbc3d852 247
embeddedartists 0:0fdadbc3d852 248 if (cfg->invertVsync)
embeddedartists 0:0fdadbc3d852 249 {
embeddedartists 0:0fdadbc3d852 250 tmp |= CLCDC_LCDTIMING2_IVS;
embeddedartists 0:0fdadbc3d852 251 }
embeddedartists 0:0fdadbc3d852 252
embeddedartists 0:0fdadbc3d852 253 // Compute clocks per line based on panel type
embeddedartists 0:0fdadbc3d852 254 switch (cfg->panelType)
embeddedartists 0:0fdadbc3d852 255 {
embeddedartists 0:0fdadbc3d852 256 case Mono_4Bit:
embeddedartists 0:0fdadbc3d852 257 // Clocks per line is a quarter of pixels per line
embeddedartists 0:0fdadbc3d852 258 tmp = tmp | CLCDC_LCDTIMING2_CPL((cfg->width / 4) - 1);
embeddedartists 0:0fdadbc3d852 259 break;
embeddedartists 0:0fdadbc3d852 260
embeddedartists 0:0fdadbc3d852 261 case Mono_8Bit:
embeddedartists 0:0fdadbc3d852 262 // Clocks per line is an eighth of pixels per line
embeddedartists 0:0fdadbc3d852 263 tmp = tmp | CLCDC_LCDTIMING2_CPL((cfg->width / 8) - 1);
embeddedartists 0:0fdadbc3d852 264 break;
embeddedartists 0:0fdadbc3d852 265
embeddedartists 0:0fdadbc3d852 266 case ColorStn:
embeddedartists 0:0fdadbc3d852 267 // CSTN Clocks per line (* 3 / 8)
embeddedartists 0:0fdadbc3d852 268 tmp = tmp | CLCDC_LCDTIMING2_CPL(((cfg->width * 3) / 8) - 1);
embeddedartists 0:0fdadbc3d852 269 break;
embeddedartists 0:0fdadbc3d852 270
embeddedartists 0:0fdadbc3d852 271 case Tft:
embeddedartists 0:0fdadbc3d852 272 case AdTft:
embeddedartists 0:0fdadbc3d852 273 case HrTft:
embeddedartists 0:0fdadbc3d852 274 default:
embeddedartists 0:0fdadbc3d852 275 // Clocks per line and pixels per line are the same
embeddedartists 0:0fdadbc3d852 276 tmp = tmp | CLCDC_LCDTIMING2_CPL(cfg->width - 1);
embeddedartists 0:0fdadbc3d852 277 break;
embeddedartists 0:0fdadbc3d852 278 }
embeddedartists 0:0fdadbc3d852 279
embeddedartists 0:0fdadbc3d852 280 // clock
embeddedartists 0:0fdadbc3d852 281 tmp = tmp | getClockDivisor(cfg->optimalClock);
embeddedartists 0:0fdadbc3d852 282
embeddedartists 0:0fdadbc3d852 283 LPC_LCD->POL = tmp;
embeddedartists 0:0fdadbc3d852 284
embeddedartists 0:0fdadbc3d852 285 // Skip line end control word - just set to 0x0
embeddedartists 0:0fdadbc3d852 286 LPC_LCD->LE = 0x00000000;
embeddedartists 0:0fdadbc3d852 287
embeddedartists 0:0fdadbc3d852 288 // Default with all interrupts of
embeddedartists 0:0fdadbc3d852 289 LPC_LCD->INTMSK = 0x00000000;
embeddedartists 0:0fdadbc3d852 290
embeddedartists 0:0fdadbc3d852 291
embeddedartists 0:0fdadbc3d852 292 switch(cfg->bpp) {
embeddedartists 0:0fdadbc3d852 293 case Bpp_1:
embeddedartists 0:0fdadbc3d852 294 tmp = CLCDC_LCDCTRL_BPP1;
embeddedartists 0:0fdadbc3d852 295 break;
embeddedartists 0:0fdadbc3d852 296 case Bpp_2:
embeddedartists 0:0fdadbc3d852 297 tmp = CLCDC_LCDCTRL_BPP2;
embeddedartists 0:0fdadbc3d852 298 break;
embeddedartists 0:0fdadbc3d852 299 case Bpp_4:
embeddedartists 0:0fdadbc3d852 300 tmp = CLCDC_LCDCTRL_BPP4;
embeddedartists 0:0fdadbc3d852 301 break;
embeddedartists 0:0fdadbc3d852 302 case Bpp_8:
embeddedartists 0:0fdadbc3d852 303 tmp = CLCDC_LCDCTRL_BPP8;
embeddedartists 0:0fdadbc3d852 304 break;
embeddedartists 0:0fdadbc3d852 305 case Bpp_16:
embeddedartists 0:0fdadbc3d852 306 tmp = CLCDC_LCDCTRL_BPP16;
embeddedartists 0:0fdadbc3d852 307 break;
embeddedartists 0:0fdadbc3d852 308 case Bpp_24:
embeddedartists 0:0fdadbc3d852 309 tmp = CLCDC_LCDCTRL_BPP24;
embeddedartists 0:0fdadbc3d852 310 break;
embeddedartists 0:0fdadbc3d852 311 case Bpp_16_565:
embeddedartists 0:0fdadbc3d852 312 tmp = CLCDC_LCDCTRL_BPP16_565_MODE;
embeddedartists 0:0fdadbc3d852 313 break;
embeddedartists 0:0fdadbc3d852 314 case Bpp_12_444:
embeddedartists 0:0fdadbc3d852 315 tmp = CLCDC_LCDCTRL_BPP12_444_MODE;
embeddedartists 0:0fdadbc3d852 316 break;
embeddedartists 0:0fdadbc3d852 317 default:
embeddedartists 0:0fdadbc3d852 318 tmp = CLCDC_LCDCTRL_BPP16_565_MODE;
embeddedartists 0:0fdadbc3d852 319 break;
embeddedartists 0:0fdadbc3d852 320 }
embeddedartists 0:0fdadbc3d852 321
embeddedartists 0:0fdadbc3d852 322 // red and blue swapped
embeddedartists 0:0fdadbc3d852 323 tmp |= CLCDC_LCDCTRL_BGR;
embeddedartists 0:0fdadbc3d852 324
embeddedartists 0:0fdadbc3d852 325 switch (cfg->panelType)
embeddedartists 0:0fdadbc3d852 326 {
embeddedartists 0:0fdadbc3d852 327 case AdTft:
embeddedartists 0:0fdadbc3d852 328 case HrTft:
embeddedartists 0:0fdadbc3d852 329 case Tft:
embeddedartists 0:0fdadbc3d852 330 tmp |= CLCDC_LCDCTRL_TFT;
embeddedartists 0:0fdadbc3d852 331 break;
embeddedartists 0:0fdadbc3d852 332
embeddedartists 0:0fdadbc3d852 333 case Mono_4Bit:
embeddedartists 0:0fdadbc3d852 334 tmp |= CLCDC_LCDCTRL_BW_MONO;
embeddedartists 0:0fdadbc3d852 335 break;
embeddedartists 0:0fdadbc3d852 336
embeddedartists 0:0fdadbc3d852 337 case Mono_8Bit:
embeddedartists 0:0fdadbc3d852 338 tmp |= (CLCDC_LCDCTRL_MON8 | CLCDC_LCDCTRL_BW_MONO);
embeddedartists 0:0fdadbc3d852 339 break;
embeddedartists 0:0fdadbc3d852 340
embeddedartists 0:0fdadbc3d852 341 case ColorStn:
embeddedartists 0:0fdadbc3d852 342 ;
embeddedartists 0:0fdadbc3d852 343 break;
embeddedartists 0:0fdadbc3d852 344
embeddedartists 0:0fdadbc3d852 345 default:
embeddedartists 0:0fdadbc3d852 346 // Unsupported panel type
embeddedartists 0:0fdadbc3d852 347 break;
embeddedartists 0:0fdadbc3d852 348 }
embeddedartists 0:0fdadbc3d852 349
embeddedartists 0:0fdadbc3d852 350 // Dual panel operation
embeddedartists 0:0fdadbc3d852 351 if (cfg->dualPanel)
embeddedartists 0:0fdadbc3d852 352 {
embeddedartists 0:0fdadbc3d852 353 tmp |= CLCDC_LCDCTRL_DUAL;
embeddedartists 0:0fdadbc3d852 354 }
embeddedartists 0:0fdadbc3d852 355
embeddedartists 0:0fdadbc3d852 356 LPC_LCD->CTRL = tmp;
embeddedartists 0:0fdadbc3d852 357
embeddedartists 0:0fdadbc3d852 358 // clear the palette (color is black )
embeddedartists 0:0fdadbc3d852 359 for (i = 0; i < sizeof(LPC_LCD->PAL)/sizeof(LPC_LCD->PAL[0]); i++)
embeddedartists 0:0fdadbc3d852 360 {
embeddedartists 0:0fdadbc3d852 361 LPC_LCD->PAL[i] = 0;
embeddedartists 0:0fdadbc3d852 362 }
embeddedartists 0:0fdadbc3d852 363
embeddedartists 0:0fdadbc3d852 364 LPC_SC->LCD_CFG = 0x0;
embeddedartists 0:0fdadbc3d852 365
embeddedartists 0:0fdadbc3d852 366 }
embeddedartists 0:0fdadbc3d852 367
embeddedartists 0:0fdadbc3d852 368 void LcdController::pinConfig() {
embeddedartists 0:0fdadbc3d852 369
embeddedartists 0:0fdadbc3d852 370 LPC_IOCON->P0_4 |= 7; /* LCD_VD_0 @ P0.4 */
embeddedartists 0:0fdadbc3d852 371 LPC_IOCON->P0_5 |= 7; /* LCD_VD_1 @ P0.5 */
embeddedartists 0:0fdadbc3d852 372 LPC_IOCON->P0_6 |= 7; /* LCD_VD_8 @ P0.6 */
embeddedartists 0:0fdadbc3d852 373 LPC_IOCON->P0_7 |= 7; /* LCD_VD_9 @ P0.7 */
embeddedartists 0:0fdadbc3d852 374 LPC_IOCON->P0_8 |= 7; /* LCD_VD_16 @ P0.8 */
embeddedartists 0:0fdadbc3d852 375 LPC_IOCON->P0_9 |= 7; /* LCD_VD_17 @ P0.9 */
embeddedartists 0:0fdadbc3d852 376 LPC_IOCON->P0_10 |= 7; /* LCD_VD_5 @ P0.10 */ /* LPC4088 */
embeddedartists 0:0fdadbc3d852 377
embeddedartists 0:0fdadbc3d852 378 #ifdef LPC4088_OEM
embeddedartists 0:0fdadbc3d852 379 LPC_IOCON->P1_20 |= 7; /* LCD_VD_10 @ P1.20 */
embeddedartists 0:0fdadbc3d852 380 LPC_IOCON->P1_23 |= 7; /* LCD_VD_13 @ P1.23 */
embeddedartists 0:0fdadbc3d852 381 LPC_IOCON->P1_24 |= 7; /* LCD_VD_14 @ P1.24 */
embeddedartists 0:0fdadbc3d852 382 #else
embeddedartists 0:0fdadbc3d852 383 LPC_IOCON->P0_11 |= 7; /* LCD_VD_10 @ P0.11 */
embeddedartists 0:0fdadbc3d852 384 LPC_IOCON->P0_19 |= 7; /* LCD_VD_13 @ P0.19 */
embeddedartists 0:0fdadbc3d852 385 LPC_IOCON->P0_20 |= 7; /* LCD_VD_14 @ P0.20 */
embeddedartists 0:0fdadbc3d852 386 #endif
embeddedartists 0:0fdadbc3d852 387
embeddedartists 0:0fdadbc3d852 388 LPC_IOCON->P1_21 |= 7; /* LCD_VD_11 @ P1.21 */
embeddedartists 0:0fdadbc3d852 389 LPC_IOCON->P1_22 |= 7; /* LCD_VD_12 @ P1.22 */
embeddedartists 0:0fdadbc3d852 390
embeddedartists 0:0fdadbc3d852 391 LPC_IOCON->P1_25 |= 7; /* LCD_VD_15 @ P1.25 */
embeddedartists 0:0fdadbc3d852 392 LPC_IOCON->P1_26 |= 7; /* LCD_VD_20 @ P1.26 */
embeddedartists 0:0fdadbc3d852 393 LPC_IOCON->P1_27 |= 7; /* LCD_VD_21 @ P1.27 */
embeddedartists 0:0fdadbc3d852 394 LPC_IOCON->P1_28 |= 7; /* LCD_VD_22 @ P1.28 */
embeddedartists 0:0fdadbc3d852 395 LPC_IOCON->P1_29 |= 7; /* LCD_VD_23 @ P1.29 */
embeddedartists 0:0fdadbc3d852 396
embeddedartists 4:b32cf4ef45c5 397 // pwr always controlled by gpio
embeddedartists 4:b32cf4ef45c5 398 // LPC_IOCON->P2_0 |= 7; /* LCD_PWR @ P2.0 */
embeddedartists 0:0fdadbc3d852 399 LPC_IOCON->P2_1 |= 7; /* LCD_LE @ P2.1 */
embeddedartists 0:0fdadbc3d852 400 LPC_IOCON->P2_2 |= 7; /* LCD_DCLK @ P2.2 */
embeddedartists 0:0fdadbc3d852 401 LPC_IOCON->P2_3 |= 7; /* LCD_FP @ P2.3 */
embeddedartists 0:0fdadbc3d852 402 LPC_IOCON->P2_4 |= 7; /* LCD_ENAB_M @ P2.4 */
embeddedartists 0:0fdadbc3d852 403 LPC_IOCON->P2_5 |= 7; /* LCD_LP @ P2.5 */
embeddedartists 0:0fdadbc3d852 404 LPC_IOCON->P2_6 |= 7; /* LCD_VD_4 @ P2.6 */
embeddedartists 0:0fdadbc3d852 405 //LPC_IOCON->P2_7 |= 7; /* LCD_VD_5 @ P2.7 */ /* LPC4088 */
embeddedartists 0:0fdadbc3d852 406 LPC_IOCON->P2_8 |= 7; /* LCD_VD_6 @ P2.8 */
embeddedartists 0:0fdadbc3d852 407 LPC_IOCON->P2_9 |= 7; /* LCD_VD_7 @ P2.9 */
embeddedartists 0:0fdadbc3d852 408
embeddedartists 0:0fdadbc3d852 409 LPC_IOCON->P2_11 |= 7; /* LCD_CLKIN @ P2.11 */
embeddedartists 0:0fdadbc3d852 410 LPC_IOCON->P2_12 |= 5; /* LCD_VD_3 @ P2.12 Signal marked as LCD_VD_18 on base board, but shall carry the LCD_VD_3 signal */
embeddedartists 0:0fdadbc3d852 411 LPC_IOCON->P2_13 |= 7; /* LCD_VD_19 @ P2.13 */
embeddedartists 0:0fdadbc3d852 412 }
embeddedartists 0:0fdadbc3d852 413
embeddedartists 0:0fdadbc3d852 414 uint32_t LcdController::getClockDivisor(int clock) {
embeddedartists 0:0fdadbc3d852 415 uint32_t pixel_div, tmp = 0;
embeddedartists 0:0fdadbc3d852 416 uint32_t clk;
embeddedartists 0:0fdadbc3d852 417
embeddedartists 0:0fdadbc3d852 418 clk = SystemCoreClock;
embeddedartists 0:0fdadbc3d852 419
embeddedartists 0:0fdadbc3d852 420 // Find closest clock divider to get clock rate
embeddedartists 0:0fdadbc3d852 421 pixel_div = 1;
embeddedartists 0:0fdadbc3d852 422 while (((clk / pixel_div) > clock) && (pixel_div <= 0x3F))
embeddedartists 0:0fdadbc3d852 423 {
embeddedartists 0:0fdadbc3d852 424 pixel_div++;
embeddedartists 0:0fdadbc3d852 425 }
embeddedartists 0:0fdadbc3d852 426
embeddedartists 0:0fdadbc3d852 427 if (pixel_div <= 1)
embeddedartists 0:0fdadbc3d852 428 {
embeddedartists 0:0fdadbc3d852 429 // Pixel clock divider is 1, skip divider logic
embeddedartists 0:0fdadbc3d852 430 tmp = CLCDC_LCDTIMING2_BCD;
embeddedartists 0:0fdadbc3d852 431 }
embeddedartists 0:0fdadbc3d852 432 else
embeddedartists 0:0fdadbc3d852 433 {
embeddedartists 0:0fdadbc3d852 434 // Add in new divider
embeddedartists 0:0fdadbc3d852 435 pixel_div -= 2;
embeddedartists 0:0fdadbc3d852 436
embeddedartists 0:0fdadbc3d852 437 tmp |= (((pixel_div >> 0) & 0x1F)
embeddedartists 0:0fdadbc3d852 438 | (((pixel_div >> 5) & 0x1F) << 27));
embeddedartists 0:0fdadbc3d852 439 }
embeddedartists 0:0fdadbc3d852 440
embeddedartists 0:0fdadbc3d852 441 return tmp;
embeddedartists 0:0fdadbc3d852 442 }
embeddedartists 0:0fdadbc3d852 443
embeddedartists 0:0fdadbc3d852 444