Dragica Stoiljkovic / Mbed 2 deprecated BMS_LV_VERZIJA_TESTIRANJE

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Dependencies:   mbed

bq79606.cpp@1:d0662d4ffb8c, 2020-12-20 (annotated)

Committer:
minamax
Date:
Sun Dec 20 18:07:17 2020 +0000
Revision:
1:d0662d4ffb8c
Child:
2:03a6da61d834
Revised

Who changed what in which revision?

UserRevisionLine numberNew contents of line
minamax 1:d0662d4ffb8c 1 #include "mbed.h"
minamax 1:d0662d4ffb8c 2 #include "bq79606.h"
minamax 1:d0662d4ffb8c 3
minamax 1:d0662d4ffb8c 4 int bRes = 0;
minamax 1:d0662d4ffb8c 5 int count = 10000;
minamax 1:d0662d4ffb8c 6 uint8_t pFrame[(MAXBYTES+6)*TOTALBOARDS];
minamax 1:d0662d4ffb8c 7 BYTE bBuf[8];
minamax 1:d0662d4ffb8c 8 BYTE bReturn = 0;
minamax 1:d0662d4ffb8c 9 BYTE response_frame2[(MAXBYTES+6)*TOTALBOARDS];
minamax 1:d0662d4ffb8c 10 BYTE bFrame[(2+6)*TOTALBOARDS];
minamax 1:d0662d4ffb8c 11 int nCurrentBoard = 0;
minamax 1:d0662d4ffb8c 12
minamax 1:d0662d4ffb8c 13 extern Serial bms, pc1;
minamax 1:d0662d4ffb8c 14 extern DigitalIn bmsFault;
minamax 1:d0662d4ffb8c 15 extern DigitalOut bmsWakeUp;
minamax 1:d0662d4ffb8c 16
minamax 1:d0662d4ffb8c 17 void sendUART(int length, uint8_t * data){
minamax 1:d0662d4ffb8c 18 for(int i = 0; i < length; i++)
minamax 1:d0662d4ffb8c 19 bms.putc(data[i]);
minamax 1:d0662d4ffb8c 20 //wait_ms(1);
minamax 1:d0662d4ffb8c 21 }
minamax 1:d0662d4ffb8c 22
minamax 1:d0662d4ffb8c 23 void Wake79606(){
minamax 1:d0662d4ffb8c 24 bmsWakeUp = 1;
minamax 1:d0662d4ffb8c 25 wait_ms(50);
minamax 1:d0662d4ffb8c 26 bmsWakeUp = 0;
minamax 1:d0662d4ffb8c 27 wait_ms(10);
minamax 1:d0662d4ffb8c 28 }
minamax 1:d0662d4ffb8c 29
minamax 1:d0662d4ffb8c 30 void AutoAddress()
minamax 1:d0662d4ffb8c 31 {
minamax 1:d0662d4ffb8c 32 memset(response_frame2,0,sizeof(response_frame2)); //clear out the response frame buffer
minamax 1:d0662d4ffb8c 33
minamax 1:d0662d4ffb8c 34 //dummy write to ECC_TEST (sync DLL)
minamax 1:d0662d4ffb8c 35 WriteReg(0, ECC_TEST, 0x00, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 36
minamax 1:d0662d4ffb8c 37 //clear CONFIG in case it is set
minamax 1:d0662d4ffb8c 38 WriteReg(0, CONFIG, 0x00, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 39
minamax 1:d0662d4ffb8c 40 //enter auto addressing mode
minamax 1:d0662d4ffb8c 41 WriteReg(0, CONTROL1, 0x01, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 42
minamax 1:d0662d4ffb8c 43 //set addresses for all boards in daisy-chain
minamax 1:d0662d4ffb8c 44 for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++)
minamax 1:d0662d4ffb8c 45 {
minamax 1:d0662d4ffb8c 46 WriteReg(nCurrentBoard, DEVADD_USR, nCurrentBoard, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 47 }
minamax 1:d0662d4ffb8c 48
minamax 1:d0662d4ffb8c 49 //set all devices as a stack device
minamax 1:d0662d4ffb8c 50 WriteReg(0, CONFIG, 0x02, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 51
minamax 1:d0662d4ffb8c 52 //if there's only 1 board, it's the base AND the top of stack, so change it to those
minamax 1:d0662d4ffb8c 53 if(TOTALBOARDS==1)
minamax 1:d0662d4ffb8c 54 {
minamax 1:d0662d4ffb8c 55 WriteReg(0, CONFIG, 0x01, 1, FRMWRT_SGL_NR);
minamax 1:d0662d4ffb8c 56 }
minamax 1:d0662d4ffb8c 57 //otherwise set the base and top of stack individually
minamax 1:d0662d4ffb8c 58 else
minamax 1:d0662d4ffb8c 59 {
minamax 1:d0662d4ffb8c 60 WriteReg(0, CONFIG, 0x00, 1, FRMWRT_SGL_NR); //base
minamax 1:d0662d4ffb8c 61 WriteReg(TOTALBOARDS-1, CONFIG, 0x03, 1, FRMWRT_SGL_NR); //top of stack
minamax 1:d0662d4ffb8c 62 }
minamax 1:d0662d4ffb8c 63
minamax 1:d0662d4ffb8c 64 //dummy read from ECC_TEST (sync DLL)
minamax 1:d0662d4ffb8c 65 ReadReg(TOTALBOARDS-1, ECC_TEST, response_frame2, 1, 0, FRMWRT_ALL_R);
minamax 1:d0662d4ffb8c 66
minamax 1:d0662d4ffb8c 67 // //OPTIONAL: read back all device addresses
minamax 1:d0662d4ffb8c 68 // WriteReg(0, COMM_TO, 0x00, 1, FRMWRT_ALL_NR); //Disable communication timeout because printf takes a long time
minamax 1:d0662d4ffb8c 69 // for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) {
minamax 1:d0662d4ffb8c 70 // memset(response_frame2, 0, sizeof(response_frame2));
minamax 1:d0662d4ffb8c 71 // ReadReg(nCurrentBoard, DEVADD_USR, response_frame2, 1, 0, FRMWRT_SGL_R);
minamax 1:d0662d4ffb8c 72 // printf("Board %d=%02x\n",nCurrentBoard,response_frame2[4]);
minamax 1:d0662d4ffb8c 73 // }
minamax 1:d0662d4ffb8c 74 }
minamax 1:d0662d4ffb8c 75 //**************************
minamax 1:d0662d4ffb8c 76 //END AUTO ADDRESS SEQUENCE
minamax 1:d0662d4ffb8c 77 //**************************
minamax 1:d0662d4ffb8c 78
minamax 1:d0662d4ffb8c 79
minamax 1:d0662d4ffb8c 80 //************************
minamax 1:d0662d4ffb8c 81 //WRITE AND READ FUNCTIONS
minamax 1:d0662d4ffb8c 82 //************************
minamax 1:d0662d4ffb8c 83 int WriteReg(BYTE bID, uint16_t wAddr, uint64_t dwData, BYTE bLen, BYTE bWriteType) {
minamax 1:d0662d4ffb8c 84 // device address, register start address, data bytes, data length, write type (single, broadcast, stack)
minamax 1:d0662d4ffb8c 85 bRes = 0;
minamax 1:d0662d4ffb8c 86 memset(bBuf,0,sizeof(bBuf));
minamax 1:d0662d4ffb8c 87 switch (bLen) {
minamax 1:d0662d4ffb8c 88 case 1:
minamax 1:d0662d4ffb8c 89 bBuf[0] = dwData & 0x00000000000000FF;
minamax 1:d0662d4ffb8c 90 bRes = WriteFrame(bID, wAddr, bBuf, 1, bWriteType);
minamax 1:d0662d4ffb8c 91 break;
minamax 1:d0662d4ffb8c 92 case 2:
minamax 1:d0662d4ffb8c 93 bBuf[0] = (dwData & 0x000000000000FF00) >> 8;
minamax 1:d0662d4ffb8c 94 bBuf[1] = dwData & 0x00000000000000FF;
minamax 1:d0662d4ffb8c 95 bRes = WriteFrame(bID, wAddr, bBuf, 2, bWriteType);
minamax 1:d0662d4ffb8c 96 break;
minamax 1:d0662d4ffb8c 97 case 3:
minamax 1:d0662d4ffb8c 98 bBuf[0] = (dwData & 0x0000000000FF0000) >> 16;
minamax 1:d0662d4ffb8c 99 bBuf[1] = (dwData & 0x000000000000FF00) >> 8;
minamax 1:d0662d4ffb8c 100 bBuf[2] = dwData & 0x00000000000000FF;
minamax 1:d0662d4ffb8c 101 bRes = WriteFrame(bID, wAddr, bBuf, 3, bWriteType);
minamax 1:d0662d4ffb8c 102 break;
minamax 1:d0662d4ffb8c 103 case 4:
minamax 1:d0662d4ffb8c 104 bBuf[0] = (dwData & 0x00000000FF000000) >> 24;
minamax 1:d0662d4ffb8c 105 bBuf[1] = (dwData & 0x0000000000FF0000) >> 16;
minamax 1:d0662d4ffb8c 106 bBuf[2] = (dwData & 0x000000000000FF00) >> 8;
minamax 1:d0662d4ffb8c 107 bBuf[3] = dwData & 0x00000000000000FF;
minamax 1:d0662d4ffb8c 108 bRes = WriteFrame(bID, wAddr, bBuf, 4, bWriteType);
minamax 1:d0662d4ffb8c 109 break;
minamax 1:d0662d4ffb8c 110 case 5:
minamax 1:d0662d4ffb8c 111 bBuf[0] = (dwData & 0x000000FF00000000) >> 32;
minamax 1:d0662d4ffb8c 112 bBuf[1] = (dwData & 0x00000000FF000000) >> 24;
minamax 1:d0662d4ffb8c 113 bBuf[2] = (dwData & 0x0000000000FF0000) >> 16;
minamax 1:d0662d4ffb8c 114 bBuf[3] = (dwData & 0x000000000000FF00) >> 8;
minamax 1:d0662d4ffb8c 115 bBuf[4] = dwData & 0x00000000000000FF;
minamax 1:d0662d4ffb8c 116 bRes = WriteFrame(bID, wAddr, bBuf, 5, bWriteType);
minamax 1:d0662d4ffb8c 117 break;
minamax 1:d0662d4ffb8c 118 case 6:
minamax 1:d0662d4ffb8c 119 bBuf[0] = (dwData & 0x0000FF0000000000) >> 40;
minamax 1:d0662d4ffb8c 120 bBuf[1] = (dwData & 0x000000FF00000000) >> 32;
minamax 1:d0662d4ffb8c 121 bBuf[2] = (dwData & 0x00000000FF000000) >> 24;
minamax 1:d0662d4ffb8c 122 bBuf[3] = (dwData & 0x0000000000FF0000) >> 16;
minamax 1:d0662d4ffb8c 123 bBuf[4] = (dwData & 0x000000000000FF00) >> 8;
minamax 1:d0662d4ffb8c 124 bBuf[5] = dwData & 0x00000000000000FF;
minamax 1:d0662d4ffb8c 125 bRes = WriteFrame(bID, wAddr, bBuf, 6, bWriteType);
minamax 1:d0662d4ffb8c 126 break;
minamax 1:d0662d4ffb8c 127 case 7:
minamax 1:d0662d4ffb8c 128 bBuf[0] = (dwData & 0x00FF000000000000) >> 48;
minamax 1:d0662d4ffb8c 129 bBuf[1] = (dwData & 0x0000FF0000000000) >> 40;
minamax 1:d0662d4ffb8c 130 bBuf[2] = (dwData & 0x000000FF00000000) >> 32;
minamax 1:d0662d4ffb8c 131 bBuf[3] = (dwData & 0x00000000FF000000) >> 24;
minamax 1:d0662d4ffb8c 132 bBuf[4] = (dwData & 0x0000000000FF0000) >> 16;
minamax 1:d0662d4ffb8c 133 bBuf[5] = (dwData & 0x000000000000FF00) >> 8;
minamax 1:d0662d4ffb8c 134 bBuf[6] = dwData & 0x00000000000000FF;
minamax 1:d0662d4ffb8c 135 bRes = WriteFrame(bID, wAddr, bBuf, 7, bWriteType);
minamax 1:d0662d4ffb8c 136 break;
minamax 1:d0662d4ffb8c 137 case 8:
minamax 1:d0662d4ffb8c 138 bBuf[0] = (dwData & 0xFF00000000000000) >> 56;
minamax 1:d0662d4ffb8c 139 bBuf[1] = (dwData & 0x00FF000000000000) >> 48;
minamax 1:d0662d4ffb8c 140 bBuf[2] = (dwData & 0x0000FF0000000000) >> 40;
minamax 1:d0662d4ffb8c 141 bBuf[3] = (dwData & 0x000000FF00000000) >> 32;
minamax 1:d0662d4ffb8c 142 bBuf[4] = (dwData & 0x00000000FF000000) >> 24;
minamax 1:d0662d4ffb8c 143 bBuf[5] = (dwData & 0x0000000000FF0000) >> 16;
minamax 1:d0662d4ffb8c 144 bBuf[6] = (dwData & 0x000000000000FF00) >> 8;
minamax 1:d0662d4ffb8c 145 bBuf[7] = dwData & 0x00000000000000FF;
minamax 1:d0662d4ffb8c 146 bRes = WriteFrame(bID, wAddr, bBuf, 8, bWriteType);
minamax 1:d0662d4ffb8c 147 break;
minamax 1:d0662d4ffb8c 148 default:
minamax 1:d0662d4ffb8c 149 break;
minamax 1:d0662d4ffb8c 150 }
minamax 1:d0662d4ffb8c 151 return bRes;
minamax 1:d0662d4ffb8c 152 }
minamax 1:d0662d4ffb8c 153
minamax 1:d0662d4ffb8c 154 int WriteFrame(BYTE bID, uint16_t wAddr, BYTE * pData, BYTE bLen, BYTE bWriteType) {
minamax 1:d0662d4ffb8c 155 int bPktLen = 0;
minamax 1:d0662d4ffb8c 156 uint8_t * pBuf = pFrame;
minamax 1:d0662d4ffb8c 157 uint16_t wCRC;
minamax 1:d0662d4ffb8c 158 memset(pFrame, 0x7F, sizeof(pFrame));
minamax 1:d0662d4ffb8c 159 *pBuf++ = 0x80 | (bWriteType) | ((bWriteType & 0x10) ? bLen - 0x01 : 0x00); //Only include blen if it is a write; Writes are 0x90, 0xB0, 0xD0
minamax 1:d0662d4ffb8c 160 if (bWriteType == FRMWRT_SGL_R || bWriteType == FRMWRT_SGL_NR)
minamax 1:d0662d4ffb8c 161 {
minamax 1:d0662d4ffb8c 162 *pBuf++ = (bID & 0x00FF);
minamax 1:d0662d4ffb8c 163 }
minamax 1:d0662d4ffb8c 164 *pBuf++ = (wAddr & 0xFF00) >> 8;
minamax 1:d0662d4ffb8c 165 *pBuf++ = wAddr & 0x00FF;
minamax 1:d0662d4ffb8c 166
minamax 1:d0662d4ffb8c 167 while (bLen--)
minamax 1:d0662d4ffb8c 168 *pBuf++ = *pData++;
minamax 1:d0662d4ffb8c 169
minamax 1:d0662d4ffb8c 170 bPktLen = pBuf - pFrame;
minamax 1:d0662d4ffb8c 171
minamax 1:d0662d4ffb8c 172 wCRC = CRC16(pFrame, bPktLen);
minamax 1:d0662d4ffb8c 173 *pBuf++ = wCRC & 0x00FF;
minamax 1:d0662d4ffb8c 174 *pBuf++ = (wCRC & 0xFF00) >> 8;
minamax 1:d0662d4ffb8c 175 bPktLen += 2;
minamax 1:d0662d4ffb8c 176 //THIS SEEMS to occasionally drop bytes from the frame. Sometimes is not sending the last frame of the CRC.
minamax 1:d0662d4ffb8c 177 //(Seems to be caused by stack overflow, so take precautions to reduce stack usage in function calls)
minamax 1:d0662d4ffb8c 178 //sciSend(scilinREG, bPktLen, pFrame);
minamax 1:d0662d4ffb8c 179
minamax 1:d0662d4ffb8c 180 sendUART(bPktLen, pFrame);
minamax 1:d0662d4ffb8c 181
minamax 1:d0662d4ffb8c 182 return bPktLen;
minamax 1:d0662d4ffb8c 183 }
minamax 1:d0662d4ffb8c 184
minamax 1:d0662d4ffb8c 185 int ReadReg(BYTE bID, uint16_t wAddr, BYTE * pData, BYTE bLen, uint32_t dwTimeOut,
minamax 1:d0662d4ffb8c 186 BYTE bWriteType) {
minamax 1:d0662d4ffb8c 187 bRes = 0;
minamax 1:d0662d4ffb8c 188 //count = 100000;
minamax 1:d0662d4ffb8c 189 if (bWriteType == FRMWRT_SGL_R) {
minamax 1:d0662d4ffb8c 190 ReadFrameReq(bID, wAddr, bLen, bWriteType);
minamax 1:d0662d4ffb8c 191 //memset(pData, 0, sizeof(pData));
minamax 1:d0662d4ffb8c 192 //sciEnableNotification(scilinREG, SCI_RX_INT);
minamax 1:d0662d4ffb8c 193 //sciReceive(scilinREG, bLen + 6, pData);
minamax 1:d0662d4ffb8c 194 //while(UART_RX_RDY == 0U && count>0) count--; /*wait*/
minamax 1:d0662d4ffb8c 195 //if(count == 0) printf("COUNT REACHED 0\n");
minamax 1:d0662d4ffb8c 196 //UART_RX_RDY = 0;
minamax 1:d0662d4ffb8c 197 //bRes = bLen + 6;
minamax 1:d0662d4ffb8c 198 } /*else if (bWriteType == FRMWRT_STK_R) {
minamax 1:d0662d4ffb8c 199 bRes = ReadFrameReq(bID, wAddr, bLen, bWriteType);
minamax 1:d0662d4ffb8c 200 memset(pData, 0, sizeof(pData));
minamax 1:d0662d4ffb8c 201 sciEnableNotification(scilinREG, SCI_RX_INT);
minamax 1:d0662d4ffb8c 202 sciReceive(scilinREG, (bLen + 6) * (TOTALBOARDS - 1), pData);
minamax 1:d0662d4ffb8c 203 while(UART_RX_RDY == 0U && count>0) count--; //wait
minamax 1:d0662d4ffb8c 204 UART_RX_RDY = 0;
minamax 1:d0662d4ffb8c 205 bRes = (bLen + 6) * (TOTALBOARDS - 1);
minamax 1:d0662d4ffb8c 206 } else if (bWriteType == FRMWRT_ALL_R) {
minamax 1:d0662d4ffb8c 207 bRes = ReadFrameReq(bID, wAddr, bLen, bWriteType);
minamax 1:d0662d4ffb8c 208 memset(pData, 0, sizeof(pData));
minamax 1:d0662d4ffb8c 209 sciEnableNotification(scilinREG, SCI_RX_INT);
minamax 1:d0662d4ffb8c 210 sciReceive(scilinREG, (bLen + 6) * TOTALBOARDS, pData);
minamax 1:d0662d4ffb8c 211 while(UART_RX_RDY == 0U && count>0) count--; //wait
minamax 1:d0662d4ffb8c 212 UART_RX_RDY = 0;
minamax 1:d0662d4ffb8c 213 bRes = (bLen + 6) * TOTALBOARDS;
minamax 1:d0662d4ffb8c 214 } else {
minamax 1:d0662d4ffb8c 215 bRes = 0;
minamax 1:d0662d4ffb8c 216 }*/
minamax 1:d0662d4ffb8c 217 return bRes;
minamax 1:d0662d4ffb8c 218 }
minamax 1:d0662d4ffb8c 219
minamax 1:d0662d4ffb8c 220 int ReadFrameReq(BYTE bID, uint16_t wAddr, BYTE bByteToReturn, BYTE bWriteType) {
minamax 1:d0662d4ffb8c 221 bReturn = bByteToReturn - 1;
minamax 1:d0662d4ffb8c 222
minamax 1:d0662d4ffb8c 223 if (bReturn > 127)
minamax 1:d0662d4ffb8c 224 return 0;
minamax 1:d0662d4ffb8c 225
minamax 1:d0662d4ffb8c 226 return WriteFrame(bID, wAddr, &bReturn, 1, bWriteType);
minamax 1:d0662d4ffb8c 227 }
minamax 1:d0662d4ffb8c 228
minamax 1:d0662d4ffb8c 229
minamax 1:d0662d4ffb8c 230
minamax 1:d0662d4ffb8c 231 void init(){
minamax 1:d0662d4ffb8c 232
minamax 1:d0662d4ffb8c 233 /* mask all low level faults... user should unmask necessary faults */
minamax 1:d0662d4ffb8c 234 WriteReg(0, GPIO_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask GPIO faults
minamax 1:d0662d4ffb8c 235 //WriteReg(0, UV_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask UV faults
minamax 1:d0662d4ffb8c 236 //WriteReg(0, OV_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask OV faults
minamax 1:d0662d4ffb8c 237 //WriteReg(0, UT_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask UT faults
minamax 1:d0662d4ffb8c 238 //WriteReg(0, OT_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask OT faults
minamax 1:d0662d4ffb8c 239 WriteReg(0, TONE_FLT_MSK, 0x07, 1, FRMWRT_ALL_NR); //mask all tone faults
minamax 1:d0662d4ffb8c 240 WriteReg(0, COMM_UART_FLT_MSK, 0x07, 1, FRMWRT_ALL_NR); //mask UART faults
minamax 1:d0662d4ffb8c 241 WriteReg(0, COMM_UART_RC_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask UART fault contd
minamax 1:d0662d4ffb8c 242 WriteReg(0, COMM_UART_RR_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 243 WriteReg(0, COMM_UART_TR_FLT_MSK, 0x03, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 244 WriteReg(0, COMM_COMH_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 245 WriteReg(0, COMM_COMH_RC_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 246 WriteReg(0, COMM_COMH_RR_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 247 WriteReg(0, COMM_COMH_TR_FLT_MSK, 0x03, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 248 WriteReg(0, COMM_COML_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 249 WriteReg(0, COMM_COML_RC_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 250 WriteReg(0, COMM_COML_RR_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 251 WriteReg(0, COMM_COML_TR_FLT_MSK, 0x03, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 252 WriteReg(0, OTP_FLT_MSK, 0x07, 1, FRMWRT_ALL_NR); // mask otp faults
minamax 1:d0662d4ffb8c 253 WriteReg(0, RAIL_FLT_MSK, 0xFF, 1, FRMWRT_ALL_NR); //mask power rail faults
minamax 1:d0662d4ffb8c 254 WriteReg(0, SYSFLT1_FLT_MSK, 0x7F, 1, FRMWRT_ALL_NR); //sys fault mask 1
minamax 1:d0662d4ffb8c 255 WriteReg(0, SYSFLT2_FLT_MSK, 0xFF, 1, FRMWRT_ALL_NR); //sys fault mask 2
minamax 1:d0662d4ffb8c 256 WriteReg(0, SYSFLT3_FLT_MSK, 0x7F, 1, FRMWRT_ALL_NR); //sys fault mask 3
minamax 1:d0662d4ffb8c 257 WriteReg(0, OVUV_BIST_FLT_MSK, 0x03, 1, FRMWRT_ALL_NR); //mask ov/uv bist faults
minamax 1:d0662d4ffb8c 258 WriteReg(0, OTUT_BIST_FLT_MSK, 0xFF, 1, FRMWRT_ALL_NR);
minamax 1:d0662d4ffb8c 259
minamax 1:d0662d4ffb8c 260 WriteReg(0, CELL_ADC_CTRL, 0x3F, 1, FRMWRT_ALL_NR); //enables ADC for all 6 cell channels
minamax 1:d0662d4ffb8c 261 WriteReg(0, OVUV_CTRL, 0x3F, 1, FRMWRT_ALL_NR); //enable all cell ov/uv
minamax 1:d0662d4ffb8c 262 WriteReg(0, UV_THRESH, 0x53, 1, FRMWRT_ALL_NR); //sets cell UV to 2.8V
minamax 1:d0662d4ffb8c 263 WriteReg(0, OV_THRESH, 0x5B, 1, FRMWRT_ALL_NR); //sets cell OV to 4.3V
minamax 1:d0662d4ffb8c 264
minamax 1:d0662d4ffb8c 265 WriteReg(0, AUX_ADC_CONF, 0x08, 1, FRMWRT_ALL_NR); //1MHz AUX sample rate, 128 decimation ratio
minamax 1:d0662d4ffb8c 266 WriteReg(0, CELL_ADC_CONF1, 0x67, 1, FRMWRT_ALL_NR); //256 decimation ratio, 1MHz sample. 1.2 Hz LPF
minamax 1:d0662d4ffb8c 267 WriteReg(0, CELL_ADC_CONF2, 0x00, 1, FRMWRT_ALL_NR); //single conversion
minamax 1:d0662d4ffb8c 268 ///enable continuous sampling. Otherwise, single conversions with CONTROL2[CELL_ADC_GO]
minamax 1:d0662d4ffb8c 269 //WriteReg(0,CELL_ADC_CONF2, 0x0A,1,FRMWRT_ALL_NR);//continuous sampling with 5ms interval
minamax 1:d0662d4ffb8c 270 //WriteReg(0, CONTROL2, 0x10, 1, FRMWRT_ALL_NR);// enable TSREF to give enough settling time
minamax 1:d0662d4ffb8c 271 //wait_ms(2); // provides settling time for TSREF
minamax 1:d0662d4ffb8c 272
minamax 1:d0662d4ffb8c 273
minamax 1:d0662d4ffb8c 274
minamax 1:d0662d4ffb8c 275 }
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minamax 1:d0662d4ffb8c 282
minamax 1:d0662d4ffb8c 283 // CRC16 TABLE
minamax 1:d0662d4ffb8c 284 // ITU_T polynomial: x^16 + x^15 + x^2 + 1
minamax 1:d0662d4ffb8c 285 const uint16_t crc16_table[256] = { 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301,
minamax 1:d0662d4ffb8c 286 0x03C0, 0x0280, 0xC241, 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1,
minamax 1:d0662d4ffb8c 287 0xC481, 0x0440, 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81,
minamax 1:d0662d4ffb8c 288 0x0E40, 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
minamax 1:d0662d4ffb8c 289 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, 0x1E00,
minamax 1:d0662d4ffb8c 290 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, 0x1400, 0xD4C1,
minamax 1:d0662d4ffb8c 291 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, 0xD201, 0x12C0, 0x1380,
minamax 1:d0662d4ffb8c 292 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, 0xF001, 0x30C0, 0x3180, 0xF141,
minamax 1:d0662d4ffb8c 293 0x3300, 0xF3C1, 0xF281, 0x3240, 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501,
minamax 1:d0662d4ffb8c 294 0x35C0, 0x3480, 0xF441, 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0,
minamax 1:d0662d4ffb8c 295 0x3E80, 0xFE41, 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881,
minamax 1:d0662d4ffb8c 296 0x3840, 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
minamax 1:d0662d4ffb8c 297 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, 0xE401,
minamax 1:d0662d4ffb8c 298 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, 0x2200, 0xE2C1,
minamax 1:d0662d4ffb8c 299 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, 0xA001, 0x60C0, 0x6180,
minamax 1:d0662d4ffb8c 300 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, 0x6600, 0xA6C1, 0xA781, 0x6740,
minamax 1:d0662d4ffb8c 301 0xA501, 0x65C0, 0x6480, 0xA441, 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01,
minamax 1:d0662d4ffb8c 302 0x6FC0, 0x6E80, 0xAE41, 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1,
minamax 1:d0662d4ffb8c 303 0xA881, 0x6840, 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80,
minamax 1:d0662d4ffb8c 304 0xBA41, 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
minamax 1:d0662d4ffb8c 305 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, 0x7200,
minamax 1:d0662d4ffb8c 306 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, 0x5000, 0x90C1,
minamax 1:d0662d4ffb8c 307 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, 0x9601, 0x56C0, 0x5780,
minamax 1:d0662d4ffb8c 308 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, 0x9C01, 0x5CC0, 0x5D80, 0x9D41,
minamax 1:d0662d4ffb8c 309 0x5F00, 0x9FC1, 0x9E81, 0x5E40, 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901,
minamax 1:d0662d4ffb8c 310 0x59C0, 0x5880, 0x9841, 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1,
minamax 1:d0662d4ffb8c 311 0x8A81, 0x4A40, 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80,
minamax 1:d0662d4ffb8c 312 0x8C41, 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
minamax 1:d0662d4ffb8c 313 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 };
minamax 1:d0662d4ffb8c 314
minamax 1:d0662d4ffb8c 315 uint16_t CRC16(BYTE *pBuf, int nLen) {
minamax 1:d0662d4ffb8c 316 uint16_t wCRC = 0xFFFF;
minamax 1:d0662d4ffb8c 317 int i;
minamax 1:d0662d4ffb8c 318
minamax 1:d0662d4ffb8c 319 for (i = 0; i < nLen; i++) {
minamax 1:d0662d4ffb8c 320 wCRC ^= (*pBuf++) & 0x00FF;
minamax 1:d0662d4ffb8c 321 wCRC = crc16_table[wCRC & 0x00FF] ^ (wCRC >> 8);
minamax 1:d0662d4ffb8c 322 }
minamax 1:d0662d4ffb8c 323
minamax 1:d0662d4ffb8c 324 return wCRC;
minamax 1:d0662d4ffb8c 325 }
minamax 1:d0662d4ffb8c 326
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