Dragica Stoiljkovic / Mbed 2 deprecated BMS_LV_VERZIJA_TESTIRANJE

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Dependencies:   mbed

main.cpp@5:38b2b8790b40, 2021-04-11 (annotated)

Committer:
dragica
Date:
Sun Apr 11 09:08:16 2021 +0000
Revision:
5:38b2b8790b40
Parent:
4:28919318b141 
SW napisan za testiranje nedelja 11 april 2021.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
minamax 1:d0662d4ffb8c 1 #include "mbed.h"
minamax 1:d0662d4ffb8c 2 #include "bq79606.h"
dragica 5:38b2b8790b40 3 #include "math.h"
dragica 5:38b2b8790b40 4 #include "handlers.h"
dragica 5:38b2b8790b40 5 #include "ntc.h"
minamax 1:d0662d4ffb8c 6 // - - - PIN CONFIGURATION - - -
minamax 1:d0662d4ffb8c 7
minamax 1:d0662d4ffb8c 8 DigitalIn bmsFault(PB_4);
minamax 1:d0662d4ffb8c 9 DigitalOut bmsWakeUp(PB_5);
minamax 1:d0662d4ffb8c 10
minamax 1:d0662d4ffb8c 11 // - - - UART CONFIGURATION - - -
minamax 1:d0662d4ffb8c 12
minamax 2:03a6da61d834 13 Serial bms(PA_0, PA_1, 250000); //UART ka BMS Slaveu
dragica 5:38b2b8790b40 14 Serial pc1(USBTX, USBRX, 9600);//PC_10, PC_11,9600); //UART ka PCu Serijskom monitoru
minamax 1:d0662d4ffb8c 15
dragica 5:38b2b8790b40 16 //- - - CAN CONFIGURATION - - -
minamax 2:03a6da61d834 17 CAN can1(PB_8, PB_9, 500000);
dragica 5:38b2b8790b40 18 CANMessage message1;
minamax 2:03a6da61d834 19
minamax 1:d0662d4ffb8c 20 BYTE recBuff[1024];
minamax 2:03a6da61d834 21 volatile int recLen=0;
minamax 2:03a6da61d834 22 volatile int expected=0;
minamax 1:d0662d4ffb8c 23 volatile bool full = false;
minamax 2:03a6da61d834 24 volatile int rdLen=0;
minamax 1:d0662d4ffb8c 25 int counter = 0;
dragica 5:38b2b8790b40 26 volatile int devStat = 0;
dragica 5:38b2b8790b40 27 volatile int cbRun = 1;
dragica 5:38b2b8790b40 28 volatile int cbDone = 0;
dragica 5:38b2b8790b40 29
dragica 5:38b2b8790b40 30 volatile int faultSUM = 0;
dragica 5:38b2b8790b40 31 volatile int DEVStat = 0;
dragica 5:38b2b8790b40 32
dragica 5:38b2b8790b40 33 volatile double extern Vin;
dragica 5:38b2b8790b40 34 volatile double extern Rref;
minamax 1:d0662d4ffb8c 35
minamax 1:d0662d4ffb8c 36 uint8_t pFrame1[(MAXBYTES+6)*TOTALBOARDS];
minamax 1:d0662d4ffb8c 37
minamax 1:d0662d4ffb8c 38 void callback() {
minamax 1:d0662d4ffb8c 39 // Note: you need to actually read from the serial to clear the RX interrupt
minamax 1:d0662d4ffb8c 40 recBuff[recLen++] = bms.getc();
minamax 2:03a6da61d834 41 if(expected==0) expected = recBuff[0]+7; //prvi bajt je (broj data - 1), +1 device id, +2 reg address, +2 CRC
minamax 1:d0662d4ffb8c 42 if(expected == recLen){
minamax 1:d0662d4ffb8c 43 rdLen = expected;
minamax 1:d0662d4ffb8c 44 expected = 0;
minamax 1:d0662d4ffb8c 45 recLen = 0;
dragica 5:38b2b8790b40 46 full = true;
minamax 1:d0662d4ffb8c 47 }
minamax 1:d0662d4ffb8c 48 }
minamax 1:d0662d4ffb8c 49
dragica 5:38b2b8790b40 50 int waitRegRead()
dragica 5:38b2b8790b40 51 {
minamax 1:d0662d4ffb8c 52 while(!full);
dragica 5:38b2b8790b40 53 wait_us(500);
minamax 1:d0662d4ffb8c 54 full=false;
dragica 5:38b2b8790b40 55 return recBuff[4];
dragica 5:38b2b8790b40 56 }
dragica 5:38b2b8790b40 57
dragica 5:38b2b8790b40 58
dragica 5:38b2b8790b40 59
dragica 5:38b2b8790b40 60
dragica 5:38b2b8790b40 61 void waitFrame(){
dragica 5:38b2b8790b40 62 while(!full);
dragica 5:38b2b8790b40 63 wait_us(500);
dragica 5:38b2b8790b40 64 full=false;
minamax 1:d0662d4ffb8c 65
minamax 1:d0662d4ffb8c 66 pc1.printf("\n\n- - - VOLTAGE - - -\n");
dragica 5:38b2b8790b40 67 message1.id = voltID;
minamax 2:03a6da61d834 68 int j = 0;
minamax 1:d0662d4ffb8c 69 for(int i = 4; i < recBuff[0] + 4; i += 2){
minamax 1:d0662d4ffb8c 70 int voltage = recBuff[i+1]; //LSB
minamax 1:d0662d4ffb8c 71 voltage |= (recBuff[i]) << 8; //MSB
minamax 2:03a6da61d834 72 double vol = voltage*0.0001907349;
minamax 2:03a6da61d834 73 pc1.printf("CELL[%d] = %6.2f V\n", i/2-1, vol);
dragica 5:38b2b8790b40 74 //sendCAN(voltID, vol);
minamax 2:03a6da61d834 75 message1.data[j++] = recBuff[i];
minamax 2:03a6da61d834 76
minamax 1:d0662d4ffb8c 77 }
minamax 2:03a6da61d834 78 can1.write(message1);
minamax 1:d0662d4ffb8c 79
minamax 1:d0662d4ffb8c 80 pc1.printf("\n");
minamax 1:d0662d4ffb8c 81 }
minamax 3:4dc457ed63d5 82
minamax 3:4dc457ed63d5 83
dragica 5:38b2b8790b40 84 void waitFrameTemp(){
minamax 3:4dc457ed63d5 85 while(!full);
minamax 3:4dc457ed63d5 86 full=false;
dragica 4:28919318b141 87 pc1.printf("****** TEMPERATURA *****");
minamax 3:4dc457ed63d5 88 pc1.printf("\n%d\n", rdLen);
minamax 3:4dc457ed63d5 89 for(int i = 0;i<rdLen;i++){
minamax 3:4dc457ed63d5 90 pc1.printf("%X ",recBuff[i]);
minamax 3:4dc457ed63d5 91 }
dragica 5:38b2b8790b40 92 int voltage = recBuff[5]; //LSB
dragica 5:38b2b8790b40 93 voltage |= (recBuff[4]) << 8; //MSB
dragica 5:38b2b8790b40 94 double Vout = voltage*0.0001907349;
dragica 5:38b2b8790b40 95 int temp = naponskiRazdelnik(Vout);
dragica 5:38b2b8790b40 96 sendCANbyte(tempID, temp);
dragica 5:38b2b8790b40 97 }
dragica 5:38b2b8790b40 98
dragica 5:38b2b8790b40 99 void StartBalancingAndWaitToFinish()
dragica 5:38b2b8790b40 100 {
dragica 5:38b2b8790b40 101 cbRun = 1;
dragica 5:38b2b8790b40 102 cbDone = 0;
dragica 5:38b2b8790b40 103 WriteReg(0, CB_CONFIG, 0xFA, 1, FRMWRT_ALL_NR); // Odds then Evens, continue regardless of fault condition, 30sec, seconds
dragica 5:38b2b8790b40 104
dragica 5:38b2b8790b40 105 WriteReg(0, CB_DONE_THRESHOLD, 0x5F, 1, FRMWRT_ALL_NR); // Thresh hold set to value 3.6V, CBDONE comparators enabled
dragica 5:38b2b8790b40 106 //Enabling the CBDONE voltage threshold overrides the OVUV function and pauses it.
dragica 5:38b2b8790b40 107
dragica 5:38b2b8790b40 108 WriteReg(0, CB_CELL1_CTRL, 0xBC, 1, FRMWRT_ALL_NR);//cell 1- 1 minute balance timer
dragica 5:38b2b8790b40 109 WriteReg(0, CB_CELL2_CTRL, 0xBC, 1, FRMWRT_ALL_NR);//cell 2- 1 minute balance timer
dragica 5:38b2b8790b40 110 WriteReg(0, CB_CELL3_CTRL, 0xBC, 1, FRMWRT_ALL_NR);//cell 3- 1 minute balance timer
dragica 5:38b2b8790b40 111
dragica 5:38b2b8790b40 112 WriteReg(0, CONTROL2, 0x30, 1, FRMWRT_ALL_NR);//BAL_GO set to 1, and TSREF enabled
dragica 5:38b2b8790b40 113 wait_us(100);
dragica 5:38b2b8790b40 114 pc1.printf("Setupovano balansiranje\n");
dragica 5:38b2b8790b40 115 while (cbRun)
dragica 5:38b2b8790b40 116 {
dragica 5:38b2b8790b40 117 ReadReg(0, DEV_STAT, pFrame1, 1 , 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 118 wait(1);
dragica 5:38b2b8790b40 119 devStat = recBuff[4];
dragica 5:38b2b8790b40 120 cbRun = (devStat & 0x10) >> 4;
dragica 5:38b2b8790b40 121 wait_us(500);
dragica 5:38b2b8790b40 122 if (!cbRun)
dragica 5:38b2b8790b40 123 {
dragica 5:38b2b8790b40 124 pc1.printf("DEV STAT = %d\n", devStat);
dragica 5:38b2b8790b40 125 pc1.printf("CBRUN = %d\n", cbRun);
dragica 5:38b2b8790b40 126 //wait(10);
dragica 5:38b2b8790b40 127 }
dragica 5:38b2b8790b40 128 }
dragica 5:38b2b8790b40 129
dragica 5:38b2b8790b40 130 while(!cbDone)
dragica 5:38b2b8790b40 131 {
dragica 5:38b2b8790b40 132 ReadReg(0, DEV_STAT, pFrame1, 1 , 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 133 wait(1);
dragica 5:38b2b8790b40 134 devStat = recBuff[4];
dragica 5:38b2b8790b40 135 cbDone = (devStat & 0x40) >> 6;
dragica 5:38b2b8790b40 136 wait_us(500);
dragica 5:38b2b8790b40 137 if (cbDone)
dragica 5:38b2b8790b40 138 {
dragica 5:38b2b8790b40 139 pc1.printf("DEV STAT = %d\n", devStat);
dragica 5:38b2b8790b40 140 pc1.printf("CBDONE = %d\n", cbDone);
dragica 5:38b2b8790b40 141 //wait(10);
dragica 5:38b2b8790b40 142 }
dragica 5:38b2b8790b40 143 }
dragica 5:38b2b8790b40 144 // Cleanup
dragica 5:38b2b8790b40 145 WriteReg(0, CONTROL2, 0x00, 1, FRMWRT_ALL_NR);//Reset
dragica 5:38b2b8790b40 146 WriteReg(0, CB_DONE_THRESHOLD, 0x20, 1, FRMWRT_ALL_NR);
minamax 3:4dc457ed63d5 147 }
dragica 5:38b2b8790b40 148
dragica 5:38b2b8790b40 149 void cellBalanceEnable()
dragica 5:38b2b8790b40 150 {
dragica 5:38b2b8790b40 151 cbRun = 1;
dragica 5:38b2b8790b40 152 cbDone = 0;
dragica 5:38b2b8790b40 153 WriteReg(0, CB_CONFIG, 0xFA, 1, FRMWRT_ALL_NR); // Odds then Evens, continue regardless of fault condition, 30sec, seconds
dragica 5:38b2b8790b40 154
dragica 5:38b2b8790b40 155 WriteReg(0, CB_DONE_THRESHOLD, 0x5F, 1, FRMWRT_ALL_NR); // Thresh hold set to value 3.6V, CBDONE comparators enabled
dragica 5:38b2b8790b40 156 //Enabling the CBDONE voltage threshold overrides the OVUV function and pauses it.
dragica 5:38b2b8790b40 157
dragica 5:38b2b8790b40 158 WriteReg(0, CB_CELL1_CTRL, 0xBC, 1, FRMWRT_ALL_NR);//cell 1- 1 minute balance timer
dragica 5:38b2b8790b40 159 WriteReg(0, CB_CELL2_CTRL, 0xBC, 1, FRMWRT_ALL_NR);//cell 2- 1 minute balance timer
dragica 5:38b2b8790b40 160 WriteReg(0, CB_CELL3_CTRL, 0xBC, 1, FRMWRT_ALL_NR);//cell 3- 1 minute balance timer
dragica 5:38b2b8790b40 161
dragica 5:38b2b8790b40 162 WriteReg(0, CONTROL2, 0x30, 1, FRMWRT_ALL_NR);//BAL_GO set to 1, and TSREF enabled
dragica 5:38b2b8790b40 163 wait_us(100);
dragica 5:38b2b8790b40 164 pc1.printf("Setupovano balansiranje\n");
dragica 5:38b2b8790b40 165 }
dragica 5:38b2b8790b40 166
dragica 5:38b2b8790b40 167 void waitBalancingToFinish()
dragica 5:38b2b8790b40 168 {
dragica 5:38b2b8790b40 169 while (cbRun)
dragica 5:38b2b8790b40 170 {
dragica 5:38b2b8790b40 171 ReadReg(0, DEV_STAT, pFrame1, 1 , 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 172 wait(1);
dragica 5:38b2b8790b40 173 devStat = recBuff[4];
dragica 5:38b2b8790b40 174 cbRun = (devStat & 0x10) >> 4;
dragica 5:38b2b8790b40 175 wait_us(500);
dragica 5:38b2b8790b40 176 if (!cbRun)
dragica 5:38b2b8790b40 177 {
dragica 5:38b2b8790b40 178 pc1.printf("DEV STAT = %d\n", devStat);
dragica 5:38b2b8790b40 179 pc1.printf("CBRUN = %d\n", cbRun);
dragica 5:38b2b8790b40 180 }
minamax 1:d0662d4ffb8c 181 }
dragica 5:38b2b8790b40 182
dragica 5:38b2b8790b40 183 while(!cbDone)
dragica 5:38b2b8790b40 184 {
dragica 5:38b2b8790b40 185 ReadReg(0, DEV_STAT, pFrame1, 1 , 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 186 wait(1);
dragica 5:38b2b8790b40 187 devStat = recBuff[4];
dragica 5:38b2b8790b40 188 cbDone = (devStat & 0x40) >> 6;
dragica 5:38b2b8790b40 189 wait_us(500);
dragica 5:38b2b8790b40 190 if (cbDone)
dragica 5:38b2b8790b40 191 {
dragica 5:38b2b8790b40 192 pc1.printf("DEV STAT = %d\n", devStat);
dragica 5:38b2b8790b40 193 pc1.printf("CBDONE = %d\n", cbDone);
dragica 5:38b2b8790b40 194 //wait(10);
dragica 5:38b2b8790b40 195 }
dragica 5:38b2b8790b40 196 }
dragica 5:38b2b8790b40 197 }
dragica 5:38b2b8790b40 198
dragica 5:38b2b8790b40 199 void cellBalanceDisable()
dragica 5:38b2b8790b40 200 {
dragica 5:38b2b8790b40 201 WriteReg(0, CONTROL2, 0x00, 1, FRMWRT_ALL_NR);//Reset
dragica 5:38b2b8790b40 202 WriteReg(0, CB_DONE_THRESHOLD, 0x20, 1, FRMWRT_ALL_NR);
dragica 5:38b2b8790b40 203 }
dragica 5:38b2b8790b40 204
dragica 5:38b2b8790b40 205 void isCellBalancingDone()
dragica 5:38b2b8790b40 206 {
dragica 5:38b2b8790b40 207 ReadReg(0, DEV_STAT, pFrame1, 1 , 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 208 wait(1);
dragica 5:38b2b8790b40 209 devStat = recBuff[4];
dragica 5:38b2b8790b40 210 cbDone = (devStat & 0x40) >> 6;
dragica 5:38b2b8790b40 211 cbRun = (devStat & 0x10) >> 4;
dragica 5:38b2b8790b40 212 wait_us(500);
dragica 5:38b2b8790b40 213 pc1.printf("cbDone= %d cbRun= %d\n", cbDone, cbRun);
dragica 5:38b2b8790b40 214 wait(104);
dragica 5:38b2b8790b40 215 ReadReg(0, DEV_STAT, pFrame1, 1 , 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 216 wait(1);
dragica 5:38b2b8790b40 217 devStat = recBuff[4];
dragica 5:38b2b8790b40 218 cbDone = (devStat & 0x40) >> 6;
dragica 5:38b2b8790b40 219 cbRun = (devStat & 0x10) >> 4;
minamax 1:d0662d4ffb8c 220 }
minamax 1:d0662d4ffb8c 221
dragica 5:38b2b8790b40 222 void faultRead()
dragica 5:38b2b8790b40 223 {
dragica 5:38b2b8790b40 224 pc1.printf("\n FAULT REGISTER STATUS START \n");
dragica 5:38b2b8790b40 225
dragica 5:38b2b8790b40 226 ReadReg(0, GPIO_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 227 gpioFault = waitRegRead();
dragica 5:38b2b8790b40 228 GPIOHandler();
dragica 5:38b2b8790b40 229
dragica 5:38b2b8790b40 230 ReadReg(0, UV_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 231 uvFault = waitRegRead();
dragica 5:38b2b8790b40 232 UVHandler();
dragica 5:38b2b8790b40 233
dragica 5:38b2b8790b40 234 ReadReg(0, OV_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 235 ovFault = waitRegRead();
dragica 5:38b2b8790b40 236 OVHandler();
dragica 5:38b2b8790b40 237
dragica 5:38b2b8790b40 238 ReadReg(0, UT_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 239 utFault = waitRegRead();
dragica 5:38b2b8790b40 240 UTHandler();
dragica 5:38b2b8790b40 241
dragica 5:38b2b8790b40 242 ReadReg(0, OT_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 243 otFault = waitRegRead();
dragica 5:38b2b8790b40 244 OTHandler();
dragica 5:38b2b8790b40 245
dragica 5:38b2b8790b40 246 ReadReg(0, TONE_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 247 toneFault = waitRegRead();
dragica 5:38b2b8790b40 248 ToneHandler();
dragica 5:38b2b8790b40 249
dragica 5:38b2b8790b40 250 ReadReg(0, COMM_UART_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 251 uartFault = waitRegRead();
dragica 5:38b2b8790b40 252 UARTHandler();
dragica 5:38b2b8790b40 253
dragica 5:38b2b8790b40 254 ReadReg(0, COMM_UART_RC_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 255 uartRCFault = waitRegRead();
dragica 5:38b2b8790b40 256 UARTRCHandler();
dragica 5:38b2b8790b40 257
dragica 5:38b2b8790b40 258 ReadReg(0, COMM_UART_RR_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 259 uartRRFault = waitRegRead();
dragica 5:38b2b8790b40 260 UARTRRHandler();
dragica 5:38b2b8790b40 261
dragica 5:38b2b8790b40 262 ReadReg(0, COMM_UART_TR_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 263 uartTRFault = waitRegRead();
dragica 5:38b2b8790b40 264 UARTTRHandler();
dragica 5:38b2b8790b40 265
dragica 5:38b2b8790b40 266 ReadReg(0, COMM_COMH_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 267 COMHFault = waitRegRead();
dragica 5:38b2b8790b40 268 COMHHandler();
dragica 5:38b2b8790b40 269
dragica 5:38b2b8790b40 270 ReadReg(0, COMM_COMH_RC_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 271 COMHRCFault = waitRegRead();
dragica 5:38b2b8790b40 272 COMHRCHandler();
dragica 5:38b2b8790b40 273
dragica 5:38b2b8790b40 274 ReadReg(0, COMM_COMH_RR_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 275 COMHRRFault = waitRegRead();
dragica 5:38b2b8790b40 276 COMHRRHandler();
dragica 5:38b2b8790b40 277
dragica 5:38b2b8790b40 278 ReadReg(0, COMM_COMH_TR_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 279 COMHTRFault = waitRegRead();
dragica 5:38b2b8790b40 280 COMHTRHandler();
dragica 5:38b2b8790b40 281
dragica 5:38b2b8790b40 282 ReadReg(0, COMM_COML_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 283 COMLFault = waitRegRead();
dragica 5:38b2b8790b40 284 COMLHandler();
dragica 5:38b2b8790b40 285
dragica 5:38b2b8790b40 286 ReadReg(0, COMM_COML_RC_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 287 COMLRCFault = waitRegRead();
dragica 5:38b2b8790b40 288 COMLRCHandler();
dragica 5:38b2b8790b40 289
dragica 5:38b2b8790b40 290 ReadReg(0, COMM_COML_RR_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 291 COMLRRFault = waitRegRead();
dragica 5:38b2b8790b40 292 COMLRRHandler();
dragica 5:38b2b8790b40 293
dragica 5:38b2b8790b40 294 ReadReg(0, COMM_COML_TR_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 295 COMLTRFault = waitRegRead();
dragica 5:38b2b8790b40 296 COMLHandler();
dragica 5:38b2b8790b40 297
dragica 5:38b2b8790b40 298 ReadReg(0, OTP_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 299 otpFault = waitRegRead();
dragica 5:38b2b8790b40 300 OTPHandler();
dragica 5:38b2b8790b40 301
dragica 5:38b2b8790b40 302 ReadReg(0, RAIL_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 303 railFault = waitRegRead();
dragica 5:38b2b8790b40 304 RAILHandler();
dragica 5:38b2b8790b40 305
dragica 5:38b2b8790b40 306 ReadReg(0, OVUV_BIST_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 307 ovuvBistFault = waitRegRead();
dragica 5:38b2b8790b40 308 OVUVBISTHandler();
dragica 5:38b2b8790b40 309
dragica 5:38b2b8790b40 310 ReadReg(0, OTUT_BIST_FAULT, pFrame1, 1, 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 311 otutBistFault = waitRegRead();
dragica 5:38b2b8790b40 312 OTUTBISTHandler();
dragica 5:38b2b8790b40 313
dragica 5:38b2b8790b40 314 pc1.printf("FAULT REGISTER STATUS END \n\n");
dragica 5:38b2b8790b40 315 }
dragica 5:38b2b8790b40 316
dragica 5:38b2b8790b40 317 void checkDeviceStatus()
dragica 5:38b2b8790b40 318 {
dragica 5:38b2b8790b40 319 pc1.printf("\n DEVICE STATUS START \n");
dragica 5:38b2b8790b40 320
dragica 5:38b2b8790b40 321 ReadReg(0, FAULT_SUM, pFrame1, 1, 0, FRMWRT_SGL_R);
dragica 5:38b2b8790b40 322 faultSUM = waitRegRead();
dragica 5:38b2b8790b40 323 pc1.printf("Fault sum = %X\n", faultSUM);
dragica 5:38b2b8790b40 324
dragica 5:38b2b8790b40 325 if(faultSUM != 0)
dragica 5:38b2b8790b40 326 {
dragica 5:38b2b8790b40 327 faultRead();
dragica 5:38b2b8790b40 328 }
dragica 5:38b2b8790b40 329
dragica 5:38b2b8790b40 330 ReadReg(0, DEV_STAT, pFrame1, 1, 0, FRMWRT_SGL_R);
dragica 5:38b2b8790b40 331 DEVStat = waitRegRead();
dragica 5:38b2b8790b40 332 pc1.printf("DEV STAT = %X\n", DEVStat);
dragica 5:38b2b8790b40 333
dragica 5:38b2b8790b40 334 pc1.printf("DEVICE STATUS END\n");
dragica 5:38b2b8790b40 335 }
dragica 5:38b2b8790b40 336
dragica 5:38b2b8790b40 337 void requestTemperature()
dragica 5:38b2b8790b40 338 {
dragica 5:38b2b8790b40 339 WriteReg(0, CONTROL2, 0x02, 1, FRMWRT_ALL_NR);
dragica 5:38b2b8790b40 340 ReadReg(0, AUX_GPIO1H, pFrame1, 2 , 0, FRMWRT_ALL_R);
dragica 5:38b2b8790b40 341
dragica 5:38b2b8790b40 342 waitFrameTemp();
dragica 5:38b2b8790b40 343 wait(1);
dragica 5:38b2b8790b40 344 }
dragica 5:38b2b8790b40 345
dragica 5:38b2b8790b40 346 void requestVoltage()
dragica 5:38b2b8790b40 347 {
dragica 5:38b2b8790b40 348 ReadReg(0, VCELL1H , pFrame1, 6 , 0, FRMWRT_ALL_R); //6 bajtova jer cita od adrese VCELL1H po dva bajta za svaki kanal (ima 3 kanala)
dragica 5:38b2b8790b40 349 waitFrame();
dragica 5:38b2b8790b40 350 }
minamax 2:03a6da61d834 351
minamax 1:d0662d4ffb8c 352 int main(){
minamax 1:d0662d4ffb8c 353 bms.attach(&callback);
minamax 1:d0662d4ffb8c 354 Wake79606();
dragica 5:38b2b8790b40 355
minamax 2:03a6da61d834 356 bms.baud(10);
minamax 2:03a6da61d834 357 bms.send_break();
minamax 2:03a6da61d834 358 bms.baud(250000);
minamax 2:03a6da61d834 359
dragica 5:38b2b8790b40 360 //wait(2); //marta rekla da mozda treba da se doda wait
minamax 1:d0662d4ffb8c 361 AutoAddress();
minamax 2:03a6da61d834 362
minamax 2:03a6da61d834 363
minamax 2:03a6da61d834 364 //WriteReg(0, COMM_CTRL, 0x343C, 2, FRMWRT_ALL_NR); //mask GPIO faults
minamax 2:03a6da61d834 365
minamax 2:03a6da61d834 366 wait(2);
minamax 1:d0662d4ffb8c 367 init();
dragica 5:38b2b8790b40 368 arrayInit();
minamax 2:03a6da61d834 369 /*WriteReg(0, COMM_TO, 0x00, 1, FRMWRT_ALL_NR); //disable COMM timeout because printf takes a long time between reads
minamax 2:03a6da61d834 370 WriteReg(0, SYSFLT1_FLT_RST, 0xFFFFFF, 3, FRMWRT_ALL_NR); //reset system faults
minamax 2:03a6da61d834 371 WriteReg(0, SYSFLT1_FLT_MSK, 0xFFFFFF, 3, FRMWRT_ALL_NR); //mask system faults (so we can test boards and not worry about triggering these faults accidentally)
minamax 2:03a6da61d834 372
minamax 2:03a6da61d834 373 //SET UP MAIN ADC
minamax 2:03a6da61d834 374 WriteReg(0, CELL_ADC_CTRL, 0x3F, 1, FRMWRT_ALL_NR); //enable conversions for all cells
minamax 2:03a6da61d834 375 WriteReg(0, CELL_ADC_CONF2, 0x08, 1, FRMWRT_ALL_NR); //set continuous ADC conversions, and set minimum conversion interval
dragica 5:38b2b8790b40 376 WriteReg(0, CONTROL2, 0x01, 1, FRMWRT_ALL_NR); //CELL_ADC_GO = 1*/
minamax 1:d0662d4ffb8c 377
minamax 1:d0662d4ffb8c 378 while (1) {
minamax 2:03a6da61d834 379
dragica 5:38b2b8790b40 380 requestVoltage();
dragica 5:38b2b8790b40 381 requestTemperature();
dragica 5:38b2b8790b40 382 /*cellBalanceEnable();
dragica 5:38b2b8790b40 383 waitBalancingToFinish();
dragica 5:38b2b8790b40 384 cellBalanceDisable();
dragica 5:38b2b8790b40 385 isCellBalancingDone();*/
minamax 1:d0662d4ffb8c 386
dragica 5:38b2b8790b40 387 checkDeviceStatus();
minamax 1:d0662d4ffb8c 388
minamax 1:d0662d4ffb8c 389 }
minamax 1:d0662d4ffb8c 390
minamax 1:d0662d4ffb8c 391
minamax 1:d0662d4ffb8c 392
minamax 1:d0662d4ffb8c 393 }