RYUICHI NAKAYAMA / mbed-dev

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common/SPI.cpp@119:3921aeca8633, 2016-04-29 (annotated)

Committer:
mbed_official
Date:
Fri Apr 29 01:15:11 2016 +0100
Revision:
119:3921aeca8633
Parent:
0:9b334a45a8ff 
Synchronized with git revision fe9720f24b1adc71ab6962506ec51290f6afd270



Full URL: https://github.com/mbedmicro/mbed/commit/fe9720f24b1adc71ab6962506ec51290f6afd270/



[Renesas RZ/A1H] Enable asynchronous communications

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #include "SPI.h"
bogdanm 0:9b334a45a8ff 17
bogdanm 0:9b334a45a8ff 18 #if DEVICE_SPI
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 namespace mbed {
bogdanm 0:9b334a45a8ff 21
bogdanm 0:9b334a45a8ff 22 #if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
bogdanm 0:9b334a45a8ff 23 CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
bogdanm 0:9b334a45a8ff 24 #endif
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
bogdanm 0:9b334a45a8ff 27 _spi(),
bogdanm 0:9b334a45a8ff 28 #if DEVICE_SPI_ASYNCH
bogdanm 0:9b334a45a8ff 29 _irq(this),
bogdanm 0:9b334a45a8ff 30 _usage(DMA_USAGE_NEVER),
bogdanm 0:9b334a45a8ff 31 #endif
bogdanm 0:9b334a45a8ff 32 _bits(8),
bogdanm 0:9b334a45a8ff 33 _mode(0),
bogdanm 0:9b334a45a8ff 34 _hz(1000000) {
bogdanm 0:9b334a45a8ff 35 spi_init(&_spi, mosi, miso, sclk, ssel);
bogdanm 0:9b334a45a8ff 36 spi_format(&_spi, _bits, _mode, 0);
bogdanm 0:9b334a45a8ff 37 spi_frequency(&_spi, _hz);
bogdanm 0:9b334a45a8ff 38 }
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 void SPI::format(int bits, int mode) {
bogdanm 0:9b334a45a8ff 41 _bits = bits;
bogdanm 0:9b334a45a8ff 42 _mode = mode;
bogdanm 0:9b334a45a8ff 43 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
bogdanm 0:9b334a45a8ff 44 aquire();
bogdanm 0:9b334a45a8ff 45 }
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 void SPI::frequency(int hz) {
bogdanm 0:9b334a45a8ff 48 _hz = hz;
bogdanm 0:9b334a45a8ff 49 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
bogdanm 0:9b334a45a8ff 50 aquire();
bogdanm 0:9b334a45a8ff 51 }
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 SPI* SPI::_owner = NULL;
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 // ignore the fact there are multiple physical spis, and always update if it wasnt us last
bogdanm 0:9b334a45a8ff 56 void SPI::aquire() {
bogdanm 0:9b334a45a8ff 57 if (_owner != this) {
bogdanm 0:9b334a45a8ff 58 spi_format(&_spi, _bits, _mode, 0);
bogdanm 0:9b334a45a8ff 59 spi_frequency(&_spi, _hz);
bogdanm 0:9b334a45a8ff 60 _owner = this;
bogdanm 0:9b334a45a8ff 61 }
bogdanm 0:9b334a45a8ff 62 }
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 int SPI::write(int value) {
bogdanm 0:9b334a45a8ff 65 aquire();
bogdanm 0:9b334a45a8ff 66 return spi_master_write(&_spi, value);
bogdanm 0:9b334a45a8ff 67 }
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 #if DEVICE_SPI_ASYNCH
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
bogdanm 0:9b334a45a8ff 72 {
bogdanm 0:9b334a45a8ff 73 if (spi_active(&_spi)) {
bogdanm 0:9b334a45a8ff 74 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
bogdanm 0:9b334a45a8ff 75 }
bogdanm 0:9b334a45a8ff 76 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
bogdanm 0:9b334a45a8ff 77 return 0;
bogdanm 0:9b334a45a8ff 78 }
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 void SPI::abort_transfer()
bogdanm 0:9b334a45a8ff 81 {
bogdanm 0:9b334a45a8ff 82 spi_abort_asynch(&_spi);
bogdanm 0:9b334a45a8ff 83 #if TRANSACTION_QUEUE_SIZE_SPI
bogdanm 0:9b334a45a8ff 84 dequeue_transaction();
bogdanm 0:9b334a45a8ff 85 #endif
bogdanm 0:9b334a45a8ff 86 }
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 void SPI::clear_transfer_buffer()
bogdanm 0:9b334a45a8ff 90 {
bogdanm 0:9b334a45a8ff 91 #if TRANSACTION_QUEUE_SIZE_SPI
bogdanm 0:9b334a45a8ff 92 _transaction_buffer.reset();
bogdanm 0:9b334a45a8ff 93 #endif
bogdanm 0:9b334a45a8ff 94 }
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 void SPI::abort_all_transfers()
bogdanm 0:9b334a45a8ff 97 {
bogdanm 0:9b334a45a8ff 98 clear_transfer_buffer();
bogdanm 0:9b334a45a8ff 99 abort_transfer();
bogdanm 0:9b334a45a8ff 100 }
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 int SPI::set_dma_usage(DMAUsage usage)
bogdanm 0:9b334a45a8ff 103 {
bogdanm 0:9b334a45a8ff 104 if (spi_active(&_spi)) {
bogdanm 0:9b334a45a8ff 105 return -1;
bogdanm 0:9b334a45a8ff 106 }
bogdanm 0:9b334a45a8ff 107 _usage = usage;
bogdanm 0:9b334a45a8ff 108 return 0;
bogdanm 0:9b334a45a8ff 109 }
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
bogdanm 0:9b334a45a8ff 112 {
bogdanm 0:9b334a45a8ff 113 #if TRANSACTION_QUEUE_SIZE_SPI
bogdanm 0:9b334a45a8ff 114 transaction_t t;
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 t.tx_buffer = const_cast<void *>(tx_buffer);
bogdanm 0:9b334a45a8ff 117 t.tx_length = tx_length;
bogdanm 0:9b334a45a8ff 118 t.rx_buffer = rx_buffer;
bogdanm 0:9b334a45a8ff 119 t.rx_length = rx_length;
bogdanm 0:9b334a45a8ff 120 t.event = event;
bogdanm 0:9b334a45a8ff 121 t.callback = callback;
bogdanm 0:9b334a45a8ff 122 t.width = bit_width;
bogdanm 0:9b334a45a8ff 123 Transaction<SPI> transaction(this, t);
bogdanm 0:9b334a45a8ff 124 if (_transaction_buffer.full()) {
bogdanm 0:9b334a45a8ff 125 return -1; // the buffer is full
bogdanm 0:9b334a45a8ff 126 } else {
mbed_official 119:3921aeca8633 127 __disable_irq();
bogdanm 0:9b334a45a8ff 128 _transaction_buffer.push(transaction);
mbed_official 119:3921aeca8633 129 if (!spi_active(&_spi)) {
mbed_official 119:3921aeca8633 130 dequeue_transaction();
mbed_official 119:3921aeca8633 131 }
mbed_official 119:3921aeca8633 132 __enable_irq();
bogdanm 0:9b334a45a8ff 133 return 0;
bogdanm 0:9b334a45a8ff 134 }
bogdanm 0:9b334a45a8ff 135 #else
bogdanm 0:9b334a45a8ff 136 return -1;
bogdanm 0:9b334a45a8ff 137 #endif
bogdanm 0:9b334a45a8ff 138 }
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
bogdanm 0:9b334a45a8ff 141 {
bogdanm 0:9b334a45a8ff 142 aquire();
bogdanm 0:9b334a45a8ff 143 _callback = callback;
bogdanm 0:9b334a45a8ff 144 _irq.callback(&SPI::irq_handler_asynch);
bogdanm 0:9b334a45a8ff 145 spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
bogdanm 0:9b334a45a8ff 146 }
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 #if TRANSACTION_QUEUE_SIZE_SPI
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 void SPI::start_transaction(transaction_t *data)
bogdanm 0:9b334a45a8ff 151 {
bogdanm 0:9b334a45a8ff 152 start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
bogdanm 0:9b334a45a8ff 153 }
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 void SPI::dequeue_transaction()
bogdanm 0:9b334a45a8ff 156 {
bogdanm 0:9b334a45a8ff 157 Transaction<SPI> t;
bogdanm 0:9b334a45a8ff 158 if (_transaction_buffer.pop(t)) {
bogdanm 0:9b334a45a8ff 159 SPI* obj = t.get_object();
bogdanm 0:9b334a45a8ff 160 transaction_t* data = t.get_transaction();
bogdanm 0:9b334a45a8ff 161 obj->start_transaction(data);
bogdanm 0:9b334a45a8ff 162 }
bogdanm 0:9b334a45a8ff 163 }
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 #endif
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 void SPI::irq_handler_asynch(void)
bogdanm 0:9b334a45a8ff 168 {
bogdanm 0:9b334a45a8ff 169 int event = spi_irq_handler_asynch(&_spi);
bogdanm 0:9b334a45a8ff 170 if (_callback && (event & SPI_EVENT_ALL)) {
bogdanm 0:9b334a45a8ff 171 _callback.call(event & SPI_EVENT_ALL);
bogdanm 0:9b334a45a8ff 172 }
bogdanm 0:9b334a45a8ff 173 #if TRANSACTION_QUEUE_SIZE_SPI
bogdanm 0:9b334a45a8ff 174 if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
bogdanm 0:9b334a45a8ff 175 // SPI peripheral is free (event happend), dequeue transaction
bogdanm 0:9b334a45a8ff 176 dequeue_transaction();
bogdanm 0:9b334a45a8ff 177 }
bogdanm 0:9b334a45a8ff 178 #endif
bogdanm 0:9b334a45a8ff 179 }
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 #endif
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 } // namespace mbed
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 #endif