Daiki Kato / mbed-os-lychee

mbed-os for GR-LYCHEE

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cmsis/core_sc300.h@0:f782d9c66c49, 2018-02-02 (annotated)

Committer:
dkato
Date:
Fri Feb 02 05:42:23 2018 +0000
Revision:
0:f782d9c66c49
mbed-os for GR-LYCHEE

Who changed what in which revision?

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dkato 0:f782d9c66c49 1 /**************************************************************************//**
dkato 0:f782d9c66c49 2 * @file core_sc300.h
dkato 0:f782d9c66c49 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
dkato 0:f782d9c66c49 4 * @version V4.10
dkato 0:f782d9c66c49 5 * @date 18. March 2015
dkato 0:f782d9c66c49 6 *
dkato 0:f782d9c66c49 7 * @note
dkato 0:f782d9c66c49 8 *
dkato 0:f782d9c66c49 9 ******************************************************************************/
dkato 0:f782d9c66c49 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
dkato 0:f782d9c66c49 11
dkato 0:f782d9c66c49 12 All rights reserved.
dkato 0:f782d9c66c49 13 Redistribution and use in source and binary forms, with or without
dkato 0:f782d9c66c49 14 modification, are permitted provided that the following conditions are met:
dkato 0:f782d9c66c49 15 - Redistributions of source code must retain the above copyright
dkato 0:f782d9c66c49 16 notice, this list of conditions and the following disclaimer.
dkato 0:f782d9c66c49 17 - Redistributions in binary form must reproduce the above copyright
dkato 0:f782d9c66c49 18 notice, this list of conditions and the following disclaimer in the
dkato 0:f782d9c66c49 19 documentation and/or other materials provided with the distribution.
dkato 0:f782d9c66c49 20 - Neither the name of ARM nor the names of its contributors may be used
dkato 0:f782d9c66c49 21 to endorse or promote products derived from this software without
dkato 0:f782d9c66c49 22 specific prior written permission.
dkato 0:f782d9c66c49 23 *
dkato 0:f782d9c66c49 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
dkato 0:f782d9c66c49 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
dkato 0:f782d9c66c49 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
dkato 0:f782d9c66c49 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
dkato 0:f782d9c66c49 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
dkato 0:f782d9c66c49 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
dkato 0:f782d9c66c49 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
dkato 0:f782d9c66c49 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
dkato 0:f782d9c66c49 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
dkato 0:f782d9c66c49 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
dkato 0:f782d9c66c49 34 POSSIBILITY OF SUCH DAMAGE.
dkato 0:f782d9c66c49 35 ---------------------------------------------------------------------------*/
dkato 0:f782d9c66c49 36
dkato 0:f782d9c66c49 37
dkato 0:f782d9c66c49 38 #if defined ( __ICCARM__ )
dkato 0:f782d9c66c49 39 #pragma system_include /* treat file as system include file for MISRA check */
dkato 0:f782d9c66c49 40 #endif
dkato 0:f782d9c66c49 41
dkato 0:f782d9c66c49 42 #ifndef __CORE_SC300_H_GENERIC
dkato 0:f782d9c66c49 43 #define __CORE_SC300_H_GENERIC
dkato 0:f782d9c66c49 44
dkato 0:f782d9c66c49 45 #ifdef __cplusplus
dkato 0:f782d9c66c49 46 extern "C" {
dkato 0:f782d9c66c49 47 #endif
dkato 0:f782d9c66c49 48
dkato 0:f782d9c66c49 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
dkato 0:f782d9c66c49 50 CMSIS violates the following MISRA-C:2004 rules:
dkato 0:f782d9c66c49 51
dkato 0:f782d9c66c49 52 \li Required Rule 8.5, object/function definition in header file.<br>
dkato 0:f782d9c66c49 53 Function definitions in header files are used to allow 'inlining'.
dkato 0:f782d9c66c49 54
dkato 0:f782d9c66c49 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
dkato 0:f782d9c66c49 56 Unions are used for effective representation of core registers.
dkato 0:f782d9c66c49 57
dkato 0:f782d9c66c49 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
dkato 0:f782d9c66c49 59 Function-like macros are used to allow more efficient code.
dkato 0:f782d9c66c49 60 */
dkato 0:f782d9c66c49 61
dkato 0:f782d9c66c49 62
dkato 0:f782d9c66c49 63 /*******************************************************************************
dkato 0:f782d9c66c49 64 * CMSIS definitions
dkato 0:f782d9c66c49 65 ******************************************************************************/
dkato 0:f782d9c66c49 66 /** \ingroup SC3000
dkato 0:f782d9c66c49 67 @{
dkato 0:f782d9c66c49 68 */
dkato 0:f782d9c66c49 69
dkato 0:f782d9c66c49 70 /* CMSIS SC300 definitions */
dkato 0:f782d9c66c49 71 #define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
dkato 0:f782d9c66c49 72 #define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
dkato 0:f782d9c66c49 73 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
dkato 0:f782d9c66c49 74 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
dkato 0:f782d9c66c49 75
dkato 0:f782d9c66c49 76 #define __CORTEX_SC (300) /*!< Cortex secure core */
dkato 0:f782d9c66c49 77
dkato 0:f782d9c66c49 78
dkato 0:f782d9c66c49 79 #if defined ( __CC_ARM )
dkato 0:f782d9c66c49 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
dkato 0:f782d9c66c49 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
dkato 0:f782d9c66c49 82 #define __STATIC_INLINE static __inline
dkato 0:f782d9c66c49 83
dkato 0:f782d9c66c49 84 #elif defined ( __GNUC__ )
dkato 0:f782d9c66c49 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
dkato 0:f782d9c66c49 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
dkato 0:f782d9c66c49 87 #define __STATIC_INLINE static inline
dkato 0:f782d9c66c49 88
dkato 0:f782d9c66c49 89 #elif defined ( __ICCARM__ )
dkato 0:f782d9c66c49 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
dkato 0:f782d9c66c49 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
dkato 0:f782d9c66c49 92 #define __STATIC_INLINE static inline
dkato 0:f782d9c66c49 93
dkato 0:f782d9c66c49 94 #elif defined ( __TMS470__ )
dkato 0:f782d9c66c49 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
dkato 0:f782d9c66c49 96 #define __STATIC_INLINE static inline
dkato 0:f782d9c66c49 97
dkato 0:f782d9c66c49 98 #elif defined ( __TASKING__ )
dkato 0:f782d9c66c49 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
dkato 0:f782d9c66c49 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
dkato 0:f782d9c66c49 101 #define __STATIC_INLINE static inline
dkato 0:f782d9c66c49 102
dkato 0:f782d9c66c49 103 #elif defined ( __CSMC__ )
dkato 0:f782d9c66c49 104 #define __packed
dkato 0:f782d9c66c49 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
dkato 0:f782d9c66c49 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
dkato 0:f782d9c66c49 107 #define __STATIC_INLINE static inline
dkato 0:f782d9c66c49 108
dkato 0:f782d9c66c49 109 #endif
dkato 0:f782d9c66c49 110
dkato 0:f782d9c66c49 111 /** __FPU_USED indicates whether an FPU is used or not.
dkato 0:f782d9c66c49 112 This core does not support an FPU at all
dkato 0:f782d9c66c49 113 */
dkato 0:f782d9c66c49 114 #define __FPU_USED 0
dkato 0:f782d9c66c49 115
dkato 0:f782d9c66c49 116 #if defined ( __CC_ARM )
dkato 0:f782d9c66c49 117 #if defined __TARGET_FPU_VFP
dkato 0:f782d9c66c49 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato 0:f782d9c66c49 119 #endif
dkato 0:f782d9c66c49 120
dkato 0:f782d9c66c49 121 #elif defined ( __GNUC__ )
dkato 0:f782d9c66c49 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
dkato 0:f782d9c66c49 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato 0:f782d9c66c49 124 #endif
dkato 0:f782d9c66c49 125
dkato 0:f782d9c66c49 126 #elif defined ( __ICCARM__ )
dkato 0:f782d9c66c49 127 #if defined __ARMVFP__
dkato 0:f782d9c66c49 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato 0:f782d9c66c49 129 #endif
dkato 0:f782d9c66c49 130
dkato 0:f782d9c66c49 131 #elif defined ( __TMS470__ )
dkato 0:f782d9c66c49 132 #if defined __TI__VFP_SUPPORT____
dkato 0:f782d9c66c49 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato 0:f782d9c66c49 134 #endif
dkato 0:f782d9c66c49 135
dkato 0:f782d9c66c49 136 #elif defined ( __TASKING__ )
dkato 0:f782d9c66c49 137 #if defined __FPU_VFP__
dkato 0:f782d9c66c49 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato 0:f782d9c66c49 139 #endif
dkato 0:f782d9c66c49 140
dkato 0:f782d9c66c49 141 #elif defined ( __CSMC__ ) /* Cosmic */
dkato 0:f782d9c66c49 142 #if ( __CSMC__ & 0x400) // FPU present for parser
dkato 0:f782d9c66c49 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato 0:f782d9c66c49 144 #endif
dkato 0:f782d9c66c49 145 #endif
dkato 0:f782d9c66c49 146
dkato 0:f782d9c66c49 147 #include <stdint.h> /* standard types definitions */
dkato 0:f782d9c66c49 148 #include <core_cmInstr.h> /* Core Instruction Access */
dkato 0:f782d9c66c49 149 #include <core_cmFunc.h> /* Core Function Access */
dkato 0:f782d9c66c49 150
dkato 0:f782d9c66c49 151 #ifdef __cplusplus
dkato 0:f782d9c66c49 152 }
dkato 0:f782d9c66c49 153 #endif
dkato 0:f782d9c66c49 154
dkato 0:f782d9c66c49 155 #endif /* __CORE_SC300_H_GENERIC */
dkato 0:f782d9c66c49 156
dkato 0:f782d9c66c49 157 #ifndef __CMSIS_GENERIC
dkato 0:f782d9c66c49 158
dkato 0:f782d9c66c49 159 #ifndef __CORE_SC300_H_DEPENDANT
dkato 0:f782d9c66c49 160 #define __CORE_SC300_H_DEPENDANT
dkato 0:f782d9c66c49 161
dkato 0:f782d9c66c49 162 #ifdef __cplusplus
dkato 0:f782d9c66c49 163 extern "C" {
dkato 0:f782d9c66c49 164 #endif
dkato 0:f782d9c66c49 165
dkato 0:f782d9c66c49 166 /* check device defines and use defaults */
dkato 0:f782d9c66c49 167 #if defined __CHECK_DEVICE_DEFINES
dkato 0:f782d9c66c49 168 #ifndef __SC300_REV
dkato 0:f782d9c66c49 169 #define __SC300_REV 0x0000
dkato 0:f782d9c66c49 170 #warning "__SC300_REV not defined in device header file; using default!"
dkato 0:f782d9c66c49 171 #endif
dkato 0:f782d9c66c49 172
dkato 0:f782d9c66c49 173 #ifndef __MPU_PRESENT
dkato 0:f782d9c66c49 174 #define __MPU_PRESENT 0
dkato 0:f782d9c66c49 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
dkato 0:f782d9c66c49 176 #endif
dkato 0:f782d9c66c49 177
dkato 0:f782d9c66c49 178 #ifndef __NVIC_PRIO_BITS
dkato 0:f782d9c66c49 179 #define __NVIC_PRIO_BITS 4
dkato 0:f782d9c66c49 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
dkato 0:f782d9c66c49 181 #endif
dkato 0:f782d9c66c49 182
dkato 0:f782d9c66c49 183 #ifndef __Vendor_SysTickConfig
dkato 0:f782d9c66c49 184 #define __Vendor_SysTickConfig 0
dkato 0:f782d9c66c49 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
dkato 0:f782d9c66c49 186 #endif
dkato 0:f782d9c66c49 187 #endif
dkato 0:f782d9c66c49 188
dkato 0:f782d9c66c49 189 /* IO definitions (access restrictions to peripheral registers) */
dkato 0:f782d9c66c49 190 /**
dkato 0:f782d9c66c49 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
dkato 0:f782d9c66c49 192
dkato 0:f782d9c66c49 193 <strong>IO Type Qualifiers</strong> are used
dkato 0:f782d9c66c49 194 \li to specify the access to peripheral variables.
dkato 0:f782d9c66c49 195 \li for automatic generation of peripheral register debug information.
dkato 0:f782d9c66c49 196 */
dkato 0:f782d9c66c49 197 #ifdef __cplusplus
dkato 0:f782d9c66c49 198 #define __I volatile /*!< Defines 'read only' permissions */
dkato 0:f782d9c66c49 199 #else
dkato 0:f782d9c66c49 200 #define __I volatile const /*!< Defines 'read only' permissions */
dkato 0:f782d9c66c49 201 #endif
dkato 0:f782d9c66c49 202 #define __O volatile /*!< Defines 'write only' permissions */
dkato 0:f782d9c66c49 203 #define __IO volatile /*!< Defines 'read / write' permissions */
dkato 0:f782d9c66c49 204
dkato 0:f782d9c66c49 205 /*@} end of group SC300 */
dkato 0:f782d9c66c49 206
dkato 0:f782d9c66c49 207
dkato 0:f782d9c66c49 208
dkato 0:f782d9c66c49 209 /*******************************************************************************
dkato 0:f782d9c66c49 210 * Register Abstraction
dkato 0:f782d9c66c49 211 Core Register contain:
dkato 0:f782d9c66c49 212 - Core Register
dkato 0:f782d9c66c49 213 - Core NVIC Register
dkato 0:f782d9c66c49 214 - Core SCB Register
dkato 0:f782d9c66c49 215 - Core SysTick Register
dkato 0:f782d9c66c49 216 - Core Debug Register
dkato 0:f782d9c66c49 217 - Core MPU Register
dkato 0:f782d9c66c49 218 ******************************************************************************/
dkato 0:f782d9c66c49 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
dkato 0:f782d9c66c49 220 \brief Type definitions and defines for Cortex-M processor based devices.
dkato 0:f782d9c66c49 221 */
dkato 0:f782d9c66c49 222
dkato 0:f782d9c66c49 223 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 224 \defgroup CMSIS_CORE Status and Control Registers
dkato 0:f782d9c66c49 225 \brief Core Register type definitions.
dkato 0:f782d9c66c49 226 @{
dkato 0:f782d9c66c49 227 */
dkato 0:f782d9c66c49 228
dkato 0:f782d9c66c49 229 /** \brief Union type to access the Application Program Status Register (APSR).
dkato 0:f782d9c66c49 230 */
dkato 0:f782d9c66c49 231 typedef union
dkato 0:f782d9c66c49 232 {
dkato 0:f782d9c66c49 233 struct
dkato 0:f782d9c66c49 234 {
dkato 0:f782d9c66c49 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
dkato 0:f782d9c66c49 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
dkato 0:f782d9c66c49 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
dkato 0:f782d9c66c49 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
dkato 0:f782d9c66c49 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
dkato 0:f782d9c66c49 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
dkato 0:f782d9c66c49 241 } b; /*!< Structure used for bit access */
dkato 0:f782d9c66c49 242 uint32_t w; /*!< Type used for word access */
dkato 0:f782d9c66c49 243 } APSR_Type;
dkato 0:f782d9c66c49 244
dkato 0:f782d9c66c49 245 /* APSR Register Definitions */
dkato 0:f782d9c66c49 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
dkato 0:f782d9c66c49 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
dkato 0:f782d9c66c49 248
dkato 0:f782d9c66c49 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
dkato 0:f782d9c66c49 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
dkato 0:f782d9c66c49 251
dkato 0:f782d9c66c49 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
dkato 0:f782d9c66c49 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
dkato 0:f782d9c66c49 254
dkato 0:f782d9c66c49 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
dkato 0:f782d9c66c49 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
dkato 0:f782d9c66c49 257
dkato 0:f782d9c66c49 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
dkato 0:f782d9c66c49 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
dkato 0:f782d9c66c49 260
dkato 0:f782d9c66c49 261
dkato 0:f782d9c66c49 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
dkato 0:f782d9c66c49 263 */
dkato 0:f782d9c66c49 264 typedef union
dkato 0:f782d9c66c49 265 {
dkato 0:f782d9c66c49 266 struct
dkato 0:f782d9c66c49 267 {
dkato 0:f782d9c66c49 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
dkato 0:f782d9c66c49 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
dkato 0:f782d9c66c49 270 } b; /*!< Structure used for bit access */
dkato 0:f782d9c66c49 271 uint32_t w; /*!< Type used for word access */
dkato 0:f782d9c66c49 272 } IPSR_Type;
dkato 0:f782d9c66c49 273
dkato 0:f782d9c66c49 274 /* IPSR Register Definitions */
dkato 0:f782d9c66c49 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
dkato 0:f782d9c66c49 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
dkato 0:f782d9c66c49 277
dkato 0:f782d9c66c49 278
dkato 0:f782d9c66c49 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
dkato 0:f782d9c66c49 280 */
dkato 0:f782d9c66c49 281 typedef union
dkato 0:f782d9c66c49 282 {
dkato 0:f782d9c66c49 283 struct
dkato 0:f782d9c66c49 284 {
dkato 0:f782d9c66c49 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
dkato 0:f782d9c66c49 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
dkato 0:f782d9c66c49 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
dkato 0:f782d9c66c49 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
dkato 0:f782d9c66c49 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
dkato 0:f782d9c66c49 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
dkato 0:f782d9c66c49 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
dkato 0:f782d9c66c49 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
dkato 0:f782d9c66c49 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
dkato 0:f782d9c66c49 294 } b; /*!< Structure used for bit access */
dkato 0:f782d9c66c49 295 uint32_t w; /*!< Type used for word access */
dkato 0:f782d9c66c49 296 } xPSR_Type;
dkato 0:f782d9c66c49 297
dkato 0:f782d9c66c49 298 /* xPSR Register Definitions */
dkato 0:f782d9c66c49 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
dkato 0:f782d9c66c49 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
dkato 0:f782d9c66c49 301
dkato 0:f782d9c66c49 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
dkato 0:f782d9c66c49 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
dkato 0:f782d9c66c49 304
dkato 0:f782d9c66c49 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
dkato 0:f782d9c66c49 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
dkato 0:f782d9c66c49 307
dkato 0:f782d9c66c49 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
dkato 0:f782d9c66c49 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
dkato 0:f782d9c66c49 310
dkato 0:f782d9c66c49 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
dkato 0:f782d9c66c49 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
dkato 0:f782d9c66c49 313
dkato 0:f782d9c66c49 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
dkato 0:f782d9c66c49 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
dkato 0:f782d9c66c49 316
dkato 0:f782d9c66c49 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
dkato 0:f782d9c66c49 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
dkato 0:f782d9c66c49 319
dkato 0:f782d9c66c49 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
dkato 0:f782d9c66c49 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
dkato 0:f782d9c66c49 322
dkato 0:f782d9c66c49 323
dkato 0:f782d9c66c49 324 /** \brief Union type to access the Control Registers (CONTROL).
dkato 0:f782d9c66c49 325 */
dkato 0:f782d9c66c49 326 typedef union
dkato 0:f782d9c66c49 327 {
dkato 0:f782d9c66c49 328 struct
dkato 0:f782d9c66c49 329 {
dkato 0:f782d9c66c49 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
dkato 0:f782d9c66c49 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
dkato 0:f782d9c66c49 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
dkato 0:f782d9c66c49 333 } b; /*!< Structure used for bit access */
dkato 0:f782d9c66c49 334 uint32_t w; /*!< Type used for word access */
dkato 0:f782d9c66c49 335 } CONTROL_Type;
dkato 0:f782d9c66c49 336
dkato 0:f782d9c66c49 337 /* CONTROL Register Definitions */
dkato 0:f782d9c66c49 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
dkato 0:f782d9c66c49 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
dkato 0:f782d9c66c49 340
dkato 0:f782d9c66c49 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
dkato 0:f782d9c66c49 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
dkato 0:f782d9c66c49 343
dkato 0:f782d9c66c49 344 /*@} end of group CMSIS_CORE */
dkato 0:f782d9c66c49 345
dkato 0:f782d9c66c49 346
dkato 0:f782d9c66c49 347 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
dkato 0:f782d9c66c49 349 \brief Type definitions for the NVIC Registers
dkato 0:f782d9c66c49 350 @{
dkato 0:f782d9c66c49 351 */
dkato 0:f782d9c66c49 352
dkato 0:f782d9c66c49 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
dkato 0:f782d9c66c49 354 */
dkato 0:f782d9c66c49 355 typedef struct
dkato 0:f782d9c66c49 356 {
dkato 0:f782d9c66c49 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
dkato 0:f782d9c66c49 358 uint32_t RESERVED0[24];
dkato 0:f782d9c66c49 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
dkato 0:f782d9c66c49 360 uint32_t RSERVED1[24];
dkato 0:f782d9c66c49 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
dkato 0:f782d9c66c49 362 uint32_t RESERVED2[24];
dkato 0:f782d9c66c49 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
dkato 0:f782d9c66c49 364 uint32_t RESERVED3[24];
dkato 0:f782d9c66c49 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
dkato 0:f782d9c66c49 366 uint32_t RESERVED4[56];
dkato 0:f782d9c66c49 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
dkato 0:f782d9c66c49 368 uint32_t RESERVED5[644];
dkato 0:f782d9c66c49 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
dkato 0:f782d9c66c49 370 } NVIC_Type;
dkato 0:f782d9c66c49 371
dkato 0:f782d9c66c49 372 /* Software Triggered Interrupt Register Definitions */
dkato 0:f782d9c66c49 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
dkato 0:f782d9c66c49 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
dkato 0:f782d9c66c49 375
dkato 0:f782d9c66c49 376 /*@} end of group CMSIS_NVIC */
dkato 0:f782d9c66c49 377
dkato 0:f782d9c66c49 378
dkato 0:f782d9c66c49 379 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 380 \defgroup CMSIS_SCB System Control Block (SCB)
dkato 0:f782d9c66c49 381 \brief Type definitions for the System Control Block Registers
dkato 0:f782d9c66c49 382 @{
dkato 0:f782d9c66c49 383 */
dkato 0:f782d9c66c49 384
dkato 0:f782d9c66c49 385 /** \brief Structure type to access the System Control Block (SCB).
dkato 0:f782d9c66c49 386 */
dkato 0:f782d9c66c49 387 typedef struct
dkato 0:f782d9c66c49 388 {
dkato 0:f782d9c66c49 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
dkato 0:f782d9c66c49 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
dkato 0:f782d9c66c49 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
dkato 0:f782d9c66c49 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
dkato 0:f782d9c66c49 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
dkato 0:f782d9c66c49 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
dkato 0:f782d9c66c49 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
dkato 0:f782d9c66c49 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
dkato 0:f782d9c66c49 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
dkato 0:f782d9c66c49 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
dkato 0:f782d9c66c49 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
dkato 0:f782d9c66c49 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
dkato 0:f782d9c66c49 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
dkato 0:f782d9c66c49 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
dkato 0:f782d9c66c49 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
dkato 0:f782d9c66c49 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
dkato 0:f782d9c66c49 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
dkato 0:f782d9c66c49 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
dkato 0:f782d9c66c49 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
dkato 0:f782d9c66c49 408 uint32_t RESERVED0[5];
dkato 0:f782d9c66c49 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
dkato 0:f782d9c66c49 410 uint32_t RESERVED1[129];
dkato 0:f782d9c66c49 411 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
dkato 0:f782d9c66c49 412 } SCB_Type;
dkato 0:f782d9c66c49 413
dkato 0:f782d9c66c49 414 /* SCB CPUID Register Definitions */
dkato 0:f782d9c66c49 415 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
dkato 0:f782d9c66c49 416 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
dkato 0:f782d9c66c49 417
dkato 0:f782d9c66c49 418 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
dkato 0:f782d9c66c49 419 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
dkato 0:f782d9c66c49 420
dkato 0:f782d9c66c49 421 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
dkato 0:f782d9c66c49 422 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
dkato 0:f782d9c66c49 423
dkato 0:f782d9c66c49 424 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
dkato 0:f782d9c66c49 425 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
dkato 0:f782d9c66c49 426
dkato 0:f782d9c66c49 427 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
dkato 0:f782d9c66c49 428 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
dkato 0:f782d9c66c49 429
dkato 0:f782d9c66c49 430 /* SCB Interrupt Control State Register Definitions */
dkato 0:f782d9c66c49 431 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
dkato 0:f782d9c66c49 432 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
dkato 0:f782d9c66c49 433
dkato 0:f782d9c66c49 434 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
dkato 0:f782d9c66c49 435 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
dkato 0:f782d9c66c49 436
dkato 0:f782d9c66c49 437 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
dkato 0:f782d9c66c49 438 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
dkato 0:f782d9c66c49 439
dkato 0:f782d9c66c49 440 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
dkato 0:f782d9c66c49 441 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
dkato 0:f782d9c66c49 442
dkato 0:f782d9c66c49 443 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
dkato 0:f782d9c66c49 444 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
dkato 0:f782d9c66c49 445
dkato 0:f782d9c66c49 446 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
dkato 0:f782d9c66c49 447 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
dkato 0:f782d9c66c49 448
dkato 0:f782d9c66c49 449 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
dkato 0:f782d9c66c49 450 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
dkato 0:f782d9c66c49 451
dkato 0:f782d9c66c49 452 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
dkato 0:f782d9c66c49 453 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
dkato 0:f782d9c66c49 454
dkato 0:f782d9c66c49 455 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
dkato 0:f782d9c66c49 456 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
dkato 0:f782d9c66c49 457
dkato 0:f782d9c66c49 458 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
dkato 0:f782d9c66c49 459 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
dkato 0:f782d9c66c49 460
dkato 0:f782d9c66c49 461 /* SCB Vector Table Offset Register Definitions */
dkato 0:f782d9c66c49 462 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
dkato 0:f782d9c66c49 463 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
dkato 0:f782d9c66c49 464
dkato 0:f782d9c66c49 465 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
dkato 0:f782d9c66c49 466 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
dkato 0:f782d9c66c49 467
dkato 0:f782d9c66c49 468 /* SCB Application Interrupt and Reset Control Register Definitions */
dkato 0:f782d9c66c49 469 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
dkato 0:f782d9c66c49 470 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
dkato 0:f782d9c66c49 471
dkato 0:f782d9c66c49 472 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
dkato 0:f782d9c66c49 473 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
dkato 0:f782d9c66c49 474
dkato 0:f782d9c66c49 475 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
dkato 0:f782d9c66c49 476 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
dkato 0:f782d9c66c49 477
dkato 0:f782d9c66c49 478 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
dkato 0:f782d9c66c49 479 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
dkato 0:f782d9c66c49 480
dkato 0:f782d9c66c49 481 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
dkato 0:f782d9c66c49 482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
dkato 0:f782d9c66c49 483
dkato 0:f782d9c66c49 484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
dkato 0:f782d9c66c49 485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
dkato 0:f782d9c66c49 486
dkato 0:f782d9c66c49 487 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
dkato 0:f782d9c66c49 488 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
dkato 0:f782d9c66c49 489
dkato 0:f782d9c66c49 490 /* SCB System Control Register Definitions */
dkato 0:f782d9c66c49 491 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
dkato 0:f782d9c66c49 492 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
dkato 0:f782d9c66c49 493
dkato 0:f782d9c66c49 494 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
dkato 0:f782d9c66c49 495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
dkato 0:f782d9c66c49 496
dkato 0:f782d9c66c49 497 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
dkato 0:f782d9c66c49 498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
dkato 0:f782d9c66c49 499
dkato 0:f782d9c66c49 500 /* SCB Configuration Control Register Definitions */
dkato 0:f782d9c66c49 501 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
dkato 0:f782d9c66c49 502 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
dkato 0:f782d9c66c49 503
dkato 0:f782d9c66c49 504 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
dkato 0:f782d9c66c49 505 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
dkato 0:f782d9c66c49 506
dkato 0:f782d9c66c49 507 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
dkato 0:f782d9c66c49 508 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
dkato 0:f782d9c66c49 509
dkato 0:f782d9c66c49 510 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
dkato 0:f782d9c66c49 511 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
dkato 0:f782d9c66c49 512
dkato 0:f782d9c66c49 513 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
dkato 0:f782d9c66c49 514 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
dkato 0:f782d9c66c49 515
dkato 0:f782d9c66c49 516 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
dkato 0:f782d9c66c49 517 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
dkato 0:f782d9c66c49 518
dkato 0:f782d9c66c49 519 /* SCB System Handler Control and State Register Definitions */
dkato 0:f782d9c66c49 520 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
dkato 0:f782d9c66c49 521 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
dkato 0:f782d9c66c49 522
dkato 0:f782d9c66c49 523 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
dkato 0:f782d9c66c49 524 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
dkato 0:f782d9c66c49 525
dkato 0:f782d9c66c49 526 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
dkato 0:f782d9c66c49 527 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
dkato 0:f782d9c66c49 528
dkato 0:f782d9c66c49 529 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
dkato 0:f782d9c66c49 530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
dkato 0:f782d9c66c49 531
dkato 0:f782d9c66c49 532 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
dkato 0:f782d9c66c49 533 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
dkato 0:f782d9c66c49 534
dkato 0:f782d9c66c49 535 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
dkato 0:f782d9c66c49 536 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
dkato 0:f782d9c66c49 537
dkato 0:f782d9c66c49 538 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
dkato 0:f782d9c66c49 539 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
dkato 0:f782d9c66c49 540
dkato 0:f782d9c66c49 541 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
dkato 0:f782d9c66c49 542 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
dkato 0:f782d9c66c49 543
dkato 0:f782d9c66c49 544 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
dkato 0:f782d9c66c49 545 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
dkato 0:f782d9c66c49 546
dkato 0:f782d9c66c49 547 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
dkato 0:f782d9c66c49 548 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
dkato 0:f782d9c66c49 549
dkato 0:f782d9c66c49 550 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
dkato 0:f782d9c66c49 551 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
dkato 0:f782d9c66c49 552
dkato 0:f782d9c66c49 553 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
dkato 0:f782d9c66c49 554 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
dkato 0:f782d9c66c49 555
dkato 0:f782d9c66c49 556 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
dkato 0:f782d9c66c49 557 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
dkato 0:f782d9c66c49 558
dkato 0:f782d9c66c49 559 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
dkato 0:f782d9c66c49 560 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
dkato 0:f782d9c66c49 561
dkato 0:f782d9c66c49 562 /* SCB Configurable Fault Status Registers Definitions */
dkato 0:f782d9c66c49 563 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
dkato 0:f782d9c66c49 564 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
dkato 0:f782d9c66c49 565
dkato 0:f782d9c66c49 566 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
dkato 0:f782d9c66c49 567 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
dkato 0:f782d9c66c49 568
dkato 0:f782d9c66c49 569 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
dkato 0:f782d9c66c49 570 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
dkato 0:f782d9c66c49 571
dkato 0:f782d9c66c49 572 /* SCB Hard Fault Status Registers Definitions */
dkato 0:f782d9c66c49 573 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
dkato 0:f782d9c66c49 574 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
dkato 0:f782d9c66c49 575
dkato 0:f782d9c66c49 576 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
dkato 0:f782d9c66c49 577 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
dkato 0:f782d9c66c49 578
dkato 0:f782d9c66c49 579 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
dkato 0:f782d9c66c49 580 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
dkato 0:f782d9c66c49 581
dkato 0:f782d9c66c49 582 /* SCB Debug Fault Status Register Definitions */
dkato 0:f782d9c66c49 583 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
dkato 0:f782d9c66c49 584 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
dkato 0:f782d9c66c49 585
dkato 0:f782d9c66c49 586 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
dkato 0:f782d9c66c49 587 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
dkato 0:f782d9c66c49 588
dkato 0:f782d9c66c49 589 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
dkato 0:f782d9c66c49 590 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
dkato 0:f782d9c66c49 591
dkato 0:f782d9c66c49 592 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
dkato 0:f782d9c66c49 593 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
dkato 0:f782d9c66c49 594
dkato 0:f782d9c66c49 595 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
dkato 0:f782d9c66c49 596 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
dkato 0:f782d9c66c49 597
dkato 0:f782d9c66c49 598 /*@} end of group CMSIS_SCB */
dkato 0:f782d9c66c49 599
dkato 0:f782d9c66c49 600
dkato 0:f782d9c66c49 601 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 602 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
dkato 0:f782d9c66c49 603 \brief Type definitions for the System Control and ID Register not in the SCB
dkato 0:f782d9c66c49 604 @{
dkato 0:f782d9c66c49 605 */
dkato 0:f782d9c66c49 606
dkato 0:f782d9c66c49 607 /** \brief Structure type to access the System Control and ID Register not in the SCB.
dkato 0:f782d9c66c49 608 */
dkato 0:f782d9c66c49 609 typedef struct
dkato 0:f782d9c66c49 610 {
dkato 0:f782d9c66c49 611 uint32_t RESERVED0[1];
dkato 0:f782d9c66c49 612 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
dkato 0:f782d9c66c49 613 uint32_t RESERVED1[1];
dkato 0:f782d9c66c49 614 } SCnSCB_Type;
dkato 0:f782d9c66c49 615
dkato 0:f782d9c66c49 616 /* Interrupt Controller Type Register Definitions */
dkato 0:f782d9c66c49 617 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
dkato 0:f782d9c66c49 618 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
dkato 0:f782d9c66c49 619
dkato 0:f782d9c66c49 620 /*@} end of group CMSIS_SCnotSCB */
dkato 0:f782d9c66c49 621
dkato 0:f782d9c66c49 622
dkato 0:f782d9c66c49 623 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 624 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
dkato 0:f782d9c66c49 625 \brief Type definitions for the System Timer Registers.
dkato 0:f782d9c66c49 626 @{
dkato 0:f782d9c66c49 627 */
dkato 0:f782d9c66c49 628
dkato 0:f782d9c66c49 629 /** \brief Structure type to access the System Timer (SysTick).
dkato 0:f782d9c66c49 630 */
dkato 0:f782d9c66c49 631 typedef struct
dkato 0:f782d9c66c49 632 {
dkato 0:f782d9c66c49 633 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
dkato 0:f782d9c66c49 634 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
dkato 0:f782d9c66c49 635 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
dkato 0:f782d9c66c49 636 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
dkato 0:f782d9c66c49 637 } SysTick_Type;
dkato 0:f782d9c66c49 638
dkato 0:f782d9c66c49 639 /* SysTick Control / Status Register Definitions */
dkato 0:f782d9c66c49 640 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
dkato 0:f782d9c66c49 641 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
dkato 0:f782d9c66c49 642
dkato 0:f782d9c66c49 643 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
dkato 0:f782d9c66c49 644 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
dkato 0:f782d9c66c49 645
dkato 0:f782d9c66c49 646 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
dkato 0:f782d9c66c49 647 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
dkato 0:f782d9c66c49 648
dkato 0:f782d9c66c49 649 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
dkato 0:f782d9c66c49 650 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
dkato 0:f782d9c66c49 651
dkato 0:f782d9c66c49 652 /* SysTick Reload Register Definitions */
dkato 0:f782d9c66c49 653 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
dkato 0:f782d9c66c49 654 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
dkato 0:f782d9c66c49 655
dkato 0:f782d9c66c49 656 /* SysTick Current Register Definitions */
dkato 0:f782d9c66c49 657 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
dkato 0:f782d9c66c49 658 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
dkato 0:f782d9c66c49 659
dkato 0:f782d9c66c49 660 /* SysTick Calibration Register Definitions */
dkato 0:f782d9c66c49 661 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
dkato 0:f782d9c66c49 662 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
dkato 0:f782d9c66c49 663
dkato 0:f782d9c66c49 664 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
dkato 0:f782d9c66c49 665 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
dkato 0:f782d9c66c49 666
dkato 0:f782d9c66c49 667 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
dkato 0:f782d9c66c49 668 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
dkato 0:f782d9c66c49 669
dkato 0:f782d9c66c49 670 /*@} end of group CMSIS_SysTick */
dkato 0:f782d9c66c49 671
dkato 0:f782d9c66c49 672
dkato 0:f782d9c66c49 673 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 674 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
dkato 0:f782d9c66c49 675 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
dkato 0:f782d9c66c49 676 @{
dkato 0:f782d9c66c49 677 */
dkato 0:f782d9c66c49 678
dkato 0:f782d9c66c49 679 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
dkato 0:f782d9c66c49 680 */
dkato 0:f782d9c66c49 681 typedef struct
dkato 0:f782d9c66c49 682 {
dkato 0:f782d9c66c49 683 __O union
dkato 0:f782d9c66c49 684 {
dkato 0:f782d9c66c49 685 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
dkato 0:f782d9c66c49 686 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
dkato 0:f782d9c66c49 687 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
dkato 0:f782d9c66c49 688 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
dkato 0:f782d9c66c49 689 uint32_t RESERVED0[864];
dkato 0:f782d9c66c49 690 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
dkato 0:f782d9c66c49 691 uint32_t RESERVED1[15];
dkato 0:f782d9c66c49 692 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
dkato 0:f782d9c66c49 693 uint32_t RESERVED2[15];
dkato 0:f782d9c66c49 694 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
dkato 0:f782d9c66c49 695 uint32_t RESERVED3[29];
dkato 0:f782d9c66c49 696 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
dkato 0:f782d9c66c49 697 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
dkato 0:f782d9c66c49 698 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
dkato 0:f782d9c66c49 699 uint32_t RESERVED4[43];
dkato 0:f782d9c66c49 700 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
dkato 0:f782d9c66c49 701 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
dkato 0:f782d9c66c49 702 uint32_t RESERVED5[6];
dkato 0:f782d9c66c49 703 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
dkato 0:f782d9c66c49 704 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
dkato 0:f782d9c66c49 705 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
dkato 0:f782d9c66c49 706 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
dkato 0:f782d9c66c49 707 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
dkato 0:f782d9c66c49 708 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
dkato 0:f782d9c66c49 709 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
dkato 0:f782d9c66c49 710 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
dkato 0:f782d9c66c49 711 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
dkato 0:f782d9c66c49 712 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
dkato 0:f782d9c66c49 713 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
dkato 0:f782d9c66c49 714 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
dkato 0:f782d9c66c49 715 } ITM_Type;
dkato 0:f782d9c66c49 716
dkato 0:f782d9c66c49 717 /* ITM Trace Privilege Register Definitions */
dkato 0:f782d9c66c49 718 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
dkato 0:f782d9c66c49 719 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
dkato 0:f782d9c66c49 720
dkato 0:f782d9c66c49 721 /* ITM Trace Control Register Definitions */
dkato 0:f782d9c66c49 722 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
dkato 0:f782d9c66c49 723 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
dkato 0:f782d9c66c49 724
dkato 0:f782d9c66c49 725 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
dkato 0:f782d9c66c49 726 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
dkato 0:f782d9c66c49 727
dkato 0:f782d9c66c49 728 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
dkato 0:f782d9c66c49 729 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
dkato 0:f782d9c66c49 730
dkato 0:f782d9c66c49 731 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
dkato 0:f782d9c66c49 732 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
dkato 0:f782d9c66c49 733
dkato 0:f782d9c66c49 734 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
dkato 0:f782d9c66c49 735 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
dkato 0:f782d9c66c49 736
dkato 0:f782d9c66c49 737 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
dkato 0:f782d9c66c49 738 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
dkato 0:f782d9c66c49 739
dkato 0:f782d9c66c49 740 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
dkato 0:f782d9c66c49 741 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
dkato 0:f782d9c66c49 742
dkato 0:f782d9c66c49 743 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
dkato 0:f782d9c66c49 744 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
dkato 0:f782d9c66c49 745
dkato 0:f782d9c66c49 746 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
dkato 0:f782d9c66c49 747 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
dkato 0:f782d9c66c49 748
dkato 0:f782d9c66c49 749 /* ITM Integration Write Register Definitions */
dkato 0:f782d9c66c49 750 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
dkato 0:f782d9c66c49 751 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
dkato 0:f782d9c66c49 752
dkato 0:f782d9c66c49 753 /* ITM Integration Read Register Definitions */
dkato 0:f782d9c66c49 754 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
dkato 0:f782d9c66c49 755 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
dkato 0:f782d9c66c49 756
dkato 0:f782d9c66c49 757 /* ITM Integration Mode Control Register Definitions */
dkato 0:f782d9c66c49 758 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
dkato 0:f782d9c66c49 759 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
dkato 0:f782d9c66c49 760
dkato 0:f782d9c66c49 761 /* ITM Lock Status Register Definitions */
dkato 0:f782d9c66c49 762 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
dkato 0:f782d9c66c49 763 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
dkato 0:f782d9c66c49 764
dkato 0:f782d9c66c49 765 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
dkato 0:f782d9c66c49 766 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
dkato 0:f782d9c66c49 767
dkato 0:f782d9c66c49 768 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
dkato 0:f782d9c66c49 769 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
dkato 0:f782d9c66c49 770
dkato 0:f782d9c66c49 771 /*@}*/ /* end of group CMSIS_ITM */
dkato 0:f782d9c66c49 772
dkato 0:f782d9c66c49 773
dkato 0:f782d9c66c49 774 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 775 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
dkato 0:f782d9c66c49 776 \brief Type definitions for the Data Watchpoint and Trace (DWT)
dkato 0:f782d9c66c49 777 @{
dkato 0:f782d9c66c49 778 */
dkato 0:f782d9c66c49 779
dkato 0:f782d9c66c49 780 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
dkato 0:f782d9c66c49 781 */
dkato 0:f782d9c66c49 782 typedef struct
dkato 0:f782d9c66c49 783 {
dkato 0:f782d9c66c49 784 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
dkato 0:f782d9c66c49 785 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
dkato 0:f782d9c66c49 786 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
dkato 0:f782d9c66c49 787 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
dkato 0:f782d9c66c49 788 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
dkato 0:f782d9c66c49 789 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
dkato 0:f782d9c66c49 790 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
dkato 0:f782d9c66c49 791 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
dkato 0:f782d9c66c49 792 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
dkato 0:f782d9c66c49 793 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
dkato 0:f782d9c66c49 794 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
dkato 0:f782d9c66c49 795 uint32_t RESERVED0[1];
dkato 0:f782d9c66c49 796 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
dkato 0:f782d9c66c49 797 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
dkato 0:f782d9c66c49 798 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
dkato 0:f782d9c66c49 799 uint32_t RESERVED1[1];
dkato 0:f782d9c66c49 800 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
dkato 0:f782d9c66c49 801 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
dkato 0:f782d9c66c49 802 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
dkato 0:f782d9c66c49 803 uint32_t RESERVED2[1];
dkato 0:f782d9c66c49 804 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
dkato 0:f782d9c66c49 805 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
dkato 0:f782d9c66c49 806 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
dkato 0:f782d9c66c49 807 } DWT_Type;
dkato 0:f782d9c66c49 808
dkato 0:f782d9c66c49 809 /* DWT Control Register Definitions */
dkato 0:f782d9c66c49 810 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
dkato 0:f782d9c66c49 811 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
dkato 0:f782d9c66c49 812
dkato 0:f782d9c66c49 813 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
dkato 0:f782d9c66c49 814 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
dkato 0:f782d9c66c49 815
dkato 0:f782d9c66c49 816 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
dkato 0:f782d9c66c49 817 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
dkato 0:f782d9c66c49 818
dkato 0:f782d9c66c49 819 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
dkato 0:f782d9c66c49 820 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
dkato 0:f782d9c66c49 821
dkato 0:f782d9c66c49 822 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
dkato 0:f782d9c66c49 823 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
dkato 0:f782d9c66c49 824
dkato 0:f782d9c66c49 825 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
dkato 0:f782d9c66c49 826 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
dkato 0:f782d9c66c49 827
dkato 0:f782d9c66c49 828 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
dkato 0:f782d9c66c49 829 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
dkato 0:f782d9c66c49 830
dkato 0:f782d9c66c49 831 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
dkato 0:f782d9c66c49 832 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
dkato 0:f782d9c66c49 833
dkato 0:f782d9c66c49 834 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
dkato 0:f782d9c66c49 835 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
dkato 0:f782d9c66c49 836
dkato 0:f782d9c66c49 837 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
dkato 0:f782d9c66c49 838 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
dkato 0:f782d9c66c49 839
dkato 0:f782d9c66c49 840 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
dkato 0:f782d9c66c49 841 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
dkato 0:f782d9c66c49 842
dkato 0:f782d9c66c49 843 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
dkato 0:f782d9c66c49 844 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
dkato 0:f782d9c66c49 845
dkato 0:f782d9c66c49 846 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
dkato 0:f782d9c66c49 847 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
dkato 0:f782d9c66c49 848
dkato 0:f782d9c66c49 849 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
dkato 0:f782d9c66c49 850 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
dkato 0:f782d9c66c49 851
dkato 0:f782d9c66c49 852 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
dkato 0:f782d9c66c49 853 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
dkato 0:f782d9c66c49 854
dkato 0:f782d9c66c49 855 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
dkato 0:f782d9c66c49 856 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
dkato 0:f782d9c66c49 857
dkato 0:f782d9c66c49 858 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
dkato 0:f782d9c66c49 859 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
dkato 0:f782d9c66c49 860
dkato 0:f782d9c66c49 861 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
dkato 0:f782d9c66c49 862 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
dkato 0:f782d9c66c49 863
dkato 0:f782d9c66c49 864 /* DWT CPI Count Register Definitions */
dkato 0:f782d9c66c49 865 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
dkato 0:f782d9c66c49 866 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
dkato 0:f782d9c66c49 867
dkato 0:f782d9c66c49 868 /* DWT Exception Overhead Count Register Definitions */
dkato 0:f782d9c66c49 869 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
dkato 0:f782d9c66c49 870 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
dkato 0:f782d9c66c49 871
dkato 0:f782d9c66c49 872 /* DWT Sleep Count Register Definitions */
dkato 0:f782d9c66c49 873 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
dkato 0:f782d9c66c49 874 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
dkato 0:f782d9c66c49 875
dkato 0:f782d9c66c49 876 /* DWT LSU Count Register Definitions */
dkato 0:f782d9c66c49 877 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
dkato 0:f782d9c66c49 878 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
dkato 0:f782d9c66c49 879
dkato 0:f782d9c66c49 880 /* DWT Folded-instruction Count Register Definitions */
dkato 0:f782d9c66c49 881 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
dkato 0:f782d9c66c49 882 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
dkato 0:f782d9c66c49 883
dkato 0:f782d9c66c49 884 /* DWT Comparator Mask Register Definitions */
dkato 0:f782d9c66c49 885 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
dkato 0:f782d9c66c49 886 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
dkato 0:f782d9c66c49 887
dkato 0:f782d9c66c49 888 /* DWT Comparator Function Register Definitions */
dkato 0:f782d9c66c49 889 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
dkato 0:f782d9c66c49 890 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
dkato 0:f782d9c66c49 891
dkato 0:f782d9c66c49 892 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
dkato 0:f782d9c66c49 893 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
dkato 0:f782d9c66c49 894
dkato 0:f782d9c66c49 895 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
dkato 0:f782d9c66c49 896 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
dkato 0:f782d9c66c49 897
dkato 0:f782d9c66c49 898 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
dkato 0:f782d9c66c49 899 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
dkato 0:f782d9c66c49 900
dkato 0:f782d9c66c49 901 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
dkato 0:f782d9c66c49 902 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
dkato 0:f782d9c66c49 903
dkato 0:f782d9c66c49 904 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
dkato 0:f782d9c66c49 905 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
dkato 0:f782d9c66c49 906
dkato 0:f782d9c66c49 907 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
dkato 0:f782d9c66c49 908 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
dkato 0:f782d9c66c49 909
dkato 0:f782d9c66c49 910 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
dkato 0:f782d9c66c49 911 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
dkato 0:f782d9c66c49 912
dkato 0:f782d9c66c49 913 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
dkato 0:f782d9c66c49 914 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
dkato 0:f782d9c66c49 915
dkato 0:f782d9c66c49 916 /*@}*/ /* end of group CMSIS_DWT */
dkato 0:f782d9c66c49 917
dkato 0:f782d9c66c49 918
dkato 0:f782d9c66c49 919 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 920 \defgroup CMSIS_TPI Trace Port Interface (TPI)
dkato 0:f782d9c66c49 921 \brief Type definitions for the Trace Port Interface (TPI)
dkato 0:f782d9c66c49 922 @{
dkato 0:f782d9c66c49 923 */
dkato 0:f782d9c66c49 924
dkato 0:f782d9c66c49 925 /** \brief Structure type to access the Trace Port Interface Register (TPI).
dkato 0:f782d9c66c49 926 */
dkato 0:f782d9c66c49 927 typedef struct
dkato 0:f782d9c66c49 928 {
dkato 0:f782d9c66c49 929 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
dkato 0:f782d9c66c49 930 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
dkato 0:f782d9c66c49 931 uint32_t RESERVED0[2];
dkato 0:f782d9c66c49 932 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
dkato 0:f782d9c66c49 933 uint32_t RESERVED1[55];
dkato 0:f782d9c66c49 934 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
dkato 0:f782d9c66c49 935 uint32_t RESERVED2[131];
dkato 0:f782d9c66c49 936 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
dkato 0:f782d9c66c49 937 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
dkato 0:f782d9c66c49 938 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
dkato 0:f782d9c66c49 939 uint32_t RESERVED3[759];
dkato 0:f782d9c66c49 940 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
dkato 0:f782d9c66c49 941 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
dkato 0:f782d9c66c49 942 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
dkato 0:f782d9c66c49 943 uint32_t RESERVED4[1];
dkato 0:f782d9c66c49 944 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
dkato 0:f782d9c66c49 945 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
dkato 0:f782d9c66c49 946 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
dkato 0:f782d9c66c49 947 uint32_t RESERVED5[39];
dkato 0:f782d9c66c49 948 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
dkato 0:f782d9c66c49 949 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
dkato 0:f782d9c66c49 950 uint32_t RESERVED7[8];
dkato 0:f782d9c66c49 951 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
dkato 0:f782d9c66c49 952 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
dkato 0:f782d9c66c49 953 } TPI_Type;
dkato 0:f782d9c66c49 954
dkato 0:f782d9c66c49 955 /* TPI Asynchronous Clock Prescaler Register Definitions */
dkato 0:f782d9c66c49 956 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
dkato 0:f782d9c66c49 957 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
dkato 0:f782d9c66c49 958
dkato 0:f782d9c66c49 959 /* TPI Selected Pin Protocol Register Definitions */
dkato 0:f782d9c66c49 960 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
dkato 0:f782d9c66c49 961 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
dkato 0:f782d9c66c49 962
dkato 0:f782d9c66c49 963 /* TPI Formatter and Flush Status Register Definitions */
dkato 0:f782d9c66c49 964 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
dkato 0:f782d9c66c49 965 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
dkato 0:f782d9c66c49 966
dkato 0:f782d9c66c49 967 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
dkato 0:f782d9c66c49 968 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
dkato 0:f782d9c66c49 969
dkato 0:f782d9c66c49 970 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
dkato 0:f782d9c66c49 971 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
dkato 0:f782d9c66c49 972
dkato 0:f782d9c66c49 973 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
dkato 0:f782d9c66c49 974 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
dkato 0:f782d9c66c49 975
dkato 0:f782d9c66c49 976 /* TPI Formatter and Flush Control Register Definitions */
dkato 0:f782d9c66c49 977 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
dkato 0:f782d9c66c49 978 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
dkato 0:f782d9c66c49 979
dkato 0:f782d9c66c49 980 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
dkato 0:f782d9c66c49 981 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
dkato 0:f782d9c66c49 982
dkato 0:f782d9c66c49 983 /* TPI TRIGGER Register Definitions */
dkato 0:f782d9c66c49 984 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
dkato 0:f782d9c66c49 985 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
dkato 0:f782d9c66c49 986
dkato 0:f782d9c66c49 987 /* TPI Integration ETM Data Register Definitions (FIFO0) */
dkato 0:f782d9c66c49 988 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
dkato 0:f782d9c66c49 989 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
dkato 0:f782d9c66c49 990
dkato 0:f782d9c66c49 991 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
dkato 0:f782d9c66c49 992 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
dkato 0:f782d9c66c49 993
dkato 0:f782d9c66c49 994 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
dkato 0:f782d9c66c49 995 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
dkato 0:f782d9c66c49 996
dkato 0:f782d9c66c49 997 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
dkato 0:f782d9c66c49 998 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
dkato 0:f782d9c66c49 999
dkato 0:f782d9c66c49 1000 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
dkato 0:f782d9c66c49 1001 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
dkato 0:f782d9c66c49 1002
dkato 0:f782d9c66c49 1003 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
dkato 0:f782d9c66c49 1004 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
dkato 0:f782d9c66c49 1005
dkato 0:f782d9c66c49 1006 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
dkato 0:f782d9c66c49 1007 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
dkato 0:f782d9c66c49 1008
dkato 0:f782d9c66c49 1009 /* TPI ITATBCTR2 Register Definitions */
dkato 0:f782d9c66c49 1010 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
dkato 0:f782d9c66c49 1011 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
dkato 0:f782d9c66c49 1012
dkato 0:f782d9c66c49 1013 /* TPI Integration ITM Data Register Definitions (FIFO1) */
dkato 0:f782d9c66c49 1014 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
dkato 0:f782d9c66c49 1015 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
dkato 0:f782d9c66c49 1016
dkato 0:f782d9c66c49 1017 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
dkato 0:f782d9c66c49 1018 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
dkato 0:f782d9c66c49 1019
dkato 0:f782d9c66c49 1020 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
dkato 0:f782d9c66c49 1021 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
dkato 0:f782d9c66c49 1022
dkato 0:f782d9c66c49 1023 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
dkato 0:f782d9c66c49 1024 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
dkato 0:f782d9c66c49 1025
dkato 0:f782d9c66c49 1026 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
dkato 0:f782d9c66c49 1027 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
dkato 0:f782d9c66c49 1028
dkato 0:f782d9c66c49 1029 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
dkato 0:f782d9c66c49 1030 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
dkato 0:f782d9c66c49 1031
dkato 0:f782d9c66c49 1032 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
dkato 0:f782d9c66c49 1033 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
dkato 0:f782d9c66c49 1034
dkato 0:f782d9c66c49 1035 /* TPI ITATBCTR0 Register Definitions */
dkato 0:f782d9c66c49 1036 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
dkato 0:f782d9c66c49 1037 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
dkato 0:f782d9c66c49 1038
dkato 0:f782d9c66c49 1039 /* TPI Integration Mode Control Register Definitions */
dkato 0:f782d9c66c49 1040 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
dkato 0:f782d9c66c49 1041 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
dkato 0:f782d9c66c49 1042
dkato 0:f782d9c66c49 1043 /* TPI DEVID Register Definitions */
dkato 0:f782d9c66c49 1044 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
dkato 0:f782d9c66c49 1045 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
dkato 0:f782d9c66c49 1046
dkato 0:f782d9c66c49 1047 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
dkato 0:f782d9c66c49 1048 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
dkato 0:f782d9c66c49 1049
dkato 0:f782d9c66c49 1050 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
dkato 0:f782d9c66c49 1051 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
dkato 0:f782d9c66c49 1052
dkato 0:f782d9c66c49 1053 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
dkato 0:f782d9c66c49 1054 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
dkato 0:f782d9c66c49 1055
dkato 0:f782d9c66c49 1056 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
dkato 0:f782d9c66c49 1057 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
dkato 0:f782d9c66c49 1058
dkato 0:f782d9c66c49 1059 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
dkato 0:f782d9c66c49 1060 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
dkato 0:f782d9c66c49 1061
dkato 0:f782d9c66c49 1062 /* TPI DEVTYPE Register Definitions */
dkato 0:f782d9c66c49 1063 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
dkato 0:f782d9c66c49 1064 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
dkato 0:f782d9c66c49 1065
dkato 0:f782d9c66c49 1066 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
dkato 0:f782d9c66c49 1067 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
dkato 0:f782d9c66c49 1068
dkato 0:f782d9c66c49 1069 /*@}*/ /* end of group CMSIS_TPI */
dkato 0:f782d9c66c49 1070
dkato 0:f782d9c66c49 1071
dkato 0:f782d9c66c49 1072 #if (__MPU_PRESENT == 1)
dkato 0:f782d9c66c49 1073 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 1074 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
dkato 0:f782d9c66c49 1075 \brief Type definitions for the Memory Protection Unit (MPU)
dkato 0:f782d9c66c49 1076 @{
dkato 0:f782d9c66c49 1077 */
dkato 0:f782d9c66c49 1078
dkato 0:f782d9c66c49 1079 /** \brief Structure type to access the Memory Protection Unit (MPU).
dkato 0:f782d9c66c49 1080 */
dkato 0:f782d9c66c49 1081 typedef struct
dkato 0:f782d9c66c49 1082 {
dkato 0:f782d9c66c49 1083 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
dkato 0:f782d9c66c49 1084 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
dkato 0:f782d9c66c49 1085 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
dkato 0:f782d9c66c49 1086 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
dkato 0:f782d9c66c49 1087 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
dkato 0:f782d9c66c49 1088 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
dkato 0:f782d9c66c49 1089 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
dkato 0:f782d9c66c49 1090 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
dkato 0:f782d9c66c49 1091 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
dkato 0:f782d9c66c49 1092 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
dkato 0:f782d9c66c49 1093 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
dkato 0:f782d9c66c49 1094 } MPU_Type;
dkato 0:f782d9c66c49 1095
dkato 0:f782d9c66c49 1096 /* MPU Type Register */
dkato 0:f782d9c66c49 1097 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
dkato 0:f782d9c66c49 1098 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
dkato 0:f782d9c66c49 1099
dkato 0:f782d9c66c49 1100 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
dkato 0:f782d9c66c49 1101 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
dkato 0:f782d9c66c49 1102
dkato 0:f782d9c66c49 1103 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
dkato 0:f782d9c66c49 1104 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
dkato 0:f782d9c66c49 1105
dkato 0:f782d9c66c49 1106 /* MPU Control Register */
dkato 0:f782d9c66c49 1107 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
dkato 0:f782d9c66c49 1108 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
dkato 0:f782d9c66c49 1109
dkato 0:f782d9c66c49 1110 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
dkato 0:f782d9c66c49 1111 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
dkato 0:f782d9c66c49 1112
dkato 0:f782d9c66c49 1113 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
dkato 0:f782d9c66c49 1114 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
dkato 0:f782d9c66c49 1115
dkato 0:f782d9c66c49 1116 /* MPU Region Number Register */
dkato 0:f782d9c66c49 1117 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
dkato 0:f782d9c66c49 1118 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
dkato 0:f782d9c66c49 1119
dkato 0:f782d9c66c49 1120 /* MPU Region Base Address Register */
dkato 0:f782d9c66c49 1121 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
dkato 0:f782d9c66c49 1122 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
dkato 0:f782d9c66c49 1123
dkato 0:f782d9c66c49 1124 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
dkato 0:f782d9c66c49 1125 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
dkato 0:f782d9c66c49 1126
dkato 0:f782d9c66c49 1127 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
dkato 0:f782d9c66c49 1128 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
dkato 0:f782d9c66c49 1129
dkato 0:f782d9c66c49 1130 /* MPU Region Attribute and Size Register */
dkato 0:f782d9c66c49 1131 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
dkato 0:f782d9c66c49 1132 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
dkato 0:f782d9c66c49 1133
dkato 0:f782d9c66c49 1134 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
dkato 0:f782d9c66c49 1135 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
dkato 0:f782d9c66c49 1136
dkato 0:f782d9c66c49 1137 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
dkato 0:f782d9c66c49 1138 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
dkato 0:f782d9c66c49 1139
dkato 0:f782d9c66c49 1140 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
dkato 0:f782d9c66c49 1141 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
dkato 0:f782d9c66c49 1142
dkato 0:f782d9c66c49 1143 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
dkato 0:f782d9c66c49 1144 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
dkato 0:f782d9c66c49 1145
dkato 0:f782d9c66c49 1146 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
dkato 0:f782d9c66c49 1147 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
dkato 0:f782d9c66c49 1148
dkato 0:f782d9c66c49 1149 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
dkato 0:f782d9c66c49 1150 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
dkato 0:f782d9c66c49 1151
dkato 0:f782d9c66c49 1152 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
dkato 0:f782d9c66c49 1153 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
dkato 0:f782d9c66c49 1154
dkato 0:f782d9c66c49 1155 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
dkato 0:f782d9c66c49 1156 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
dkato 0:f782d9c66c49 1157
dkato 0:f782d9c66c49 1158 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
dkato 0:f782d9c66c49 1159 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
dkato 0:f782d9c66c49 1160
dkato 0:f782d9c66c49 1161 /*@} end of group CMSIS_MPU */
dkato 0:f782d9c66c49 1162 #endif
dkato 0:f782d9c66c49 1163
dkato 0:f782d9c66c49 1164
dkato 0:f782d9c66c49 1165 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 1166 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
dkato 0:f782d9c66c49 1167 \brief Type definitions for the Core Debug Registers
dkato 0:f782d9c66c49 1168 @{
dkato 0:f782d9c66c49 1169 */
dkato 0:f782d9c66c49 1170
dkato 0:f782d9c66c49 1171 /** \brief Structure type to access the Core Debug Register (CoreDebug).
dkato 0:f782d9c66c49 1172 */
dkato 0:f782d9c66c49 1173 typedef struct
dkato 0:f782d9c66c49 1174 {
dkato 0:f782d9c66c49 1175 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
dkato 0:f782d9c66c49 1176 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
dkato 0:f782d9c66c49 1177 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
dkato 0:f782d9c66c49 1178 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
dkato 0:f782d9c66c49 1179 } CoreDebug_Type;
dkato 0:f782d9c66c49 1180
dkato 0:f782d9c66c49 1181 /* Debug Halting Control and Status Register */
dkato 0:f782d9c66c49 1182 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
dkato 0:f782d9c66c49 1183 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
dkato 0:f782d9c66c49 1184
dkato 0:f782d9c66c49 1185 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
dkato 0:f782d9c66c49 1186 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
dkato 0:f782d9c66c49 1187
dkato 0:f782d9c66c49 1188 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
dkato 0:f782d9c66c49 1189 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
dkato 0:f782d9c66c49 1190
dkato 0:f782d9c66c49 1191 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
dkato 0:f782d9c66c49 1192 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
dkato 0:f782d9c66c49 1193
dkato 0:f782d9c66c49 1194 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
dkato 0:f782d9c66c49 1195 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
dkato 0:f782d9c66c49 1196
dkato 0:f782d9c66c49 1197 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
dkato 0:f782d9c66c49 1198 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
dkato 0:f782d9c66c49 1199
dkato 0:f782d9c66c49 1200 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
dkato 0:f782d9c66c49 1201 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
dkato 0:f782d9c66c49 1202
dkato 0:f782d9c66c49 1203 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
dkato 0:f782d9c66c49 1204 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
dkato 0:f782d9c66c49 1205
dkato 0:f782d9c66c49 1206 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
dkato 0:f782d9c66c49 1207 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
dkato 0:f782d9c66c49 1208
dkato 0:f782d9c66c49 1209 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
dkato 0:f782d9c66c49 1210 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
dkato 0:f782d9c66c49 1211
dkato 0:f782d9c66c49 1212 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
dkato 0:f782d9c66c49 1213 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
dkato 0:f782d9c66c49 1214
dkato 0:f782d9c66c49 1215 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
dkato 0:f782d9c66c49 1216 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
dkato 0:f782d9c66c49 1217
dkato 0:f782d9c66c49 1218 /* Debug Core Register Selector Register */
dkato 0:f782d9c66c49 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
dkato 0:f782d9c66c49 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
dkato 0:f782d9c66c49 1221
dkato 0:f782d9c66c49 1222 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
dkato 0:f782d9c66c49 1223 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
dkato 0:f782d9c66c49 1224
dkato 0:f782d9c66c49 1225 /* Debug Exception and Monitor Control Register */
dkato 0:f782d9c66c49 1226 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
dkato 0:f782d9c66c49 1227 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
dkato 0:f782d9c66c49 1228
dkato 0:f782d9c66c49 1229 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
dkato 0:f782d9c66c49 1230 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
dkato 0:f782d9c66c49 1231
dkato 0:f782d9c66c49 1232 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
dkato 0:f782d9c66c49 1233 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
dkato 0:f782d9c66c49 1234
dkato 0:f782d9c66c49 1235 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
dkato 0:f782d9c66c49 1236 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
dkato 0:f782d9c66c49 1237
dkato 0:f782d9c66c49 1238 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
dkato 0:f782d9c66c49 1239 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
dkato 0:f782d9c66c49 1240
dkato 0:f782d9c66c49 1241 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
dkato 0:f782d9c66c49 1242 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
dkato 0:f782d9c66c49 1243
dkato 0:f782d9c66c49 1244 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
dkato 0:f782d9c66c49 1245 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
dkato 0:f782d9c66c49 1246
dkato 0:f782d9c66c49 1247 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
dkato 0:f782d9c66c49 1248 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
dkato 0:f782d9c66c49 1249
dkato 0:f782d9c66c49 1250 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
dkato 0:f782d9c66c49 1251 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
dkato 0:f782d9c66c49 1252
dkato 0:f782d9c66c49 1253 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
dkato 0:f782d9c66c49 1254 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
dkato 0:f782d9c66c49 1255
dkato 0:f782d9c66c49 1256 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
dkato 0:f782d9c66c49 1257 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
dkato 0:f782d9c66c49 1258
dkato 0:f782d9c66c49 1259 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
dkato 0:f782d9c66c49 1260 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
dkato 0:f782d9c66c49 1261
dkato 0:f782d9c66c49 1262 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
dkato 0:f782d9c66c49 1263 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
dkato 0:f782d9c66c49 1264
dkato 0:f782d9c66c49 1265 /*@} end of group CMSIS_CoreDebug */
dkato 0:f782d9c66c49 1266
dkato 0:f782d9c66c49 1267
dkato 0:f782d9c66c49 1268 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 1269 \defgroup CMSIS_core_base Core Definitions
dkato 0:f782d9c66c49 1270 \brief Definitions for base addresses, unions, and structures.
dkato 0:f782d9c66c49 1271 @{
dkato 0:f782d9c66c49 1272 */
dkato 0:f782d9c66c49 1273
dkato 0:f782d9c66c49 1274 /* Memory mapping of Cortex-M3 Hardware */
dkato 0:f782d9c66c49 1275 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
dkato 0:f782d9c66c49 1276 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
dkato 0:f782d9c66c49 1277 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
dkato 0:f782d9c66c49 1278 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
dkato 0:f782d9c66c49 1279 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
dkato 0:f782d9c66c49 1280 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
dkato 0:f782d9c66c49 1281 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
dkato 0:f782d9c66c49 1282 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
dkato 0:f782d9c66c49 1283
dkato 0:f782d9c66c49 1284 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
dkato 0:f782d9c66c49 1285 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
dkato 0:f782d9c66c49 1286 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
dkato 0:f782d9c66c49 1287 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
dkato 0:f782d9c66c49 1288 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
dkato 0:f782d9c66c49 1289 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
dkato 0:f782d9c66c49 1290 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
dkato 0:f782d9c66c49 1291 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
dkato 0:f782d9c66c49 1292
dkato 0:f782d9c66c49 1293 #if (__MPU_PRESENT == 1)
dkato 0:f782d9c66c49 1294 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
dkato 0:f782d9c66c49 1295 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
dkato 0:f782d9c66c49 1296 #endif
dkato 0:f782d9c66c49 1297
dkato 0:f782d9c66c49 1298 /*@} */
dkato 0:f782d9c66c49 1299
dkato 0:f782d9c66c49 1300
dkato 0:f782d9c66c49 1301
dkato 0:f782d9c66c49 1302 /*******************************************************************************
dkato 0:f782d9c66c49 1303 * Hardware Abstraction Layer
dkato 0:f782d9c66c49 1304 Core Function Interface contains:
dkato 0:f782d9c66c49 1305 - Core NVIC Functions
dkato 0:f782d9c66c49 1306 - Core SysTick Functions
dkato 0:f782d9c66c49 1307 - Core Debug Functions
dkato 0:f782d9c66c49 1308 - Core Register Access Functions
dkato 0:f782d9c66c49 1309 ******************************************************************************/
dkato 0:f782d9c66c49 1310 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
dkato 0:f782d9c66c49 1311 */
dkato 0:f782d9c66c49 1312
dkato 0:f782d9c66c49 1313
dkato 0:f782d9c66c49 1314
dkato 0:f782d9c66c49 1315 /* ########################## NVIC functions #################################### */
dkato 0:f782d9c66c49 1316 /** \ingroup CMSIS_Core_FunctionInterface
dkato 0:f782d9c66c49 1317 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
dkato 0:f782d9c66c49 1318 \brief Functions that manage interrupts and exceptions via the NVIC.
dkato 0:f782d9c66c49 1319 @{
dkato 0:f782d9c66c49 1320 */
dkato 0:f782d9c66c49 1321
dkato 0:f782d9c66c49 1322 /** \brief Set Priority Grouping
dkato 0:f782d9c66c49 1323
dkato 0:f782d9c66c49 1324 The function sets the priority grouping field using the required unlock sequence.
dkato 0:f782d9c66c49 1325 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
dkato 0:f782d9c66c49 1326 Only values from 0..7 are used.
dkato 0:f782d9c66c49 1327 In case of a conflict between priority grouping and available
dkato 0:f782d9c66c49 1328 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
dkato 0:f782d9c66c49 1329
dkato 0:f782d9c66c49 1330 \param [in] PriorityGroup Priority grouping field.
dkato 0:f782d9c66c49 1331 */
dkato 0:f782d9c66c49 1332 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
dkato 0:f782d9c66c49 1333 {
dkato 0:f782d9c66c49 1334 uint32_t reg_value;
dkato 0:f782d9c66c49 1335 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
dkato 0:f782d9c66c49 1336
dkato 0:f782d9c66c49 1337 reg_value = SCB->AIRCR; /* read old register configuration */
dkato 0:f782d9c66c49 1338 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
dkato 0:f782d9c66c49 1339 reg_value = (reg_value |
dkato 0:f782d9c66c49 1340 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
dkato 0:f782d9c66c49 1341 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
dkato 0:f782d9c66c49 1342 SCB->AIRCR = reg_value;
dkato 0:f782d9c66c49 1343 }
dkato 0:f782d9c66c49 1344
dkato 0:f782d9c66c49 1345
dkato 0:f782d9c66c49 1346 /** \brief Get Priority Grouping
dkato 0:f782d9c66c49 1347
dkato 0:f782d9c66c49 1348 The function reads the priority grouping field from the NVIC Interrupt Controller.
dkato 0:f782d9c66c49 1349
dkato 0:f782d9c66c49 1350 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
dkato 0:f782d9c66c49 1351 */
dkato 0:f782d9c66c49 1352 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
dkato 0:f782d9c66c49 1353 {
dkato 0:f782d9c66c49 1354 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
dkato 0:f782d9c66c49 1355 }
dkato 0:f782d9c66c49 1356
dkato 0:f782d9c66c49 1357
dkato 0:f782d9c66c49 1358 /** \brief Enable External Interrupt
dkato 0:f782d9c66c49 1359
dkato 0:f782d9c66c49 1360 The function enables a device-specific interrupt in the NVIC interrupt controller.
dkato 0:f782d9c66c49 1361
dkato 0:f782d9c66c49 1362 \param [in] IRQn External interrupt number. Value cannot be negative.
dkato 0:f782d9c66c49 1363 */
dkato 0:f782d9c66c49 1364 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
dkato 0:f782d9c66c49 1365 {
dkato 0:f782d9c66c49 1366 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
dkato 0:f782d9c66c49 1367 }
dkato 0:f782d9c66c49 1368
dkato 0:f782d9c66c49 1369
dkato 0:f782d9c66c49 1370 /** \brief Disable External Interrupt
dkato 0:f782d9c66c49 1371
dkato 0:f782d9c66c49 1372 The function disables a device-specific interrupt in the NVIC interrupt controller.
dkato 0:f782d9c66c49 1373
dkato 0:f782d9c66c49 1374 \param [in] IRQn External interrupt number. Value cannot be negative.
dkato 0:f782d9c66c49 1375 */
dkato 0:f782d9c66c49 1376 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
dkato 0:f782d9c66c49 1377 {
dkato 0:f782d9c66c49 1378 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
dkato 0:f782d9c66c49 1379 __DSB();
dkato 0:f782d9c66c49 1380 __ISB();
dkato 0:f782d9c66c49 1381 }
dkato 0:f782d9c66c49 1382
dkato 0:f782d9c66c49 1383
dkato 0:f782d9c66c49 1384 /** \brief Get Pending Interrupt
dkato 0:f782d9c66c49 1385
dkato 0:f782d9c66c49 1386 The function reads the pending register in the NVIC and returns the pending bit
dkato 0:f782d9c66c49 1387 for the specified interrupt.
dkato 0:f782d9c66c49 1388
dkato 0:f782d9c66c49 1389 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 1390
dkato 0:f782d9c66c49 1391 \return 0 Interrupt status is not pending.
dkato 0:f782d9c66c49 1392 \return 1 Interrupt status is pending.
dkato 0:f782d9c66c49 1393 */
dkato 0:f782d9c66c49 1394 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
dkato 0:f782d9c66c49 1395 {
dkato 0:f782d9c66c49 1396 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
dkato 0:f782d9c66c49 1397 }
dkato 0:f782d9c66c49 1398
dkato 0:f782d9c66c49 1399
dkato 0:f782d9c66c49 1400 /** \brief Set Pending Interrupt
dkato 0:f782d9c66c49 1401
dkato 0:f782d9c66c49 1402 The function sets the pending bit of an external interrupt.
dkato 0:f782d9c66c49 1403
dkato 0:f782d9c66c49 1404 \param [in] IRQn Interrupt number. Value cannot be negative.
dkato 0:f782d9c66c49 1405 */
dkato 0:f782d9c66c49 1406 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
dkato 0:f782d9c66c49 1407 {
dkato 0:f782d9c66c49 1408 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
dkato 0:f782d9c66c49 1409 }
dkato 0:f782d9c66c49 1410
dkato 0:f782d9c66c49 1411
dkato 0:f782d9c66c49 1412 /** \brief Clear Pending Interrupt
dkato 0:f782d9c66c49 1413
dkato 0:f782d9c66c49 1414 The function clears the pending bit of an external interrupt.
dkato 0:f782d9c66c49 1415
dkato 0:f782d9c66c49 1416 \param [in] IRQn External interrupt number. Value cannot be negative.
dkato 0:f782d9c66c49 1417 */
dkato 0:f782d9c66c49 1418 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
dkato 0:f782d9c66c49 1419 {
dkato 0:f782d9c66c49 1420 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
dkato 0:f782d9c66c49 1421 }
dkato 0:f782d9c66c49 1422
dkato 0:f782d9c66c49 1423
dkato 0:f782d9c66c49 1424 /** \brief Get Active Interrupt
dkato 0:f782d9c66c49 1425
dkato 0:f782d9c66c49 1426 The function reads the active register in NVIC and returns the active bit.
dkato 0:f782d9c66c49 1427
dkato 0:f782d9c66c49 1428 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 1429
dkato 0:f782d9c66c49 1430 \return 0 Interrupt status is not active.
dkato 0:f782d9c66c49 1431 \return 1 Interrupt status is active.
dkato 0:f782d9c66c49 1432 */
dkato 0:f782d9c66c49 1433 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
dkato 0:f782d9c66c49 1434 {
dkato 0:f782d9c66c49 1435 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
dkato 0:f782d9c66c49 1436 }
dkato 0:f782d9c66c49 1437
dkato 0:f782d9c66c49 1438
dkato 0:f782d9c66c49 1439 /** \brief Set Interrupt Priority
dkato 0:f782d9c66c49 1440
dkato 0:f782d9c66c49 1441 The function sets the priority of an interrupt.
dkato 0:f782d9c66c49 1442
dkato 0:f782d9c66c49 1443 \note The priority cannot be set for every core interrupt.
dkato 0:f782d9c66c49 1444
dkato 0:f782d9c66c49 1445 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 1446 \param [in] priority Priority to set.
dkato 0:f782d9c66c49 1447 */
dkato 0:f782d9c66c49 1448 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
dkato 0:f782d9c66c49 1449 {
dkato 0:f782d9c66c49 1450 if((int32_t)IRQn < 0) {
dkato 0:f782d9c66c49 1451 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
dkato 0:f782d9c66c49 1452 }
dkato 0:f782d9c66c49 1453 else {
dkato 0:f782d9c66c49 1454 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
dkato 0:f782d9c66c49 1455 }
dkato 0:f782d9c66c49 1456 }
dkato 0:f782d9c66c49 1457
dkato 0:f782d9c66c49 1458
dkato 0:f782d9c66c49 1459 /** \brief Get Interrupt Priority
dkato 0:f782d9c66c49 1460
dkato 0:f782d9c66c49 1461 The function reads the priority of an interrupt. The interrupt
dkato 0:f782d9c66c49 1462 number can be positive to specify an external (device specific)
dkato 0:f782d9c66c49 1463 interrupt, or negative to specify an internal (core) interrupt.
dkato 0:f782d9c66c49 1464
dkato 0:f782d9c66c49 1465
dkato 0:f782d9c66c49 1466 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 1467 \return Interrupt Priority. Value is aligned automatically to the implemented
dkato 0:f782d9c66c49 1468 priority bits of the microcontroller.
dkato 0:f782d9c66c49 1469 */
dkato 0:f782d9c66c49 1470 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
dkato 0:f782d9c66c49 1471 {
dkato 0:f782d9c66c49 1472
dkato 0:f782d9c66c49 1473 if((int32_t)IRQn < 0) {
dkato 0:f782d9c66c49 1474 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
dkato 0:f782d9c66c49 1475 }
dkato 0:f782d9c66c49 1476 else {
dkato 0:f782d9c66c49 1477 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
dkato 0:f782d9c66c49 1478 }
dkato 0:f782d9c66c49 1479 }
dkato 0:f782d9c66c49 1480
dkato 0:f782d9c66c49 1481
dkato 0:f782d9c66c49 1482 /** \brief Encode Priority
dkato 0:f782d9c66c49 1483
dkato 0:f782d9c66c49 1484 The function encodes the priority for an interrupt with the given priority group,
dkato 0:f782d9c66c49 1485 preemptive priority value, and subpriority value.
dkato 0:f782d9c66c49 1486 In case of a conflict between priority grouping and available
dkato 0:f782d9c66c49 1487 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
dkato 0:f782d9c66c49 1488
dkato 0:f782d9c66c49 1489 \param [in] PriorityGroup Used priority group.
dkato 0:f782d9c66c49 1490 \param [in] PreemptPriority Preemptive priority value (starting from 0).
dkato 0:f782d9c66c49 1491 \param [in] SubPriority Subpriority value (starting from 0).
dkato 0:f782d9c66c49 1492 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
dkato 0:f782d9c66c49 1493 */
dkato 0:f782d9c66c49 1494 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
dkato 0:f782d9c66c49 1495 {
dkato 0:f782d9c66c49 1496 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
dkato 0:f782d9c66c49 1497 uint32_t PreemptPriorityBits;
dkato 0:f782d9c66c49 1498 uint32_t SubPriorityBits;
dkato 0:f782d9c66c49 1499
dkato 0:f782d9c66c49 1500 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
dkato 0:f782d9c66c49 1501 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
dkato 0:f782d9c66c49 1502
dkato 0:f782d9c66c49 1503 return (
dkato 0:f782d9c66c49 1504 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
dkato 0:f782d9c66c49 1505 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
dkato 0:f782d9c66c49 1506 );
dkato 0:f782d9c66c49 1507 }
dkato 0:f782d9c66c49 1508
dkato 0:f782d9c66c49 1509
dkato 0:f782d9c66c49 1510 /** \brief Decode Priority
dkato 0:f782d9c66c49 1511
dkato 0:f782d9c66c49 1512 The function decodes an interrupt priority value with a given priority group to
dkato 0:f782d9c66c49 1513 preemptive priority value and subpriority value.
dkato 0:f782d9c66c49 1514 In case of a conflict between priority grouping and available
dkato 0:f782d9c66c49 1515 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
dkato 0:f782d9c66c49 1516
dkato 0:f782d9c66c49 1517 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
dkato 0:f782d9c66c49 1518 \param [in] PriorityGroup Used priority group.
dkato 0:f782d9c66c49 1519 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
dkato 0:f782d9c66c49 1520 \param [out] pSubPriority Subpriority value (starting from 0).
dkato 0:f782d9c66c49 1521 */
dkato 0:f782d9c66c49 1522 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
dkato 0:f782d9c66c49 1523 {
dkato 0:f782d9c66c49 1524 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
dkato 0:f782d9c66c49 1525 uint32_t PreemptPriorityBits;
dkato 0:f782d9c66c49 1526 uint32_t SubPriorityBits;
dkato 0:f782d9c66c49 1527
dkato 0:f782d9c66c49 1528 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
dkato 0:f782d9c66c49 1529 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
dkato 0:f782d9c66c49 1530
dkato 0:f782d9c66c49 1531 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
dkato 0:f782d9c66c49 1532 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
dkato 0:f782d9c66c49 1533 }
dkato 0:f782d9c66c49 1534
dkato 0:f782d9c66c49 1535
dkato 0:f782d9c66c49 1536 /** \brief System Reset
dkato 0:f782d9c66c49 1537
dkato 0:f782d9c66c49 1538 The function initiates a system reset request to reset the MCU.
dkato 0:f782d9c66c49 1539 */
dkato 0:f782d9c66c49 1540 __STATIC_INLINE void NVIC_SystemReset(void)
dkato 0:f782d9c66c49 1541 {
dkato 0:f782d9c66c49 1542 __DSB(); /* Ensure all outstanding memory accesses included
dkato 0:f782d9c66c49 1543 buffered write are completed before reset */
dkato 0:f782d9c66c49 1544 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
dkato 0:f782d9c66c49 1545 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
dkato 0:f782d9c66c49 1546 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
dkato 0:f782d9c66c49 1547 __DSB(); /* Ensure completion of memory access */
dkato 0:f782d9c66c49 1548 while(1) { __NOP(); } /* wait until reset */
dkato 0:f782d9c66c49 1549 }
dkato 0:f782d9c66c49 1550
dkato 0:f782d9c66c49 1551 /*@} end of CMSIS_Core_NVICFunctions */
dkato 0:f782d9c66c49 1552
dkato 0:f782d9c66c49 1553
dkato 0:f782d9c66c49 1554
dkato 0:f782d9c66c49 1555 /* ################################## SysTick function ############################################ */
dkato 0:f782d9c66c49 1556 /** \ingroup CMSIS_Core_FunctionInterface
dkato 0:f782d9c66c49 1557 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
dkato 0:f782d9c66c49 1558 \brief Functions that configure the System.
dkato 0:f782d9c66c49 1559 @{
dkato 0:f782d9c66c49 1560 */
dkato 0:f782d9c66c49 1561
dkato 0:f782d9c66c49 1562 #if (__Vendor_SysTickConfig == 0)
dkato 0:f782d9c66c49 1563
dkato 0:f782d9c66c49 1564 /** \brief System Tick Configuration
dkato 0:f782d9c66c49 1565
dkato 0:f782d9c66c49 1566 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
dkato 0:f782d9c66c49 1567 Counter is in free running mode to generate periodic interrupts.
dkato 0:f782d9c66c49 1568
dkato 0:f782d9c66c49 1569 \param [in] ticks Number of ticks between two interrupts.
dkato 0:f782d9c66c49 1570
dkato 0:f782d9c66c49 1571 \return 0 Function succeeded.
dkato 0:f782d9c66c49 1572 \return 1 Function failed.
dkato 0:f782d9c66c49 1573
dkato 0:f782d9c66c49 1574 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
dkato 0:f782d9c66c49 1575 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
dkato 0:f782d9c66c49 1576 must contain a vendor-specific implementation of this function.
dkato 0:f782d9c66c49 1577
dkato 0:f782d9c66c49 1578 */
dkato 0:f782d9c66c49 1579 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
dkato 0:f782d9c66c49 1580 {
dkato 0:f782d9c66c49 1581 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
dkato 0:f782d9c66c49 1582
dkato 0:f782d9c66c49 1583 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
dkato 0:f782d9c66c49 1584 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
dkato 0:f782d9c66c49 1585 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
dkato 0:f782d9c66c49 1586 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
dkato 0:f782d9c66c49 1587 SysTick_CTRL_TICKINT_Msk |
dkato 0:f782d9c66c49 1588 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
dkato 0:f782d9c66c49 1589 return (0UL); /* Function successful */
dkato 0:f782d9c66c49 1590 }
dkato 0:f782d9c66c49 1591
dkato 0:f782d9c66c49 1592 #endif
dkato 0:f782d9c66c49 1593
dkato 0:f782d9c66c49 1594 /*@} end of CMSIS_Core_SysTickFunctions */
dkato 0:f782d9c66c49 1595
dkato 0:f782d9c66c49 1596
dkato 0:f782d9c66c49 1597
dkato 0:f782d9c66c49 1598 /* ##################################### Debug In/Output function ########################################### */
dkato 0:f782d9c66c49 1599 /** \ingroup CMSIS_Core_FunctionInterface
dkato 0:f782d9c66c49 1600 \defgroup CMSIS_core_DebugFunctions ITM Functions
dkato 0:f782d9c66c49 1601 \brief Functions that access the ITM debug interface.
dkato 0:f782d9c66c49 1602 @{
dkato 0:f782d9c66c49 1603 */
dkato 0:f782d9c66c49 1604
dkato 0:f782d9c66c49 1605 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
dkato 0:f782d9c66c49 1606 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
dkato 0:f782d9c66c49 1607
dkato 0:f782d9c66c49 1608
dkato 0:f782d9c66c49 1609 /** \brief ITM Send Character
dkato 0:f782d9c66c49 1610
dkato 0:f782d9c66c49 1611 The function transmits a character via the ITM channel 0, and
dkato 0:f782d9c66c49 1612 \li Just returns when no debugger is connected that has booked the output.
dkato 0:f782d9c66c49 1613 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
dkato 0:f782d9c66c49 1614
dkato 0:f782d9c66c49 1615 \param [in] ch Character to transmit.
dkato 0:f782d9c66c49 1616
dkato 0:f782d9c66c49 1617 \returns Character to transmit.
dkato 0:f782d9c66c49 1618 */
dkato 0:f782d9c66c49 1619 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
dkato 0:f782d9c66c49 1620 {
dkato 0:f782d9c66c49 1621 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
dkato 0:f782d9c66c49 1622 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
dkato 0:f782d9c66c49 1623 {
dkato 0:f782d9c66c49 1624 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
dkato 0:f782d9c66c49 1625 ITM->PORT[0].u8 = (uint8_t)ch;
dkato 0:f782d9c66c49 1626 }
dkato 0:f782d9c66c49 1627 return (ch);
dkato 0:f782d9c66c49 1628 }
dkato 0:f782d9c66c49 1629
dkato 0:f782d9c66c49 1630
dkato 0:f782d9c66c49 1631 /** \brief ITM Receive Character
dkato 0:f782d9c66c49 1632
dkato 0:f782d9c66c49 1633 The function inputs a character via the external variable \ref ITM_RxBuffer.
dkato 0:f782d9c66c49 1634
dkato 0:f782d9c66c49 1635 \return Received character.
dkato 0:f782d9c66c49 1636 \return -1 No character pending.
dkato 0:f782d9c66c49 1637 */
dkato 0:f782d9c66c49 1638 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
dkato 0:f782d9c66c49 1639 int32_t ch = -1; /* no character available */
dkato 0:f782d9c66c49 1640
dkato 0:f782d9c66c49 1641 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
dkato 0:f782d9c66c49 1642 ch = ITM_RxBuffer;
dkato 0:f782d9c66c49 1643 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
dkato 0:f782d9c66c49 1644 }
dkato 0:f782d9c66c49 1645
dkato 0:f782d9c66c49 1646 return (ch);
dkato 0:f782d9c66c49 1647 }
dkato 0:f782d9c66c49 1648
dkato 0:f782d9c66c49 1649
dkato 0:f782d9c66c49 1650 /** \brief ITM Check Character
dkato 0:f782d9c66c49 1651
dkato 0:f782d9c66c49 1652 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
dkato 0:f782d9c66c49 1653
dkato 0:f782d9c66c49 1654 \return 0 No character available.
dkato 0:f782d9c66c49 1655 \return 1 Character available.
dkato 0:f782d9c66c49 1656 */
dkato 0:f782d9c66c49 1657 __STATIC_INLINE int32_t ITM_CheckChar (void) {
dkato 0:f782d9c66c49 1658
dkato 0:f782d9c66c49 1659 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
dkato 0:f782d9c66c49 1660 return (0); /* no character available */
dkato 0:f782d9c66c49 1661 } else {
dkato 0:f782d9c66c49 1662 return (1); /* character available */
dkato 0:f782d9c66c49 1663 }
dkato 0:f782d9c66c49 1664 }
dkato 0:f782d9c66c49 1665
dkato 0:f782d9c66c49 1666 /*@} end of CMSIS_core_DebugFunctions */
dkato 0:f782d9c66c49 1667
dkato 0:f782d9c66c49 1668
dkato 0:f782d9c66c49 1669
dkato 0:f782d9c66c49 1670
dkato 0:f782d9c66c49 1671 #ifdef __cplusplus
dkato 0:f782d9c66c49 1672 }
dkato 0:f782d9c66c49 1673 #endif
dkato 0:f782d9c66c49 1674
dkato 0:f782d9c66c49 1675 #endif /* __CORE_SC300_H_DEPENDANT */
dkato 0:f782d9c66c49 1676
dkato 0:f782d9c66c49 1677 #endif /* __CMSIS_GENERIC */