Daiki Kato / mbed-os-lychee

mbed-os for GR-LYCHEE

Dependents:   mbed-os-example-blinky-gr-lychee GR-Boads_Camera_sample GR-Boards_Audio_Recoder GR-Boads_Camera_DisplayApp ... more

cmsis/core_cm0plus.h@0:f782d9c66c49, 2018-02-02 (annotated)

Committer:
dkato
Date:
Fri Feb 02 05:42:23 2018 +0000
Revision:
0:f782d9c66c49
mbed-os for GR-LYCHEE

Who changed what in which revision?

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dkato 0:f782d9c66c49 1 /**************************************************************************//**
dkato 0:f782d9c66c49 2 * @file core_cm0plus.h
dkato 0:f782d9c66c49 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
dkato 0:f782d9c66c49 4 * @version V4.10
dkato 0:f782d9c66c49 5 * @date 18. March 2015
dkato 0:f782d9c66c49 6 *
dkato 0:f782d9c66c49 7 * @note
dkato 0:f782d9c66c49 8 *
dkato 0:f782d9c66c49 9 ******************************************************************************/
dkato 0:f782d9c66c49 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
dkato 0:f782d9c66c49 11
dkato 0:f782d9c66c49 12 All rights reserved.
dkato 0:f782d9c66c49 13 Redistribution and use in source and binary forms, with or without
dkato 0:f782d9c66c49 14 modification, are permitted provided that the following conditions are met:
dkato 0:f782d9c66c49 15 - Redistributions of source code must retain the above copyright
dkato 0:f782d9c66c49 16 notice, this list of conditions and the following disclaimer.
dkato 0:f782d9c66c49 17 - Redistributions in binary form must reproduce the above copyright
dkato 0:f782d9c66c49 18 notice, this list of conditions and the following disclaimer in the
dkato 0:f782d9c66c49 19 documentation and/or other materials provided with the distribution.
dkato 0:f782d9c66c49 20 - Neither the name of ARM nor the names of its contributors may be used
dkato 0:f782d9c66c49 21 to endorse or promote products derived from this software without
dkato 0:f782d9c66c49 22 specific prior written permission.
dkato 0:f782d9c66c49 23 *
dkato 0:f782d9c66c49 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
dkato 0:f782d9c66c49 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
dkato 0:f782d9c66c49 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
dkato 0:f782d9c66c49 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
dkato 0:f782d9c66c49 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
dkato 0:f782d9c66c49 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
dkato 0:f782d9c66c49 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
dkato 0:f782d9c66c49 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
dkato 0:f782d9c66c49 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
dkato 0:f782d9c66c49 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
dkato 0:f782d9c66c49 34 POSSIBILITY OF SUCH DAMAGE.
dkato 0:f782d9c66c49 35 ---------------------------------------------------------------------------*/
dkato 0:f782d9c66c49 36
dkato 0:f782d9c66c49 37
dkato 0:f782d9c66c49 38 #if defined ( __ICCARM__ )
dkato 0:f782d9c66c49 39 #pragma system_include /* treat file as system include file for MISRA check */
dkato 0:f782d9c66c49 40 #endif
dkato 0:f782d9c66c49 41
dkato 0:f782d9c66c49 42 #ifndef __CORE_CM0PLUS_H_GENERIC
dkato 0:f782d9c66c49 43 #define __CORE_CM0PLUS_H_GENERIC
dkato 0:f782d9c66c49 44
dkato 0:f782d9c66c49 45 #ifdef __cplusplus
dkato 0:f782d9c66c49 46 extern "C" {
dkato 0:f782d9c66c49 47 #endif
dkato 0:f782d9c66c49 48
dkato 0:f782d9c66c49 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
dkato 0:f782d9c66c49 50 CMSIS violates the following MISRA-C:2004 rules:
dkato 0:f782d9c66c49 51
dkato 0:f782d9c66c49 52 \li Required Rule 8.5, object/function definition in header file.<br>
dkato 0:f782d9c66c49 53 Function definitions in header files are used to allow 'inlining'.
dkato 0:f782d9c66c49 54
dkato 0:f782d9c66c49 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
dkato 0:f782d9c66c49 56 Unions are used for effective representation of core registers.
dkato 0:f782d9c66c49 57
dkato 0:f782d9c66c49 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
dkato 0:f782d9c66c49 59 Function-like macros are used to allow more efficient code.
dkato 0:f782d9c66c49 60 */
dkato 0:f782d9c66c49 61
dkato 0:f782d9c66c49 62
dkato 0:f782d9c66c49 63 /*******************************************************************************
dkato 0:f782d9c66c49 64 * CMSIS definitions
dkato 0:f782d9c66c49 65 ******************************************************************************/
dkato 0:f782d9c66c49 66 /** \ingroup Cortex-M0+
dkato 0:f782d9c66c49 67 @{
dkato 0:f782d9c66c49 68 */
dkato 0:f782d9c66c49 69
dkato 0:f782d9c66c49 70 /* CMSIS CM0P definitions */
dkato 0:f782d9c66c49 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
dkato 0:f782d9c66c49 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
dkato 0:f782d9c66c49 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
dkato 0:f782d9c66c49 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
dkato 0:f782d9c66c49 75
dkato 0:f782d9c66c49 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
dkato 0:f782d9c66c49 77
dkato 0:f782d9c66c49 78
dkato 0:f782d9c66c49 79 #if defined ( __CC_ARM )
dkato 0:f782d9c66c49 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
dkato 0:f782d9c66c49 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
dkato 0:f782d9c66c49 82 #define __STATIC_INLINE static __inline
dkato 0:f782d9c66c49 83
dkato 0:f782d9c66c49 84 #elif defined ( __GNUC__ )
dkato 0:f782d9c66c49 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
dkato 0:f782d9c66c49 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
dkato 0:f782d9c66c49 87 #define __STATIC_INLINE static inline
dkato 0:f782d9c66c49 88
dkato 0:f782d9c66c49 89 #elif defined ( __ICCARM__ )
dkato 0:f782d9c66c49 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
dkato 0:f782d9c66c49 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
dkato 0:f782d9c66c49 92 #define __STATIC_INLINE static inline
dkato 0:f782d9c66c49 93
dkato 0:f782d9c66c49 94 #elif defined ( __TMS470__ )
dkato 0:f782d9c66c49 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
dkato 0:f782d9c66c49 96 #define __STATIC_INLINE static inline
dkato 0:f782d9c66c49 97
dkato 0:f782d9c66c49 98 #elif defined ( __TASKING__ )
dkato 0:f782d9c66c49 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
dkato 0:f782d9c66c49 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
dkato 0:f782d9c66c49 101 #define __STATIC_INLINE static inline
dkato 0:f782d9c66c49 102
dkato 0:f782d9c66c49 103 #elif defined ( __CSMC__ )
dkato 0:f782d9c66c49 104 #define __packed
dkato 0:f782d9c66c49 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
dkato 0:f782d9c66c49 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
dkato 0:f782d9c66c49 107 #define __STATIC_INLINE static inline
dkato 0:f782d9c66c49 108
dkato 0:f782d9c66c49 109 #endif
dkato 0:f782d9c66c49 110
dkato 0:f782d9c66c49 111 /** __FPU_USED indicates whether an FPU is used or not.
dkato 0:f782d9c66c49 112 This core does not support an FPU at all
dkato 0:f782d9c66c49 113 */
dkato 0:f782d9c66c49 114 #define __FPU_USED 0
dkato 0:f782d9c66c49 115
dkato 0:f782d9c66c49 116 #if defined ( __CC_ARM )
dkato 0:f782d9c66c49 117 #if defined __TARGET_FPU_VFP
dkato 0:f782d9c66c49 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato 0:f782d9c66c49 119 #endif
dkato 0:f782d9c66c49 120
dkato 0:f782d9c66c49 121 #elif defined ( __GNUC__ )
dkato 0:f782d9c66c49 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
dkato 0:f782d9c66c49 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato 0:f782d9c66c49 124 #endif
dkato 0:f782d9c66c49 125
dkato 0:f782d9c66c49 126 #elif defined ( __ICCARM__ )
dkato 0:f782d9c66c49 127 #if defined __ARMVFP__
dkato 0:f782d9c66c49 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato 0:f782d9c66c49 129 #endif
dkato 0:f782d9c66c49 130
dkato 0:f782d9c66c49 131 #elif defined ( __TMS470__ )
dkato 0:f782d9c66c49 132 #if defined __TI__VFP_SUPPORT____
dkato 0:f782d9c66c49 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato 0:f782d9c66c49 134 #endif
dkato 0:f782d9c66c49 135
dkato 0:f782d9c66c49 136 #elif defined ( __TASKING__ )
dkato 0:f782d9c66c49 137 #if defined __FPU_VFP__
dkato 0:f782d9c66c49 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato 0:f782d9c66c49 139 #endif
dkato 0:f782d9c66c49 140
dkato 0:f782d9c66c49 141 #elif defined ( __CSMC__ ) /* Cosmic */
dkato 0:f782d9c66c49 142 #if ( __CSMC__ & 0x400) // FPU present for parser
dkato 0:f782d9c66c49 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato 0:f782d9c66c49 144 #endif
dkato 0:f782d9c66c49 145 #endif
dkato 0:f782d9c66c49 146
dkato 0:f782d9c66c49 147 #include <stdint.h> /* standard types definitions */
dkato 0:f782d9c66c49 148 #include <core_cmInstr.h> /* Core Instruction Access */
dkato 0:f782d9c66c49 149 #include <core_cmFunc.h> /* Core Function Access */
dkato 0:f782d9c66c49 150
dkato 0:f782d9c66c49 151 #ifdef __cplusplus
dkato 0:f782d9c66c49 152 }
dkato 0:f782d9c66c49 153 #endif
dkato 0:f782d9c66c49 154
dkato 0:f782d9c66c49 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
dkato 0:f782d9c66c49 156
dkato 0:f782d9c66c49 157 #ifndef __CMSIS_GENERIC
dkato 0:f782d9c66c49 158
dkato 0:f782d9c66c49 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
dkato 0:f782d9c66c49 160 #define __CORE_CM0PLUS_H_DEPENDANT
dkato 0:f782d9c66c49 161
dkato 0:f782d9c66c49 162 #ifdef __cplusplus
dkato 0:f782d9c66c49 163 extern "C" {
dkato 0:f782d9c66c49 164 #endif
dkato 0:f782d9c66c49 165
dkato 0:f782d9c66c49 166 /* check device defines and use defaults */
dkato 0:f782d9c66c49 167 #if defined __CHECK_DEVICE_DEFINES
dkato 0:f782d9c66c49 168 #ifndef __CM0PLUS_REV
dkato 0:f782d9c66c49 169 #define __CM0PLUS_REV 0x0000
dkato 0:f782d9c66c49 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
dkato 0:f782d9c66c49 171 #endif
dkato 0:f782d9c66c49 172
dkato 0:f782d9c66c49 173 #ifndef __MPU_PRESENT
dkato 0:f782d9c66c49 174 #define __MPU_PRESENT 0
dkato 0:f782d9c66c49 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
dkato 0:f782d9c66c49 176 #endif
dkato 0:f782d9c66c49 177
dkato 0:f782d9c66c49 178 #ifndef __VTOR_PRESENT
dkato 0:f782d9c66c49 179 #define __VTOR_PRESENT 0
dkato 0:f782d9c66c49 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
dkato 0:f782d9c66c49 181 #endif
dkato 0:f782d9c66c49 182
dkato 0:f782d9c66c49 183 #ifndef __NVIC_PRIO_BITS
dkato 0:f782d9c66c49 184 #define __NVIC_PRIO_BITS 2
dkato 0:f782d9c66c49 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
dkato 0:f782d9c66c49 186 #endif
dkato 0:f782d9c66c49 187
dkato 0:f782d9c66c49 188 #ifndef __Vendor_SysTickConfig
dkato 0:f782d9c66c49 189 #define __Vendor_SysTickConfig 0
dkato 0:f782d9c66c49 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
dkato 0:f782d9c66c49 191 #endif
dkato 0:f782d9c66c49 192 #endif
dkato 0:f782d9c66c49 193
dkato 0:f782d9c66c49 194 /* IO definitions (access restrictions to peripheral registers) */
dkato 0:f782d9c66c49 195 /**
dkato 0:f782d9c66c49 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
dkato 0:f782d9c66c49 197
dkato 0:f782d9c66c49 198 <strong>IO Type Qualifiers</strong> are used
dkato 0:f782d9c66c49 199 \li to specify the access to peripheral variables.
dkato 0:f782d9c66c49 200 \li for automatic generation of peripheral register debug information.
dkato 0:f782d9c66c49 201 */
dkato 0:f782d9c66c49 202 #ifdef __cplusplus
dkato 0:f782d9c66c49 203 #define __I volatile /*!< Defines 'read only' permissions */
dkato 0:f782d9c66c49 204 #else
dkato 0:f782d9c66c49 205 #define __I volatile const /*!< Defines 'read only' permissions */
dkato 0:f782d9c66c49 206 #endif
dkato 0:f782d9c66c49 207 #define __O volatile /*!< Defines 'write only' permissions */
dkato 0:f782d9c66c49 208 #define __IO volatile /*!< Defines 'read / write' permissions */
dkato 0:f782d9c66c49 209
dkato 0:f782d9c66c49 210 #ifdef __cplusplus
dkato 0:f782d9c66c49 211 #define __IM volatile /*!< Defines 'read only' permissions */
dkato 0:f782d9c66c49 212 #else
dkato 0:f782d9c66c49 213 #define __IM volatile const /*!< Defines 'read only' permissions */
dkato 0:f782d9c66c49 214 #endif
dkato 0:f782d9c66c49 215 #define __OM volatile /*!< Defines 'write only' permissions */
dkato 0:f782d9c66c49 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
dkato 0:f782d9c66c49 217
dkato 0:f782d9c66c49 218 /*@} end of group Cortex-M0+ */
dkato 0:f782d9c66c49 219
dkato 0:f782d9c66c49 220
dkato 0:f782d9c66c49 221
dkato 0:f782d9c66c49 222 /*******************************************************************************
dkato 0:f782d9c66c49 223 * Register Abstraction
dkato 0:f782d9c66c49 224 Core Register contain:
dkato 0:f782d9c66c49 225 - Core Register
dkato 0:f782d9c66c49 226 - Core NVIC Register
dkato 0:f782d9c66c49 227 - Core SCB Register
dkato 0:f782d9c66c49 228 - Core SysTick Register
dkato 0:f782d9c66c49 229 - Core MPU Register
dkato 0:f782d9c66c49 230 ******************************************************************************/
dkato 0:f782d9c66c49 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
dkato 0:f782d9c66c49 232 \brief Type definitions and defines for Cortex-M processor based devices.
dkato 0:f782d9c66c49 233 */
dkato 0:f782d9c66c49 234
dkato 0:f782d9c66c49 235 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 236 \defgroup CMSIS_CORE Status and Control Registers
dkato 0:f782d9c66c49 237 \brief Core Register type definitions.
dkato 0:f782d9c66c49 238 @{
dkato 0:f782d9c66c49 239 */
dkato 0:f782d9c66c49 240
dkato 0:f782d9c66c49 241 /** \brief Union type to access the Application Program Status Register (APSR).
dkato 0:f782d9c66c49 242 */
dkato 0:f782d9c66c49 243 typedef union
dkato 0:f782d9c66c49 244 {
dkato 0:f782d9c66c49 245 struct
dkato 0:f782d9c66c49 246 {
dkato 0:f782d9c66c49 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
dkato 0:f782d9c66c49 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
dkato 0:f782d9c66c49 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
dkato 0:f782d9c66c49 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
dkato 0:f782d9c66c49 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
dkato 0:f782d9c66c49 252 } b; /*!< Structure used for bit access */
dkato 0:f782d9c66c49 253 uint32_t w; /*!< Type used for word access */
dkato 0:f782d9c66c49 254 } APSR_Type;
dkato 0:f782d9c66c49 255
dkato 0:f782d9c66c49 256 /* APSR Register Definitions */
dkato 0:f782d9c66c49 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
dkato 0:f782d9c66c49 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
dkato 0:f782d9c66c49 259
dkato 0:f782d9c66c49 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
dkato 0:f782d9c66c49 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
dkato 0:f782d9c66c49 262
dkato 0:f782d9c66c49 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
dkato 0:f782d9c66c49 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
dkato 0:f782d9c66c49 265
dkato 0:f782d9c66c49 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
dkato 0:f782d9c66c49 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
dkato 0:f782d9c66c49 268
dkato 0:f782d9c66c49 269
dkato 0:f782d9c66c49 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
dkato 0:f782d9c66c49 271 */
dkato 0:f782d9c66c49 272 typedef union
dkato 0:f782d9c66c49 273 {
dkato 0:f782d9c66c49 274 struct
dkato 0:f782d9c66c49 275 {
dkato 0:f782d9c66c49 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
dkato 0:f782d9c66c49 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
dkato 0:f782d9c66c49 278 } b; /*!< Structure used for bit access */
dkato 0:f782d9c66c49 279 uint32_t w; /*!< Type used for word access */
dkato 0:f782d9c66c49 280 } IPSR_Type;
dkato 0:f782d9c66c49 281
dkato 0:f782d9c66c49 282 /* IPSR Register Definitions */
dkato 0:f782d9c66c49 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
dkato 0:f782d9c66c49 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
dkato 0:f782d9c66c49 285
dkato 0:f782d9c66c49 286
dkato 0:f782d9c66c49 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
dkato 0:f782d9c66c49 288 */
dkato 0:f782d9c66c49 289 typedef union
dkato 0:f782d9c66c49 290 {
dkato 0:f782d9c66c49 291 struct
dkato 0:f782d9c66c49 292 {
dkato 0:f782d9c66c49 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
dkato 0:f782d9c66c49 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
dkato 0:f782d9c66c49 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
dkato 0:f782d9c66c49 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
dkato 0:f782d9c66c49 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
dkato 0:f782d9c66c49 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
dkato 0:f782d9c66c49 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
dkato 0:f782d9c66c49 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
dkato 0:f782d9c66c49 301 } b; /*!< Structure used for bit access */
dkato 0:f782d9c66c49 302 uint32_t w; /*!< Type used for word access */
dkato 0:f782d9c66c49 303 } xPSR_Type;
dkato 0:f782d9c66c49 304
dkato 0:f782d9c66c49 305 /* xPSR Register Definitions */
dkato 0:f782d9c66c49 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
dkato 0:f782d9c66c49 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
dkato 0:f782d9c66c49 308
dkato 0:f782d9c66c49 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
dkato 0:f782d9c66c49 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
dkato 0:f782d9c66c49 311
dkato 0:f782d9c66c49 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
dkato 0:f782d9c66c49 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
dkato 0:f782d9c66c49 314
dkato 0:f782d9c66c49 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
dkato 0:f782d9c66c49 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
dkato 0:f782d9c66c49 317
dkato 0:f782d9c66c49 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
dkato 0:f782d9c66c49 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
dkato 0:f782d9c66c49 320
dkato 0:f782d9c66c49 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
dkato 0:f782d9c66c49 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
dkato 0:f782d9c66c49 323
dkato 0:f782d9c66c49 324
dkato 0:f782d9c66c49 325 /** \brief Union type to access the Control Registers (CONTROL).
dkato 0:f782d9c66c49 326 */
dkato 0:f782d9c66c49 327 typedef union
dkato 0:f782d9c66c49 328 {
dkato 0:f782d9c66c49 329 struct
dkato 0:f782d9c66c49 330 {
dkato 0:f782d9c66c49 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
dkato 0:f782d9c66c49 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
dkato 0:f782d9c66c49 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
dkato 0:f782d9c66c49 334 } b; /*!< Structure used for bit access */
dkato 0:f782d9c66c49 335 uint32_t w; /*!< Type used for word access */
dkato 0:f782d9c66c49 336 } CONTROL_Type;
dkato 0:f782d9c66c49 337
dkato 0:f782d9c66c49 338 /* CONTROL Register Definitions */
dkato 0:f782d9c66c49 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
dkato 0:f782d9c66c49 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
dkato 0:f782d9c66c49 341
dkato 0:f782d9c66c49 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
dkato 0:f782d9c66c49 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
dkato 0:f782d9c66c49 344
dkato 0:f782d9c66c49 345 /*@} end of group CMSIS_CORE */
dkato 0:f782d9c66c49 346
dkato 0:f782d9c66c49 347
dkato 0:f782d9c66c49 348 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
dkato 0:f782d9c66c49 350 \brief Type definitions for the NVIC Registers
dkato 0:f782d9c66c49 351 @{
dkato 0:f782d9c66c49 352 */
dkato 0:f782d9c66c49 353
dkato 0:f782d9c66c49 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
dkato 0:f782d9c66c49 355 */
dkato 0:f782d9c66c49 356 typedef struct
dkato 0:f782d9c66c49 357 {
dkato 0:f782d9c66c49 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
dkato 0:f782d9c66c49 359 uint32_t RESERVED0[31];
dkato 0:f782d9c66c49 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
dkato 0:f782d9c66c49 361 uint32_t RSERVED1[31];
dkato 0:f782d9c66c49 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
dkato 0:f782d9c66c49 363 uint32_t RESERVED2[31];
dkato 0:f782d9c66c49 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
dkato 0:f782d9c66c49 365 uint32_t RESERVED3[31];
dkato 0:f782d9c66c49 366 uint32_t RESERVED4[64];
dkato 0:f782d9c66c49 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
dkato 0:f782d9c66c49 368 } NVIC_Type;
dkato 0:f782d9c66c49 369
dkato 0:f782d9c66c49 370 /*@} end of group CMSIS_NVIC */
dkato 0:f782d9c66c49 371
dkato 0:f782d9c66c49 372
dkato 0:f782d9c66c49 373 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 374 \defgroup CMSIS_SCB System Control Block (SCB)
dkato 0:f782d9c66c49 375 \brief Type definitions for the System Control Block Registers
dkato 0:f782d9c66c49 376 @{
dkato 0:f782d9c66c49 377 */
dkato 0:f782d9c66c49 378
dkato 0:f782d9c66c49 379 /** \brief Structure type to access the System Control Block (SCB).
dkato 0:f782d9c66c49 380 */
dkato 0:f782d9c66c49 381 typedef struct
dkato 0:f782d9c66c49 382 {
dkato 0:f782d9c66c49 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
dkato 0:f782d9c66c49 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
dkato 0:f782d9c66c49 385 #if (__VTOR_PRESENT == 1)
dkato 0:f782d9c66c49 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
dkato 0:f782d9c66c49 387 #else
dkato 0:f782d9c66c49 388 uint32_t RESERVED0;
dkato 0:f782d9c66c49 389 #endif
dkato 0:f782d9c66c49 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
dkato 0:f782d9c66c49 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
dkato 0:f782d9c66c49 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
dkato 0:f782d9c66c49 393 uint32_t RESERVED1;
dkato 0:f782d9c66c49 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
dkato 0:f782d9c66c49 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
dkato 0:f782d9c66c49 396 } SCB_Type;
dkato 0:f782d9c66c49 397
dkato 0:f782d9c66c49 398 /* SCB CPUID Register Definitions */
dkato 0:f782d9c66c49 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
dkato 0:f782d9c66c49 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
dkato 0:f782d9c66c49 401
dkato 0:f782d9c66c49 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
dkato 0:f782d9c66c49 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
dkato 0:f782d9c66c49 404
dkato 0:f782d9c66c49 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
dkato 0:f782d9c66c49 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
dkato 0:f782d9c66c49 407
dkato 0:f782d9c66c49 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
dkato 0:f782d9c66c49 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
dkato 0:f782d9c66c49 410
dkato 0:f782d9c66c49 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
dkato 0:f782d9c66c49 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
dkato 0:f782d9c66c49 413
dkato 0:f782d9c66c49 414 /* SCB Interrupt Control State Register Definitions */
dkato 0:f782d9c66c49 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
dkato 0:f782d9c66c49 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
dkato 0:f782d9c66c49 417
dkato 0:f782d9c66c49 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
dkato 0:f782d9c66c49 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
dkato 0:f782d9c66c49 420
dkato 0:f782d9c66c49 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
dkato 0:f782d9c66c49 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
dkato 0:f782d9c66c49 423
dkato 0:f782d9c66c49 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
dkato 0:f782d9c66c49 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
dkato 0:f782d9c66c49 426
dkato 0:f782d9c66c49 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
dkato 0:f782d9c66c49 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
dkato 0:f782d9c66c49 429
dkato 0:f782d9c66c49 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
dkato 0:f782d9c66c49 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
dkato 0:f782d9c66c49 432
dkato 0:f782d9c66c49 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
dkato 0:f782d9c66c49 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
dkato 0:f782d9c66c49 435
dkato 0:f782d9c66c49 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
dkato 0:f782d9c66c49 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
dkato 0:f782d9c66c49 438
dkato 0:f782d9c66c49 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
dkato 0:f782d9c66c49 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
dkato 0:f782d9c66c49 441
dkato 0:f782d9c66c49 442 #if (__VTOR_PRESENT == 1)
dkato 0:f782d9c66c49 443 /* SCB Interrupt Control State Register Definitions */
dkato 0:f782d9c66c49 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
dkato 0:f782d9c66c49 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
dkato 0:f782d9c66c49 446 #endif
dkato 0:f782d9c66c49 447
dkato 0:f782d9c66c49 448 /* SCB Application Interrupt and Reset Control Register Definitions */
dkato 0:f782d9c66c49 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
dkato 0:f782d9c66c49 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
dkato 0:f782d9c66c49 451
dkato 0:f782d9c66c49 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
dkato 0:f782d9c66c49 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
dkato 0:f782d9c66c49 454
dkato 0:f782d9c66c49 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
dkato 0:f782d9c66c49 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
dkato 0:f782d9c66c49 457
dkato 0:f782d9c66c49 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
dkato 0:f782d9c66c49 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
dkato 0:f782d9c66c49 460
dkato 0:f782d9c66c49 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
dkato 0:f782d9c66c49 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
dkato 0:f782d9c66c49 463
dkato 0:f782d9c66c49 464 /* SCB System Control Register Definitions */
dkato 0:f782d9c66c49 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
dkato 0:f782d9c66c49 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
dkato 0:f782d9c66c49 467
dkato 0:f782d9c66c49 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
dkato 0:f782d9c66c49 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
dkato 0:f782d9c66c49 470
dkato 0:f782d9c66c49 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
dkato 0:f782d9c66c49 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
dkato 0:f782d9c66c49 473
dkato 0:f782d9c66c49 474 /* SCB Configuration Control Register Definitions */
dkato 0:f782d9c66c49 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
dkato 0:f782d9c66c49 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
dkato 0:f782d9c66c49 477
dkato 0:f782d9c66c49 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
dkato 0:f782d9c66c49 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
dkato 0:f782d9c66c49 480
dkato 0:f782d9c66c49 481 /* SCB System Handler Control and State Register Definitions */
dkato 0:f782d9c66c49 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
dkato 0:f782d9c66c49 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
dkato 0:f782d9c66c49 484
dkato 0:f782d9c66c49 485 /*@} end of group CMSIS_SCB */
dkato 0:f782d9c66c49 486
dkato 0:f782d9c66c49 487
dkato 0:f782d9c66c49 488 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
dkato 0:f782d9c66c49 490 \brief Type definitions for the System Timer Registers.
dkato 0:f782d9c66c49 491 @{
dkato 0:f782d9c66c49 492 */
dkato 0:f782d9c66c49 493
dkato 0:f782d9c66c49 494 /** \brief Structure type to access the System Timer (SysTick).
dkato 0:f782d9c66c49 495 */
dkato 0:f782d9c66c49 496 typedef struct
dkato 0:f782d9c66c49 497 {
dkato 0:f782d9c66c49 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
dkato 0:f782d9c66c49 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
dkato 0:f782d9c66c49 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
dkato 0:f782d9c66c49 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
dkato 0:f782d9c66c49 502 } SysTick_Type;
dkato 0:f782d9c66c49 503
dkato 0:f782d9c66c49 504 /* SysTick Control / Status Register Definitions */
dkato 0:f782d9c66c49 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
dkato 0:f782d9c66c49 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
dkato 0:f782d9c66c49 507
dkato 0:f782d9c66c49 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
dkato 0:f782d9c66c49 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
dkato 0:f782d9c66c49 510
dkato 0:f782d9c66c49 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
dkato 0:f782d9c66c49 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
dkato 0:f782d9c66c49 513
dkato 0:f782d9c66c49 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
dkato 0:f782d9c66c49 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
dkato 0:f782d9c66c49 516
dkato 0:f782d9c66c49 517 /* SysTick Reload Register Definitions */
dkato 0:f782d9c66c49 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
dkato 0:f782d9c66c49 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
dkato 0:f782d9c66c49 520
dkato 0:f782d9c66c49 521 /* SysTick Current Register Definitions */
dkato 0:f782d9c66c49 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
dkato 0:f782d9c66c49 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
dkato 0:f782d9c66c49 524
dkato 0:f782d9c66c49 525 /* SysTick Calibration Register Definitions */
dkato 0:f782d9c66c49 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
dkato 0:f782d9c66c49 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
dkato 0:f782d9c66c49 528
dkato 0:f782d9c66c49 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
dkato 0:f782d9c66c49 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
dkato 0:f782d9c66c49 531
dkato 0:f782d9c66c49 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
dkato 0:f782d9c66c49 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
dkato 0:f782d9c66c49 534
dkato 0:f782d9c66c49 535 /*@} end of group CMSIS_SysTick */
dkato 0:f782d9c66c49 536
dkato 0:f782d9c66c49 537 #if (__MPU_PRESENT == 1)
dkato 0:f782d9c66c49 538 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
dkato 0:f782d9c66c49 540 \brief Type definitions for the Memory Protection Unit (MPU)
dkato 0:f782d9c66c49 541 @{
dkato 0:f782d9c66c49 542 */
dkato 0:f782d9c66c49 543
dkato 0:f782d9c66c49 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
dkato 0:f782d9c66c49 545 */
dkato 0:f782d9c66c49 546 typedef struct
dkato 0:f782d9c66c49 547 {
dkato 0:f782d9c66c49 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
dkato 0:f782d9c66c49 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
dkato 0:f782d9c66c49 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
dkato 0:f782d9c66c49 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
dkato 0:f782d9c66c49 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
dkato 0:f782d9c66c49 553 } MPU_Type;
dkato 0:f782d9c66c49 554
dkato 0:f782d9c66c49 555 /* MPU Type Register */
dkato 0:f782d9c66c49 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
dkato 0:f782d9c66c49 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
dkato 0:f782d9c66c49 558
dkato 0:f782d9c66c49 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
dkato 0:f782d9c66c49 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
dkato 0:f782d9c66c49 561
dkato 0:f782d9c66c49 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
dkato 0:f782d9c66c49 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
dkato 0:f782d9c66c49 564
dkato 0:f782d9c66c49 565 /* MPU Control Register */
dkato 0:f782d9c66c49 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
dkato 0:f782d9c66c49 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
dkato 0:f782d9c66c49 568
dkato 0:f782d9c66c49 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
dkato 0:f782d9c66c49 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
dkato 0:f782d9c66c49 571
dkato 0:f782d9c66c49 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
dkato 0:f782d9c66c49 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
dkato 0:f782d9c66c49 574
dkato 0:f782d9c66c49 575 /* MPU Region Number Register */
dkato 0:f782d9c66c49 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
dkato 0:f782d9c66c49 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
dkato 0:f782d9c66c49 578
dkato 0:f782d9c66c49 579 /* MPU Region Base Address Register */
dkato 0:f782d9c66c49 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
dkato 0:f782d9c66c49 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
dkato 0:f782d9c66c49 582
dkato 0:f782d9c66c49 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
dkato 0:f782d9c66c49 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
dkato 0:f782d9c66c49 585
dkato 0:f782d9c66c49 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
dkato 0:f782d9c66c49 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
dkato 0:f782d9c66c49 588
dkato 0:f782d9c66c49 589 /* MPU Region Attribute and Size Register */
dkato 0:f782d9c66c49 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
dkato 0:f782d9c66c49 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
dkato 0:f782d9c66c49 592
dkato 0:f782d9c66c49 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
dkato 0:f782d9c66c49 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
dkato 0:f782d9c66c49 595
dkato 0:f782d9c66c49 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
dkato 0:f782d9c66c49 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
dkato 0:f782d9c66c49 598
dkato 0:f782d9c66c49 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
dkato 0:f782d9c66c49 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
dkato 0:f782d9c66c49 601
dkato 0:f782d9c66c49 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
dkato 0:f782d9c66c49 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
dkato 0:f782d9c66c49 604
dkato 0:f782d9c66c49 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
dkato 0:f782d9c66c49 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
dkato 0:f782d9c66c49 607
dkato 0:f782d9c66c49 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
dkato 0:f782d9c66c49 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
dkato 0:f782d9c66c49 610
dkato 0:f782d9c66c49 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
dkato 0:f782d9c66c49 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
dkato 0:f782d9c66c49 613
dkato 0:f782d9c66c49 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
dkato 0:f782d9c66c49 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
dkato 0:f782d9c66c49 616
dkato 0:f782d9c66c49 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
dkato 0:f782d9c66c49 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
dkato 0:f782d9c66c49 619
dkato 0:f782d9c66c49 620 /*@} end of group CMSIS_MPU */
dkato 0:f782d9c66c49 621 #endif
dkato 0:f782d9c66c49 622
dkato 0:f782d9c66c49 623
dkato 0:f782d9c66c49 624 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
dkato 0:f782d9c66c49 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
dkato 0:f782d9c66c49 627 are only accessible over DAP and not via processor. Therefore
dkato 0:f782d9c66c49 628 they are not covered by the Cortex-M0 header file.
dkato 0:f782d9c66c49 629 @{
dkato 0:f782d9c66c49 630 */
dkato 0:f782d9c66c49 631 /*@} end of group CMSIS_CoreDebug */
dkato 0:f782d9c66c49 632
dkato 0:f782d9c66c49 633
dkato 0:f782d9c66c49 634 /** \ingroup CMSIS_core_register
dkato 0:f782d9c66c49 635 \defgroup CMSIS_core_base Core Definitions
dkato 0:f782d9c66c49 636 \brief Definitions for base addresses, unions, and structures.
dkato 0:f782d9c66c49 637 @{
dkato 0:f782d9c66c49 638 */
dkato 0:f782d9c66c49 639
dkato 0:f782d9c66c49 640 /* Memory mapping of Cortex-M0+ Hardware */
dkato 0:f782d9c66c49 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
dkato 0:f782d9c66c49 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
dkato 0:f782d9c66c49 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
dkato 0:f782d9c66c49 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
dkato 0:f782d9c66c49 645
dkato 0:f782d9c66c49 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
dkato 0:f782d9c66c49 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
dkato 0:f782d9c66c49 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
dkato 0:f782d9c66c49 649
dkato 0:f782d9c66c49 650 #if (__MPU_PRESENT == 1)
dkato 0:f782d9c66c49 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
dkato 0:f782d9c66c49 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
dkato 0:f782d9c66c49 653 #endif
dkato 0:f782d9c66c49 654
dkato 0:f782d9c66c49 655 /*@} */
dkato 0:f782d9c66c49 656
dkato 0:f782d9c66c49 657
dkato 0:f782d9c66c49 658
dkato 0:f782d9c66c49 659 /*******************************************************************************
dkato 0:f782d9c66c49 660 * Hardware Abstraction Layer
dkato 0:f782d9c66c49 661 Core Function Interface contains:
dkato 0:f782d9c66c49 662 - Core NVIC Functions
dkato 0:f782d9c66c49 663 - Core SysTick Functions
dkato 0:f782d9c66c49 664 - Core Register Access Functions
dkato 0:f782d9c66c49 665 ******************************************************************************/
dkato 0:f782d9c66c49 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
dkato 0:f782d9c66c49 667 */
dkato 0:f782d9c66c49 668
dkato 0:f782d9c66c49 669
dkato 0:f782d9c66c49 670
dkato 0:f782d9c66c49 671 /* ########################## NVIC functions #################################### */
dkato 0:f782d9c66c49 672 /** \ingroup CMSIS_Core_FunctionInterface
dkato 0:f782d9c66c49 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
dkato 0:f782d9c66c49 674 \brief Functions that manage interrupts and exceptions via the NVIC.
dkato 0:f782d9c66c49 675 @{
dkato 0:f782d9c66c49 676 */
dkato 0:f782d9c66c49 677
dkato 0:f782d9c66c49 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
dkato 0:f782d9c66c49 679 /* The following MACROS handle generation of the register offset and byte masks */
dkato 0:f782d9c66c49 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
dkato 0:f782d9c66c49 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
dkato 0:f782d9c66c49 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
dkato 0:f782d9c66c49 683
dkato 0:f782d9c66c49 684
dkato 0:f782d9c66c49 685 /** \brief Enable External Interrupt
dkato 0:f782d9c66c49 686
dkato 0:f782d9c66c49 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
dkato 0:f782d9c66c49 688
dkato 0:f782d9c66c49 689 \param [in] IRQn External interrupt number. Value cannot be negative.
dkato 0:f782d9c66c49 690 */
dkato 0:f782d9c66c49 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
dkato 0:f782d9c66c49 692 {
dkato 0:f782d9c66c49 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
dkato 0:f782d9c66c49 694 }
dkato 0:f782d9c66c49 695
dkato 0:f782d9c66c49 696
dkato 0:f782d9c66c49 697 /** \brief Disable External Interrupt
dkato 0:f782d9c66c49 698
dkato 0:f782d9c66c49 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
dkato 0:f782d9c66c49 700
dkato 0:f782d9c66c49 701 \param [in] IRQn External interrupt number. Value cannot be negative.
dkato 0:f782d9c66c49 702 */
dkato 0:f782d9c66c49 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
dkato 0:f782d9c66c49 704 {
dkato 0:f782d9c66c49 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
dkato 0:f782d9c66c49 706 __DSB();
dkato 0:f782d9c66c49 707 __ISB();
dkato 0:f782d9c66c49 708 }
dkato 0:f782d9c66c49 709
dkato 0:f782d9c66c49 710
dkato 0:f782d9c66c49 711 /** \brief Get Pending Interrupt
dkato 0:f782d9c66c49 712
dkato 0:f782d9c66c49 713 The function reads the pending register in the NVIC and returns the pending bit
dkato 0:f782d9c66c49 714 for the specified interrupt.
dkato 0:f782d9c66c49 715
dkato 0:f782d9c66c49 716 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 717
dkato 0:f782d9c66c49 718 \return 0 Interrupt status is not pending.
dkato 0:f782d9c66c49 719 \return 1 Interrupt status is pending.
dkato 0:f782d9c66c49 720 */
dkato 0:f782d9c66c49 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
dkato 0:f782d9c66c49 722 {
dkato 0:f782d9c66c49 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
dkato 0:f782d9c66c49 724 }
dkato 0:f782d9c66c49 725
dkato 0:f782d9c66c49 726
dkato 0:f782d9c66c49 727 /** \brief Set Pending Interrupt
dkato 0:f782d9c66c49 728
dkato 0:f782d9c66c49 729 The function sets the pending bit of an external interrupt.
dkato 0:f782d9c66c49 730
dkato 0:f782d9c66c49 731 \param [in] IRQn Interrupt number. Value cannot be negative.
dkato 0:f782d9c66c49 732 */
dkato 0:f782d9c66c49 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
dkato 0:f782d9c66c49 734 {
dkato 0:f782d9c66c49 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
dkato 0:f782d9c66c49 736 }
dkato 0:f782d9c66c49 737
dkato 0:f782d9c66c49 738
dkato 0:f782d9c66c49 739 /** \brief Clear Pending Interrupt
dkato 0:f782d9c66c49 740
dkato 0:f782d9c66c49 741 The function clears the pending bit of an external interrupt.
dkato 0:f782d9c66c49 742
dkato 0:f782d9c66c49 743 \param [in] IRQn External interrupt number. Value cannot be negative.
dkato 0:f782d9c66c49 744 */
dkato 0:f782d9c66c49 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
dkato 0:f782d9c66c49 746 {
dkato 0:f782d9c66c49 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
dkato 0:f782d9c66c49 748 }
dkato 0:f782d9c66c49 749
dkato 0:f782d9c66c49 750
dkato 0:f782d9c66c49 751 /** \brief Set Interrupt Priority
dkato 0:f782d9c66c49 752
dkato 0:f782d9c66c49 753 The function sets the priority of an interrupt.
dkato 0:f782d9c66c49 754
dkato 0:f782d9c66c49 755 \note The priority cannot be set for every core interrupt.
dkato 0:f782d9c66c49 756
dkato 0:f782d9c66c49 757 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 758 \param [in] priority Priority to set.
dkato 0:f782d9c66c49 759 */
dkato 0:f782d9c66c49 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
dkato 0:f782d9c66c49 761 {
dkato 0:f782d9c66c49 762 if((int32_t)(IRQn) < 0) {
dkato 0:f782d9c66c49 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
dkato 0:f782d9c66c49 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
dkato 0:f782d9c66c49 765 }
dkato 0:f782d9c66c49 766 else {
dkato 0:f782d9c66c49 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
dkato 0:f782d9c66c49 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
dkato 0:f782d9c66c49 769 }
dkato 0:f782d9c66c49 770 }
dkato 0:f782d9c66c49 771
dkato 0:f782d9c66c49 772
dkato 0:f782d9c66c49 773 /** \brief Get Interrupt Priority
dkato 0:f782d9c66c49 774
dkato 0:f782d9c66c49 775 The function reads the priority of an interrupt. The interrupt
dkato 0:f782d9c66c49 776 number can be positive to specify an external (device specific)
dkato 0:f782d9c66c49 777 interrupt, or negative to specify an internal (core) interrupt.
dkato 0:f782d9c66c49 778
dkato 0:f782d9c66c49 779
dkato 0:f782d9c66c49 780 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 781 \return Interrupt Priority. Value is aligned automatically to the implemented
dkato 0:f782d9c66c49 782 priority bits of the microcontroller.
dkato 0:f782d9c66c49 783 */
dkato 0:f782d9c66c49 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
dkato 0:f782d9c66c49 785 {
dkato 0:f782d9c66c49 786
dkato 0:f782d9c66c49 787 if((int32_t)(IRQn) < 0) {
dkato 0:f782d9c66c49 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
dkato 0:f782d9c66c49 789 }
dkato 0:f782d9c66c49 790 else {
dkato 0:f782d9c66c49 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
dkato 0:f782d9c66c49 792 }
dkato 0:f782d9c66c49 793 }
dkato 0:f782d9c66c49 794
dkato 0:f782d9c66c49 795
dkato 0:f782d9c66c49 796 /** \brief System Reset
dkato 0:f782d9c66c49 797
dkato 0:f782d9c66c49 798 The function initiates a system reset request to reset the MCU.
dkato 0:f782d9c66c49 799 */
dkato 0:f782d9c66c49 800 __STATIC_INLINE void NVIC_SystemReset(void)
dkato 0:f782d9c66c49 801 {
dkato 0:f782d9c66c49 802 __DSB(); /* Ensure all outstanding memory accesses included
dkato 0:f782d9c66c49 803 buffered write are completed before reset */
dkato 0:f782d9c66c49 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
dkato 0:f782d9c66c49 805 SCB_AIRCR_SYSRESETREQ_Msk);
dkato 0:f782d9c66c49 806 __DSB(); /* Ensure completion of memory access */
dkato 0:f782d9c66c49 807 while(1) { __NOP(); } /* wait until reset */
dkato 0:f782d9c66c49 808 }
dkato 0:f782d9c66c49 809
dkato 0:f782d9c66c49 810 /*@} end of CMSIS_Core_NVICFunctions */
dkato 0:f782d9c66c49 811
dkato 0:f782d9c66c49 812
dkato 0:f782d9c66c49 813
dkato 0:f782d9c66c49 814 /* ################################## SysTick function ############################################ */
dkato 0:f782d9c66c49 815 /** \ingroup CMSIS_Core_FunctionInterface
dkato 0:f782d9c66c49 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
dkato 0:f782d9c66c49 817 \brief Functions that configure the System.
dkato 0:f782d9c66c49 818 @{
dkato 0:f782d9c66c49 819 */
dkato 0:f782d9c66c49 820
dkato 0:f782d9c66c49 821 #if (__Vendor_SysTickConfig == 0)
dkato 0:f782d9c66c49 822
dkato 0:f782d9c66c49 823 /** \brief System Tick Configuration
dkato 0:f782d9c66c49 824
dkato 0:f782d9c66c49 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
dkato 0:f782d9c66c49 826 Counter is in free running mode to generate periodic interrupts.
dkato 0:f782d9c66c49 827
dkato 0:f782d9c66c49 828 \param [in] ticks Number of ticks between two interrupts.
dkato 0:f782d9c66c49 829
dkato 0:f782d9c66c49 830 \return 0 Function succeeded.
dkato 0:f782d9c66c49 831 \return 1 Function failed.
dkato 0:f782d9c66c49 832
dkato 0:f782d9c66c49 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
dkato 0:f782d9c66c49 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
dkato 0:f782d9c66c49 835 must contain a vendor-specific implementation of this function.
dkato 0:f782d9c66c49 836
dkato 0:f782d9c66c49 837 */
dkato 0:f782d9c66c49 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
dkato 0:f782d9c66c49 839 {
dkato 0:f782d9c66c49 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
dkato 0:f782d9c66c49 841
dkato 0:f782d9c66c49 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
dkato 0:f782d9c66c49 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
dkato 0:f782d9c66c49 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
dkato 0:f782d9c66c49 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
dkato 0:f782d9c66c49 846 SysTick_CTRL_TICKINT_Msk |
dkato 0:f782d9c66c49 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
dkato 0:f782d9c66c49 848 return (0UL); /* Function successful */
dkato 0:f782d9c66c49 849 }
dkato 0:f782d9c66c49 850
dkato 0:f782d9c66c49 851 #endif
dkato 0:f782d9c66c49 852
dkato 0:f782d9c66c49 853 /*@} end of CMSIS_Core_SysTickFunctions */
dkato 0:f782d9c66c49 854
dkato 0:f782d9c66c49 855
dkato 0:f782d9c66c49 856
dkato 0:f782d9c66c49 857
dkato 0:f782d9c66c49 858 #ifdef __cplusplus
dkato 0:f782d9c66c49 859 }
dkato 0:f782d9c66c49 860 #endif
dkato 0:f782d9c66c49 861
dkato 0:f782d9c66c49 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
dkato 0:f782d9c66c49 863
dkato 0:f782d9c66c49 864 #endif /* __CMSIS_GENERIC */