Daiki Kato / mbed-os-lychee

mbed-os for GR-LYCHEE

Dependents:   mbed-os-example-blinky-gr-lychee GR-Boads_Camera_sample GR-Boards_Audio_Recoder GR-Boads_Camera_DisplayApp ... more

cmsis/core_caFunc.h@0:f782d9c66c49, 2018-02-02 (annotated)

Committer:
dkato
Date:
Fri Feb 02 05:42:23 2018 +0000
Revision:
0:f782d9c66c49
mbed-os for GR-LYCHEE

Who changed what in which revision?

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dkato 0:f782d9c66c49 1 /**************************************************************************//**
dkato 0:f782d9c66c49 2 * @file core_caFunc.h
dkato 0:f782d9c66c49 3 * @brief CMSIS Cortex-A Core Function Access Header File
dkato 0:f782d9c66c49 4 * @version V3.10
dkato 0:f782d9c66c49 5 * @date 30 Oct 2013
dkato 0:f782d9c66c49 6 *
dkato 0:f782d9c66c49 7 * @note
dkato 0:f782d9c66c49 8 *
dkato 0:f782d9c66c49 9 ******************************************************************************/
dkato 0:f782d9c66c49 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
dkato 0:f782d9c66c49 11
dkato 0:f782d9c66c49 12 All rights reserved.
dkato 0:f782d9c66c49 13 Redistribution and use in source and binary forms, with or without
dkato 0:f782d9c66c49 14 modification, are permitted provided that the following conditions are met:
dkato 0:f782d9c66c49 15 - Redistributions of source code must retain the above copyright
dkato 0:f782d9c66c49 16 notice, this list of conditions and the following disclaimer.
dkato 0:f782d9c66c49 17 - Redistributions in binary form must reproduce the above copyright
dkato 0:f782d9c66c49 18 notice, this list of conditions and the following disclaimer in the
dkato 0:f782d9c66c49 19 documentation and/or other materials provided with the distribution.
dkato 0:f782d9c66c49 20 - Neither the name of ARM nor the names of its contributors may be used
dkato 0:f782d9c66c49 21 to endorse or promote products derived from this software without
dkato 0:f782d9c66c49 22 specific prior written permission.
dkato 0:f782d9c66c49 23 *
dkato 0:f782d9c66c49 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
dkato 0:f782d9c66c49 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
dkato 0:f782d9c66c49 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
dkato 0:f782d9c66c49 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
dkato 0:f782d9c66c49 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
dkato 0:f782d9c66c49 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
dkato 0:f782d9c66c49 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
dkato 0:f782d9c66c49 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
dkato 0:f782d9c66c49 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
dkato 0:f782d9c66c49 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
dkato 0:f782d9c66c49 34 POSSIBILITY OF SUCH DAMAGE.
dkato 0:f782d9c66c49 35 ---------------------------------------------------------------------------*/
dkato 0:f782d9c66c49 36
dkato 0:f782d9c66c49 37
dkato 0:f782d9c66c49 38 #ifndef __CORE_CAFUNC_H__
dkato 0:f782d9c66c49 39 #define __CORE_CAFUNC_H__
dkato 0:f782d9c66c49 40
dkato 0:f782d9c66c49 41
dkato 0:f782d9c66c49 42 /* ########################### Core Function Access ########################### */
dkato 0:f782d9c66c49 43 /** \ingroup CMSIS_Core_FunctionInterface
dkato 0:f782d9c66c49 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
dkato 0:f782d9c66c49 45 @{
dkato 0:f782d9c66c49 46 */
dkato 0:f782d9c66c49 47
dkato 0:f782d9c66c49 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
dkato 0:f782d9c66c49 49 /* ARM armcc specific functions */
dkato 0:f782d9c66c49 50
dkato 0:f782d9c66c49 51 #if (__ARMCC_VERSION < 400677)
dkato 0:f782d9c66c49 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
dkato 0:f782d9c66c49 53 #endif
dkato 0:f782d9c66c49 54
dkato 0:f782d9c66c49 55 #define MODE_USR 0x10
dkato 0:f782d9c66c49 56 #define MODE_FIQ 0x11
dkato 0:f782d9c66c49 57 #define MODE_IRQ 0x12
dkato 0:f782d9c66c49 58 #define MODE_SVC 0x13
dkato 0:f782d9c66c49 59 #define MODE_MON 0x16
dkato 0:f782d9c66c49 60 #define MODE_ABT 0x17
dkato 0:f782d9c66c49 61 #define MODE_HYP 0x1A
dkato 0:f782d9c66c49 62 #define MODE_UND 0x1B
dkato 0:f782d9c66c49 63 #define MODE_SYS 0x1F
dkato 0:f782d9c66c49 64
dkato 0:f782d9c66c49 65 /** \brief Get APSR Register
dkato 0:f782d9c66c49 66
dkato 0:f782d9c66c49 67 This function returns the content of the APSR Register.
dkato 0:f782d9c66c49 68
dkato 0:f782d9c66c49 69 \return APSR Register value
dkato 0:f782d9c66c49 70 */
dkato 0:f782d9c66c49 71 __STATIC_INLINE uint32_t __get_APSR(void)
dkato 0:f782d9c66c49 72 {
dkato 0:f782d9c66c49 73 register uint32_t __regAPSR __ASM("apsr");
dkato 0:f782d9c66c49 74 return(__regAPSR);
dkato 0:f782d9c66c49 75 }
dkato 0:f782d9c66c49 76
dkato 0:f782d9c66c49 77
dkato 0:f782d9c66c49 78 /** \brief Get CPSR Register
dkato 0:f782d9c66c49 79
dkato 0:f782d9c66c49 80 This function returns the content of the CPSR Register.
dkato 0:f782d9c66c49 81
dkato 0:f782d9c66c49 82 \return CPSR Register value
dkato 0:f782d9c66c49 83 */
dkato 0:f782d9c66c49 84 __STATIC_INLINE uint32_t __get_CPSR(void)
dkato 0:f782d9c66c49 85 {
dkato 0:f782d9c66c49 86 register uint32_t __regCPSR __ASM("cpsr");
dkato 0:f782d9c66c49 87 return(__regCPSR);
dkato 0:f782d9c66c49 88 }
dkato 0:f782d9c66c49 89
dkato 0:f782d9c66c49 90 /** \brief Set Stack Pointer
dkato 0:f782d9c66c49 91
dkato 0:f782d9c66c49 92 This function assigns the given value to the current stack pointer.
dkato 0:f782d9c66c49 93
dkato 0:f782d9c66c49 94 \param [in] topOfStack Stack Pointer value to set
dkato 0:f782d9c66c49 95 */
dkato 0:f782d9c66c49 96 register uint32_t __regSP __ASM("sp");
dkato 0:f782d9c66c49 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
dkato 0:f782d9c66c49 98 {
dkato 0:f782d9c66c49 99 __regSP = topOfStack;
dkato 0:f782d9c66c49 100 }
dkato 0:f782d9c66c49 101
dkato 0:f782d9c66c49 102
dkato 0:f782d9c66c49 103 /** \brief Get link register
dkato 0:f782d9c66c49 104
dkato 0:f782d9c66c49 105 This function returns the value of the link register
dkato 0:f782d9c66c49 106
dkato 0:f782d9c66c49 107 \return Value of link register
dkato 0:f782d9c66c49 108 */
dkato 0:f782d9c66c49 109 register uint32_t __reglr __ASM("lr");
dkato 0:f782d9c66c49 110 __STATIC_INLINE uint32_t __get_LR(void)
dkato 0:f782d9c66c49 111 {
dkato 0:f782d9c66c49 112 return(__reglr);
dkato 0:f782d9c66c49 113 }
dkato 0:f782d9c66c49 114
dkato 0:f782d9c66c49 115 /** \brief Set link register
dkato 0:f782d9c66c49 116
dkato 0:f782d9c66c49 117 This function sets the value of the link register
dkato 0:f782d9c66c49 118
dkato 0:f782d9c66c49 119 \param [in] lr LR value to set
dkato 0:f782d9c66c49 120 */
dkato 0:f782d9c66c49 121 __STATIC_INLINE void __set_LR(uint32_t lr)
dkato 0:f782d9c66c49 122 {
dkato 0:f782d9c66c49 123 __reglr = lr;
dkato 0:f782d9c66c49 124 }
dkato 0:f782d9c66c49 125
dkato 0:f782d9c66c49 126 /** \brief Set Process Stack Pointer
dkato 0:f782d9c66c49 127
dkato 0:f782d9c66c49 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
dkato 0:f782d9c66c49 129
dkato 0:f782d9c66c49 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
dkato 0:f782d9c66c49 131 */
dkato 0:f782d9c66c49 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
dkato 0:f782d9c66c49 133 {
dkato 0:f782d9c66c49 134 ARM
dkato 0:f782d9c66c49 135 PRESERVE8
dkato 0:f782d9c66c49 136
dkato 0:f782d9c66c49 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
dkato 0:f782d9c66c49 138 MRS R1, CPSR
dkato 0:f782d9c66c49 139 CPS #MODE_SYS ;no effect in USR mode
dkato 0:f782d9c66c49 140 MOV SP, R0
dkato 0:f782d9c66c49 141 MSR CPSR_c, R1 ;no effect in USR mode
dkato 0:f782d9c66c49 142 ISB
dkato 0:f782d9c66c49 143 BX LR
dkato 0:f782d9c66c49 144
dkato 0:f782d9c66c49 145 }
dkato 0:f782d9c66c49 146
dkato 0:f782d9c66c49 147 /** \brief Set User Mode
dkato 0:f782d9c66c49 148
dkato 0:f782d9c66c49 149 This function changes the processor state to User Mode
dkato 0:f782d9c66c49 150 */
dkato 0:f782d9c66c49 151 __STATIC_ASM void __set_CPS_USR(void)
dkato 0:f782d9c66c49 152 {
dkato 0:f782d9c66c49 153 ARM
dkato 0:f782d9c66c49 154
dkato 0:f782d9c66c49 155 CPS #MODE_USR
dkato 0:f782d9c66c49 156 BX LR
dkato 0:f782d9c66c49 157 }
dkato 0:f782d9c66c49 158
dkato 0:f782d9c66c49 159
dkato 0:f782d9c66c49 160 /** \brief Enable FIQ
dkato 0:f782d9c66c49 161
dkato 0:f782d9c66c49 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
dkato 0:f782d9c66c49 163 Can only be executed in Privileged modes.
dkato 0:f782d9c66c49 164 */
dkato 0:f782d9c66c49 165 #define __enable_fault_irq __enable_fiq
dkato 0:f782d9c66c49 166
dkato 0:f782d9c66c49 167
dkato 0:f782d9c66c49 168 /** \brief Disable FIQ
dkato 0:f782d9c66c49 169
dkato 0:f782d9c66c49 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
dkato 0:f782d9c66c49 171 Can only be executed in Privileged modes.
dkato 0:f782d9c66c49 172 */
dkato 0:f782d9c66c49 173 #define __disable_fault_irq __disable_fiq
dkato 0:f782d9c66c49 174
dkato 0:f782d9c66c49 175
dkato 0:f782d9c66c49 176 /** \brief Get FPSCR
dkato 0:f782d9c66c49 177
dkato 0:f782d9c66c49 178 This function returns the current value of the Floating Point Status/Control register.
dkato 0:f782d9c66c49 179
dkato 0:f782d9c66c49 180 \return Floating Point Status/Control register value
dkato 0:f782d9c66c49 181 */
dkato 0:f782d9c66c49 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
dkato 0:f782d9c66c49 183 {
dkato 0:f782d9c66c49 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
dkato 0:f782d9c66c49 185 register uint32_t __regfpscr __ASM("fpscr");
dkato 0:f782d9c66c49 186 return(__regfpscr);
dkato 0:f782d9c66c49 187 #else
dkato 0:f782d9c66c49 188 return(0);
dkato 0:f782d9c66c49 189 #endif
dkato 0:f782d9c66c49 190 }
dkato 0:f782d9c66c49 191
dkato 0:f782d9c66c49 192
dkato 0:f782d9c66c49 193 /** \brief Set FPSCR
dkato 0:f782d9c66c49 194
dkato 0:f782d9c66c49 195 This function assigns the given value to the Floating Point Status/Control register.
dkato 0:f782d9c66c49 196
dkato 0:f782d9c66c49 197 \param [in] fpscr Floating Point Status/Control value to set
dkato 0:f782d9c66c49 198 */
dkato 0:f782d9c66c49 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
dkato 0:f782d9c66c49 200 {
dkato 0:f782d9c66c49 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
dkato 0:f782d9c66c49 202 register uint32_t __regfpscr __ASM("fpscr");
dkato 0:f782d9c66c49 203 __regfpscr = (fpscr);
dkato 0:f782d9c66c49 204 #endif
dkato 0:f782d9c66c49 205 }
dkato 0:f782d9c66c49 206
dkato 0:f782d9c66c49 207 /** \brief Get FPEXC
dkato 0:f782d9c66c49 208
dkato 0:f782d9c66c49 209 This function returns the current value of the Floating Point Exception Control register.
dkato 0:f782d9c66c49 210
dkato 0:f782d9c66c49 211 \return Floating Point Exception Control register value
dkato 0:f782d9c66c49 212 */
dkato 0:f782d9c66c49 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
dkato 0:f782d9c66c49 214 {
dkato 0:f782d9c66c49 215 #if (__FPU_PRESENT == 1)
dkato 0:f782d9c66c49 216 register uint32_t __regfpexc __ASM("fpexc");
dkato 0:f782d9c66c49 217 return(__regfpexc);
dkato 0:f782d9c66c49 218 #else
dkato 0:f782d9c66c49 219 return(0);
dkato 0:f782d9c66c49 220 #endif
dkato 0:f782d9c66c49 221 }
dkato 0:f782d9c66c49 222
dkato 0:f782d9c66c49 223
dkato 0:f782d9c66c49 224 /** \brief Set FPEXC
dkato 0:f782d9c66c49 225
dkato 0:f782d9c66c49 226 This function assigns the given value to the Floating Point Exception Control register.
dkato 0:f782d9c66c49 227
dkato 0:f782d9c66c49 228 \param [in] fpscr Floating Point Exception Control value to set
dkato 0:f782d9c66c49 229 */
dkato 0:f782d9c66c49 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
dkato 0:f782d9c66c49 231 {
dkato 0:f782d9c66c49 232 #if (__FPU_PRESENT == 1)
dkato 0:f782d9c66c49 233 register uint32_t __regfpexc __ASM("fpexc");
dkato 0:f782d9c66c49 234 __regfpexc = (fpexc);
dkato 0:f782d9c66c49 235 #endif
dkato 0:f782d9c66c49 236 }
dkato 0:f782d9c66c49 237
dkato 0:f782d9c66c49 238 /** \brief Get CPACR
dkato 0:f782d9c66c49 239
dkato 0:f782d9c66c49 240 This function returns the current value of the Coprocessor Access Control register.
dkato 0:f782d9c66c49 241
dkato 0:f782d9c66c49 242 \return Coprocessor Access Control register value
dkato 0:f782d9c66c49 243 */
dkato 0:f782d9c66c49 244 __STATIC_INLINE uint32_t __get_CPACR(void)
dkato 0:f782d9c66c49 245 {
dkato 0:f782d9c66c49 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
dkato 0:f782d9c66c49 247 return __regCPACR;
dkato 0:f782d9c66c49 248 }
dkato 0:f782d9c66c49 249
dkato 0:f782d9c66c49 250 /** \brief Set CPACR
dkato 0:f782d9c66c49 251
dkato 0:f782d9c66c49 252 This function assigns the given value to the Coprocessor Access Control register.
dkato 0:f782d9c66c49 253
dkato 0:f782d9c66c49 254 \param [in] cpacr Coprocessor Acccess Control value to set
dkato 0:f782d9c66c49 255 */
dkato 0:f782d9c66c49 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
dkato 0:f782d9c66c49 257 {
dkato 0:f782d9c66c49 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
dkato 0:f782d9c66c49 259 __regCPACR = cpacr;
dkato 0:f782d9c66c49 260 __ISB();
dkato 0:f782d9c66c49 261 }
dkato 0:f782d9c66c49 262
dkato 0:f782d9c66c49 263 /** \brief Get CBAR
dkato 0:f782d9c66c49 264
dkato 0:f782d9c66c49 265 This function returns the value of the Configuration Base Address register.
dkato 0:f782d9c66c49 266
dkato 0:f782d9c66c49 267 \return Configuration Base Address register value
dkato 0:f782d9c66c49 268 */
dkato 0:f782d9c66c49 269 __STATIC_INLINE uint32_t __get_CBAR() {
dkato 0:f782d9c66c49 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
dkato 0:f782d9c66c49 271 return(__regCBAR);
dkato 0:f782d9c66c49 272 }
dkato 0:f782d9c66c49 273
dkato 0:f782d9c66c49 274 /** \brief Get TTBR0
dkato 0:f782d9c66c49 275
dkato 0:f782d9c66c49 276 This function returns the value of the Translation Table Base Register 0.
dkato 0:f782d9c66c49 277
dkato 0:f782d9c66c49 278 \return Translation Table Base Register 0 value
dkato 0:f782d9c66c49 279 */
dkato 0:f782d9c66c49 280 __STATIC_INLINE uint32_t __get_TTBR0() {
dkato 0:f782d9c66c49 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
dkato 0:f782d9c66c49 282 return(__regTTBR0);
dkato 0:f782d9c66c49 283 }
dkato 0:f782d9c66c49 284
dkato 0:f782d9c66c49 285 /** \brief Set TTBR0
dkato 0:f782d9c66c49 286
dkato 0:f782d9c66c49 287 This function assigns the given value to the Translation Table Base Register 0.
dkato 0:f782d9c66c49 288
dkato 0:f782d9c66c49 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
dkato 0:f782d9c66c49 290 */
dkato 0:f782d9c66c49 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
dkato 0:f782d9c66c49 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
dkato 0:f782d9c66c49 293 __regTTBR0 = ttbr0;
dkato 0:f782d9c66c49 294 __ISB();
dkato 0:f782d9c66c49 295 }
dkato 0:f782d9c66c49 296
dkato 0:f782d9c66c49 297 /** \brief Get DACR
dkato 0:f782d9c66c49 298
dkato 0:f782d9c66c49 299 This function returns the value of the Domain Access Control Register.
dkato 0:f782d9c66c49 300
dkato 0:f782d9c66c49 301 \return Domain Access Control Register value
dkato 0:f782d9c66c49 302 */
dkato 0:f782d9c66c49 303 __STATIC_INLINE uint32_t __get_DACR() {
dkato 0:f782d9c66c49 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
dkato 0:f782d9c66c49 305 return(__regDACR);
dkato 0:f782d9c66c49 306 }
dkato 0:f782d9c66c49 307
dkato 0:f782d9c66c49 308 /** \brief Set DACR
dkato 0:f782d9c66c49 309
dkato 0:f782d9c66c49 310 This function assigns the given value to the Domain Access Control Register.
dkato 0:f782d9c66c49 311
dkato 0:f782d9c66c49 312 \param [in] dacr Domain Access Control Register value to set
dkato 0:f782d9c66c49 313 */
dkato 0:f782d9c66c49 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
dkato 0:f782d9c66c49 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
dkato 0:f782d9c66c49 316 __regDACR = dacr;
dkato 0:f782d9c66c49 317 __ISB();
dkato 0:f782d9c66c49 318 }
dkato 0:f782d9c66c49 319
dkato 0:f782d9c66c49 320 /******************************** Cache and BTAC enable ****************************************************/
dkato 0:f782d9c66c49 321
dkato 0:f782d9c66c49 322 /** \brief Set SCTLR
dkato 0:f782d9c66c49 323
dkato 0:f782d9c66c49 324 This function assigns the given value to the System Control Register.
dkato 0:f782d9c66c49 325
dkato 0:f782d9c66c49 326 \param [in] sctlr System Control Register value to set
dkato 0:f782d9c66c49 327 */
dkato 0:f782d9c66c49 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
dkato 0:f782d9c66c49 329 {
dkato 0:f782d9c66c49 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
dkato 0:f782d9c66c49 331 __regSCTLR = sctlr;
dkato 0:f782d9c66c49 332 }
dkato 0:f782d9c66c49 333
dkato 0:f782d9c66c49 334 /** \brief Get SCTLR
dkato 0:f782d9c66c49 335
dkato 0:f782d9c66c49 336 This function returns the value of the System Control Register.
dkato 0:f782d9c66c49 337
dkato 0:f782d9c66c49 338 \return System Control Register value
dkato 0:f782d9c66c49 339 */
dkato 0:f782d9c66c49 340 __STATIC_INLINE uint32_t __get_SCTLR() {
dkato 0:f782d9c66c49 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
dkato 0:f782d9c66c49 342 return(__regSCTLR);
dkato 0:f782d9c66c49 343 }
dkato 0:f782d9c66c49 344
dkato 0:f782d9c66c49 345 /** \brief Enable Caches
dkato 0:f782d9c66c49 346
dkato 0:f782d9c66c49 347 Enable Caches
dkato 0:f782d9c66c49 348 */
dkato 0:f782d9c66c49 349 __STATIC_INLINE void __enable_caches(void) {
dkato 0:f782d9c66c49 350 // Set I bit 12 to enable I Cache
dkato 0:f782d9c66c49 351 // Set C bit 2 to enable D Cache
dkato 0:f782d9c66c49 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
dkato 0:f782d9c66c49 353 }
dkato 0:f782d9c66c49 354
dkato 0:f782d9c66c49 355 /** \brief Disable Caches
dkato 0:f782d9c66c49 356
dkato 0:f782d9c66c49 357 Disable Caches
dkato 0:f782d9c66c49 358 */
dkato 0:f782d9c66c49 359 __STATIC_INLINE void __disable_caches(void) {
dkato 0:f782d9c66c49 360 // Clear I bit 12 to disable I Cache
dkato 0:f782d9c66c49 361 // Clear C bit 2 to disable D Cache
dkato 0:f782d9c66c49 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
dkato 0:f782d9c66c49 363 __ISB();
dkato 0:f782d9c66c49 364 }
dkato 0:f782d9c66c49 365
dkato 0:f782d9c66c49 366 /** \brief Enable BTAC
dkato 0:f782d9c66c49 367
dkato 0:f782d9c66c49 368 Enable BTAC
dkato 0:f782d9c66c49 369 */
dkato 0:f782d9c66c49 370 __STATIC_INLINE void __enable_btac(void) {
dkato 0:f782d9c66c49 371 // Set Z bit 11 to enable branch prediction
dkato 0:f782d9c66c49 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
dkato 0:f782d9c66c49 373 __ISB();
dkato 0:f782d9c66c49 374 }
dkato 0:f782d9c66c49 375
dkato 0:f782d9c66c49 376 /** \brief Disable BTAC
dkato 0:f782d9c66c49 377
dkato 0:f782d9c66c49 378 Disable BTAC
dkato 0:f782d9c66c49 379 */
dkato 0:f782d9c66c49 380 __STATIC_INLINE void __disable_btac(void) {
dkato 0:f782d9c66c49 381 // Clear Z bit 11 to disable branch prediction
dkato 0:f782d9c66c49 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
dkato 0:f782d9c66c49 383 }
dkato 0:f782d9c66c49 384
dkato 0:f782d9c66c49 385
dkato 0:f782d9c66c49 386 /** \brief Enable MMU
dkato 0:f782d9c66c49 387
dkato 0:f782d9c66c49 388 Enable MMU
dkato 0:f782d9c66c49 389 */
dkato 0:f782d9c66c49 390 __STATIC_INLINE void __enable_mmu(void) {
dkato 0:f782d9c66c49 391 // Set M bit 0 to enable the MMU
dkato 0:f782d9c66c49 392 // Set AFE bit to enable simplified access permissions model
dkato 0:f782d9c66c49 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
dkato 0:f782d9c66c49 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
dkato 0:f782d9c66c49 395 __ISB();
dkato 0:f782d9c66c49 396 }
dkato 0:f782d9c66c49 397
dkato 0:f782d9c66c49 398 /** \brief Disable MMU
dkato 0:f782d9c66c49 399
dkato 0:f782d9c66c49 400 Disable MMU
dkato 0:f782d9c66c49 401 */
dkato 0:f782d9c66c49 402 __STATIC_INLINE void __disable_mmu(void) {
dkato 0:f782d9c66c49 403 // Clear M bit 0 to disable the MMU
dkato 0:f782d9c66c49 404 __set_SCTLR( __get_SCTLR() & ~1);
dkato 0:f782d9c66c49 405 __ISB();
dkato 0:f782d9c66c49 406 }
dkato 0:f782d9c66c49 407
dkato 0:f782d9c66c49 408 /******************************** TLB maintenance operations ************************************************/
dkato 0:f782d9c66c49 409 /** \brief Invalidate the whole tlb
dkato 0:f782d9c66c49 410
dkato 0:f782d9c66c49 411 TLBIALL. Invalidate the whole tlb
dkato 0:f782d9c66c49 412 */
dkato 0:f782d9c66c49 413
dkato 0:f782d9c66c49 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
dkato 0:f782d9c66c49 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
dkato 0:f782d9c66c49 416 __TLBIALL = 0;
dkato 0:f782d9c66c49 417 __DSB();
dkato 0:f782d9c66c49 418 __ISB();
dkato 0:f782d9c66c49 419 }
dkato 0:f782d9c66c49 420
dkato 0:f782d9c66c49 421 /******************************** BTB maintenance operations ************************************************/
dkato 0:f782d9c66c49 422 /** \brief Invalidate entire branch predictor array
dkato 0:f782d9c66c49 423
dkato 0:f782d9c66c49 424 BPIALL. Branch Predictor Invalidate All.
dkato 0:f782d9c66c49 425 */
dkato 0:f782d9c66c49 426
dkato 0:f782d9c66c49 427 __STATIC_INLINE void __v7_inv_btac(void) {
dkato 0:f782d9c66c49 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
dkato 0:f782d9c66c49 429 __BPIALL = 0;
dkato 0:f782d9c66c49 430 __DSB(); //ensure completion of the invalidation
dkato 0:f782d9c66c49 431 __ISB(); //ensure instruction fetch path sees new state
dkato 0:f782d9c66c49 432 }
dkato 0:f782d9c66c49 433
dkato 0:f782d9c66c49 434
dkato 0:f782d9c66c49 435 /******************************** L1 cache operations ******************************************************/
dkato 0:f782d9c66c49 436
dkato 0:f782d9c66c49 437 /** \brief Invalidate the whole I$
dkato 0:f782d9c66c49 438
dkato 0:f782d9c66c49 439 ICIALLU. Instruction Cache Invalidate All to PoU
dkato 0:f782d9c66c49 440 */
dkato 0:f782d9c66c49 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
dkato 0:f782d9c66c49 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
dkato 0:f782d9c66c49 443 __ICIALLU = 0;
dkato 0:f782d9c66c49 444 __DSB(); //ensure completion of the invalidation
dkato 0:f782d9c66c49 445 __ISB(); //ensure instruction fetch path sees new I cache state
dkato 0:f782d9c66c49 446 }
dkato 0:f782d9c66c49 447
dkato 0:f782d9c66c49 448 /** \brief Clean D$ by MVA
dkato 0:f782d9c66c49 449
dkato 0:f782d9c66c49 450 DCCMVAC. Data cache clean by MVA to PoC
dkato 0:f782d9c66c49 451 */
dkato 0:f782d9c66c49 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
dkato 0:f782d9c66c49 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
dkato 0:f782d9c66c49 454 __DCCMVAC = (uint32_t)va;
dkato 0:f782d9c66c49 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
dkato 0:f782d9c66c49 456 }
dkato 0:f782d9c66c49 457
dkato 0:f782d9c66c49 458 /** \brief Invalidate D$ by MVA
dkato 0:f782d9c66c49 459
dkato 0:f782d9c66c49 460 DCIMVAC. Data cache invalidate by MVA to PoC
dkato 0:f782d9c66c49 461 */
dkato 0:f782d9c66c49 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
dkato 0:f782d9c66c49 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
dkato 0:f782d9c66c49 464 __DCIMVAC = (uint32_t)va;
dkato 0:f782d9c66c49 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
dkato 0:f782d9c66c49 466 }
dkato 0:f782d9c66c49 467
dkato 0:f782d9c66c49 468 /** \brief Clean and Invalidate D$ by MVA
dkato 0:f782d9c66c49 469
dkato 0:f782d9c66c49 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
dkato 0:f782d9c66c49 471 */
dkato 0:f782d9c66c49 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
dkato 0:f782d9c66c49 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
dkato 0:f782d9c66c49 474 __DCCIMVAC = (uint32_t)va;
dkato 0:f782d9c66c49 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
dkato 0:f782d9c66c49 476 }
dkato 0:f782d9c66c49 477
dkato 0:f782d9c66c49 478 /** \brief Clean and Invalidate the entire data or unified cache
dkato 0:f782d9c66c49 479
dkato 0:f782d9c66c49 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
dkato 0:f782d9c66c49 481 */
dkato 0:f782d9c66c49 482 #pragma push
dkato 0:f782d9c66c49 483 #pragma arm
dkato 0:f782d9c66c49 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
dkato 0:f782d9c66c49 485 ARM
dkato 0:f782d9c66c49 486
dkato 0:f782d9c66c49 487 PUSH {R4-R11}
dkato 0:f782d9c66c49 488
dkato 0:f782d9c66c49 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
dkato 0:f782d9c66c49 490 ANDS R3, R6, #0x07000000 // Extract coherency level
dkato 0:f782d9c66c49 491 MOV R3, R3, LSR #23 // Total cache levels << 1
dkato 0:f782d9c66c49 492 BEQ Finished // If 0, no need to clean
dkato 0:f782d9c66c49 493
dkato 0:f782d9c66c49 494 MOV R10, #0 // R10 holds current cache level << 1
dkato 0:f782d9c66c49 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
dkato 0:f782d9c66c49 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
dkato 0:f782d9c66c49 497 AND R1, R1, #7 // Isolate those lower 3 bits
dkato 0:f782d9c66c49 498 CMP R1, #2
dkato 0:f782d9c66c49 499 BLT Skip // No cache or only instruction cache at this level
dkato 0:f782d9c66c49 500
dkato 0:f782d9c66c49 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
dkato 0:f782d9c66c49 502 ISB // ISB to sync the change to the CacheSizeID reg
dkato 0:f782d9c66c49 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
dkato 0:f782d9c66c49 504 AND R2, R1, #7 // Extract the line length field
dkato 0:f782d9c66c49 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
dkato 0:f782d9c66c49 506 LDR R4, =0x3FF
dkato 0:f782d9c66c49 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
dkato 0:f782d9c66c49 508 CLZ R5, R4 // R5 is the bit position of the way size increment
dkato 0:f782d9c66c49 509 LDR R7, =0x7FFF
dkato 0:f782d9c66c49 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
dkato 0:f782d9c66c49 511
dkato 0:f782d9c66c49 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
dkato 0:f782d9c66c49 513
dkato 0:f782d9c66c49 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
dkato 0:f782d9c66c49 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
dkato 0:f782d9c66c49 516 CMP R0, #0
dkato 0:f782d9c66c49 517 BNE Dccsw
dkato 0:f782d9c66c49 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
dkato 0:f782d9c66c49 519 B cont
dkato 0:f782d9c66c49 520 Dccsw CMP R0, #1
dkato 0:f782d9c66c49 521 BNE Dccisw
dkato 0:f782d9c66c49 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
dkato 0:f782d9c66c49 523 B cont
dkato 0:f782d9c66c49 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
dkato 0:f782d9c66c49 525 cont SUBS R9, R9, #1 // Decrement the Way number
dkato 0:f782d9c66c49 526 BGE Loop3
dkato 0:f782d9c66c49 527 SUBS R7, R7, #1 // Decrement the Set number
dkato 0:f782d9c66c49 528 BGE Loop2
dkato 0:f782d9c66c49 529 Skip ADD R10, R10, #2 // Increment the cache number
dkato 0:f782d9c66c49 530 CMP R3, R10
dkato 0:f782d9c66c49 531 BGT Loop1
dkato 0:f782d9c66c49 532
dkato 0:f782d9c66c49 533 Finished
dkato 0:f782d9c66c49 534 DSB
dkato 0:f782d9c66c49 535 POP {R4-R11}
dkato 0:f782d9c66c49 536 BX lr
dkato 0:f782d9c66c49 537
dkato 0:f782d9c66c49 538 }
dkato 0:f782d9c66c49 539 #pragma pop
dkato 0:f782d9c66c49 540
dkato 0:f782d9c66c49 541
dkato 0:f782d9c66c49 542 /** \brief Invalidate the whole D$
dkato 0:f782d9c66c49 543
dkato 0:f782d9c66c49 544 DCISW. Invalidate by Set/Way
dkato 0:f782d9c66c49 545 */
dkato 0:f782d9c66c49 546
dkato 0:f782d9c66c49 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
dkato 0:f782d9c66c49 548 __v7_all_cache(0);
dkato 0:f782d9c66c49 549 }
dkato 0:f782d9c66c49 550
dkato 0:f782d9c66c49 551 /** \brief Clean the whole D$
dkato 0:f782d9c66c49 552
dkato 0:f782d9c66c49 553 DCCSW. Clean by Set/Way
dkato 0:f782d9c66c49 554 */
dkato 0:f782d9c66c49 555
dkato 0:f782d9c66c49 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
dkato 0:f782d9c66c49 557 __v7_all_cache(1);
dkato 0:f782d9c66c49 558 }
dkato 0:f782d9c66c49 559
dkato 0:f782d9c66c49 560 /** \brief Clean and invalidate the whole D$
dkato 0:f782d9c66c49 561
dkato 0:f782d9c66c49 562 DCCISW. Clean and Invalidate by Set/Way
dkato 0:f782d9c66c49 563 */
dkato 0:f782d9c66c49 564
dkato 0:f782d9c66c49 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
dkato 0:f782d9c66c49 566 __v7_all_cache(2);
dkato 0:f782d9c66c49 567 }
dkato 0:f782d9c66c49 568
dkato 0:f782d9c66c49 569 #include "core_ca_mmu.h"
dkato 0:f782d9c66c49 570
dkato 0:f782d9c66c49 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
dkato 0:f782d9c66c49 572
dkato 0:f782d9c66c49 573 #define __inline inline
dkato 0:f782d9c66c49 574
dkato 0:f782d9c66c49 575 inline static uint32_t __disable_irq_iar() {
dkato 0:f782d9c66c49 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
dkato 0:f782d9c66c49 577 __disable_irq();
dkato 0:f782d9c66c49 578 return irq_dis;
dkato 0:f782d9c66c49 579 }
dkato 0:f782d9c66c49 580
dkato 0:f782d9c66c49 581 #define MODE_USR 0x10
dkato 0:f782d9c66c49 582 #define MODE_FIQ 0x11
dkato 0:f782d9c66c49 583 #define MODE_IRQ 0x12
dkato 0:f782d9c66c49 584 #define MODE_SVC 0x13
dkato 0:f782d9c66c49 585 #define MODE_MON 0x16
dkato 0:f782d9c66c49 586 #define MODE_ABT 0x17
dkato 0:f782d9c66c49 587 #define MODE_HYP 0x1A
dkato 0:f782d9c66c49 588 #define MODE_UND 0x1B
dkato 0:f782d9c66c49 589 #define MODE_SYS 0x1F
dkato 0:f782d9c66c49 590
dkato 0:f782d9c66c49 591 /** \brief Set Process Stack Pointer
dkato 0:f782d9c66c49 592
dkato 0:f782d9c66c49 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
dkato 0:f782d9c66c49 594
dkato 0:f782d9c66c49 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
dkato 0:f782d9c66c49 596 */
dkato 0:f782d9c66c49 597 // from rt_CMSIS.c
dkato 0:f782d9c66c49 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
dkato 0:f782d9c66c49 599 __asm(
dkato 0:f782d9c66c49 600 " ARM\n"
dkato 0:f782d9c66c49 601 // " PRESERVE8\n"
dkato 0:f782d9c66c49 602
dkato 0:f782d9c66c49 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
dkato 0:f782d9c66c49 604 " MRS R1, CPSR \n"
dkato 0:f782d9c66c49 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
dkato 0:f782d9c66c49 606 " MOV SP, R0 \n"
dkato 0:f782d9c66c49 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
dkato 0:f782d9c66c49 608 " ISB \n"
dkato 0:f782d9c66c49 609 " BX LR \n");
dkato 0:f782d9c66c49 610 }
dkato 0:f782d9c66c49 611
dkato 0:f782d9c66c49 612 /** \brief Set User Mode
dkato 0:f782d9c66c49 613
dkato 0:f782d9c66c49 614 This function changes the processor state to User Mode
dkato 0:f782d9c66c49 615 */
dkato 0:f782d9c66c49 616 // from rt_CMSIS.c
dkato 0:f782d9c66c49 617 __arm static inline void __set_CPS_USR(void) {
dkato 0:f782d9c66c49 618 __asm(
dkato 0:f782d9c66c49 619 " ARM \n"
dkato 0:f782d9c66c49 620
dkato 0:f782d9c66c49 621 " CPS #0x10 \n" // MODE_USR
dkato 0:f782d9c66c49 622 " BX LR\n");
dkato 0:f782d9c66c49 623 }
dkato 0:f782d9c66c49 624
dkato 0:f782d9c66c49 625 /** \brief Set TTBR0
dkato 0:f782d9c66c49 626
dkato 0:f782d9c66c49 627 This function assigns the given value to the Translation Table Base Register 0.
dkato 0:f782d9c66c49 628
dkato 0:f782d9c66c49 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
dkato 0:f782d9c66c49 630 */
dkato 0:f782d9c66c49 631 // from mmu_Renesas_RZ_A1.c
dkato 0:f782d9c66c49 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
dkato 0:f782d9c66c49 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
dkato 0:f782d9c66c49 634 __ISB();
dkato 0:f782d9c66c49 635 }
dkato 0:f782d9c66c49 636
dkato 0:f782d9c66c49 637 /** \brief Set DACR
dkato 0:f782d9c66c49 638
dkato 0:f782d9c66c49 639 This function assigns the given value to the Domain Access Control Register.
dkato 0:f782d9c66c49 640
dkato 0:f782d9c66c49 641 \param [in] dacr Domain Access Control Register value to set
dkato 0:f782d9c66c49 642 */
dkato 0:f782d9c66c49 643 // from mmu_Renesas_RZ_A1.c
dkato 0:f782d9c66c49 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
dkato 0:f782d9c66c49 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
dkato 0:f782d9c66c49 646 __ISB();
dkato 0:f782d9c66c49 647 }
dkato 0:f782d9c66c49 648
dkato 0:f782d9c66c49 649
dkato 0:f782d9c66c49 650 /******************************** Cache and BTAC enable ****************************************************/
dkato 0:f782d9c66c49 651 /** \brief Set SCTLR
dkato 0:f782d9c66c49 652
dkato 0:f782d9c66c49 653 This function assigns the given value to the System Control Register.
dkato 0:f782d9c66c49 654
dkato 0:f782d9c66c49 655 \param [in] sctlr System Control Register value to set
dkato 0:f782d9c66c49 656 */
dkato 0:f782d9c66c49 657 // from __enable_mmu()
dkato 0:f782d9c66c49 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
dkato 0:f782d9c66c49 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
dkato 0:f782d9c66c49 660 }
dkato 0:f782d9c66c49 661
dkato 0:f782d9c66c49 662 /** \brief Get SCTLR
dkato 0:f782d9c66c49 663
dkato 0:f782d9c66c49 664 This function returns the value of the System Control Register.
dkato 0:f782d9c66c49 665
dkato 0:f782d9c66c49 666 \return System Control Register value
dkato 0:f782d9c66c49 667 */
dkato 0:f782d9c66c49 668 // from __enable_mmu()
dkato 0:f782d9c66c49 669 __STATIC_INLINE uint32_t __get_SCTLR() {
dkato 0:f782d9c66c49 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
dkato 0:f782d9c66c49 671 return __regSCTLR;
dkato 0:f782d9c66c49 672 }
dkato 0:f782d9c66c49 673
dkato 0:f782d9c66c49 674 /** \brief Enable Caches
dkato 0:f782d9c66c49 675
dkato 0:f782d9c66c49 676 Enable Caches
dkato 0:f782d9c66c49 677 */
dkato 0:f782d9c66c49 678 // from system_Renesas_RZ_A1.c
dkato 0:f782d9c66c49 679 __STATIC_INLINE void __enable_caches(void) {
dkato 0:f782d9c66c49 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
dkato 0:f782d9c66c49 681 }
dkato 0:f782d9c66c49 682
dkato 0:f782d9c66c49 683 /** \brief Enable BTAC
dkato 0:f782d9c66c49 684
dkato 0:f782d9c66c49 685 Enable BTAC
dkato 0:f782d9c66c49 686 */
dkato 0:f782d9c66c49 687 // from system_Renesas_RZ_A1.c
dkato 0:f782d9c66c49 688 __STATIC_INLINE void __enable_btac(void) {
dkato 0:f782d9c66c49 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
dkato 0:f782d9c66c49 690 __ISB();
dkato 0:f782d9c66c49 691 }
dkato 0:f782d9c66c49 692
dkato 0:f782d9c66c49 693 /** \brief Enable MMU
dkato 0:f782d9c66c49 694
dkato 0:f782d9c66c49 695 Enable MMU
dkato 0:f782d9c66c49 696 */
dkato 0:f782d9c66c49 697 // from system_Renesas_RZ_A1.c
dkato 0:f782d9c66c49 698 __STATIC_INLINE void __enable_mmu(void) {
dkato 0:f782d9c66c49 699 // Set M bit 0 to enable the MMU
dkato 0:f782d9c66c49 700 // Set AFE bit to enable simplified access permissions model
dkato 0:f782d9c66c49 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
dkato 0:f782d9c66c49 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
dkato 0:f782d9c66c49 703 __ISB();
dkato 0:f782d9c66c49 704 }
dkato 0:f782d9c66c49 705
dkato 0:f782d9c66c49 706 /******************************** TLB maintenance operations ************************************************/
dkato 0:f782d9c66c49 707 /** \brief Invalidate the whole tlb
dkato 0:f782d9c66c49 708
dkato 0:f782d9c66c49 709 TLBIALL. Invalidate the whole tlb
dkato 0:f782d9c66c49 710 */
dkato 0:f782d9c66c49 711 // from system_Renesas_RZ_A1.c
dkato 0:f782d9c66c49 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
dkato 0:f782d9c66c49 713 uint32_t val = 0;
dkato 0:f782d9c66c49 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
dkato 0:f782d9c66c49 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
dkato 0:f782d9c66c49 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
dkato 0:f782d9c66c49 717 __DSB();
dkato 0:f782d9c66c49 718 __ISB();
dkato 0:f782d9c66c49 719 }
dkato 0:f782d9c66c49 720
dkato 0:f782d9c66c49 721 /******************************** BTB maintenance operations ************************************************/
dkato 0:f782d9c66c49 722 /** \brief Invalidate entire branch predictor array
dkato 0:f782d9c66c49 723
dkato 0:f782d9c66c49 724 BPIALL. Branch Predictor Invalidate All.
dkato 0:f782d9c66c49 725 */
dkato 0:f782d9c66c49 726 // from system_Renesas_RZ_A1.c
dkato 0:f782d9c66c49 727 __STATIC_INLINE void __v7_inv_btac(void) {
dkato 0:f782d9c66c49 728 uint32_t val = 0;
dkato 0:f782d9c66c49 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
dkato 0:f782d9c66c49 730 __DSB(); //ensure completion of the invalidation
dkato 0:f782d9c66c49 731 __ISB(); //ensure instruction fetch path sees new state
dkato 0:f782d9c66c49 732 }
dkato 0:f782d9c66c49 733
dkato 0:f782d9c66c49 734
dkato 0:f782d9c66c49 735 /******************************** L1 cache operations ******************************************************/
dkato 0:f782d9c66c49 736
dkato 0:f782d9c66c49 737 /** \brief Invalidate the whole I$
dkato 0:f782d9c66c49 738
dkato 0:f782d9c66c49 739 ICIALLU. Instruction Cache Invalidate All to PoU
dkato 0:f782d9c66c49 740 */
dkato 0:f782d9c66c49 741 // from system_Renesas_RZ_A1.c
dkato 0:f782d9c66c49 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
dkato 0:f782d9c66c49 743 uint32_t val = 0;
dkato 0:f782d9c66c49 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
dkato 0:f782d9c66c49 745 __DSB(); //ensure completion of the invalidation
dkato 0:f782d9c66c49 746 __ISB(); //ensure instruction fetch path sees new I cache state
dkato 0:f782d9c66c49 747 }
dkato 0:f782d9c66c49 748
dkato 0:f782d9c66c49 749 // from __v7_inv_dcache_all()
dkato 0:f782d9c66c49 750 __arm static inline void __v7_all_cache(uint32_t op) {
dkato 0:f782d9c66c49 751 __asm(
dkato 0:f782d9c66c49 752 " ARM \n"
dkato 0:f782d9c66c49 753
dkato 0:f782d9c66c49 754 " PUSH {R4-R11} \n"
dkato 0:f782d9c66c49 755
dkato 0:f782d9c66c49 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
dkato 0:f782d9c66c49 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
dkato 0:f782d9c66c49 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
dkato 0:f782d9c66c49 759 " BEQ Finished\n" // If 0, no need to clean
dkato 0:f782d9c66c49 760
dkato 0:f782d9c66c49 761 " MOV R10, #0\n" // R10 holds current cache level << 1
dkato 0:f782d9c66c49 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
dkato 0:f782d9c66c49 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
dkato 0:f782d9c66c49 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
dkato 0:f782d9c66c49 765 " CMP R1, #2 \n"
dkato 0:f782d9c66c49 766 " BLT Skip \n" // No cache or only instruction cache at this level
dkato 0:f782d9c66c49 767
dkato 0:f782d9c66c49 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
dkato 0:f782d9c66c49 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
dkato 0:f782d9c66c49 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
dkato 0:f782d9c66c49 771 " AND R2, R1, #7 \n" // Extract the line length field
dkato 0:f782d9c66c49 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
dkato 0:f782d9c66c49 773 " movw R4, #0x3FF \n"
dkato 0:f782d9c66c49 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
dkato 0:f782d9c66c49 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
dkato 0:f782d9c66c49 776 " movw R7, #0x7FFF \n"
dkato 0:f782d9c66c49 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
dkato 0:f782d9c66c49 778
dkato 0:f782d9c66c49 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
dkato 0:f782d9c66c49 780
dkato 0:f782d9c66c49 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
dkato 0:f782d9c66c49 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
dkato 0:f782d9c66c49 783 " CMP R0, #0 \n"
dkato 0:f782d9c66c49 784 " BNE Dccsw \n"
dkato 0:f782d9c66c49 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
dkato 0:f782d9c66c49 786 " B cont \n"
dkato 0:f782d9c66c49 787 "Dccsw: CMP R0, #1 \n"
dkato 0:f782d9c66c49 788 " BNE Dccisw \n"
dkato 0:f782d9c66c49 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
dkato 0:f782d9c66c49 790 " B cont \n"
dkato 0:f782d9c66c49 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
dkato 0:f782d9c66c49 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
dkato 0:f782d9c66c49 793 " BGE Loop3 \n"
dkato 0:f782d9c66c49 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
dkato 0:f782d9c66c49 795 " BGE Loop2 \n"
dkato 0:f782d9c66c49 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
dkato 0:f782d9c66c49 797 " CMP R3, R10 \n"
dkato 0:f782d9c66c49 798 " BGT Loop1 \n"
dkato 0:f782d9c66c49 799
dkato 0:f782d9c66c49 800 "Finished: \n"
dkato 0:f782d9c66c49 801 " DSB \n"
dkato 0:f782d9c66c49 802 " POP {R4-R11} \n"
dkato 0:f782d9c66c49 803 " BX lr \n" );
dkato 0:f782d9c66c49 804 }
dkato 0:f782d9c66c49 805
dkato 0:f782d9c66c49 806 /** \brief Invalidate the whole D$
dkato 0:f782d9c66c49 807
dkato 0:f782d9c66c49 808 DCISW. Invalidate by Set/Way
dkato 0:f782d9c66c49 809 */
dkato 0:f782d9c66c49 810 // from system_Renesas_RZ_A1.c
dkato 0:f782d9c66c49 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
dkato 0:f782d9c66c49 812 __v7_all_cache(0);
dkato 0:f782d9c66c49 813 }
dkato 0:f782d9c66c49 814 /** \brief Clean the whole D$
dkato 0:f782d9c66c49 815
dkato 0:f782d9c66c49 816 DCCSW. Clean by Set/Way
dkato 0:f782d9c66c49 817 */
dkato 0:f782d9c66c49 818
dkato 0:f782d9c66c49 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
dkato 0:f782d9c66c49 820 __v7_all_cache(1);
dkato 0:f782d9c66c49 821 }
dkato 0:f782d9c66c49 822
dkato 0:f782d9c66c49 823 /** \brief Clean and invalidate the whole D$
dkato 0:f782d9c66c49 824
dkato 0:f782d9c66c49 825 DCCISW. Clean and Invalidate by Set/Way
dkato 0:f782d9c66c49 826 */
dkato 0:f782d9c66c49 827
dkato 0:f782d9c66c49 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
dkato 0:f782d9c66c49 829 __v7_all_cache(2);
dkato 0:f782d9c66c49 830 }
dkato 0:f782d9c66c49 831 /** \brief Clean and Invalidate D$ by MVA
dkato 0:f782d9c66c49 832
dkato 0:f782d9c66c49 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
dkato 0:f782d9c66c49 834 */
dkato 0:f782d9c66c49 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
dkato 0:f782d9c66c49 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
dkato 0:f782d9c66c49 837 __DMB();
dkato 0:f782d9c66c49 838 }
dkato 0:f782d9c66c49 839
dkato 0:f782d9c66c49 840 #include "core_ca_mmu.h"
dkato 0:f782d9c66c49 841
dkato 0:f782d9c66c49 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
dkato 0:f782d9c66c49 843 /* GNU gcc specific functions */
dkato 0:f782d9c66c49 844
dkato 0:f782d9c66c49 845 #define MODE_USR 0x10
dkato 0:f782d9c66c49 846 #define MODE_FIQ 0x11
dkato 0:f782d9c66c49 847 #define MODE_IRQ 0x12
dkato 0:f782d9c66c49 848 #define MODE_SVC 0x13
dkato 0:f782d9c66c49 849 #define MODE_MON 0x16
dkato 0:f782d9c66c49 850 #define MODE_ABT 0x17
dkato 0:f782d9c66c49 851 #define MODE_HYP 0x1A
dkato 0:f782d9c66c49 852 #define MODE_UND 0x1B
dkato 0:f782d9c66c49 853 #define MODE_SYS 0x1F
dkato 0:f782d9c66c49 854
dkato 0:f782d9c66c49 855
dkato 0:f782d9c66c49 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
dkato 0:f782d9c66c49 857 {
dkato 0:f782d9c66c49 858 __ASM volatile ("cpsie i");
dkato 0:f782d9c66c49 859 }
dkato 0:f782d9c66c49 860
dkato 0:f782d9c66c49 861 /** \brief Disable IRQ Interrupts
dkato 0:f782d9c66c49 862
dkato 0:f782d9c66c49 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
dkato 0:f782d9c66c49 864 Can only be executed in Privileged modes.
dkato 0:f782d9c66c49 865 */
dkato 0:f782d9c66c49 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
dkato 0:f782d9c66c49 867 {
dkato 0:f782d9c66c49 868 uint32_t result;
dkato 0:f782d9c66c49 869
dkato 0:f782d9c66c49 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
dkato 0:f782d9c66c49 871 __ASM volatile ("cpsid i");
dkato 0:f782d9c66c49 872 return(result & 0x80);
dkato 0:f782d9c66c49 873 }
dkato 0:f782d9c66c49 874
dkato 0:f782d9c66c49 875
dkato 0:f782d9c66c49 876 /** \brief Get APSR Register
dkato 0:f782d9c66c49 877
dkato 0:f782d9c66c49 878 This function returns the content of the APSR Register.
dkato 0:f782d9c66c49 879
dkato 0:f782d9c66c49 880 \return APSR Register value
dkato 0:f782d9c66c49 881 */
dkato 0:f782d9c66c49 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
dkato 0:f782d9c66c49 883 {
dkato 0:f782d9c66c49 884 #if 1
dkato 0:f782d9c66c49 885 register uint32_t __regAPSR;
dkato 0:f782d9c66c49 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
dkato 0:f782d9c66c49 887 #else
dkato 0:f782d9c66c49 888 register uint32_t __regAPSR __ASM("apsr");
dkato 0:f782d9c66c49 889 #endif
dkato 0:f782d9c66c49 890 return(__regAPSR);
dkato 0:f782d9c66c49 891 }
dkato 0:f782d9c66c49 892
dkato 0:f782d9c66c49 893
dkato 0:f782d9c66c49 894 /** \brief Get CPSR Register
dkato 0:f782d9c66c49 895
dkato 0:f782d9c66c49 896 This function returns the content of the CPSR Register.
dkato 0:f782d9c66c49 897
dkato 0:f782d9c66c49 898 \return CPSR Register value
dkato 0:f782d9c66c49 899 */
dkato 0:f782d9c66c49 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
dkato 0:f782d9c66c49 901 {
dkato 0:f782d9c66c49 902 #if 1
dkato 0:f782d9c66c49 903 register uint32_t __regCPSR;
dkato 0:f782d9c66c49 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
dkato 0:f782d9c66c49 905 #else
dkato 0:f782d9c66c49 906 register uint32_t __regCPSR __ASM("cpsr");
dkato 0:f782d9c66c49 907 #endif
dkato 0:f782d9c66c49 908 return(__regCPSR);
dkato 0:f782d9c66c49 909 }
dkato 0:f782d9c66c49 910
dkato 0:f782d9c66c49 911 #if 0
dkato 0:f782d9c66c49 912 /** \brief Set Stack Pointer
dkato 0:f782d9c66c49 913
dkato 0:f782d9c66c49 914 This function assigns the given value to the current stack pointer.
dkato 0:f782d9c66c49 915
dkato 0:f782d9c66c49 916 \param [in] topOfStack Stack Pointer value to set
dkato 0:f782d9c66c49 917 */
dkato 0:f782d9c66c49 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
dkato 0:f782d9c66c49 919 {
dkato 0:f782d9c66c49 920 register uint32_t __regSP __ASM("sp");
dkato 0:f782d9c66c49 921 __regSP = topOfStack;
dkato 0:f782d9c66c49 922 }
dkato 0:f782d9c66c49 923 #endif
dkato 0:f782d9c66c49 924
dkato 0:f782d9c66c49 925 /** \brief Get link register
dkato 0:f782d9c66c49 926
dkato 0:f782d9c66c49 927 This function returns the value of the link register
dkato 0:f782d9c66c49 928
dkato 0:f782d9c66c49 929 \return Value of link register
dkato 0:f782d9c66c49 930 */
dkato 0:f782d9c66c49 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
dkato 0:f782d9c66c49 932 {
dkato 0:f782d9c66c49 933 register uint32_t __reglr __ASM("lr");
dkato 0:f782d9c66c49 934 return(__reglr);
dkato 0:f782d9c66c49 935 }
dkato 0:f782d9c66c49 936
dkato 0:f782d9c66c49 937 #if 0
dkato 0:f782d9c66c49 938 /** \brief Set link register
dkato 0:f782d9c66c49 939
dkato 0:f782d9c66c49 940 This function sets the value of the link register
dkato 0:f782d9c66c49 941
dkato 0:f782d9c66c49 942 \param [in] lr LR value to set
dkato 0:f782d9c66c49 943 */
dkato 0:f782d9c66c49 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
dkato 0:f782d9c66c49 945 {
dkato 0:f782d9c66c49 946 register uint32_t __reglr __ASM("lr");
dkato 0:f782d9c66c49 947 __reglr = lr;
dkato 0:f782d9c66c49 948 }
dkato 0:f782d9c66c49 949 #endif
dkato 0:f782d9c66c49 950
dkato 0:f782d9c66c49 951 /** \brief Set Process Stack Pointer
dkato 0:f782d9c66c49 952
dkato 0:f782d9c66c49 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
dkato 0:f782d9c66c49 954
dkato 0:f782d9c66c49 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
dkato 0:f782d9c66c49 956 */
dkato 0:f782d9c66c49 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
dkato 0:f782d9c66c49 958 {
dkato 0:f782d9c66c49 959 __asm__ volatile (
dkato 0:f782d9c66c49 960 ".ARM;"
dkato 0:f782d9c66c49 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
dkato 0:f782d9c66c49 962
dkato 0:f782d9c66c49 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
dkato 0:f782d9c66c49 964 "MRS R1, CPSR;"
dkato 0:f782d9c66c49 965 "CPS %0;" /* ;no effect in USR mode */
dkato 0:f782d9c66c49 966 "MOV SP, R0;"
dkato 0:f782d9c66c49 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
dkato 0:f782d9c66c49 968 "ISB;"
dkato 0:f782d9c66c49 969 //"BX LR;"
dkato 0:f782d9c66c49 970 :
dkato 0:f782d9c66c49 971 : "i"(MODE_SYS)
dkato 0:f782d9c66c49 972 : "r0", "r1");
dkato 0:f782d9c66c49 973 return;
dkato 0:f782d9c66c49 974 }
dkato 0:f782d9c66c49 975
dkato 0:f782d9c66c49 976 /** \brief Set User Mode
dkato 0:f782d9c66c49 977
dkato 0:f782d9c66c49 978 This function changes the processor state to User Mode
dkato 0:f782d9c66c49 979 */
dkato 0:f782d9c66c49 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
dkato 0:f782d9c66c49 981 {
dkato 0:f782d9c66c49 982 __asm__ volatile (
dkato 0:f782d9c66c49 983 ".ARM;"
dkato 0:f782d9c66c49 984
dkato 0:f782d9c66c49 985 "CPS %0;"
dkato 0:f782d9c66c49 986 //"BX LR;"
dkato 0:f782d9c66c49 987 :
dkato 0:f782d9c66c49 988 : "i"(MODE_USR)
dkato 0:f782d9c66c49 989 : );
dkato 0:f782d9c66c49 990 return;
dkato 0:f782d9c66c49 991 }
dkato 0:f782d9c66c49 992
dkato 0:f782d9c66c49 993
dkato 0:f782d9c66c49 994 /** \brief Enable FIQ
dkato 0:f782d9c66c49 995
dkato 0:f782d9c66c49 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
dkato 0:f782d9c66c49 997 Can only be executed in Privileged modes.
dkato 0:f782d9c66c49 998 */
dkato 0:f782d9c66c49 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
dkato 0:f782d9c66c49 1000
dkato 0:f782d9c66c49 1001
dkato 0:f782d9c66c49 1002 /** \brief Disable FIQ
dkato 0:f782d9c66c49 1003
dkato 0:f782d9c66c49 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
dkato 0:f782d9c66c49 1005 Can only be executed in Privileged modes.
dkato 0:f782d9c66c49 1006 */
dkato 0:f782d9c66c49 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
dkato 0:f782d9c66c49 1008
dkato 0:f782d9c66c49 1009
dkato 0:f782d9c66c49 1010 /** \brief Get FPSCR
dkato 0:f782d9c66c49 1011
dkato 0:f782d9c66c49 1012 This function returns the current value of the Floating Point Status/Control register.
dkato 0:f782d9c66c49 1013
dkato 0:f782d9c66c49 1014 \return Floating Point Status/Control register value
dkato 0:f782d9c66c49 1015 */
dkato 0:f782d9c66c49 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
dkato 0:f782d9c66c49 1017 {
dkato 0:f782d9c66c49 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
dkato 0:f782d9c66c49 1019 #if 1
dkato 0:f782d9c66c49 1020 uint32_t result;
dkato 0:f782d9c66c49 1021
dkato 0:f782d9c66c49 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
dkato 0:f782d9c66c49 1023 return (result);
dkato 0:f782d9c66c49 1024 #else
dkato 0:f782d9c66c49 1025 register uint32_t __regfpscr __ASM("fpscr");
dkato 0:f782d9c66c49 1026 return(__regfpscr);
dkato 0:f782d9c66c49 1027 #endif
dkato 0:f782d9c66c49 1028 #else
dkato 0:f782d9c66c49 1029 return(0);
dkato 0:f782d9c66c49 1030 #endif
dkato 0:f782d9c66c49 1031 }
dkato 0:f782d9c66c49 1032
dkato 0:f782d9c66c49 1033
dkato 0:f782d9c66c49 1034 /** \brief Set FPSCR
dkato 0:f782d9c66c49 1035
dkato 0:f782d9c66c49 1036 This function assigns the given value to the Floating Point Status/Control register.
dkato 0:f782d9c66c49 1037
dkato 0:f782d9c66c49 1038 \param [in] fpscr Floating Point Status/Control value to set
dkato 0:f782d9c66c49 1039 */
dkato 0:f782d9c66c49 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
dkato 0:f782d9c66c49 1041 {
dkato 0:f782d9c66c49 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
dkato 0:f782d9c66c49 1043 #if 1
dkato 0:f782d9c66c49 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
dkato 0:f782d9c66c49 1045 #else
dkato 0:f782d9c66c49 1046 register uint32_t __regfpscr __ASM("fpscr");
dkato 0:f782d9c66c49 1047 __regfpscr = (fpscr);
dkato 0:f782d9c66c49 1048 #endif
dkato 0:f782d9c66c49 1049 #endif
dkato 0:f782d9c66c49 1050 }
dkato 0:f782d9c66c49 1051
dkato 0:f782d9c66c49 1052 /** \brief Get FPEXC
dkato 0:f782d9c66c49 1053
dkato 0:f782d9c66c49 1054 This function returns the current value of the Floating Point Exception Control register.
dkato 0:f782d9c66c49 1055
dkato 0:f782d9c66c49 1056 \return Floating Point Exception Control register value
dkato 0:f782d9c66c49 1057 */
dkato 0:f782d9c66c49 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
dkato 0:f782d9c66c49 1059 {
dkato 0:f782d9c66c49 1060 #if (__FPU_PRESENT == 1)
dkato 0:f782d9c66c49 1061 #if 1
dkato 0:f782d9c66c49 1062 uint32_t result;
dkato 0:f782d9c66c49 1063
dkato 0:f782d9c66c49 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
dkato 0:f782d9c66c49 1065 return (result);
dkato 0:f782d9c66c49 1066 #else
dkato 0:f782d9c66c49 1067 register uint32_t __regfpexc __ASM("fpexc");
dkato 0:f782d9c66c49 1068 return(__regfpexc);
dkato 0:f782d9c66c49 1069 #endif
dkato 0:f782d9c66c49 1070 #else
dkato 0:f782d9c66c49 1071 return(0);
dkato 0:f782d9c66c49 1072 #endif
dkato 0:f782d9c66c49 1073 }
dkato 0:f782d9c66c49 1074
dkato 0:f782d9c66c49 1075
dkato 0:f782d9c66c49 1076 /** \brief Set FPEXC
dkato 0:f782d9c66c49 1077
dkato 0:f782d9c66c49 1078 This function assigns the given value to the Floating Point Exception Control register.
dkato 0:f782d9c66c49 1079
dkato 0:f782d9c66c49 1080 \param [in] fpscr Floating Point Exception Control value to set
dkato 0:f782d9c66c49 1081 */
dkato 0:f782d9c66c49 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
dkato 0:f782d9c66c49 1083 {
dkato 0:f782d9c66c49 1084 #if (__FPU_PRESENT == 1)
dkato 0:f782d9c66c49 1085 #if 1
dkato 0:f782d9c66c49 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
dkato 0:f782d9c66c49 1087 #else
dkato 0:f782d9c66c49 1088 register uint32_t __regfpexc __ASM("fpexc");
dkato 0:f782d9c66c49 1089 __regfpexc = (fpexc);
dkato 0:f782d9c66c49 1090 #endif
dkato 0:f782d9c66c49 1091 #endif
dkato 0:f782d9c66c49 1092 }
dkato 0:f782d9c66c49 1093
dkato 0:f782d9c66c49 1094 /** \brief Get CPACR
dkato 0:f782d9c66c49 1095
dkato 0:f782d9c66c49 1096 This function returns the current value of the Coprocessor Access Control register.
dkato 0:f782d9c66c49 1097
dkato 0:f782d9c66c49 1098 \return Coprocessor Access Control register value
dkato 0:f782d9c66c49 1099 */
dkato 0:f782d9c66c49 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
dkato 0:f782d9c66c49 1101 {
dkato 0:f782d9c66c49 1102 #if 1
dkato 0:f782d9c66c49 1103 register uint32_t __regCPACR;
dkato 0:f782d9c66c49 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
dkato 0:f782d9c66c49 1105 #else
dkato 0:f782d9c66c49 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
dkato 0:f782d9c66c49 1107 #endif
dkato 0:f782d9c66c49 1108 return __regCPACR;
dkato 0:f782d9c66c49 1109 }
dkato 0:f782d9c66c49 1110
dkato 0:f782d9c66c49 1111 /** \brief Set CPACR
dkato 0:f782d9c66c49 1112
dkato 0:f782d9c66c49 1113 This function assigns the given value to the Coprocessor Access Control register.
dkato 0:f782d9c66c49 1114
dkato 0:f782d9c66c49 1115 \param [in] cpacr Coprocessor Acccess Control value to set
dkato 0:f782d9c66c49 1116 */
dkato 0:f782d9c66c49 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
dkato 0:f782d9c66c49 1118 {
dkato 0:f782d9c66c49 1119 #if 1
dkato 0:f782d9c66c49 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
dkato 0:f782d9c66c49 1121 #else
dkato 0:f782d9c66c49 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
dkato 0:f782d9c66c49 1123 __regCPACR = cpacr;
dkato 0:f782d9c66c49 1124 #endif
dkato 0:f782d9c66c49 1125 __ISB();
dkato 0:f782d9c66c49 1126 }
dkato 0:f782d9c66c49 1127
dkato 0:f782d9c66c49 1128 /** \brief Get CBAR
dkato 0:f782d9c66c49 1129
dkato 0:f782d9c66c49 1130 This function returns the value of the Configuration Base Address register.
dkato 0:f782d9c66c49 1131
dkato 0:f782d9c66c49 1132 \return Configuration Base Address register value
dkato 0:f782d9c66c49 1133 */
dkato 0:f782d9c66c49 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
dkato 0:f782d9c66c49 1135 #if 1
dkato 0:f782d9c66c49 1136 register uint32_t __regCBAR;
dkato 0:f782d9c66c49 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
dkato 0:f782d9c66c49 1138 #else
dkato 0:f782d9c66c49 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
dkato 0:f782d9c66c49 1140 #endif
dkato 0:f782d9c66c49 1141 return(__regCBAR);
dkato 0:f782d9c66c49 1142 }
dkato 0:f782d9c66c49 1143
dkato 0:f782d9c66c49 1144 /** \brief Get TTBR0
dkato 0:f782d9c66c49 1145
dkato 0:f782d9c66c49 1146 This function returns the value of the Translation Table Base Register 0.
dkato 0:f782d9c66c49 1147
dkato 0:f782d9c66c49 1148 \return Translation Table Base Register 0 value
dkato 0:f782d9c66c49 1149 */
dkato 0:f782d9c66c49 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
dkato 0:f782d9c66c49 1151 #if 1
dkato 0:f782d9c66c49 1152 register uint32_t __regTTBR0;
dkato 0:f782d9c66c49 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
dkato 0:f782d9c66c49 1154 #else
dkato 0:f782d9c66c49 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
dkato 0:f782d9c66c49 1156 #endif
dkato 0:f782d9c66c49 1157 return(__regTTBR0);
dkato 0:f782d9c66c49 1158 }
dkato 0:f782d9c66c49 1159
dkato 0:f782d9c66c49 1160 /** \brief Set TTBR0
dkato 0:f782d9c66c49 1161
dkato 0:f782d9c66c49 1162 This function assigns the given value to the Translation Table Base Register 0.
dkato 0:f782d9c66c49 1163
dkato 0:f782d9c66c49 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
dkato 0:f782d9c66c49 1165 */
dkato 0:f782d9c66c49 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
dkato 0:f782d9c66c49 1167 #if 1
dkato 0:f782d9c66c49 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
dkato 0:f782d9c66c49 1169 #else
dkato 0:f782d9c66c49 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
dkato 0:f782d9c66c49 1171 __regTTBR0 = ttbr0;
dkato 0:f782d9c66c49 1172 #endif
dkato 0:f782d9c66c49 1173 __ISB();
dkato 0:f782d9c66c49 1174 }
dkato 0:f782d9c66c49 1175
dkato 0:f782d9c66c49 1176 /** \brief Get DACR
dkato 0:f782d9c66c49 1177
dkato 0:f782d9c66c49 1178 This function returns the value of the Domain Access Control Register.
dkato 0:f782d9c66c49 1179
dkato 0:f782d9c66c49 1180 \return Domain Access Control Register value
dkato 0:f782d9c66c49 1181 */
dkato 0:f782d9c66c49 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
dkato 0:f782d9c66c49 1183 #if 1
dkato 0:f782d9c66c49 1184 register uint32_t __regDACR;
dkato 0:f782d9c66c49 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
dkato 0:f782d9c66c49 1186 #else
dkato 0:f782d9c66c49 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
dkato 0:f782d9c66c49 1188 #endif
dkato 0:f782d9c66c49 1189 return(__regDACR);
dkato 0:f782d9c66c49 1190 }
dkato 0:f782d9c66c49 1191
dkato 0:f782d9c66c49 1192 /** \brief Set DACR
dkato 0:f782d9c66c49 1193
dkato 0:f782d9c66c49 1194 This function assigns the given value to the Domain Access Control Register.
dkato 0:f782d9c66c49 1195
dkato 0:f782d9c66c49 1196 \param [in] dacr Domain Access Control Register value to set
dkato 0:f782d9c66c49 1197 */
dkato 0:f782d9c66c49 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
dkato 0:f782d9c66c49 1199 #if 1
dkato 0:f782d9c66c49 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
dkato 0:f782d9c66c49 1201 #else
dkato 0:f782d9c66c49 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
dkato 0:f782d9c66c49 1203 __regDACR = dacr;
dkato 0:f782d9c66c49 1204 #endif
dkato 0:f782d9c66c49 1205 __ISB();
dkato 0:f782d9c66c49 1206 }
dkato 0:f782d9c66c49 1207
dkato 0:f782d9c66c49 1208 /******************************** Cache and BTAC enable ****************************************************/
dkato 0:f782d9c66c49 1209
dkato 0:f782d9c66c49 1210 /** \brief Set SCTLR
dkato 0:f782d9c66c49 1211
dkato 0:f782d9c66c49 1212 This function assigns the given value to the System Control Register.
dkato 0:f782d9c66c49 1213
dkato 0:f782d9c66c49 1214 \param [in] sctlr System Control Register value to set
dkato 0:f782d9c66c49 1215 */
dkato 0:f782d9c66c49 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
dkato 0:f782d9c66c49 1217 {
dkato 0:f782d9c66c49 1218 #if 1
dkato 0:f782d9c66c49 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
dkato 0:f782d9c66c49 1220 #else
dkato 0:f782d9c66c49 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
dkato 0:f782d9c66c49 1222 __regSCTLR = sctlr;
dkato 0:f782d9c66c49 1223 #endif
dkato 0:f782d9c66c49 1224 }
dkato 0:f782d9c66c49 1225
dkato 0:f782d9c66c49 1226 /** \brief Get SCTLR
dkato 0:f782d9c66c49 1227
dkato 0:f782d9c66c49 1228 This function returns the value of the System Control Register.
dkato 0:f782d9c66c49 1229
dkato 0:f782d9c66c49 1230 \return System Control Register value
dkato 0:f782d9c66c49 1231 */
dkato 0:f782d9c66c49 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
dkato 0:f782d9c66c49 1233 #if 1
dkato 0:f782d9c66c49 1234 register uint32_t __regSCTLR;
dkato 0:f782d9c66c49 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
dkato 0:f782d9c66c49 1236 #else
dkato 0:f782d9c66c49 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
dkato 0:f782d9c66c49 1238 #endif
dkato 0:f782d9c66c49 1239 return(__regSCTLR);
dkato 0:f782d9c66c49 1240 }
dkato 0:f782d9c66c49 1241
dkato 0:f782d9c66c49 1242 /** \brief Enable Caches
dkato 0:f782d9c66c49 1243
dkato 0:f782d9c66c49 1244 Enable Caches
dkato 0:f782d9c66c49 1245 */
dkato 0:f782d9c66c49 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
dkato 0:f782d9c66c49 1247 // Set I bit 12 to enable I Cache
dkato 0:f782d9c66c49 1248 // Set C bit 2 to enable D Cache
dkato 0:f782d9c66c49 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
dkato 0:f782d9c66c49 1250 }
dkato 0:f782d9c66c49 1251
dkato 0:f782d9c66c49 1252 /** \brief Disable Caches
dkato 0:f782d9c66c49 1253
dkato 0:f782d9c66c49 1254 Disable Caches
dkato 0:f782d9c66c49 1255 */
dkato 0:f782d9c66c49 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
dkato 0:f782d9c66c49 1257 // Clear I bit 12 to disable I Cache
dkato 0:f782d9c66c49 1258 // Clear C bit 2 to disable D Cache
dkato 0:f782d9c66c49 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
dkato 0:f782d9c66c49 1260 __ISB();
dkato 0:f782d9c66c49 1261 }
dkato 0:f782d9c66c49 1262
dkato 0:f782d9c66c49 1263 /** \brief Enable BTAC
dkato 0:f782d9c66c49 1264
dkato 0:f782d9c66c49 1265 Enable BTAC
dkato 0:f782d9c66c49 1266 */
dkato 0:f782d9c66c49 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
dkato 0:f782d9c66c49 1268 // Set Z bit 11 to enable branch prediction
dkato 0:f782d9c66c49 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
dkato 0:f782d9c66c49 1270 __ISB();
dkato 0:f782d9c66c49 1271 }
dkato 0:f782d9c66c49 1272
dkato 0:f782d9c66c49 1273 /** \brief Disable BTAC
dkato 0:f782d9c66c49 1274
dkato 0:f782d9c66c49 1275 Disable BTAC
dkato 0:f782d9c66c49 1276 */
dkato 0:f782d9c66c49 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
dkato 0:f782d9c66c49 1278 // Clear Z bit 11 to disable branch prediction
dkato 0:f782d9c66c49 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
dkato 0:f782d9c66c49 1280 }
dkato 0:f782d9c66c49 1281
dkato 0:f782d9c66c49 1282
dkato 0:f782d9c66c49 1283 /** \brief Enable MMU
dkato 0:f782d9c66c49 1284
dkato 0:f782d9c66c49 1285 Enable MMU
dkato 0:f782d9c66c49 1286 */
dkato 0:f782d9c66c49 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
dkato 0:f782d9c66c49 1288 // Set M bit 0 to enable the MMU
dkato 0:f782d9c66c49 1289 // Set AFE bit to enable simplified access permissions model
dkato 0:f782d9c66c49 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
dkato 0:f782d9c66c49 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
dkato 0:f782d9c66c49 1292 __ISB();
dkato 0:f782d9c66c49 1293 }
dkato 0:f782d9c66c49 1294
dkato 0:f782d9c66c49 1295 /** \brief Disable MMU
dkato 0:f782d9c66c49 1296
dkato 0:f782d9c66c49 1297 Disable MMU
dkato 0:f782d9c66c49 1298 */
dkato 0:f782d9c66c49 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
dkato 0:f782d9c66c49 1300 // Clear M bit 0 to disable the MMU
dkato 0:f782d9c66c49 1301 __set_SCTLR( __get_SCTLR() & ~1);
dkato 0:f782d9c66c49 1302 __ISB();
dkato 0:f782d9c66c49 1303 }
dkato 0:f782d9c66c49 1304
dkato 0:f782d9c66c49 1305 /******************************** TLB maintenance operations ************************************************/
dkato 0:f782d9c66c49 1306 /** \brief Invalidate the whole tlb
dkato 0:f782d9c66c49 1307
dkato 0:f782d9c66c49 1308 TLBIALL. Invalidate the whole tlb
dkato 0:f782d9c66c49 1309 */
dkato 0:f782d9c66c49 1310
dkato 0:f782d9c66c49 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
dkato 0:f782d9c66c49 1312 #if 1
dkato 0:f782d9c66c49 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
dkato 0:f782d9c66c49 1314 #else
dkato 0:f782d9c66c49 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
dkato 0:f782d9c66c49 1316 __TLBIALL = 0;
dkato 0:f782d9c66c49 1317 #endif
dkato 0:f782d9c66c49 1318 __DSB();
dkato 0:f782d9c66c49 1319 __ISB();
dkato 0:f782d9c66c49 1320 }
dkato 0:f782d9c66c49 1321
dkato 0:f782d9c66c49 1322 /******************************** BTB maintenance operations ************************************************/
dkato 0:f782d9c66c49 1323 /** \brief Invalidate entire branch predictor array
dkato 0:f782d9c66c49 1324
dkato 0:f782d9c66c49 1325 BPIALL. Branch Predictor Invalidate All.
dkato 0:f782d9c66c49 1326 */
dkato 0:f782d9c66c49 1327
dkato 0:f782d9c66c49 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
dkato 0:f782d9c66c49 1329 #if 1
dkato 0:f782d9c66c49 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
dkato 0:f782d9c66c49 1331 #else
dkato 0:f782d9c66c49 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
dkato 0:f782d9c66c49 1333 __BPIALL = 0;
dkato 0:f782d9c66c49 1334 #endif
dkato 0:f782d9c66c49 1335 __DSB(); //ensure completion of the invalidation
dkato 0:f782d9c66c49 1336 __ISB(); //ensure instruction fetch path sees new state
dkato 0:f782d9c66c49 1337 }
dkato 0:f782d9c66c49 1338
dkato 0:f782d9c66c49 1339
dkato 0:f782d9c66c49 1340 /******************************** L1 cache operations ******************************************************/
dkato 0:f782d9c66c49 1341
dkato 0:f782d9c66c49 1342 /** \brief Invalidate the whole I$
dkato 0:f782d9c66c49 1343
dkato 0:f782d9c66c49 1344 ICIALLU. Instruction Cache Invalidate All to PoU
dkato 0:f782d9c66c49 1345 */
dkato 0:f782d9c66c49 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
dkato 0:f782d9c66c49 1347 #if 1
dkato 0:f782d9c66c49 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
dkato 0:f782d9c66c49 1349 #else
dkato 0:f782d9c66c49 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
dkato 0:f782d9c66c49 1351 __ICIALLU = 0;
dkato 0:f782d9c66c49 1352 #endif
dkato 0:f782d9c66c49 1353 __DSB(); //ensure completion of the invalidation
dkato 0:f782d9c66c49 1354 __ISB(); //ensure instruction fetch path sees new I cache state
dkato 0:f782d9c66c49 1355 }
dkato 0:f782d9c66c49 1356
dkato 0:f782d9c66c49 1357 /** \brief Clean D$ by MVA
dkato 0:f782d9c66c49 1358
dkato 0:f782d9c66c49 1359 DCCMVAC. Data cache clean by MVA to PoC
dkato 0:f782d9c66c49 1360 */
dkato 0:f782d9c66c49 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
dkato 0:f782d9c66c49 1362 #if 1
dkato 0:f782d9c66c49 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
dkato 0:f782d9c66c49 1364 #else
dkato 0:f782d9c66c49 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
dkato 0:f782d9c66c49 1366 __DCCMVAC = (uint32_t)va;
dkato 0:f782d9c66c49 1367 #endif
dkato 0:f782d9c66c49 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
dkato 0:f782d9c66c49 1369 }
dkato 0:f782d9c66c49 1370
dkato 0:f782d9c66c49 1371 /** \brief Invalidate D$ by MVA
dkato 0:f782d9c66c49 1372
dkato 0:f782d9c66c49 1373 DCIMVAC. Data cache invalidate by MVA to PoC
dkato 0:f782d9c66c49 1374 */
dkato 0:f782d9c66c49 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
dkato 0:f782d9c66c49 1376 #if 1
dkato 0:f782d9c66c49 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
dkato 0:f782d9c66c49 1378 #else
dkato 0:f782d9c66c49 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
dkato 0:f782d9c66c49 1380 __DCIMVAC = (uint32_t)va;
dkato 0:f782d9c66c49 1381 #endif
dkato 0:f782d9c66c49 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
dkato 0:f782d9c66c49 1383 }
dkato 0:f782d9c66c49 1384
dkato 0:f782d9c66c49 1385 /** \brief Clean and Invalidate D$ by MVA
dkato 0:f782d9c66c49 1386
dkato 0:f782d9c66c49 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
dkato 0:f782d9c66c49 1388 */
dkato 0:f782d9c66c49 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
dkato 0:f782d9c66c49 1390 #if 1
dkato 0:f782d9c66c49 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
dkato 0:f782d9c66c49 1392 #else
dkato 0:f782d9c66c49 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
dkato 0:f782d9c66c49 1394 __DCCIMVAC = (uint32_t)va;
dkato 0:f782d9c66c49 1395 #endif
dkato 0:f782d9c66c49 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
dkato 0:f782d9c66c49 1397 }
dkato 0:f782d9c66c49 1398
dkato 0:f782d9c66c49 1399 /** \brief Clean and Invalidate the entire data or unified cache
dkato 0:f782d9c66c49 1400
dkato 0:f782d9c66c49 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
dkato 0:f782d9c66c49 1402 */
dkato 0:f782d9c66c49 1403 extern void __v7_all_cache(uint32_t op);
dkato 0:f782d9c66c49 1404
dkato 0:f782d9c66c49 1405
dkato 0:f782d9c66c49 1406 /** \brief Invalidate the whole D$
dkato 0:f782d9c66c49 1407
dkato 0:f782d9c66c49 1408 DCISW. Invalidate by Set/Way
dkato 0:f782d9c66c49 1409 */
dkato 0:f782d9c66c49 1410
dkato 0:f782d9c66c49 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
dkato 0:f782d9c66c49 1412 __v7_all_cache(0);
dkato 0:f782d9c66c49 1413 }
dkato 0:f782d9c66c49 1414
dkato 0:f782d9c66c49 1415 /** \brief Clean the whole D$
dkato 0:f782d9c66c49 1416
dkato 0:f782d9c66c49 1417 DCCSW. Clean by Set/Way
dkato 0:f782d9c66c49 1418 */
dkato 0:f782d9c66c49 1419
dkato 0:f782d9c66c49 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
dkato 0:f782d9c66c49 1421 __v7_all_cache(1);
dkato 0:f782d9c66c49 1422 }
dkato 0:f782d9c66c49 1423
dkato 0:f782d9c66c49 1424 /** \brief Clean and invalidate the whole D$
dkato 0:f782d9c66c49 1425
dkato 0:f782d9c66c49 1426 DCCISW. Clean and Invalidate by Set/Way
dkato 0:f782d9c66c49 1427 */
dkato 0:f782d9c66c49 1428
dkato 0:f782d9c66c49 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
dkato 0:f782d9c66c49 1430 __v7_all_cache(2);
dkato 0:f782d9c66c49 1431 }
dkato 0:f782d9c66c49 1432
dkato 0:f782d9c66c49 1433 #include "core_ca_mmu.h"
dkato 0:f782d9c66c49 1434
dkato 0:f782d9c66c49 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
dkato 0:f782d9c66c49 1436
dkato 0:f782d9c66c49 1437 #error TASKING Compiler support not implemented for Cortex-A
dkato 0:f782d9c66c49 1438
dkato 0:f782d9c66c49 1439 #endif
dkato 0:f782d9c66c49 1440
dkato 0:f782d9c66c49 1441 /*@} end of CMSIS_Core_RegAccFunctions */
dkato 0:f782d9c66c49 1442
dkato 0:f782d9c66c49 1443
dkato 0:f782d9c66c49 1444 #endif /* __CORE_CAFUNC_H__ */