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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_features.h@108:af734d017ad0, 2016-04-26 (annotated)

Committer:
dkato
Date:
Tue Apr 26 02:02:58 2016 +0000
Revision:
108:af734d017ad0
Parent:
0:9b334a45a8ff 
bugfixs

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 ** ###################################################################
bogdanm 0:9b334a45a8ff 3 ** Version: rev. 1.0, 2014-05-14
bogdanm 0:9b334a45a8ff 4 ** Build: b140515
bogdanm 0:9b334a45a8ff 5 **
bogdanm 0:9b334a45a8ff 6 ** Abstract:
bogdanm 0:9b334a45a8ff 7 ** Chip specific module features.
bogdanm 0:9b334a45a8ff 8 **
bogdanm 0:9b334a45a8ff 9 ** Copyright: 2014 Freescale Semiconductor, Inc.
bogdanm 0:9b334a45a8ff 10 ** All rights reserved.
bogdanm 0:9b334a45a8ff 11 **
bogdanm 0:9b334a45a8ff 12 ** Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 13 ** are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 14 **
bogdanm 0:9b334a45a8ff 15 ** o Redistributions of source code must retain the above copyright notice, this list
bogdanm 0:9b334a45a8ff 16 ** of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 **
bogdanm 0:9b334a45a8ff 18 ** o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 0:9b334a45a8ff 19 ** list of conditions and the following disclaimer in the documentation and/or
bogdanm 0:9b334a45a8ff 20 ** other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 21 **
bogdanm 0:9b334a45a8ff 22 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 0:9b334a45a8ff 23 ** contributors may be used to endorse or promote products derived from this
bogdanm 0:9b334a45a8ff 24 ** software without specific prior written permission.
bogdanm 0:9b334a45a8ff 25 **
bogdanm 0:9b334a45a8ff 26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 0:9b334a45a8ff 27 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 0:9b334a45a8ff 28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 0:9b334a45a8ff 30 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 0:9b334a45a8ff 31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 0:9b334a45a8ff 32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 0:9b334a45a8ff 33 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 0:9b334a45a8ff 34 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 0:9b334a45a8ff 35 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 36 **
bogdanm 0:9b334a45a8ff 37 ** http: www.freescale.com
bogdanm 0:9b334a45a8ff 38 ** mail: support@freescale.com
bogdanm 0:9b334a45a8ff 39 **
bogdanm 0:9b334a45a8ff 40 ** Revisions:
bogdanm 0:9b334a45a8ff 41 ** - rev. 1.0 (2014-05-14)
bogdanm 0:9b334a45a8ff 42 ** Customer release.
bogdanm 0:9b334a45a8ff 43 **
bogdanm 0:9b334a45a8ff 44 ** ###################################################################
bogdanm 0:9b334a45a8ff 45 */
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 #if !defined(__FSL_DSPI_FEATURES_H__)
bogdanm 0:9b334a45a8ff 48 #define __FSL_DSPI_FEATURES_H__
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \
bogdanm 0:9b334a45a8ff 51 defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
bogdanm 0:9b334a45a8ff 52 defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10)
bogdanm 0:9b334a45a8ff 53 /* @brief Receive/transmit FIFO size in number of items. */
bogdanm 0:9b334a45a8ff 54 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
bogdanm 0:9b334a45a8ff 55 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
bogdanm 0:9b334a45a8ff 56 ((x) == 0 ? (4) : (-1))
bogdanm 0:9b334a45a8ff 57 /* @brief Maximum transfer data width in bits. */
bogdanm 0:9b334a45a8ff 58 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
bogdanm 0:9b334a45a8ff 59 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
bogdanm 0:9b334a45a8ff 60 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 61 /* @brief Number of chip select pins. */
bogdanm 0:9b334a45a8ff 62 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (4)
bogdanm 0:9b334a45a8ff 63 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
bogdanm 0:9b334a45a8ff 64 ((x) == 0 ? (4) : (-1))
bogdanm 0:9b334a45a8ff 65 /* @brief Has chip select strobe capability on the PCS5 pin. */
bogdanm 0:9b334a45a8ff 66 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
bogdanm 0:9b334a45a8ff 67 /* @brief Has 16-bit data transfer support. */
bogdanm 0:9b334a45a8ff 68 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
bogdanm 0:9b334a45a8ff 69 #elif defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || \
bogdanm 0:9b334a45a8ff 70 defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
bogdanm 0:9b334a45a8ff 71 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
bogdanm 0:9b334a45a8ff 72 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
bogdanm 0:9b334a45a8ff 73 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \
bogdanm 0:9b334a45a8ff 74 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \
bogdanm 0:9b334a45a8ff 75 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \
bogdanm 0:9b334a45a8ff 76 defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10)
bogdanm 0:9b334a45a8ff 77 /* @brief Receive/transmit FIFO size in number of items. */
bogdanm 0:9b334a45a8ff 78 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
bogdanm 0:9b334a45a8ff 79 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
bogdanm 0:9b334a45a8ff 80 ((x) == 0 ? (4) : (-1))
bogdanm 0:9b334a45a8ff 81 /* @brief Maximum transfer data width in bits. */
bogdanm 0:9b334a45a8ff 82 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
bogdanm 0:9b334a45a8ff 83 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
bogdanm 0:9b334a45a8ff 84 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 85 /* @brief Number of chip select pins. */
bogdanm 0:9b334a45a8ff 86 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5)
bogdanm 0:9b334a45a8ff 87 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
bogdanm 0:9b334a45a8ff 88 ((x) == 0 ? (5) : (-1))
bogdanm 0:9b334a45a8ff 89 /* @brief Has chip select strobe capability on the PCS5 pin. */
bogdanm 0:9b334a45a8ff 90 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
bogdanm 0:9b334a45a8ff 91 /* @brief Has 16-bit data transfer support. */
bogdanm 0:9b334a45a8ff 92 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
bogdanm 0:9b334a45a8ff 93 #elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLL12) || \
bogdanm 0:9b334a45a8ff 94 defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLL12) || \
bogdanm 0:9b334a45a8ff 95 defined(CPU_MKV31F512VLL12)
bogdanm 0:9b334a45a8ff 96 /* @brief Receive/transmit FIFO size in number of items. */
bogdanm 0:9b334a45a8ff 97 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
bogdanm 0:9b334a45a8ff 98 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
bogdanm 0:9b334a45a8ff 99 ((x) == 0 ? (4) : \
bogdanm 0:9b334a45a8ff 100 ((x) == 1 ? (1) : (-1)))
bogdanm 0:9b334a45a8ff 101 /* @brief Maximum transfer data width in bits. */
bogdanm 0:9b334a45a8ff 102 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
bogdanm 0:9b334a45a8ff 103 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
bogdanm 0:9b334a45a8ff 104 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 105 /* @brief Number of chip select pins. */
bogdanm 0:9b334a45a8ff 106 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 107 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
bogdanm 0:9b334a45a8ff 108 ((x) == 0 ? (6) : \
bogdanm 0:9b334a45a8ff 109 ((x) == 1 ? (4) : (-1)))
bogdanm 0:9b334a45a8ff 110 /* @brief Has chip select strobe capability on the PCS5 pin. */
bogdanm 0:9b334a45a8ff 111 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
bogdanm 0:9b334a45a8ff 112 /* @brief Has 16-bit data transfer support. */
bogdanm 0:9b334a45a8ff 113 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
bogdanm 0:9b334a45a8ff 114 #elif defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VMP12) || \
bogdanm 0:9b334a45a8ff 115 defined(CPU_MK22FN512VLH12) || defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F512VLH12)
bogdanm 0:9b334a45a8ff 116 /* @brief Receive/transmit FIFO size in number of items. */
bogdanm 0:9b334a45a8ff 117 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
bogdanm 0:9b334a45a8ff 118 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
bogdanm 0:9b334a45a8ff 119 ((x) == 0 ? (4) : \
bogdanm 0:9b334a45a8ff 120 ((x) == 1 ? (1) : (-1)))
bogdanm 0:9b334a45a8ff 121 /* @brief Maximum transfer data width in bits. */
bogdanm 0:9b334a45a8ff 122 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
bogdanm 0:9b334a45a8ff 123 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
bogdanm 0:9b334a45a8ff 124 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 125 /* @brief Number of chip select pins. */
bogdanm 0:9b334a45a8ff 126 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5)
bogdanm 0:9b334a45a8ff 127 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
bogdanm 0:9b334a45a8ff 128 ((x) == 0 ? (5) : \
bogdanm 0:9b334a45a8ff 129 ((x) == 1 ? (2) : (-1)))
bogdanm 0:9b334a45a8ff 130 /* @brief Has chip select strobe capability on the PCS5 pin. */
bogdanm 0:9b334a45a8ff 131 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
bogdanm 0:9b334a45a8ff 132 /* @brief Has 16-bit data transfer support. */
bogdanm 0:9b334a45a8ff 133 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
bogdanm 0:9b334a45a8ff 134 #elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \
bogdanm 0:9b334a45a8ff 135 defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLQ12) || \
bogdanm 0:9b334a45a8ff 136 defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK65FN2M0CAC18) || \
bogdanm 0:9b334a45a8ff 137 defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \
bogdanm 0:9b334a45a8ff 138 defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
bogdanm 0:9b334a45a8ff 139 /* @brief Receive/transmit FIFO size in number of items. */
bogdanm 0:9b334a45a8ff 140 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
bogdanm 0:9b334a45a8ff 141 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
bogdanm 0:9b334a45a8ff 142 ((x) == 0 ? (4) : \
bogdanm 0:9b334a45a8ff 143 ((x) == 1 ? (1) : \
bogdanm 0:9b334a45a8ff 144 ((x) == 2 ? (1) : (-1))))
bogdanm 0:9b334a45a8ff 145 /* @brief Maximum transfer data width in bits. */
bogdanm 0:9b334a45a8ff 146 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
bogdanm 0:9b334a45a8ff 147 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
bogdanm 0:9b334a45a8ff 148 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 149 /* @brief Number of chip select pins. */
bogdanm 0:9b334a45a8ff 150 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 151 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
bogdanm 0:9b334a45a8ff 152 ((x) == 0 ? (6) : \
bogdanm 0:9b334a45a8ff 153 ((x) == 1 ? (4) : \
bogdanm 0:9b334a45a8ff 154 ((x) == 2 ? (2) : (-1))))
bogdanm 0:9b334a45a8ff 155 /* @brief Has chip select strobe capability on the PCS5 pin. */
bogdanm 0:9b334a45a8ff 156 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
bogdanm 0:9b334a45a8ff 157 /* @brief Has 16-bit data transfer support. */
bogdanm 0:9b334a45a8ff 158 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
bogdanm 0:9b334a45a8ff 159 #elif defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12)
bogdanm 0:9b334a45a8ff 160 /* @brief Receive/transmit FIFO size in number of items. */
bogdanm 0:9b334a45a8ff 161 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
bogdanm 0:9b334a45a8ff 162 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
bogdanm 0:9b334a45a8ff 163 ((x) == 0 ? (4) : \
bogdanm 0:9b334a45a8ff 164 ((x) == 1 ? (1) : \
bogdanm 0:9b334a45a8ff 165 ((x) == 2 ? (1) : (-1))))
bogdanm 0:9b334a45a8ff 166 /* @brief Maximum transfer data width in bits. */
bogdanm 0:9b334a45a8ff 167 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
bogdanm 0:9b334a45a8ff 168 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
bogdanm 0:9b334a45a8ff 169 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 170 /* @brief Number of chip select pins. */
bogdanm 0:9b334a45a8ff 171 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 172 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
bogdanm 0:9b334a45a8ff 173 ((x) == 0 ? (6) : \
bogdanm 0:9b334a45a8ff 174 ((x) == 1 ? (4) : \
bogdanm 0:9b334a45a8ff 175 ((x) == 2 ? (1) : (-1))))
bogdanm 0:9b334a45a8ff 176 /* @brief Has chip select strobe capability on the PCS5 pin. */
bogdanm 0:9b334a45a8ff 177 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
bogdanm 0:9b334a45a8ff 178 /* @brief Has 16-bit data transfer support. */
bogdanm 0:9b334a45a8ff 179 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
bogdanm 0:9b334a45a8ff 180 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
bogdanm 0:9b334a45a8ff 181 defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
bogdanm 0:9b334a45a8ff 182 /* @brief Receive/transmit FIFO size in number of items. */
bogdanm 0:9b334a45a8ff 183 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
bogdanm 0:9b334a45a8ff 184 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
bogdanm 0:9b334a45a8ff 185 ((x) == 0 ? (4) : \
bogdanm 0:9b334a45a8ff 186 ((x) == 1 ? (4) : \
bogdanm 0:9b334a45a8ff 187 ((x) == 2 ? (4) : (-1))))
bogdanm 0:9b334a45a8ff 188 /* @brief Maximum transfer data width in bits. */
bogdanm 0:9b334a45a8ff 189 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
bogdanm 0:9b334a45a8ff 190 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
bogdanm 0:9b334a45a8ff 191 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 192 /* @brief Number of chip select pins. */
bogdanm 0:9b334a45a8ff 193 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 194 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
bogdanm 0:9b334a45a8ff 195 ((x) == 0 ? (6) : \
bogdanm 0:9b334a45a8ff 196 ((x) == 1 ? (4) : \
bogdanm 0:9b334a45a8ff 197 ((x) == 2 ? (2) : (-1))))
bogdanm 0:9b334a45a8ff 198 /* @brief Has chip select strobe capability on the PCS5 pin. */
bogdanm 0:9b334a45a8ff 199 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
bogdanm 0:9b334a45a8ff 200 /* @brief Has 16-bit data transfer support. */
bogdanm 0:9b334a45a8ff 201 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
bogdanm 0:9b334a45a8ff 202 #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || \
bogdanm 0:9b334a45a8ff 203 defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \
bogdanm 0:9b334a45a8ff 204 defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15)
bogdanm 0:9b334a45a8ff 205 /* @brief Receive/transmit FIFO size in number of items. */
bogdanm 0:9b334a45a8ff 206 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
bogdanm 0:9b334a45a8ff 207 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
bogdanm 0:9b334a45a8ff 208 ((x) == 0 ? (4) : (-1))
bogdanm 0:9b334a45a8ff 209 /* @brief Maximum transfer data width in bits. */
bogdanm 0:9b334a45a8ff 210 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
bogdanm 0:9b334a45a8ff 211 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
bogdanm 0:9b334a45a8ff 212 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 213 /* @brief Number of chip select pins. */
bogdanm 0:9b334a45a8ff 214 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5)
bogdanm 0:9b334a45a8ff 215 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
bogdanm 0:9b334a45a8ff 216 ((x) == 0 ? (5) : (-1))
bogdanm 0:9b334a45a8ff 217 /* @brief Has chip select strobe capability on the PCS5 pin. */
bogdanm 0:9b334a45a8ff 218 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
bogdanm 0:9b334a45a8ff 219 /* @brief Has 16-bit data transfer support. */
bogdanm 0:9b334a45a8ff 220 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
bogdanm 0:9b334a45a8ff 221 #elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV44F128VLL15) || \
bogdanm 0:9b334a45a8ff 222 defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15)
bogdanm 0:9b334a45a8ff 223 /* @brief Receive/transmit FIFO size in number of items. */
bogdanm 0:9b334a45a8ff 224 #define FSL_FEATURE_DSPI_FIFO_SIZE (4)
bogdanm 0:9b334a45a8ff 225 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
bogdanm 0:9b334a45a8ff 226 ((x) == 0 ? (4) : (-1))
bogdanm 0:9b334a45a8ff 227 /* @brief Maximum transfer data width in bits. */
bogdanm 0:9b334a45a8ff 228 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
bogdanm 0:9b334a45a8ff 229 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
bogdanm 0:9b334a45a8ff 230 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 231 /* @brief Number of chip select pins. */
bogdanm 0:9b334a45a8ff 232 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
bogdanm 0:9b334a45a8ff 233 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNTn(x) \
bogdanm 0:9b334a45a8ff 234 ((x) == 0 ? (6) : (-1))
bogdanm 0:9b334a45a8ff 235 /* @brief Has chip select strobe capability on the PCS5 pin. */
bogdanm 0:9b334a45a8ff 236 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
bogdanm 0:9b334a45a8ff 237 /* @brief Has 16-bit data transfer support. */
bogdanm 0:9b334a45a8ff 238 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
bogdanm 0:9b334a45a8ff 239 #else
bogdanm 0:9b334a45a8ff 240 #error "No valid CPU defined!"
bogdanm 0:9b334a45a8ff 241 #endif
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 #endif /* __FSL_DSPI_FEATURES_H__ */
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 /*******************************************************************************
bogdanm 0:9b334a45a8ff 246 * EOF
bogdanm 0:9b334a45a8ff 247 ******************************************************************************/