spibsc.h

00001 /*******************************************************************************
00002 * DISCLAIMER
00003 * This software is supplied by Renesas Electronics Corporation and is only
00004 * intended for use with Renesas products. No other uses are authorized. This
00005 * software is owned by Renesas Electronics Corporation and is protected under
00006 * all applicable laws, including copyright laws.
00007 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
00008 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
00009 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
00010 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
00011 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
00012 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
00013 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
00014 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
00015 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
00016 * Renesas reserves the right, without notice, to make changes to this software
00017 * and to discontinue the availability of this software. By using this software,
00018 * you agree to the additional terms and conditions found by accessing the
00019 * following link:
00020 * http://www.renesas.com/disclaimer
00021 *
00022 * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
00023 *******************************************************************************/
00024 /******************************************************************************
00025 * File Name    : spibsc.h
00026 * $Rev: 12 $
00027 * $Date:: 2016-05-19 17:26:37 +0900#$
00028 * Description  : 
00029 ******************************************************************************/
00030 #ifndef _SPIBSC_H_
00031 #define _SPIBSC_H_
00032 
00033 /******************************************************************************
00034 Includes <System Includes> , "Project Includes"
00035 ******************************************************************************/
00036 #include "iodefine.h"
00037 
00038 /******************************************************************************
00039 Macro definitions
00040 ******************************************************************************/
00041 #define SPIBSC_CMNCR_MD_EXTRD       (0u)
00042 #define SPIBSC_CMNCR_MD_SPI         (1u)
00043 
00044 #define SPIBSC_OUTPUT_LOW           (0u)
00045 #define SPIBSC_OUTPUT_HIGH          (1u)
00046 #define SPIBSC_OUTPUT_LAST          (2u)
00047 #define SPIBSC_OUTPUT_HiZ           (3u)
00048 
00049 #define SPIBSC_CMNCR_CPHAT_EVEN     (0u)
00050 #define SPIBSC_CMNCR_CPHAT_ODD      (1u)
00051 
00052 #define SPIBSC_CMNCR_CPHAR_ODD      (0u)
00053 #define SPIBSC_CMNCR_CPHAR_EVEN     (1u)
00054 
00055 #define SPIBSC_CMNCR_SSLP_LOW       (0u)
00056 #define SPIBSC_CMNCR_SSLP_HIGH      (1u)
00057 
00058 #define SPIBSC_CMNCR_CPOL_LOW       (0u)
00059 #define SPIBSC_CMNCR_CPOL_HIGH      (1u)
00060 
00061 #define SPIBSC_CMNCR_BSZ_SINGLE     (0u)
00062 #define SPIBSC_CMNCR_BSZ_DUAL       (1u)
00063 
00064 #define SPIBSC_DELAY_1SPBCLK        (0u)
00065 #define SPIBSC_DELAY_2SPBCLK        (1u)
00066 #define SPIBSC_DELAY_3SPBCLK        (2u)
00067 #define SPIBSC_DELAY_4SPBCLK        (3u)
00068 #define SPIBSC_DELAY_5SPBCLK        (4u)
00069 #define SPIBSC_DELAY_6SPBCLK        (5u)
00070 #define SPIBSC_DELAY_7SPBCLK        (6u)
00071 #define SPIBSC_DELAY_8SPBCLK        (7u)
00072 
00073 
00074 #define SPIBSC_BURST_1              (0x00u)
00075 #define SPIBSC_BURST_2              (0x01u)
00076 #define SPIBSC_BURST_3              (0x02u)
00077 #define SPIBSC_BURST_4              (0x03u)
00078 #define SPIBSC_BURST_5              (0x04u)
00079 #define SPIBSC_BURST_6              (0x05u)
00080 #define SPIBSC_BURST_7              (0x06u)
00081 #define SPIBSC_BURST_8              (0x07u)
00082 #define SPIBSC_BURST_9              (0x08u)
00083 #define SPIBSC_BURST_10             (0x09u)
00084 #define SPIBSC_BURST_11             (0x0au)
00085 #define SPIBSC_BURST_12             (0x0bu)
00086 #define SPIBSC_BURST_13             (0x0cu)
00087 #define SPIBSC_BURST_14             (0x0du)
00088 #define SPIBSC_BURST_15             (0x0eu)
00089 #define SPIBSC_BURST_16             (0x0fu)
00090 
00091 #define SPIBSC_BURST_DISABLE        (0u)
00092 #define SPIBSC_BURST_ENABLE         (1u)
00093 
00094 #define SPIBSC_DRCR_RCF_EXE         (1u)
00095 
00096 #define SPIBSC_SSL_NEGATE           (0u)
00097 #define SPIBSC_TRANS_END            (1u)
00098 
00099 #define SPIBSC_1BIT                 (0u)
00100 #define SPIBSC_2BIT                 (1u)
00101 #define SPIBSC_4BIT                 (2u)
00102 
00103 #define SPIBSC_OUTPUT_DISABLE       (0u)
00104 #define SPIBSC_OUTPUT_ENABLE        (1u)
00105 #define SPIBSC_OUTPUT_ADDR_24       (0x07u)
00106 #define SPIBSC_OUTPUT_ADDR_32       (0x0fu)
00107 #define SPIBSC_OUTPUT_OPD_3         (0x08u)
00108 #define SPIBSC_OUTPUT_OPD_32        (0x0cu)
00109 #define SPIBSC_OUTPUT_OPD_321       (0x0eu)
00110 #define SPIBSC_OUTPUT_OPD_3210      (0x0fu)
00111 
00112 #define SPIBSC_OUTPUT_SPID_8        (0x08u)
00113 #define SPIBSC_OUTPUT_SPID_16       (0x0cu)
00114 #define SPIBSC_OUTPUT_SPID_32       (0x0fu)
00115 
00116 #define SPIBSC_SPISSL_NEGATE        (0u)
00117 #define SPIBSC_SPISSL_KEEP          (1u)
00118 
00119 #define SPIBSC_SPIDATA_DISABLE      (0u)
00120 #define SPIBSC_SPIDATA_ENABLE       (1u)
00121 
00122 #define SPIBSC_SPI_DISABLE          (0u)
00123 #define SPIBSC_SPI_ENABLE           (1u)
00124 
00125 
00126 /* Use for setting of the DME bit of "data read enable register"(DRENR) */
00127 #define SPIBSC_DUMMY_CYC_DISABLE    (0u)
00128 #define SPIBSC_DUMMY_CYC_ENABLE     (1u)
00129 
00130 /* Use for setting of the DMCYC [2:0] bit of "data read dummy cycle register"(DRDMCR) */
00131 #define SPIBSC_DUMMY_1CYC           (0u)
00132 #define SPIBSC_DUMMY_2CYC           (1u)
00133 #define SPIBSC_DUMMY_3CYC           (2u)
00134 #define SPIBSC_DUMMY_4CYC           (3u)
00135 #define SPIBSC_DUMMY_5CYC           (4u)
00136 #define SPIBSC_DUMMY_6CYC           (5u)
00137 #define SPIBSC_DUMMY_7CYC           (6u)
00138 #define SPIBSC_DUMMY_8CYC           (7u)
00139 
00140 /* Use for setting of "data read DDR enable register"(DRDRENR) */
00141 #define SPIBSC_SDR_TRANS            (0u)
00142 #define SPIBSC_DDR_TRANS            (1u)
00143 
00144 /* Use for setting the CKDLY regsiter */
00145 #define SPIBSC_CKDLY_DEFAULT        (0x0000A504uL)    /* Initial value */
00146 #define SPIBSC_CKDLY_TUNING         (0x0000A50AuL)    /* Shorten the data input setup time and extend the data hold time */
00147 
00148 /* Use for setting the SPODLY regsiter */
00149 #define SPIBSC_SPODLY_DEFAULT       (0xA5000000uL)    /* Initial value */
00150 #define SPIBSC_SPODLY_TUNING        (0xA5001111uL)    /* Delay the data output delay/hold/buffer-on/buffer-off time */
00151 
00152 #endif /* _SPIBSC_H_ */
00153 
00154 /* End of File */