FlashAccess.h

00001 /*******************************************************************************
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00023 *******************************************************************************/
00024 
00025 #ifndef FLASH_ACCESS_H
00026 #define FLASH_ACCESS_H
00027 
00028 #include "mbed.h"
00029 #include "iodefine.h"
00030 #include "spibsc_iobitmask.h"
00031 #include "spibsc.h"
00032 
00033 #define _RAM_PRG __attribute__((section("RAM_CODE")))
00034 
00035 /** FlashAccess class
00036  *  Flash access library for GR-Boards.
00037  */
00038 class FlashAccess {
00039 public:
00040     /** Constructor
00041      *
00042      */
00043     FlashAccess();
00044 
00045     /** Sector Erase
00046      *
00047      *  The Sector Erase instruction sets all memory within a specified sector (4K-bytes) 
00048      *  to the erased state of all 1s (FFh).
00049      *
00050      *  @param addr      sector address
00051      *  @return          true = success, false = failure
00052      */
00053     bool SectorErase(uint32_t addr) _RAM_PRG;
00054 
00055     /** Page Program
00056      *
00057      *  The Page Program instruction allows from one byte to 256 bytes (a page) of data 
00058      *  to be programmed at previously erased (FFh) memory locations.
00059      *
00060      *  @param addr      starting address
00061      *  @param buf       the buffer to read into
00062      *  @param size      size of the data
00063      *  @return          true = success, false = failure
00064      */
00065     bool PageProgram(uint32_t addr, uint8_t * buf, int32_t size) _RAM_PRG;
00066 
00067     /** Read
00068      *
00069      *  The Read Data instruction allows one or more data bytes to be sequentially read 
00070      *  from the memory.
00071      *
00072      *  @param addr      starting address
00073      *  @param buf       the buffer to write from
00074      *  @param size      size of the data
00075      *  @return          true = success, false = failure
00076      */
00077     bool Read(uint32_t addr, uint8_t * buf, int32_t size) _RAM_PRG;
00078 
00079 protected:
00080     typedef struct {
00081         uint32_t cdb;       /* bit-width : command */
00082         uint32_t ocdb;      /* bit-width : optional command */
00083         uint32_t adb;       /* bit-width : address */
00084         uint32_t opdb;      /* bit-width : option data */
00085         uint32_t spidb;     /* bit-width : data */
00086 
00087         uint32_t cde;       /* Enable : command */
00088         uint32_t ocde;      /* Enable : optional command */
00089         uint32_t ade;       /* Enable : address */
00090         uint32_t opde;      /* Enable : option data */
00091         uint32_t spide;     /* Enable : data */
00092 
00093         uint32_t sslkp;     /* SPBSSL level */
00094         uint32_t spire;     /* Enable data read */
00095         uint32_t spiwe;     /* Enable data write */
00096 
00097         uint32_t dme;       /* Enable : dummy cycle */
00098 
00099         uint32_t addre;     /* DDR enable : address  */
00100         uint32_t opdre;     /* DDR enable : option data */
00101         uint32_t spidre;    /* DDR enable : data */
00102 
00103         uint8_t dmdb;       /* bit-width : dummy cycle */
00104         uint8_t dmcyc;      /* number of dummy cycles */
00105 
00106         uint8_t  cmd;       /* command */
00107         uint8_t  ocmd;      /* optional command */
00108         uint32_t addr;      /* address */
00109         uint8_t  opd[4];    /* option data 3/2/1/0 */
00110         uint32_t smrdr[2];  /* read data */
00111         uint32_t smwdr[2];  /* write data */
00112     } st_spibsc_spimd_reg_t;
00113 
00114     volatile struct st_spibsc*  SPIBSC;
00115     st_spibsc_spimd_reg_t spimd_reg;
00116 
00117     bool _SectorErase(uint32_t addr) _RAM_PRG;
00118     bool _PageProgram(uint32_t addr, uint8_t * buf, int32_t size) _RAM_PRG;
00119     bool _Read(uint32_t addr, uint8_t * buf, int32_t size) _RAM_PRG;
00120     bool _WriteEnable(void) _RAM_PRG;
00121     bool _busy_wait(void) _RAM_PRG;
00122     bool _read_register(uint8_t cmd, uint8_t * status) _RAM_PRG;
00123     bool data_send(uint32_t bit_width, uint32_t spbssl_level, uint8_t * buf, int32_t size) _RAM_PRG;
00124     bool data_recv(uint32_t bit_width, uint32_t spbssl_level, uint8_t * buf, int32_t size) _RAM_PRG;
00125     void spi_mode(void) _RAM_PRG;
00126     void ex_mode(void) _RAM_PRG;
00127     void clear_spimd_reg(st_spibsc_spimd_reg_t * regset) _RAM_PRG;
00128     bool spibsc_transfer(st_spibsc_spimd_reg_t * regset) _RAM_PRG;
00129     uint32_t RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask) _RAM_PRG;
00130     void RegWwrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask) _RAM_PRG;
00131 
00132 private:
00133     /*  SPI Multi-I/O bus address space address definitions */
00134     #define SPIBSC_ADDR_START  (0x18000000uL)
00135     #define SPIBSC_ADDR_END    (0x1BFFFFFFuL)
00136 
00137     typedef struct {
00138         uint32_t b0             : 1 ;       /* bit 0        : -         (0)                                   */
00139         uint32_t b1             : 1 ;       /* bit 1        : -         (1)                                   */
00140         uint32_t B              : 1 ;       /* bit 2        : B         Memory region attribute bit           */
00141         uint32_t C              : 1 ;       /* bit 3        : C         Memory region attribute bit           */
00142         uint32_t XN             : 1 ;       /* bit 4        : XN        Execute-never bit                     */
00143         uint32_t Domain         : 4 ;       /* bit 8-5      : Domain    Domain field                          */
00144         uint32_t b9             : 1 ;       /* bit 9        : IMP       IMPLEMENTATION DEFINED                */
00145         uint32_t AP1_0          : 2 ;       /* bit 11-10    : AP[1:0]   Access permissions bits:bit1-0        */
00146         uint32_t TEX            : 3 ;       /* bit 14-12    : TEX[2:0]  Memory region attribute bits          */
00147         uint32_t AP2            : 1 ;       /* bit 15       : AP[2]     Access permissions bits:bit2          */
00148         uint32_t S              : 1 ;       /* bit 16       : S         Shareable bit                         */
00149         uint32_t nG             : 1 ;       /* bit 17       : nG        Not global bit                        */
00150         uint32_t b18            : 1 ;       /* bit 18       : -         (0)                                   */
00151         uint32_t NS             : 1 ;       /* bit 19       : NS        Non-secure bit                        */
00152         uint32_t base_addr      : 12;       /* bit 31-20    : PA[31:20] PA(physical address) bits:bit31-20    */
00153     } mmu_ttbl_desc_section_t;
00154 
00155     mmu_ttbl_desc_section_t desc_tbl[(SPIBSC_ADDR_END >> 20) - (SPIBSC_ADDR_START >> 20) + 1];
00156 
00157     void change_mmu_ttbl_spibsc(uint32_t type) _RAM_PRG;
00158     void spibsc_stop(void) _RAM_PRG;
00159     void cache_control(void) _RAM_PRG;
00160 };
00161 #endif