Daiki Kato / FlashAccess

Flash access library for GR-Boards.

spibsc.h@1:652a093cf264, 2017-11-28 (annotated)

Committer:
dkato
Date:
Tue Nov 28 06:46:10 2017 +0000
Revision:
1:652a093cf264
Parent:
0:5a74eeaefb5d 
Text update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:5a74eeaefb5d 1 /*******************************************************************************
dkato 0:5a74eeaefb5d 2 * DISCLAIMER
dkato 0:5a74eeaefb5d 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:5a74eeaefb5d 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:5a74eeaefb5d 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:5a74eeaefb5d 6 * all applicable laws, including copyright laws.
dkato 0:5a74eeaefb5d 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:5a74eeaefb5d 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:5a74eeaefb5d 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:5a74eeaefb5d 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:5a74eeaefb5d 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:5a74eeaefb5d 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:5a74eeaefb5d 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:5a74eeaefb5d 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:5a74eeaefb5d 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:5a74eeaefb5d 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:5a74eeaefb5d 17 * and to discontinue the availability of this software. By using this software,
dkato 0:5a74eeaefb5d 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:5a74eeaefb5d 19 * following link:
dkato 0:5a74eeaefb5d 20 * http://www.renesas.com/disclaimer
dkato 0:5a74eeaefb5d 21 *
dkato 0:5a74eeaefb5d 22 * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
dkato 0:5a74eeaefb5d 23 *******************************************************************************/
dkato 0:5a74eeaefb5d 24 /******************************************************************************
dkato 0:5a74eeaefb5d 25 * File Name : spibsc.h
dkato 0:5a74eeaefb5d 26 * $Rev: 12 $
dkato 0:5a74eeaefb5d 27 * $Date:: 2016-05-19 17:26:37 +0900#$
dkato 0:5a74eeaefb5d 28 * Description :
dkato 0:5a74eeaefb5d 29 ******************************************************************************/
dkato 0:5a74eeaefb5d 30 #ifndef _SPIBSC_H_
dkato 0:5a74eeaefb5d 31 #define _SPIBSC_H_
dkato 0:5a74eeaefb5d 32
dkato 0:5a74eeaefb5d 33 /******************************************************************************
dkato 0:5a74eeaefb5d 34 Includes <System Includes> , "Project Includes"
dkato 0:5a74eeaefb5d 35 ******************************************************************************/
dkato 0:5a74eeaefb5d 36 #include "iodefine.h"
dkato 0:5a74eeaefb5d 37
dkato 0:5a74eeaefb5d 38 /******************************************************************************
dkato 0:5a74eeaefb5d 39 Macro definitions
dkato 0:5a74eeaefb5d 40 ******************************************************************************/
dkato 0:5a74eeaefb5d 41 #define SPIBSC_CMNCR_MD_EXTRD (0u)
dkato 0:5a74eeaefb5d 42 #define SPIBSC_CMNCR_MD_SPI (1u)
dkato 0:5a74eeaefb5d 43
dkato 0:5a74eeaefb5d 44 #define SPIBSC_OUTPUT_LOW (0u)
dkato 0:5a74eeaefb5d 45 #define SPIBSC_OUTPUT_HIGH (1u)
dkato 0:5a74eeaefb5d 46 #define SPIBSC_OUTPUT_LAST (2u)
dkato 0:5a74eeaefb5d 47 #define SPIBSC_OUTPUT_HiZ (3u)
dkato 0:5a74eeaefb5d 48
dkato 0:5a74eeaefb5d 49 #define SPIBSC_CMNCR_CPHAT_EVEN (0u)
dkato 0:5a74eeaefb5d 50 #define SPIBSC_CMNCR_CPHAT_ODD (1u)
dkato 0:5a74eeaefb5d 51
dkato 0:5a74eeaefb5d 52 #define SPIBSC_CMNCR_CPHAR_ODD (0u)
dkato 0:5a74eeaefb5d 53 #define SPIBSC_CMNCR_CPHAR_EVEN (1u)
dkato 0:5a74eeaefb5d 54
dkato 0:5a74eeaefb5d 55 #define SPIBSC_CMNCR_SSLP_LOW (0u)
dkato 0:5a74eeaefb5d 56 #define SPIBSC_CMNCR_SSLP_HIGH (1u)
dkato 0:5a74eeaefb5d 57
dkato 0:5a74eeaefb5d 58 #define SPIBSC_CMNCR_CPOL_LOW (0u)
dkato 0:5a74eeaefb5d 59 #define SPIBSC_CMNCR_CPOL_HIGH (1u)
dkato 0:5a74eeaefb5d 60
dkato 0:5a74eeaefb5d 61 #define SPIBSC_CMNCR_BSZ_SINGLE (0u)
dkato 0:5a74eeaefb5d 62 #define SPIBSC_CMNCR_BSZ_DUAL (1u)
dkato 0:5a74eeaefb5d 63
dkato 0:5a74eeaefb5d 64 #define SPIBSC_DELAY_1SPBCLK (0u)
dkato 0:5a74eeaefb5d 65 #define SPIBSC_DELAY_2SPBCLK (1u)
dkato 0:5a74eeaefb5d 66 #define SPIBSC_DELAY_3SPBCLK (2u)
dkato 0:5a74eeaefb5d 67 #define SPIBSC_DELAY_4SPBCLK (3u)
dkato 0:5a74eeaefb5d 68 #define SPIBSC_DELAY_5SPBCLK (4u)
dkato 0:5a74eeaefb5d 69 #define SPIBSC_DELAY_6SPBCLK (5u)
dkato 0:5a74eeaefb5d 70 #define SPIBSC_DELAY_7SPBCLK (6u)
dkato 0:5a74eeaefb5d 71 #define SPIBSC_DELAY_8SPBCLK (7u)
dkato 0:5a74eeaefb5d 72
dkato 0:5a74eeaefb5d 73
dkato 0:5a74eeaefb5d 74 #define SPIBSC_BURST_1 (0x00u)
dkato 0:5a74eeaefb5d 75 #define SPIBSC_BURST_2 (0x01u)
dkato 0:5a74eeaefb5d 76 #define SPIBSC_BURST_3 (0x02u)
dkato 0:5a74eeaefb5d 77 #define SPIBSC_BURST_4 (0x03u)
dkato 0:5a74eeaefb5d 78 #define SPIBSC_BURST_5 (0x04u)
dkato 0:5a74eeaefb5d 79 #define SPIBSC_BURST_6 (0x05u)
dkato 0:5a74eeaefb5d 80 #define SPIBSC_BURST_7 (0x06u)
dkato 0:5a74eeaefb5d 81 #define SPIBSC_BURST_8 (0x07u)
dkato 0:5a74eeaefb5d 82 #define SPIBSC_BURST_9 (0x08u)
dkato 0:5a74eeaefb5d 83 #define SPIBSC_BURST_10 (0x09u)
dkato 0:5a74eeaefb5d 84 #define SPIBSC_BURST_11 (0x0au)
dkato 0:5a74eeaefb5d 85 #define SPIBSC_BURST_12 (0x0bu)
dkato 0:5a74eeaefb5d 86 #define SPIBSC_BURST_13 (0x0cu)
dkato 0:5a74eeaefb5d 87 #define SPIBSC_BURST_14 (0x0du)
dkato 0:5a74eeaefb5d 88 #define SPIBSC_BURST_15 (0x0eu)
dkato 0:5a74eeaefb5d 89 #define SPIBSC_BURST_16 (0x0fu)
dkato 0:5a74eeaefb5d 90
dkato 0:5a74eeaefb5d 91 #define SPIBSC_BURST_DISABLE (0u)
dkato 0:5a74eeaefb5d 92 #define SPIBSC_BURST_ENABLE (1u)
dkato 0:5a74eeaefb5d 93
dkato 0:5a74eeaefb5d 94 #define SPIBSC_DRCR_RCF_EXE (1u)
dkato 0:5a74eeaefb5d 95
dkato 0:5a74eeaefb5d 96 #define SPIBSC_SSL_NEGATE (0u)
dkato 0:5a74eeaefb5d 97 #define SPIBSC_TRANS_END (1u)
dkato 0:5a74eeaefb5d 98
dkato 0:5a74eeaefb5d 99 #define SPIBSC_1BIT (0u)
dkato 0:5a74eeaefb5d 100 #define SPIBSC_2BIT (1u)
dkato 0:5a74eeaefb5d 101 #define SPIBSC_4BIT (2u)
dkato 0:5a74eeaefb5d 102
dkato 0:5a74eeaefb5d 103 #define SPIBSC_OUTPUT_DISABLE (0u)
dkato 0:5a74eeaefb5d 104 #define SPIBSC_OUTPUT_ENABLE (1u)
dkato 0:5a74eeaefb5d 105 #define SPIBSC_OUTPUT_ADDR_24 (0x07u)
dkato 0:5a74eeaefb5d 106 #define SPIBSC_OUTPUT_ADDR_32 (0x0fu)
dkato 0:5a74eeaefb5d 107 #define SPIBSC_OUTPUT_OPD_3 (0x08u)
dkato 0:5a74eeaefb5d 108 #define SPIBSC_OUTPUT_OPD_32 (0x0cu)
dkato 0:5a74eeaefb5d 109 #define SPIBSC_OUTPUT_OPD_321 (0x0eu)
dkato 0:5a74eeaefb5d 110 #define SPIBSC_OUTPUT_OPD_3210 (0x0fu)
dkato 0:5a74eeaefb5d 111
dkato 0:5a74eeaefb5d 112 #define SPIBSC_OUTPUT_SPID_8 (0x08u)
dkato 0:5a74eeaefb5d 113 #define SPIBSC_OUTPUT_SPID_16 (0x0cu)
dkato 0:5a74eeaefb5d 114 #define SPIBSC_OUTPUT_SPID_32 (0x0fu)
dkato 0:5a74eeaefb5d 115
dkato 0:5a74eeaefb5d 116 #define SPIBSC_SPISSL_NEGATE (0u)
dkato 0:5a74eeaefb5d 117 #define SPIBSC_SPISSL_KEEP (1u)
dkato 0:5a74eeaefb5d 118
dkato 0:5a74eeaefb5d 119 #define SPIBSC_SPIDATA_DISABLE (0u)
dkato 0:5a74eeaefb5d 120 #define SPIBSC_SPIDATA_ENABLE (1u)
dkato 0:5a74eeaefb5d 121
dkato 0:5a74eeaefb5d 122 #define SPIBSC_SPI_DISABLE (0u)
dkato 0:5a74eeaefb5d 123 #define SPIBSC_SPI_ENABLE (1u)
dkato 0:5a74eeaefb5d 124
dkato 0:5a74eeaefb5d 125
dkato 0:5a74eeaefb5d 126 /* Use for setting of the DME bit of "data read enable register"(DRENR) */
dkato 0:5a74eeaefb5d 127 #define SPIBSC_DUMMY_CYC_DISABLE (0u)
dkato 0:5a74eeaefb5d 128 #define SPIBSC_DUMMY_CYC_ENABLE (1u)
dkato 0:5a74eeaefb5d 129
dkato 0:5a74eeaefb5d 130 /* Use for setting of the DMCYC [2:0] bit of "data read dummy cycle register"(DRDMCR) */
dkato 0:5a74eeaefb5d 131 #define SPIBSC_DUMMY_1CYC (0u)
dkato 0:5a74eeaefb5d 132 #define SPIBSC_DUMMY_2CYC (1u)
dkato 0:5a74eeaefb5d 133 #define SPIBSC_DUMMY_3CYC (2u)
dkato 0:5a74eeaefb5d 134 #define SPIBSC_DUMMY_4CYC (3u)
dkato 0:5a74eeaefb5d 135 #define SPIBSC_DUMMY_5CYC (4u)
dkato 0:5a74eeaefb5d 136 #define SPIBSC_DUMMY_6CYC (5u)
dkato 0:5a74eeaefb5d 137 #define SPIBSC_DUMMY_7CYC (6u)
dkato 0:5a74eeaefb5d 138 #define SPIBSC_DUMMY_8CYC (7u)
dkato 0:5a74eeaefb5d 139
dkato 0:5a74eeaefb5d 140 /* Use for setting of "data read DDR enable register"(DRDRENR) */
dkato 0:5a74eeaefb5d 141 #define SPIBSC_SDR_TRANS (0u)
dkato 0:5a74eeaefb5d 142 #define SPIBSC_DDR_TRANS (1u)
dkato 0:5a74eeaefb5d 143
dkato 0:5a74eeaefb5d 144 /* Use for setting the CKDLY regsiter */
dkato 0:5a74eeaefb5d 145 #define SPIBSC_CKDLY_DEFAULT (0x0000A504uL) /* Initial value */
dkato 0:5a74eeaefb5d 146 #define SPIBSC_CKDLY_TUNING (0x0000A50AuL) /* Shorten the data input setup time and extend the data hold time */
dkato 0:5a74eeaefb5d 147
dkato 0:5a74eeaefb5d 148 /* Use for setting the SPODLY regsiter */
dkato 0:5a74eeaefb5d 149 #define SPIBSC_SPODLY_DEFAULT (0xA5000000uL) /* Initial value */
dkato 0:5a74eeaefb5d 150 #define SPIBSC_SPODLY_TUNING (0xA5001111uL) /* Delay the data output delay/hold/buffer-on/buffer-off time */
dkato 0:5a74eeaefb5d 151
dkato 0:5a74eeaefb5d 152 #endif /* _SPIBSC_H_ */
dkato 0:5a74eeaefb5d 153
dkato 0:5a74eeaefb5d 154 /* End of File */