Chihiro H / 23LCxx_SPI

Microchip SPI SRAM (23LC1024, 23LC512) access library.

23LCxx_SPI.h@0:625ac56d810e, 2015-11-26 (annotated)

Committer:
discypus
Date:
Thu Nov 26 16:24:04 2015 +0000
Revision:
0:625ac56d810e
Child:
1:56e01e806364
initial code. Microchip 23LC1024 is tested.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
discypus 0:625ac56d810e 1 #ifndef MICROCHIP_23LCXXX_SPI_H
discypus 0:625ac56d810e 2 #define MICROCHIP_23LCXXX_SPI_H
discypus 0:625ac56d810e 3
discypus 0:625ac56d810e 4 #include <mbed.h>
discypus 0:625ac56d810e 5
discypus 0:625ac56d810e 6 /**
discypus 0:625ac56d810e 7 * Microchip SPI SRAM access library for 23LC1024, 23K256
discypus 0:625ac56d810e 8 *
discypus 0:625ac56d810e 9 * @code
discypus 0:625ac56d810e 10 * #include <mbed.h>
discypus 0:625ac56d810e 11 * #include "23LCxx_SPI.h"
discypus 0:625ac56d810e 12 *
discypus 0:625ac56d810e 13 * Microchip23LCxx sram(SPI_MOSI, SPI_MISO, SPI_SCK, SPI_CS, 20 * 1000 * 1000);
discypus 0:625ac56d810e 14 *
discypus 0:625ac56d810e 15 * uint8_t buf[256] = {};
discypus 0:625ac56d810e 16 *
discypus 0:625ac56d810e 17 * void main() {
discypus 0:625ac56d810e 18 * const uint32_t address = 0x2000;
discypus 0:625ac56d810e 19 * const uint32_t size = 256;
discypus 0:625ac56d810e 20 *
discypus 0:625ac56d810e 21 * sram.change_mode(Microchip23LCxx::SEQUENTIAL);
discypus 0:625ac56d810e 22 *
discypus 0:625ac56d810e 23 * // write
discypus 0:625ac56d810e 24 * for (uint32_t i = 0; i < size; ++i) {
discypus 0:625ac56d810e 25 * buf[i] = i;
discypus 0:625ac56d810e 26 * }
discypus 0:625ac56d810e 27 * sram.write_bytes(address, buf, size);
discypus 0:625ac56d810e 28 *
discypus 0:625ac56d810e 29 * // read
discypus 0:625ac56d810e 30 * for (uint32_t i = 0; i < size; ++i) {
discypus 0:625ac56d810e 31 * buf[i] = 0;
discypus 0:625ac56d810e 32 * }
discypus 0:625ac56d810e 33 * sram.read_bytes(address, buf, size);
discypus 0:625ac56d810e 34 * }
discypus 0:625ac56d810e 35 * @endcode
discypus 0:625ac56d810e 36 */
discypus 0:625ac56d810e 37 class Microchip23LCxx {
discypus 0:625ac56d810e 38 public:
discypus 0:625ac56d810e 39 enum Microchip23LC1024Mode {
discypus 0:625ac56d810e 40 MODE_MASK = 0xc0u,
discypus 0:625ac56d810e 41 BYTE = 0x00u,
discypus 0:625ac56d810e 42 SEQUENTIAL = 0x40u, // default operation
discypus 0:625ac56d810e 43 PAGE = 0x80u,
discypus 0:625ac56d810e 44 RESERVED = 0xc0u,
discypus 0:625ac56d810e 45 };
discypus 0:625ac56d810e 46
discypus 0:625ac56d810e 47 /**
discypus 0:625ac56d810e 48 * Constructor.
discypus 0:625ac56d810e 49 */
discypus 0:625ac56d810e 50 Microchip23LCxx(PinName mosi, PinName miso, PinName sck, PinName cs, uint32_t hz);
discypus 0:625ac56d810e 51
discypus 0:625ac56d810e 52 /**
discypus 0:625ac56d810e 53 * read from mode register.
discypus 0:625ac56d810e 54 * @return register value
discypus 0:625ac56d810e 55 */
discypus 0:625ac56d810e 56 uint8_t read_mode_register();
discypus 0:625ac56d810e 57
discypus 0:625ac56d810e 58 /**
discypus 0:625ac56d810e 59 * write to mode register.
discypus 0:625ac56d810e 60 * @param[in] mode
discypus 0:625ac56d810e 61 */
discypus 0:625ac56d810e 62 void write_mode_register(const uint8_t value);
discypus 0:625ac56d810e 63
discypus 0:625ac56d810e 64 /**
discypus 0:625ac56d810e 65 * change mode bits.
discypus 0:625ac56d810e 66 * @param[in] mode mode
discypus 0:625ac56d810e 67 * @return mode before change
discypus 0:625ac56d810e 68 * @invariant other bits in register.
discypus 0:625ac56d810e 69 */
discypus 0:625ac56d810e 70 uint8_t change_mode(const uint8_t next_mode);
discypus 0:625ac56d810e 71
discypus 0:625ac56d810e 72 /**
discypus 0:625ac56d810e 73 * 1byte read
discypus 0:625ac56d810e 74 * @param[in] address adress in 24bit
discypus 0:625ac56d810e 75 * @return read data
discypus 0:625ac56d810e 76 */
discypus 0:625ac56d810e 77 uint8_t read_byte(const uint32_t address);
discypus 0:625ac56d810e 78
discypus 0:625ac56d810e 79 /**
discypus 0:625ac56d810e 80 * 1byte write
discypus 0:625ac56d810e 81 * @param[in] address address in 24bit
discypus 0:625ac56d810e 82 * @param[in] write data
discypus 0:625ac56d810e 83 */
discypus 0:625ac56d810e 84 void write_byte(const uint32_t address, const uint8_t data);
discypus 0:625ac56d810e 85
discypus 0:625ac56d810e 86 /**
discypus 0:625ac56d810e 87 * multi-byte read
discypus 0:625ac56d810e 88 * @pre sequential mode or page mode is required.
discypus 0:625ac56d810e 89 */
discypus 0:625ac56d810e 90 void read_bytes(const uint32_t address, uint8_t __restrict data[], const uint32_t size);
discypus 0:625ac56d810e 91
discypus 0:625ac56d810e 92 /**
discypus 0:625ac56d810e 93 * multi-byte write
discypus 0:625ac56d810e 94 * @pre sequential mode or page mode is required.
discypus 0:625ac56d810e 95 */
discypus 0:625ac56d810e 96 void write_bytes(const uint32_t address, const uint8_t __restrict data[], const uint32_t size);
discypus 0:625ac56d810e 97
discypus 0:625ac56d810e 98 private:
discypus 0:625ac56d810e 99 SPI _spi;
discypus 0:625ac56d810e 100 DigitalOut _cs;
discypus 0:625ac56d810e 101 void _set_address(const uint32_t address);
discypus 0:625ac56d810e 102 };
discypus 0:625ac56d810e 103
discypus 0:625ac56d810e 104 #endif