Chihiro H / 23LCxx_SPI

Microchip SPI SRAM (23LC1024, 23LC512) access library.

23LCxx_SPI.cpp@0:625ac56d810e, 2015-11-26 (annotated)

Committer:
discypus
Date:
Thu Nov 26 16:24:04 2015 +0000
Revision:
0:625ac56d810e
Child:
1:56e01e806364
initial code. Microchip 23LC1024 is tested.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
discypus 0:625ac56d810e 1
discypus 0:625ac56d810e 2 #include <mbed.h>
discypus 0:625ac56d810e 3 #include "23LCxx_SPI.h"
discypus 0:625ac56d810e 4
discypus 0:625ac56d810e 5 /** SPI COMMAND (Microchip 23LC1024, 23K256 SPI SRAM) */
discypus 0:625ac56d810e 6 enum Microchip23LC1024Commnd {
discypus 0:625ac56d810e 7 READ = 0x03u,
discypus 0:625ac56d810e 8 WRITE = 0x02u,
discypus 0:625ac56d810e 9 EDIO = 0x3bu,
discypus 0:625ac56d810e 10 EQIO = 0x38u,
discypus 0:625ac56d810e 11 RSTIO = 0xffu,
discypus 0:625ac56d810e 12 RDMR = 0x05u,
discypus 0:625ac56d810e 13 WRMR = 0x01u,
discypus 0:625ac56d810e 14 };
discypus 0:625ac56d810e 15
discypus 0:625ac56d810e 16 Microchip23LCxx::Microchip23LCxx(PinName mosi, PinName miso, PinName sck, PinName cs, uint32_t hz) : _spi(mosi, miso, sck), _cs(cs) {
discypus 0:625ac56d810e 17 _spi.format(8, 0); // 8bit, mode=0
discypus 0:625ac56d810e 18 _spi.frequency(hz); // max 20MHz (20*1000*1000) in 23LC1024.
discypus 0:625ac56d810e 19 _cs = 1;
discypus 0:625ac56d810e 20 }
discypus 0:625ac56d810e 21
discypus 0:625ac56d810e 22 uint8_t
discypus 0:625ac56d810e 23 Microchip23LCxx::read_mode_register() {
discypus 0:625ac56d810e 24 _cs = 0;
discypus 0:625ac56d810e 25 _spi.write(RDMR);
discypus 0:625ac56d810e 26 const uint8_t value = _spi.write(0x00);
discypus 0:625ac56d810e 27 _cs = 1;
discypus 0:625ac56d810e 28
discypus 0:625ac56d810e 29 return value;
discypus 0:625ac56d810e 30 }
discypus 0:625ac56d810e 31
discypus 0:625ac56d810e 32 void
discypus 0:625ac56d810e 33 Microchip23LCxx::write_mode_register(const uint8_t value) {
discypus 0:625ac56d810e 34 _cs = 0;
discypus 0:625ac56d810e 35 _spi.write(WRMR);
discypus 0:625ac56d810e 36 _spi.write(value);
discypus 0:625ac56d810e 37 _cs = 1;
discypus 0:625ac56d810e 38 }
discypus 0:625ac56d810e 39
discypus 0:625ac56d810e 40 uint8_t
discypus 0:625ac56d810e 41 Microchip23LCxx::change_mode(const uint8_t next_mode) {
discypus 0:625ac56d810e 42 const uint8_t previous_register = read_mode_register();
discypus 0:625ac56d810e 43 const uint8_t previous_mode = previous_register & MODE_MASK;
discypus 0:625ac56d810e 44 if (next_mode != previous_mode) {
discypus 0:625ac56d810e 45 const uint8_t next_register = (previous_register & ~MODE_MASK) | uint8_t(next_mode);
discypus 0:625ac56d810e 46 write_mode_register(next_register);
discypus 0:625ac56d810e 47 }
discypus 0:625ac56d810e 48 return previous_mode;
discypus 0:625ac56d810e 49 }
discypus 0:625ac56d810e 50
discypus 0:625ac56d810e 51 void
discypus 0:625ac56d810e 52 Microchip23LCxx::_set_address(const uint32_t address) {
discypus 0:625ac56d810e 53 const uint8_t address_high = (address >> (8 * 2)) & 0xFFu;
discypus 0:625ac56d810e 54 const uint8_t address_mid = (address >> (8 * 1)) & 0xFFu;
discypus 0:625ac56d810e 55 const uint8_t address_low = (address >> (8 * 0)) & 0xFFu;
discypus 0:625ac56d810e 56 _spi.write(address_high);
discypus 0:625ac56d810e 57 _spi.write(address_mid);
discypus 0:625ac56d810e 58 _spi.write(address_low);
discypus 0:625ac56d810e 59 }
discypus 0:625ac56d810e 60
discypus 0:625ac56d810e 61 uint8_t
discypus 0:625ac56d810e 62 Microchip23LCxx::read_byte(const uint32_t address) {
discypus 0:625ac56d810e 63 _cs = 0;
discypus 0:625ac56d810e 64 _spi.write(READ);
discypus 0:625ac56d810e 65 _set_address(address);
discypus 0:625ac56d810e 66 const uint8_t data = _spi.write(0);
discypus 0:625ac56d810e 67 _cs = 1;
discypus 0:625ac56d810e 68
discypus 0:625ac56d810e 69 return data;
discypus 0:625ac56d810e 70 }
discypus 0:625ac56d810e 71
discypus 0:625ac56d810e 72 void
discypus 0:625ac56d810e 73 Microchip23LCxx::write_byte(const uint32_t address, const uint8_t data) {
discypus 0:625ac56d810e 74 _cs = 0;
discypus 0:625ac56d810e 75 _spi.write(WRITE);
discypus 0:625ac56d810e 76 _set_address(address);
discypus 0:625ac56d810e 77 _spi.write(data);
discypus 0:625ac56d810e 78 _cs = 1;
discypus 0:625ac56d810e 79 }
discypus 0:625ac56d810e 80
discypus 0:625ac56d810e 81 /**
discypus 0:625ac56d810e 82 * multi-byte read
discypus 0:625ac56d810e 83 * @pre sequential mode or page mode is required.
discypus 0:625ac56d810e 84 */
discypus 0:625ac56d810e 85 void
discypus 0:625ac56d810e 86 Microchip23LCxx::read_bytes(const uint32_t address, uint8_t __restrict data[], const uint32_t size) {
discypus 0:625ac56d810e 87 _cs = 0;
discypus 0:625ac56d810e 88 _spi.write(READ);
discypus 0:625ac56d810e 89 _set_address(address);
discypus 0:625ac56d810e 90 for (uint32_t i = 0; i < size; ++i) {
discypus 0:625ac56d810e 91 data[i] = _spi.write(0x00u);
discypus 0:625ac56d810e 92 }
discypus 0:625ac56d810e 93 _cs = 1;
discypus 0:625ac56d810e 94 }
discypus 0:625ac56d810e 95
discypus 0:625ac56d810e 96 /**
discypus 0:625ac56d810e 97 * multi-byte write
discypus 0:625ac56d810e 98 * @pre sequential mode or page mode is required.
discypus 0:625ac56d810e 99 */
discypus 0:625ac56d810e 100 void
discypus 0:625ac56d810e 101 Microchip23LCxx::write_bytes(const uint32_t address, const uint8_t __restrict data[], const uint32_t size) {
discypus 0:625ac56d810e 102 _cs = 0;
discypus 0:625ac56d810e 103 _spi.write(WRITE);
discypus 0:625ac56d810e 104 _set_address(address);
discypus 0:625ac56d810e 105 for (uint32_t i = 0; i < size; ++i) {
discypus 0:625ac56d810e 106 _spi.write(data[i]);
discypus 0:625ac56d810e 107 }
discypus 0:625ac56d810e 108 _cs = 1;
discypus 0:625ac56d810e 109 }