Damian Gabino / picoGW_mcu

MCU driver/HAL for the Picocell Gateway concentrator board. The firmware implements either a USB CDC protocol or a UART protocol to bridge commands coming from host to the SX1308 SPI interface.

src/mbed-dev/api/SPI.h@0:c76361bd82e8, 2018-04-11 (annotated)

Committer:
dgabino
Date:
Wed Apr 11 14:42:47 2018 +0000
Revision:
0:c76361bd82e8
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dgabino 0:c76361bd82e8 1 /* mbed Microcontroller Library
dgabino 0:c76361bd82e8 2 * Copyright (c) 2006-2015 ARM Limited
dgabino 0:c76361bd82e8 3 *
dgabino 0:c76361bd82e8 4 * Licensed under the Apache License, Version 2.0 (the "License");
dgabino 0:c76361bd82e8 5 * you may not use this file except in compliance with the License.
dgabino 0:c76361bd82e8 6 * You may obtain a copy of the License at
dgabino 0:c76361bd82e8 7 *
dgabino 0:c76361bd82e8 8 * http://www.apache.org/licenses/LICENSE-2.0
dgabino 0:c76361bd82e8 9 *
dgabino 0:c76361bd82e8 10 * Unless required by applicable law or agreed to in writing, software
dgabino 0:c76361bd82e8 11 * distributed under the License is distributed on an "AS IS" BASIS,
dgabino 0:c76361bd82e8 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
dgabino 0:c76361bd82e8 13 * See the License for the specific language governing permissions and
dgabino 0:c76361bd82e8 14 * limitations under the License.
dgabino 0:c76361bd82e8 15 */
dgabino 0:c76361bd82e8 16 #ifndef MBED_SPI_H
dgabino 0:c76361bd82e8 17 #define MBED_SPI_H
dgabino 0:c76361bd82e8 18
dgabino 0:c76361bd82e8 19 #include "platform.h"
dgabino 0:c76361bd82e8 20
dgabino 0:c76361bd82e8 21 #if DEVICE_SPI
dgabino 0:c76361bd82e8 22
dgabino 0:c76361bd82e8 23 #include "PlatformMutex.h"
dgabino 0:c76361bd82e8 24 #include "spi_api.h"
dgabino 0:c76361bd82e8 25 #include "SingletonPtr.h"
dgabino 0:c76361bd82e8 26
dgabino 0:c76361bd82e8 27 #if DEVICE_SPI_ASYNCH
dgabino 0:c76361bd82e8 28 #include "CThunk.h"
dgabino 0:c76361bd82e8 29 #include "dma_api.h"
dgabino 0:c76361bd82e8 30 #include "CircularBuffer.h"
dgabino 0:c76361bd82e8 31 #include "FunctionPointer.h"
dgabino 0:c76361bd82e8 32 #include "Transaction.h"
dgabino 0:c76361bd82e8 33 #endif
dgabino 0:c76361bd82e8 34
dgabino 0:c76361bd82e8 35 namespace mbed {
dgabino 0:c76361bd82e8 36
dgabino 0:c76361bd82e8 37 /** A SPI Master, used for communicating with SPI slave devices
dgabino 0:c76361bd82e8 38 *
dgabino 0:c76361bd82e8 39 * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
dgabino 0:c76361bd82e8 40 *
dgabino 0:c76361bd82e8 41 * Most SPI devices will also require Chip Select and Reset signals. These
dgabino 0:c76361bd82e8 42 * can be controlled using <DigitalOut> pins
dgabino 0:c76361bd82e8 43 *
dgabino 0:c76361bd82e8 44 * @Note Synchronization level: Thread safe
dgabino 0:c76361bd82e8 45 *
dgabino 0:c76361bd82e8 46 * Example:
dgabino 0:c76361bd82e8 47 * @code
dgabino 0:c76361bd82e8 48 * // Send a byte to a SPI slave, and record the response
dgabino 0:c76361bd82e8 49 *
dgabino 0:c76361bd82e8 50 * #include "mbed.h"
dgabino 0:c76361bd82e8 51 *
dgabino 0:c76361bd82e8 52 * // hardware ssel (where applicable)
dgabino 0:c76361bd82e8 53 * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
dgabino 0:c76361bd82e8 54 *
dgabino 0:c76361bd82e8 55 * // software ssel
dgabino 0:c76361bd82e8 56 * SPI device(p5, p6, p7); // mosi, miso, sclk
dgabino 0:c76361bd82e8 57 * DigitalOut cs(p8); // ssel
dgabino 0:c76361bd82e8 58 *
dgabino 0:c76361bd82e8 59 * int main() {
dgabino 0:c76361bd82e8 60 * // hardware ssel (where applicable)
dgabino 0:c76361bd82e8 61 * //int response = device.write(0xFF);
dgabino 0:c76361bd82e8 62 *
dgabino 0:c76361bd82e8 63 * device.lock();
dgabino 0:c76361bd82e8 64 * // software ssel
dgabino 0:c76361bd82e8 65 * cs = 0;
dgabino 0:c76361bd82e8 66 * int response = device.write(0xFF);
dgabino 0:c76361bd82e8 67 * cs = 1;
dgabino 0:c76361bd82e8 68 * device.unlock();
dgabino 0:c76361bd82e8 69 *
dgabino 0:c76361bd82e8 70 * }
dgabino 0:c76361bd82e8 71 * @endcode
dgabino 0:c76361bd82e8 72 */
dgabino 0:c76361bd82e8 73 class SPI {
dgabino 0:c76361bd82e8 74
dgabino 0:c76361bd82e8 75 public:
dgabino 0:c76361bd82e8 76
dgabino 0:c76361bd82e8 77 /** Create a SPI master connected to the specified pins
dgabino 0:c76361bd82e8 78 *
dgabino 0:c76361bd82e8 79 * mosi or miso can be specfied as NC if not used
dgabino 0:c76361bd82e8 80 *
dgabino 0:c76361bd82e8 81 * @param mosi SPI Master Out, Slave In pin
dgabino 0:c76361bd82e8 82 * @param miso SPI Master In, Slave Out pin
dgabino 0:c76361bd82e8 83 * @param sclk SPI Clock pin
dgabino 0:c76361bd82e8 84 * @param ssel SPI chip select pin
dgabino 0:c76361bd82e8 85 */
dgabino 0:c76361bd82e8 86 SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);
dgabino 0:c76361bd82e8 87
dgabino 0:c76361bd82e8 88 /** Configure the data transmission format
dgabino 0:c76361bd82e8 89 *
dgabino 0:c76361bd82e8 90 * @param bits Number of bits per SPI frame (4 - 16)
dgabino 0:c76361bd82e8 91 * @param mode Clock polarity and phase mode (0 - 3)
dgabino 0:c76361bd82e8 92 *
dgabino 0:c76361bd82e8 93 * @code
dgabino 0:c76361bd82e8 94 * mode | POL PHA
dgabino 0:c76361bd82e8 95 * -----+--------
dgabino 0:c76361bd82e8 96 * 0 | 0 0
dgabino 0:c76361bd82e8 97 * 1 | 0 1
dgabino 0:c76361bd82e8 98 * 2 | 1 0
dgabino 0:c76361bd82e8 99 * 3 | 1 1
dgabino 0:c76361bd82e8 100 * @endcode
dgabino 0:c76361bd82e8 101 */
dgabino 0:c76361bd82e8 102 void format(int bits, int mode = 0);
dgabino 0:c76361bd82e8 103
dgabino 0:c76361bd82e8 104 /** Set the spi bus clock frequency
dgabino 0:c76361bd82e8 105 *
dgabino 0:c76361bd82e8 106 * @param hz SCLK frequency in hz (default = 1MHz)
dgabino 0:c76361bd82e8 107 */
dgabino 0:c76361bd82e8 108 void frequency(int hz = 1000000);
dgabino 0:c76361bd82e8 109
dgabino 0:c76361bd82e8 110 /** Write to the SPI Slave and return the response
dgabino 0:c76361bd82e8 111 *
dgabino 0:c76361bd82e8 112 * @param value Data to be sent to the SPI slave
dgabino 0:c76361bd82e8 113 *
dgabino 0:c76361bd82e8 114 * @returns
dgabino 0:c76361bd82e8 115 * Response from the SPI slave
dgabino 0:c76361bd82e8 116 */
dgabino 0:c76361bd82e8 117 virtual int write(int value);
dgabino 0:c76361bd82e8 118
dgabino 0:c76361bd82e8 119 /** Acquire exclusive access to this SPI bus
dgabino 0:c76361bd82e8 120 */
dgabino 0:c76361bd82e8 121 virtual void lock(void);
dgabino 0:c76361bd82e8 122
dgabino 0:c76361bd82e8 123 /** Release exclusive access to this SPI bus
dgabino 0:c76361bd82e8 124 */
dgabino 0:c76361bd82e8 125 virtual void unlock(void);
dgabino 0:c76361bd82e8 126
dgabino 0:c76361bd82e8 127 #if DEVICE_SPI_ASYNCH
dgabino 0:c76361bd82e8 128
dgabino 0:c76361bd82e8 129 /** Start non-blocking SPI transfer using 8bit buffers.
dgabino 0:c76361bd82e8 130 *
dgabino 0:c76361bd82e8 131 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
dgabino 0:c76361bd82e8 132 * the default SPI value is sent
dgabino 0:c76361bd82e8 133 * @param tx_length The length of TX buffer in bytes
dgabino 0:c76361bd82e8 134 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
dgabino 0:c76361bd82e8 135 * received data are ignored
dgabino 0:c76361bd82e8 136 * @param rx_length The length of RX buffer in bytes
dgabino 0:c76361bd82e8 137 * @param callback The event callback function
dgabino 0:c76361bd82e8 138 * @param event The logical OR of events to modify. Look at spi hal header file for SPI events.
dgabino 0:c76361bd82e8 139 * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
dgabino 0:c76361bd82e8 140 */
dgabino 0:c76361bd82e8 141 template<typename Type>
dgabino 0:c76361bd82e8 142 int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) {
dgabino 0:c76361bd82e8 143 if (spi_active(&_spi)) {
dgabino 0:c76361bd82e8 144 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
dgabino 0:c76361bd82e8 145 }
dgabino 0:c76361bd82e8 146 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
dgabino 0:c76361bd82e8 147 return 0;
dgabino 0:c76361bd82e8 148 }
dgabino 0:c76361bd82e8 149
dgabino 0:c76361bd82e8 150 /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
dgabino 0:c76361bd82e8 151 */
dgabino 0:c76361bd82e8 152 void abort_transfer();
dgabino 0:c76361bd82e8 153
dgabino 0:c76361bd82e8 154 /** Clear the transaction buffer
dgabino 0:c76361bd82e8 155 */
dgabino 0:c76361bd82e8 156 void clear_transfer_buffer();
dgabino 0:c76361bd82e8 157
dgabino 0:c76361bd82e8 158 /** Clear the transaction buffer and abort on-going transfer.
dgabino 0:c76361bd82e8 159 */
dgabino 0:c76361bd82e8 160 void abort_all_transfers();
dgabino 0:c76361bd82e8 161
dgabino 0:c76361bd82e8 162 /** Configure DMA usage suggestion for non-blocking transfers
dgabino 0:c76361bd82e8 163 *
dgabino 0:c76361bd82e8 164 * @param usage The usage DMA hint for peripheral
dgabino 0:c76361bd82e8 165 * @return Zero if the usage was set, -1 if a transaction is on-going
dgabino 0:c76361bd82e8 166 */
dgabino 0:c76361bd82e8 167 int set_dma_usage(DMAUsage usage);
dgabino 0:c76361bd82e8 168
dgabino 0:c76361bd82e8 169 protected:
dgabino 0:c76361bd82e8 170 /** SPI IRQ handler
dgabino 0:c76361bd82e8 171 *
dgabino 0:c76361bd82e8 172 */
dgabino 0:c76361bd82e8 173 void irq_handler_asynch(void);
dgabino 0:c76361bd82e8 174
dgabino 0:c76361bd82e8 175 /** Common transfer method
dgabino 0:c76361bd82e8 176 *
dgabino 0:c76361bd82e8 177 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
dgabino 0:c76361bd82e8 178 * the default SPI value is sent
dgabino 0:c76361bd82e8 179 * @param tx_length The length of TX buffer in bytes
dgabino 0:c76361bd82e8 180 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
dgabino 0:c76361bd82e8 181 * received data are ignored
dgabino 0:c76361bd82e8 182 * @param rx_length The length of RX buffer in bytes
dgabino 0:c76361bd82e8 183 * @param bit_width The buffers element width
dgabino 0:c76361bd82e8 184 * @param callback The event callback function
dgabino 0:c76361bd82e8 185 * @param event The logical OR of events to modify
dgabino 0:c76361bd82e8 186 * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
dgabino 0:c76361bd82e8 187 */
dgabino 0:c76361bd82e8 188 int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
dgabino 0:c76361bd82e8 189
dgabino 0:c76361bd82e8 190 /**
dgabino 0:c76361bd82e8 191 *
dgabino 0:c76361bd82e8 192 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
dgabino 0:c76361bd82e8 193 * the default SPI value is sent
dgabino 0:c76361bd82e8 194 * @param tx_length The length of TX buffer in bytes
dgabino 0:c76361bd82e8 195 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
dgabino 0:c76361bd82e8 196 * received data are ignored
dgabino 0:c76361bd82e8 197 * @param rx_length The length of RX buffer in bytes
dgabino 0:c76361bd82e8 198 * @param bit_width The buffers element width
dgabino 0:c76361bd82e8 199 * @param callback The event callback function
dgabino 0:c76361bd82e8 200 * @param event The logical OR of events to modify
dgabino 0:c76361bd82e8 201 * @return Zero if a transfer was added to the queue, or -1 if the queue is full
dgabino 0:c76361bd82e8 202 */
dgabino 0:c76361bd82e8 203 int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
dgabino 0:c76361bd82e8 204
dgabino 0:c76361bd82e8 205 /** Configures a callback, spi peripheral and initiate a new transfer
dgabino 0:c76361bd82e8 206 *
dgabino 0:c76361bd82e8 207 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
dgabino 0:c76361bd82e8 208 * the default SPI value is sent
dgabino 0:c76361bd82e8 209 * @param tx_length The length of TX buffer in bytes
dgabino 0:c76361bd82e8 210 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
dgabino 0:c76361bd82e8 211 * received data are ignored
dgabino 0:c76361bd82e8 212 * @param rx_length The length of RX buffer in bytes
dgabino 0:c76361bd82e8 213 * @param bit_width The buffers element width
dgabino 0:c76361bd82e8 214 * @param callback The event callback function
dgabino 0:c76361bd82e8 215 * @param event The logical OR of events to modify
dgabino 0:c76361bd82e8 216 */
dgabino 0:c76361bd82e8 217 void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
dgabino 0:c76361bd82e8 218
dgabino 0:c76361bd82e8 219 #if TRANSACTION_QUEUE_SIZE_SPI
dgabino 0:c76361bd82e8 220
dgabino 0:c76361bd82e8 221 /** Start a new transaction
dgabino 0:c76361bd82e8 222 *
dgabino 0:c76361bd82e8 223 * @param data Transaction data
dgabino 0:c76361bd82e8 224 */
dgabino 0:c76361bd82e8 225 void start_transaction(transaction_t *data);
dgabino 0:c76361bd82e8 226
dgabino 0:c76361bd82e8 227 /** Dequeue a transaction
dgabino 0:c76361bd82e8 228 *
dgabino 0:c76361bd82e8 229 */
dgabino 0:c76361bd82e8 230 void dequeue_transaction();
dgabino 0:c76361bd82e8 231 static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
dgabino 0:c76361bd82e8 232 #endif
dgabino 0:c76361bd82e8 233
dgabino 0:c76361bd82e8 234 #endif
dgabino 0:c76361bd82e8 235
dgabino 0:c76361bd82e8 236 public:
dgabino 0:c76361bd82e8 237 virtual ~SPI() {
dgabino 0:c76361bd82e8 238 }
dgabino 0:c76361bd82e8 239
dgabino 0:c76361bd82e8 240 protected:
dgabino 0:c76361bd82e8 241 spi_t _spi;
dgabino 0:c76361bd82e8 242
dgabino 0:c76361bd82e8 243 #if DEVICE_SPI_ASYNCH
dgabino 0:c76361bd82e8 244 CThunk<SPI> _irq;
dgabino 0:c76361bd82e8 245 event_callback_t _callback;
dgabino 0:c76361bd82e8 246 DMAUsage _usage;
dgabino 0:c76361bd82e8 247 #endif
dgabino 0:c76361bd82e8 248
dgabino 0:c76361bd82e8 249 void aquire(void);
dgabino 0:c76361bd82e8 250 static SPI *_owner;
dgabino 0:c76361bd82e8 251 static SingletonPtr<PlatformMutex> _mutex;
dgabino 0:c76361bd82e8 252 int _bits;
dgabino 0:c76361bd82e8 253 int _mode;
dgabino 0:c76361bd82e8 254 int _hz;
dgabino 0:c76361bd82e8 255 };
dgabino 0:c76361bd82e8 256
dgabino 0:c76361bd82e8 257 } // namespace mbed
dgabino 0:c76361bd82e8 258
dgabino 0:c76361bd82e8 259 #endif
dgabino 0:c76361bd82e8 260
dgabino 0:c76361bd82e8 261 #endif