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Port of TI's CC3100 Websock camera demo. Using FreeRTOS, mbedTLS, also parts of Arducam for cams ov5642 and 0v2640. Can also use MT9D111. Work in progress. Be warned some parts maybe a bit flacky. This is for Seeed Arch max only, for an M3, see the demo for CM3 using the 0v5642 aducam mini.
Diff: main.cpp
- Revision:
- 12:7d75ba5deed1
- Parent:
- 11:404bd8bb7fa6
- Child:
- 13:bf45f592c2b6
--- a/main.cpp Tue Jul 07 22:56:31 2015 +0000 +++ b/main.cpp Sun Jul 12 09:13:56 2015 +0000 @@ -60,6 +60,7 @@ #include "cli_uart.h" #include "app_config.h" #include "myBoardInit.h" +#include "camera_app.h" using namespace mbed_cc3100; @@ -73,8 +74,8 @@ static void SystemClock_Config(void) { - SystemCoreClockUpdate(); - +// SystemCoreClockUpdate(); +/* RCC_OscInitTypeDef RCC_OscInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct; // RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;//Used for ov7670 test @@ -106,27 +107,27 @@ // PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; // PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; // HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - +*/ /* RCC_MCODIV_5 33.6MHz mco2 output on pin PC_9 (cam xclk) */ /* RCC_MCODIV_4 42MHz mco2 output on pin PC_9 (cam xclk) */ /* RCC_MCODIV_3 56MHz mco2 output on pin PC_9 (cam xclk) */ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); /* RCC_MCODIV_1 16MHz mco1 output on pin PA_8 (cam xclk) */ -// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); /* RCC_MCODIV_1 8MHz mco2 output on pin PC_9 (cam xclk) */ /* RCC_MCODIV_2 4MHz mco2 output on pin PC_9 (cam xclk) */ /* RCC_MCODIV_4 2MHz mco2 output on pin PC_9 (cam xclk) */ - HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_HSE, RCC_MCODIV_4); +// HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_HSE, RCC_MCODIV_1); //Used for ov7670 test /* RCC_MCODIV_4 24MHz mco2 output on pin PC_9 (cam xclk) */ // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_PLLI2SCLK, RCC_MCODIV_4); - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); +// HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); +// HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); /* STM32F405x/407x/415x/417x Revision Z devices: prefetch is supported */ // if (HAL_GetREVID() == 0x1001) @@ -211,11 +212,13 @@ //**************************************************************************** int main(void) { + SCB->SHCSR |= 0x00070000; int rv = 0; - HAL_Init(); +// HAL_Init(); SystemClock_Config(); +// DMAConfig(); // // Configuring UART @@ -282,11 +285,11 @@ extern "C" void HardFault_Handler(void) { /* Go to infinite loop when Hard Fault exception occurs */ + Uart_Write((uint8_t*)"\n\rHardFault_Handler \n\r"); printf("Hard Fault Register SCB->HSFR 0x%X \r\n",SCB->HFSR); - printf("Call to Memory Address SCB->BFAR 0x%X ERROR!\r\n",SCB->BFAR); printf("Fault bits set SCB->CFSR 0x%X \r\n",SCB->CFSR); + printf("Call to Memory Address SCB->BFAR 0x%X ERROR!\r\n",SCB->BFAR); printf("Call to Memory Address SCB->MMFAR 0x%X ERROR!\r\n",SCB->MMFAR); - Uart_Write((uint8_t*)"HardFault_Handler \n\r"); while (1) { @@ -299,7 +302,11 @@ * @retval None */ extern "C" void MemManage_Handler(void) -{ +{ + Uart_Write((uint8_t*)"\n\rMemManage_Handler \n\r"); + printf("Fault bits set SCB->CFSR 0x%X \r\n",SCB->CFSR); + printf("Call to Memory Address SCB->BFAR 0x%X ERROR!\r\n",SCB->BFAR); + printf("Call to Memory Address SCB->MMFAR 0x%X ERROR!\r\n",SCB->MMFAR); Uart_Write((uint8_t*)"MemManage_Handler \n\r"); /* Go to infinite loop when Memory Manage exception occurs */ while (1) @@ -314,6 +321,10 @@ */ extern "C" void BusFault_Handler(void) { + Uart_Write((uint8_t*)"\n\rBusFault_Handler \n\r"); + printf("Fault bits set SCB->CFSR 0x%X \r\n",SCB->CFSR); + printf("Call to Memory Address SCB->BFAR 0x%X ERROR!\r\n",SCB->BFAR); + printf("Call to Memory Address SCB->MMFAR 0x%X ERROR!\r\n",SCB->MMFAR); Uart_Write((uint8_t*)"BusFault_Handler \n\r"); /* Go to infinite loop when Bus Fault exception occurs */ while (1)