Devin Alexander / USBDeviceHT

I changed one line of code in the file with path name: USBDeviceHT/targets/TARGET_Maxim

Fork of USBDeviceHT by Helmut Tschemernjak

targets/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_dmacdrv.c@6:c1f162fd7777, 2018-06-01 (annotated)

Committer:
dev_alexander
Date:
Fri Jun 01 21:43:55 2018 +0000
Revision:
6:c1f162fd7777
Parent:
0:a3ea811f80f2 
Fixed Error with code not compiling due to an issue with there not being a (uint32_t) cast of a (void) pointer. Maxim was the only mbed vendor to not have this one (uint32_t) cast in the spot it was added to. Look into public repos for similar cases.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Helmut64 0:a3ea811f80f2 1 /*******************************************************************************
Helmut64 0:a3ea811f80f2 2 * DISCLAIMER
Helmut64 0:a3ea811f80f2 3 * This software is supplied by Renesas Electronics Corporation and is only
Helmut64 0:a3ea811f80f2 4 * intended for use with Renesas products. No other uses are authorized. This
Helmut64 0:a3ea811f80f2 5 * software is owned by Renesas Electronics Corporation and is protected under
Helmut64 0:a3ea811f80f2 6 * all applicable laws, including copyright laws.
Helmut64 0:a3ea811f80f2 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
Helmut64 0:a3ea811f80f2 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
Helmut64 0:a3ea811f80f2 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
Helmut64 0:a3ea811f80f2 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
Helmut64 0:a3ea811f80f2 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
Helmut64 0:a3ea811f80f2 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
Helmut64 0:a3ea811f80f2 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
Helmut64 0:a3ea811f80f2 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
Helmut64 0:a3ea811f80f2 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Helmut64 0:a3ea811f80f2 16 * Renesas reserves the right, without notice, to make changes to this software
Helmut64 0:a3ea811f80f2 17 * and to discontinue the availability of this software. By using this software,
Helmut64 0:a3ea811f80f2 18 * you agree to the additional terms and conditions found by accessing the
Helmut64 0:a3ea811f80f2 19 * following link:
Helmut64 0:a3ea811f80f2 20 * http://www.renesas.com/disclaimer
Helmut64 0:a3ea811f80f2 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
Helmut64 0:a3ea811f80f2 22 *******************************************************************************/
Helmut64 0:a3ea811f80f2 23 /*******************************************************************************
Helmut64 0:a3ea811f80f2 24 * File Name : usb1_function_dmacdrv.c
Helmut64 0:a3ea811f80f2 25 * $Rev: 1116 $
Helmut64 0:a3ea811f80f2 26 * $Date:: 2014-07-09 16:29:19 +0900#$
Helmut64 0:a3ea811f80f2 27 * Device(s) : RZ/A1H
Helmut64 0:a3ea811f80f2 28 * Tool-Chain :
Helmut64 0:a3ea811f80f2 29 * OS : None
Helmut64 0:a3ea811f80f2 30 * H/W Platform :
Helmut64 0:a3ea811f80f2 31 * Description : RZ/A1H R7S72100 USB Sample Program
Helmut64 0:a3ea811f80f2 32 * Operation :
Helmut64 0:a3ea811f80f2 33 * Limitations :
Helmut64 0:a3ea811f80f2 34 *******************************************************************************/
Helmut64 0:a3ea811f80f2 35
Helmut64 0:a3ea811f80f2 36
Helmut64 0:a3ea811f80f2 37 /*******************************************************************************
Helmut64 0:a3ea811f80f2 38 Includes <System Includes> , "Project Includes"
Helmut64 0:a3ea811f80f2 39 *******************************************************************************/
Helmut64 0:a3ea811f80f2 40 #include <stdio.h>
Helmut64 0:a3ea811f80f2 41 #include "r_typedefs.h"
Helmut64 0:a3ea811f80f2 42 #include "iodefine.h"
Helmut64 0:a3ea811f80f2 43 #include "rza_io_regrw.h"
Helmut64 0:a3ea811f80f2 44 #include "usb1_function_dmacdrv.h"
Helmut64 0:a3ea811f80f2 45
Helmut64 0:a3ea811f80f2 46
Helmut64 0:a3ea811f80f2 47 /*******************************************************************************
Helmut64 0:a3ea811f80f2 48 Typedef definitions
Helmut64 0:a3ea811f80f2 49 *******************************************************************************/
Helmut64 0:a3ea811f80f2 50
Helmut64 0:a3ea811f80f2 51
Helmut64 0:a3ea811f80f2 52 /*******************************************************************************
Helmut64 0:a3ea811f80f2 53 Macro definitions
Helmut64 0:a3ea811f80f2 54 *******************************************************************************/
Helmut64 0:a3ea811f80f2 55 #define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
Helmut64 0:a3ea811f80f2 56
Helmut64 0:a3ea811f80f2 57 /* ==== Request setting information for on-chip peripheral module ==== */
Helmut64 0:a3ea811f80f2 58 typedef enum dmac_peri_req_reg_type
Helmut64 0:a3ea811f80f2 59 {
Helmut64 0:a3ea811f80f2 60 DMAC_REQ_MID,
Helmut64 0:a3ea811f80f2 61 DMAC_REQ_RID,
Helmut64 0:a3ea811f80f2 62 DMAC_REQ_AM,
Helmut64 0:a3ea811f80f2 63 DMAC_REQ_LVL,
Helmut64 0:a3ea811f80f2 64 DMAC_REQ_REQD
Helmut64 0:a3ea811f80f2 65 } dmac_peri_req_reg_type_t;
Helmut64 0:a3ea811f80f2 66
Helmut64 0:a3ea811f80f2 67
Helmut64 0:a3ea811f80f2 68 /*******************************************************************************
Helmut64 0:a3ea811f80f2 69 Imported global variables and functions (from other files)
Helmut64 0:a3ea811f80f2 70 *******************************************************************************/
Helmut64 0:a3ea811f80f2 71
Helmut64 0:a3ea811f80f2 72
Helmut64 0:a3ea811f80f2 73 /*******************************************************************************
Helmut64 0:a3ea811f80f2 74 Exported global variables and functions (to be accessed by other files)
Helmut64 0:a3ea811f80f2 75 *******************************************************************************/
Helmut64 0:a3ea811f80f2 76
Helmut64 0:a3ea811f80f2 77
Helmut64 0:a3ea811f80f2 78 /*******************************************************************************
Helmut64 0:a3ea811f80f2 79 Private global variables and functions
Helmut64 0:a3ea811f80f2 80 *******************************************************************************/
Helmut64 0:a3ea811f80f2 81 /* ==== Prototype declaration ==== */
Helmut64 0:a3ea811f80f2 82
Helmut64 0:a3ea811f80f2 83 /* ==== Global variable ==== */
Helmut64 0:a3ea811f80f2 84 /* On-chip peripheral module request setting table */
Helmut64 0:a3ea811f80f2 85 static const uint8_t usb1_function_dmac_peri_req_init_table[8][5] =
Helmut64 0:a3ea811f80f2 86 {
Helmut64 0:a3ea811f80f2 87 /* MID,RID,AM,LVL,REQD */
Helmut64 0:a3ea811f80f2 88 {32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
Helmut64 0:a3ea811f80f2 89 {32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
Helmut64 0:a3ea811f80f2 90 {33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
Helmut64 0:a3ea811f80f2 91 {33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
Helmut64 0:a3ea811f80f2 92 {34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
Helmut64 0:a3ea811f80f2 93 {34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
Helmut64 0:a3ea811f80f2 94 {35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
Helmut64 0:a3ea811f80f2 95 {35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
Helmut64 0:a3ea811f80f2 96 };
Helmut64 0:a3ea811f80f2 97
Helmut64 0:a3ea811f80f2 98
Helmut64 0:a3ea811f80f2 99 /*******************************************************************************
Helmut64 0:a3ea811f80f2 100 * Function Name: usb1_function_DMAC3_PeriReqInit
Helmut64 0:a3ea811f80f2 101 * Description : Sets the register mode for DMA mode and the on-chip peripheral
Helmut64 0:a3ea811f80f2 102 * : module request for transfer request for DMAC channel 1.
Helmut64 0:a3ea811f80f2 103 * : Executes DMAC initial setting using the DMA information
Helmut64 0:a3ea811f80f2 104 * : specified by the argument *trans_info and the enabled/disabled
Helmut64 0:a3ea811f80f2 105 * : continuous transfer specified by the argument continuation.
Helmut64 0:a3ea811f80f2 106 * : Registers DMAC channel 1 interrupt handler function and sets
Helmut64 0:a3ea811f80f2 107 * : the interrupt priority level. Then enables transfer completion
Helmut64 0:a3ea811f80f2 108 * : interrupt.
Helmut64 0:a3ea811f80f2 109 * Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register
Helmut64 0:a3ea811f80f2 110 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
Helmut64 0:a3ea811f80f2 111 * : uint32_t continuation : Set continuous transfer to be valid
Helmut64 0:a3ea811f80f2 112 * : after DMA transfer has been completed
Helmut64 0:a3ea811f80f2 113 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
Helmut64 0:a3ea811f80f2 114 * : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer
Helmut64 0:a3ea811f80f2 115 * : uint32_t request_factor : Factor for on-chip peripheral module request
Helmut64 0:a3ea811f80f2 116 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
Helmut64 0:a3ea811f80f2 117 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
Helmut64 0:a3ea811f80f2 118 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
Helmut64 0:a3ea811f80f2 119 * : :
Helmut64 0:a3ea811f80f2 120 * : uint32_t req_direction: Setting value of CHCFG_n register REQD bit
Helmut64 0:a3ea811f80f2 121 * Return Value : none
Helmut64 0:a3ea811f80f2 122 *******************************************************************************/
Helmut64 0:a3ea811f80f2 123 void usb1_function_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info,
Helmut64 0:a3ea811f80f2 124 uint32_t dmamode, uint32_t continuation,
Helmut64 0:a3ea811f80f2 125 uint32_t request_factor, uint32_t req_direction)
Helmut64 0:a3ea811f80f2 126 {
Helmut64 0:a3ea811f80f2 127 /* ==== Register mode ==== */
Helmut64 0:a3ea811f80f2 128 if (DMAC_MODE_REGISTER == dmamode)
Helmut64 0:a3ea811f80f2 129 {
Helmut64 0:a3ea811f80f2 130 /* ==== Next0 register set ==== */
Helmut64 0:a3ea811f80f2 131 DMAC3.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
Helmut64 0:a3ea811f80f2 132 DMAC3.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
Helmut64 0:a3ea811f80f2 133 DMAC3.N0TB_n = trans_info->count; /* Total transfer byte count */
Helmut64 0:a3ea811f80f2 134
Helmut64 0:a3ea811f80f2 135 /* DAD : Transfer destination address counting direction */
Helmut64 0:a3ea811f80f2 136 /* SAD : Transfer source address counting direction */
Helmut64 0:a3ea811f80f2 137 /* DDS : Transfer destination transfer size */
Helmut64 0:a3ea811f80f2 138 /* SDS : Transfer source transfer size */
Helmut64 0:a3ea811f80f2 139 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 140 trans_info->daddr_dir,
Helmut64 0:a3ea811f80f2 141 DMAC3_CHCFG_n_DAD_SHIFT,
Helmut64 0:a3ea811f80f2 142 DMAC3_CHCFG_n_DAD);
Helmut64 0:a3ea811f80f2 143 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 144 trans_info->saddr_dir,
Helmut64 0:a3ea811f80f2 145 DMAC3_CHCFG_n_SAD_SHIFT,
Helmut64 0:a3ea811f80f2 146 DMAC3_CHCFG_n_SAD);
Helmut64 0:a3ea811f80f2 147 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 148 trans_info->dst_size,
Helmut64 0:a3ea811f80f2 149 DMAC3_CHCFG_n_DDS_SHIFT,
Helmut64 0:a3ea811f80f2 150 DMAC3_CHCFG_n_DDS);
Helmut64 0:a3ea811f80f2 151 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 152 trans_info->src_size,
Helmut64 0:a3ea811f80f2 153 DMAC3_CHCFG_n_SDS_SHIFT,
Helmut64 0:a3ea811f80f2 154 DMAC3_CHCFG_n_SDS);
Helmut64 0:a3ea811f80f2 155
Helmut64 0:a3ea811f80f2 156 /* DMS : Register mode */
Helmut64 0:a3ea811f80f2 157 /* RSEL : Select Next0 register set */
Helmut64 0:a3ea811f80f2 158 /* SBE : No discharge of buffer data when aborted */
Helmut64 0:a3ea811f80f2 159 /* DEM : No DMA interrupt mask */
Helmut64 0:a3ea811f80f2 160 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 161 0,
Helmut64 0:a3ea811f80f2 162 DMAC3_CHCFG_n_DMS_SHIFT,
Helmut64 0:a3ea811f80f2 163 DMAC3_CHCFG_n_DMS);
Helmut64 0:a3ea811f80f2 164 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 165 0,
Helmut64 0:a3ea811f80f2 166 DMAC3_CHCFG_n_RSEL_SHIFT,
Helmut64 0:a3ea811f80f2 167 DMAC3_CHCFG_n_RSEL);
Helmut64 0:a3ea811f80f2 168 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 169 0,
Helmut64 0:a3ea811f80f2 170 DMAC3_CHCFG_n_SBE_SHIFT,
Helmut64 0:a3ea811f80f2 171 DMAC3_CHCFG_n_SBE);
Helmut64 0:a3ea811f80f2 172 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 173 0,
Helmut64 0:a3ea811f80f2 174 DMAC3_CHCFG_n_DEM_SHIFT,
Helmut64 0:a3ea811f80f2 175 DMAC3_CHCFG_n_DEM);
Helmut64 0:a3ea811f80f2 176
Helmut64 0:a3ea811f80f2 177 /* ---- Continuous transfer ---- */
Helmut64 0:a3ea811f80f2 178 if (DMAC_SAMPLE_CONTINUATION == continuation)
Helmut64 0:a3ea811f80f2 179 {
Helmut64 0:a3ea811f80f2 180 /* REN : Execute continuous transfer */
Helmut64 0:a3ea811f80f2 181 /* RSW : Change register set when DMA transfer is completed. */
Helmut64 0:a3ea811f80f2 182 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 183 1,
Helmut64 0:a3ea811f80f2 184 DMAC3_CHCFG_n_REN_SHIFT,
Helmut64 0:a3ea811f80f2 185 DMAC3_CHCFG_n_REN);
Helmut64 0:a3ea811f80f2 186 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 187 1,
Helmut64 0:a3ea811f80f2 188 DMAC3_CHCFG_n_RSW_SHIFT,
Helmut64 0:a3ea811f80f2 189 DMAC3_CHCFG_n_RSW);
Helmut64 0:a3ea811f80f2 190 }
Helmut64 0:a3ea811f80f2 191 /* ---- Single transfer ---- */
Helmut64 0:a3ea811f80f2 192 else
Helmut64 0:a3ea811f80f2 193 {
Helmut64 0:a3ea811f80f2 194 /* REN : Do not execute continuous transfer */
Helmut64 0:a3ea811f80f2 195 /* RSW : Do not change register set when DMA transfer is completed. */
Helmut64 0:a3ea811f80f2 196 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 197 0,
Helmut64 0:a3ea811f80f2 198 DMAC3_CHCFG_n_REN_SHIFT,
Helmut64 0:a3ea811f80f2 199 DMAC3_CHCFG_n_REN);
Helmut64 0:a3ea811f80f2 200 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 201 0,
Helmut64 0:a3ea811f80f2 202 DMAC3_CHCFG_n_RSW_SHIFT,
Helmut64 0:a3ea811f80f2 203 DMAC3_CHCFG_n_RSW);
Helmut64 0:a3ea811f80f2 204 }
Helmut64 0:a3ea811f80f2 205
Helmut64 0:a3ea811f80f2 206 /* TM : Single transfer */
Helmut64 0:a3ea811f80f2 207 /* SEL : Channel setting */
Helmut64 0:a3ea811f80f2 208 /* HIEN, LOEN : On-chip peripheral module request */
Helmut64 0:a3ea811f80f2 209 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 210 0,
Helmut64 0:a3ea811f80f2 211 DMAC3_CHCFG_n_TM_SHIFT,
Helmut64 0:a3ea811f80f2 212 DMAC3_CHCFG_n_TM);
Helmut64 0:a3ea811f80f2 213 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 214 3,
Helmut64 0:a3ea811f80f2 215 DMAC3_CHCFG_n_SEL_SHIFT,
Helmut64 0:a3ea811f80f2 216 DMAC3_CHCFG_n_SEL);
Helmut64 0:a3ea811f80f2 217 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 218 1,
Helmut64 0:a3ea811f80f2 219 DMAC3_CHCFG_n_HIEN_SHIFT,
Helmut64 0:a3ea811f80f2 220 DMAC3_CHCFG_n_HIEN);
Helmut64 0:a3ea811f80f2 221 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 222 0,
Helmut64 0:a3ea811f80f2 223 DMAC3_CHCFG_n_LOEN_SHIFT,
Helmut64 0:a3ea811f80f2 224 DMAC3_CHCFG_n_LOEN);
Helmut64 0:a3ea811f80f2 225
Helmut64 0:a3ea811f80f2 226 /* ---- Set factor by specified on-chip peripheral module request ---- */
Helmut64 0:a3ea811f80f2 227 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 228 usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
Helmut64 0:a3ea811f80f2 229 DMAC3_CHCFG_n_AM_SHIFT,
Helmut64 0:a3ea811f80f2 230 DMAC3_CHCFG_n_AM);
Helmut64 0:a3ea811f80f2 231 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 232 usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
Helmut64 0:a3ea811f80f2 233 DMAC3_CHCFG_n_LVL_SHIFT,
Helmut64 0:a3ea811f80f2 234 DMAC3_CHCFG_n_LVL);
Helmut64 0:a3ea811f80f2 235
Helmut64 0:a3ea811f80f2 236 if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
Helmut64 0:a3ea811f80f2 237 {
Helmut64 0:a3ea811f80f2 238 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 239 usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
Helmut64 0:a3ea811f80f2 240 DMAC3_CHCFG_n_REQD_SHIFT,
Helmut64 0:a3ea811f80f2 241 DMAC3_CHCFG_n_REQD);
Helmut64 0:a3ea811f80f2 242 }
Helmut64 0:a3ea811f80f2 243 else
Helmut64 0:a3ea811f80f2 244 {
Helmut64 0:a3ea811f80f2 245 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
Helmut64 0:a3ea811f80f2 246 req_direction,
Helmut64 0:a3ea811f80f2 247 DMAC3_CHCFG_n_REQD_SHIFT,
Helmut64 0:a3ea811f80f2 248 DMAC3_CHCFG_n_REQD);
Helmut64 0:a3ea811f80f2 249 }
Helmut64 0:a3ea811f80f2 250
Helmut64 0:a3ea811f80f2 251 RZA_IO_RegWrite_32(&DMAC23.DMARS,
Helmut64 0:a3ea811f80f2 252 usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
Helmut64 0:a3ea811f80f2 253 DMAC23_DMARS_CH3_RID_SHIFT,
Helmut64 0:a3ea811f80f2 254 DMAC23_DMARS_CH3_RID);
Helmut64 0:a3ea811f80f2 255 RZA_IO_RegWrite_32(&DMAC23.DMARS,
Helmut64 0:a3ea811f80f2 256 usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
Helmut64 0:a3ea811f80f2 257 DMAC23_DMARS_CH3_MID_SHIFT,
Helmut64 0:a3ea811f80f2 258 DMAC23_DMARS_CH3_MID);
Helmut64 0:a3ea811f80f2 259
Helmut64 0:a3ea811f80f2 260 /* PR : Round robin mode */
Helmut64 0:a3ea811f80f2 261 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
Helmut64 0:a3ea811f80f2 262 1,
Helmut64 0:a3ea811f80f2 263 DMAC07_DCTRL_0_7_PR_SHIFT,
Helmut64 0:a3ea811f80f2 264 DMAC07_DCTRL_0_7_PR);
Helmut64 0:a3ea811f80f2 265 }
Helmut64 0:a3ea811f80f2 266 }
Helmut64 0:a3ea811f80f2 267
Helmut64 0:a3ea811f80f2 268 /*******************************************************************************
Helmut64 0:a3ea811f80f2 269 * Function Name: usb1_function_DMAC3_Open
Helmut64 0:a3ea811f80f2 270 * Description : Enables DMAC channel 3 transfer.
Helmut64 0:a3ea811f80f2 271 * Arguments : uint32_t req : DMAC request mode
Helmut64 0:a3ea811f80f2 272 * Return Value : 0 : Succeeded in enabling DMA transfer
Helmut64 0:a3ea811f80f2 273 * : -1 : Failed to enable DMA transfer (due to DMA operation)
Helmut64 0:a3ea811f80f2 274 *******************************************************************************/
Helmut64 0:a3ea811f80f2 275 int32_t usb1_function_DMAC3_Open (uint32_t req)
Helmut64 0:a3ea811f80f2 276 {
Helmut64 0:a3ea811f80f2 277 int32_t ret;
Helmut64 0:a3ea811f80f2 278 volatile uint8_t dummy;
Helmut64 0:a3ea811f80f2 279
Helmut64 0:a3ea811f80f2 280 /* Transferable? */
Helmut64 0:a3ea811f80f2 281 if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
Helmut64 0:a3ea811f80f2 282 DMAC3_CHSTAT_n_EN_SHIFT,
Helmut64 0:a3ea811f80f2 283 DMAC3_CHSTAT_n_EN)) &&
Helmut64 0:a3ea811f80f2 284 (0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
Helmut64 0:a3ea811f80f2 285 DMAC3_CHSTAT_n_TACT_SHIFT,
Helmut64 0:a3ea811f80f2 286 DMAC3_CHSTAT_n_TACT)))
Helmut64 0:a3ea811f80f2 287 {
Helmut64 0:a3ea811f80f2 288 /* Clear Channel Status Register */
Helmut64 0:a3ea811f80f2 289 RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
Helmut64 0:a3ea811f80f2 290 1,
Helmut64 0:a3ea811f80f2 291 DMAC3_CHCTRL_n_SWRST_SHIFT,
Helmut64 0:a3ea811f80f2 292 DMAC3_CHCTRL_n_SWRST);
Helmut64 0:a3ea811f80f2 293 dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n,
Helmut64 0:a3ea811f80f2 294 DMAC3_CHCTRL_n_SWRST_SHIFT,
Helmut64 0:a3ea811f80f2 295 DMAC3_CHCTRL_n_SWRST);
Helmut64 0:a3ea811f80f2 296 /* Enable DMA transfer */
Helmut64 0:a3ea811f80f2 297 RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
Helmut64 0:a3ea811f80f2 298 1,
Helmut64 0:a3ea811f80f2 299 DMAC3_CHCTRL_n_SETEN_SHIFT,
Helmut64 0:a3ea811f80f2 300 DMAC3_CHCTRL_n_SETEN);
Helmut64 0:a3ea811f80f2 301
Helmut64 0:a3ea811f80f2 302 /* ---- Request by software ---- */
Helmut64 0:a3ea811f80f2 303 if (DMAC_REQ_MODE_SOFT == req)
Helmut64 0:a3ea811f80f2 304 {
Helmut64 0:a3ea811f80f2 305 /* DMA transfer Request by software */
Helmut64 0:a3ea811f80f2 306 RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
Helmut64 0:a3ea811f80f2 307 1,
Helmut64 0:a3ea811f80f2 308 DMAC3_CHCTRL_n_STG_SHIFT,
Helmut64 0:a3ea811f80f2 309 DMAC3_CHCTRL_n_STG);
Helmut64 0:a3ea811f80f2 310 }
Helmut64 0:a3ea811f80f2 311
Helmut64 0:a3ea811f80f2 312 ret = 0;
Helmut64 0:a3ea811f80f2 313 }
Helmut64 0:a3ea811f80f2 314 else
Helmut64 0:a3ea811f80f2 315 {
Helmut64 0:a3ea811f80f2 316 ret = -1;
Helmut64 0:a3ea811f80f2 317 }
Helmut64 0:a3ea811f80f2 318
Helmut64 0:a3ea811f80f2 319 return ret;
Helmut64 0:a3ea811f80f2 320 }
Helmut64 0:a3ea811f80f2 321
Helmut64 0:a3ea811f80f2 322 /*******************************************************************************
Helmut64 0:a3ea811f80f2 323 * Function Name: usb1_function_DMAC3_Close
Helmut64 0:a3ea811f80f2 324 * Description : Aborts DMAC channel 3 transfer. Returns the remaining transfer
Helmut64 0:a3ea811f80f2 325 * : byte count at the time of DMA transfer abort to the argument
Helmut64 0:a3ea811f80f2 326 * : *remain.
Helmut64 0:a3ea811f80f2 327 * Arguments : uint32_t * remain : Remaining transfer byte count when
Helmut64 0:a3ea811f80f2 328 * : : DMA transfer is aborted
Helmut64 0:a3ea811f80f2 329 * Return Value : none
Helmut64 0:a3ea811f80f2 330 *******************************************************************************/
Helmut64 0:a3ea811f80f2 331 void usb1_function_DMAC3_Close (uint32_t * remain)
Helmut64 0:a3ea811f80f2 332 {
Helmut64 0:a3ea811f80f2 333
Helmut64 0:a3ea811f80f2 334 /* ==== Abort transfer ==== */
Helmut64 0:a3ea811f80f2 335 RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
Helmut64 0:a3ea811f80f2 336 1,
Helmut64 0:a3ea811f80f2 337 DMAC3_CHCTRL_n_CLREN_SHIFT,
Helmut64 0:a3ea811f80f2 338 DMAC3_CHCTRL_n_CLREN);
Helmut64 0:a3ea811f80f2 339
Helmut64 0:a3ea811f80f2 340 while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
Helmut64 0:a3ea811f80f2 341 DMAC3_CHSTAT_n_TACT_SHIFT,
Helmut64 0:a3ea811f80f2 342 DMAC3_CHSTAT_n_TACT))
Helmut64 0:a3ea811f80f2 343 {
Helmut64 0:a3ea811f80f2 344 /* Loop until transfer is aborted */
Helmut64 0:a3ea811f80f2 345 }
Helmut64 0:a3ea811f80f2 346
Helmut64 0:a3ea811f80f2 347 while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
Helmut64 0:a3ea811f80f2 348 DMAC3_CHSTAT_n_EN_SHIFT,
Helmut64 0:a3ea811f80f2 349 DMAC3_CHSTAT_n_EN))
Helmut64 0:a3ea811f80f2 350 {
Helmut64 0:a3ea811f80f2 351 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
Helmut64 0:a3ea811f80f2 352 }
Helmut64 0:a3ea811f80f2 353 /* ==== Obtain remaining transfer byte count ==== */
Helmut64 0:a3ea811f80f2 354 *remain = DMAC3.CRTB_n;
Helmut64 0:a3ea811f80f2 355 }
Helmut64 0:a3ea811f80f2 356
Helmut64 0:a3ea811f80f2 357 /*******************************************************************************
Helmut64 0:a3ea811f80f2 358 * Function Name: usb1_function_DMAC3_Load_Set
Helmut64 0:a3ea811f80f2 359 * Description : Sets the transfer source address, transfer destination
Helmut64 0:a3ea811f80f2 360 * : address, and total transfer byte count respectively
Helmut64 0:a3ea811f80f2 361 * : specified by the argument src_addr, dst_addr, and count to
Helmut64 0:a3ea811f80f2 362 * : DMAC channel 3 as DMA transfer information.
Helmut64 0:a3ea811f80f2 363 * : Sets the register set selected by the CHCFG_n register
Helmut64 0:a3ea811f80f2 364 * : RSEL bit from the Next0 or Next1 register set.
Helmut64 0:a3ea811f80f2 365 * : This function should be called when DMA transfer of DMAC
Helmut64 0:a3ea811f80f2 366 * : channel 3 is aboted.
Helmut64 0:a3ea811f80f2 367 * Arguments : uint32_t src_addr : Transfer source address
Helmut64 0:a3ea811f80f2 368 * : uint32_t dst_addr : Transfer destination address
Helmut64 0:a3ea811f80f2 369 * : uint32_t count : Total transfer byte count
Helmut64 0:a3ea811f80f2 370 * Return Value : none
Helmut64 0:a3ea811f80f2 371 *******************************************************************************/
Helmut64 0:a3ea811f80f2 372 void usb1_function_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
Helmut64 0:a3ea811f80f2 373 {
Helmut64 0:a3ea811f80f2 374 uint8_t reg_set;
Helmut64 0:a3ea811f80f2 375
Helmut64 0:a3ea811f80f2 376 /* Obtain register set in use */
Helmut64 0:a3ea811f80f2 377 reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
Helmut64 0:a3ea811f80f2 378 DMAC3_CHSTAT_n_SR_SHIFT,
Helmut64 0:a3ea811f80f2 379 DMAC3_CHSTAT_n_SR);
Helmut64 0:a3ea811f80f2 380
Helmut64 0:a3ea811f80f2 381 /* ==== Load ==== */
Helmut64 0:a3ea811f80f2 382 if (0 == reg_set)
Helmut64 0:a3ea811f80f2 383 {
Helmut64 0:a3ea811f80f2 384 /* ---- Next0 Register Set ---- */
Helmut64 0:a3ea811f80f2 385 DMAC3.N0SA_n = src_addr; /* Start address of transfer source */
Helmut64 0:a3ea811f80f2 386 DMAC3.N0DA_n = dst_addr; /* Start address of transfer destination */
Helmut64 0:a3ea811f80f2 387 DMAC3.N0TB_n = count; /* Total transfer byte count */
Helmut64 0:a3ea811f80f2 388 }
Helmut64 0:a3ea811f80f2 389 else
Helmut64 0:a3ea811f80f2 390 {
Helmut64 0:a3ea811f80f2 391 /* ---- Next1 Register Set ---- */
Helmut64 0:a3ea811f80f2 392 DMAC3.N1SA_n = src_addr; /* Start address of transfer source */
Helmut64 0:a3ea811f80f2 393 DMAC3.N1DA_n = dst_addr; /* Start address of transfer destination */
Helmut64 0:a3ea811f80f2 394 DMAC3.N1TB_n = count; /* Total transfer byte count */
Helmut64 0:a3ea811f80f2 395 }
Helmut64 0:a3ea811f80f2 396 }
Helmut64 0:a3ea811f80f2 397
Helmut64 0:a3ea811f80f2 398 /*******************************************************************************
Helmut64 0:a3ea811f80f2 399 * Function Name: usb1_function_DMAC4_PeriReqInit
Helmut64 0:a3ea811f80f2 400 * Description : Sets the register mode for DMA mode and the on-chip peripheral
Helmut64 0:a3ea811f80f2 401 * : module request for transfer request for DMAC channel 2.
Helmut64 0:a3ea811f80f2 402 * : Executes DMAC initial setting using the DMA information
Helmut64 0:a3ea811f80f2 403 * : specified by the argument *trans_info and the enabled/disabled
Helmut64 0:a3ea811f80f2 404 * : continuous transfer specified by the argument continuation.
Helmut64 0:a3ea811f80f2 405 * : Registers DMAC channel 2 interrupt handler function and sets
Helmut64 0:a3ea811f80f2 406 * : the interrupt priority level. Then enables transfer completion
Helmut64 0:a3ea811f80f2 407 * : interrupt.
Helmut64 0:a3ea811f80f2 408 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
Helmut64 0:a3ea811f80f2 409 * : : register
Helmut64 0:a3ea811f80f2 410 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
Helmut64 0:a3ea811f80f2 411 * : uint32_t continuation : Set continuous transfer to be valid
Helmut64 0:a3ea811f80f2 412 * : : after DMA transfer has been completed
Helmut64 0:a3ea811f80f2 413 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
Helmut64 0:a3ea811f80f2 414 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
Helmut64 0:a3ea811f80f2 415 * : : transfer
Helmut64 0:a3ea811f80f2 416 * : uint32_t request_factor : Factor for on-chip peripheral module
Helmut64 0:a3ea811f80f2 417 * : : request
Helmut64 0:a3ea811f80f2 418 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
Helmut64 0:a3ea811f80f2 419 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
Helmut64 0:a3ea811f80f2 420 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
Helmut64 0:a3ea811f80f2 421 * : :
Helmut64 0:a3ea811f80f2 422 * : uint32_t req_direction : Setting value of CHCFG_n register
Helmut64 0:a3ea811f80f2 423 * : : REQD bit
Helmut64 0:a3ea811f80f2 424 *******************************************************************************/
Helmut64 0:a3ea811f80f2 425 void usb1_function_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info,
Helmut64 0:a3ea811f80f2 426 uint32_t dmamode, uint32_t continuation,
Helmut64 0:a3ea811f80f2 427 uint32_t request_factor, uint32_t req_direction)
Helmut64 0:a3ea811f80f2 428 {
Helmut64 0:a3ea811f80f2 429 /* ==== Register mode ==== */
Helmut64 0:a3ea811f80f2 430 if (DMAC_MODE_REGISTER == dmamode)
Helmut64 0:a3ea811f80f2 431 {
Helmut64 0:a3ea811f80f2 432 /* ==== Next0 register set ==== */
Helmut64 0:a3ea811f80f2 433 DMAC4.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
Helmut64 0:a3ea811f80f2 434 DMAC4.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
Helmut64 0:a3ea811f80f2 435 DMAC4.N0TB_n = trans_info->count; /* Total transfer byte count */
Helmut64 0:a3ea811f80f2 436
Helmut64 0:a3ea811f80f2 437 /* DAD : Transfer destination address counting direction */
Helmut64 0:a3ea811f80f2 438 /* SAD : Transfer source address counting direction */
Helmut64 0:a3ea811f80f2 439 /* DDS : Transfer destination transfer size */
Helmut64 0:a3ea811f80f2 440 /* SDS : Transfer source transfer size */
Helmut64 0:a3ea811f80f2 441 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 442 trans_info->daddr_dir,
Helmut64 0:a3ea811f80f2 443 DMAC4_CHCFG_n_DAD_SHIFT,
Helmut64 0:a3ea811f80f2 444 DMAC4_CHCFG_n_DAD);
Helmut64 0:a3ea811f80f2 445 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 446 trans_info->saddr_dir,
Helmut64 0:a3ea811f80f2 447 DMAC4_CHCFG_n_SAD_SHIFT,
Helmut64 0:a3ea811f80f2 448 DMAC4_CHCFG_n_SAD);
Helmut64 0:a3ea811f80f2 449 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 450 trans_info->dst_size,
Helmut64 0:a3ea811f80f2 451 DMAC4_CHCFG_n_DDS_SHIFT,
Helmut64 0:a3ea811f80f2 452 DMAC4_CHCFG_n_DDS);
Helmut64 0:a3ea811f80f2 453 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 454 trans_info->src_size,
Helmut64 0:a3ea811f80f2 455 DMAC4_CHCFG_n_SDS_SHIFT,
Helmut64 0:a3ea811f80f2 456 DMAC4_CHCFG_n_SDS);
Helmut64 0:a3ea811f80f2 457
Helmut64 0:a3ea811f80f2 458 /* DMS : Register mode */
Helmut64 0:a3ea811f80f2 459 /* RSEL : Select Next0 register set */
Helmut64 0:a3ea811f80f2 460 /* SBE : No discharge of buffer data when aborted */
Helmut64 0:a3ea811f80f2 461 /* DEM : No DMA interrupt mask */
Helmut64 0:a3ea811f80f2 462 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 463 0,
Helmut64 0:a3ea811f80f2 464 DMAC4_CHCFG_n_DMS_SHIFT,
Helmut64 0:a3ea811f80f2 465 DMAC4_CHCFG_n_DMS);
Helmut64 0:a3ea811f80f2 466 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 467 0,
Helmut64 0:a3ea811f80f2 468 DMAC4_CHCFG_n_RSEL_SHIFT,
Helmut64 0:a3ea811f80f2 469 DMAC4_CHCFG_n_RSEL);
Helmut64 0:a3ea811f80f2 470 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 471 0,
Helmut64 0:a3ea811f80f2 472 DMAC4_CHCFG_n_SBE_SHIFT,
Helmut64 0:a3ea811f80f2 473 DMAC4_CHCFG_n_SBE);
Helmut64 0:a3ea811f80f2 474 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 475 0,
Helmut64 0:a3ea811f80f2 476 DMAC4_CHCFG_n_DEM_SHIFT,
Helmut64 0:a3ea811f80f2 477 DMAC4_CHCFG_n_DEM);
Helmut64 0:a3ea811f80f2 478
Helmut64 0:a3ea811f80f2 479 /* ---- Continuous transfer ---- */
Helmut64 0:a3ea811f80f2 480 if (DMAC_SAMPLE_CONTINUATION == continuation)
Helmut64 0:a3ea811f80f2 481 {
Helmut64 0:a3ea811f80f2 482 /* REN : Execute continuous transfer */
Helmut64 0:a3ea811f80f2 483 /* RSW : Change register set when DMA transfer is completed. */
Helmut64 0:a3ea811f80f2 484 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 485 1,
Helmut64 0:a3ea811f80f2 486 DMAC4_CHCFG_n_REN_SHIFT,
Helmut64 0:a3ea811f80f2 487 DMAC4_CHCFG_n_REN);
Helmut64 0:a3ea811f80f2 488 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 489 1,
Helmut64 0:a3ea811f80f2 490 DMAC4_CHCFG_n_RSW_SHIFT,
Helmut64 0:a3ea811f80f2 491 DMAC4_CHCFG_n_RSW);
Helmut64 0:a3ea811f80f2 492 }
Helmut64 0:a3ea811f80f2 493 /* ---- Single transfer ---- */
Helmut64 0:a3ea811f80f2 494 else
Helmut64 0:a3ea811f80f2 495 {
Helmut64 0:a3ea811f80f2 496 /* REN : Do not execute continuous transfer */
Helmut64 0:a3ea811f80f2 497 /* RSW : Do not change register set when DMA transfer is completed. */
Helmut64 0:a3ea811f80f2 498 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 499 0,
Helmut64 0:a3ea811f80f2 500 DMAC4_CHCFG_n_REN_SHIFT,
Helmut64 0:a3ea811f80f2 501 DMAC4_CHCFG_n_REN);
Helmut64 0:a3ea811f80f2 502 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 503 0,
Helmut64 0:a3ea811f80f2 504 DMAC4_CHCFG_n_RSW_SHIFT,
Helmut64 0:a3ea811f80f2 505 DMAC4_CHCFG_n_RSW);
Helmut64 0:a3ea811f80f2 506 }
Helmut64 0:a3ea811f80f2 507
Helmut64 0:a3ea811f80f2 508 /* TM : Single transfer */
Helmut64 0:a3ea811f80f2 509 /* SEL : Channel setting */
Helmut64 0:a3ea811f80f2 510 /* HIEN, LOEN : On-chip peripheral module request */
Helmut64 0:a3ea811f80f2 511 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 512 0,
Helmut64 0:a3ea811f80f2 513 DMAC4_CHCFG_n_TM_SHIFT,
Helmut64 0:a3ea811f80f2 514 DMAC4_CHCFG_n_TM);
Helmut64 0:a3ea811f80f2 515 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 516 4,
Helmut64 0:a3ea811f80f2 517 DMAC4_CHCFG_n_SEL_SHIFT,
Helmut64 0:a3ea811f80f2 518 DMAC4_CHCFG_n_SEL);
Helmut64 0:a3ea811f80f2 519 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 520 1,
Helmut64 0:a3ea811f80f2 521 DMAC4_CHCFG_n_HIEN_SHIFT,
Helmut64 0:a3ea811f80f2 522 DMAC4_CHCFG_n_HIEN);
Helmut64 0:a3ea811f80f2 523 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 524 0,
Helmut64 0:a3ea811f80f2 525 DMAC4_CHCFG_n_LOEN_SHIFT,
Helmut64 0:a3ea811f80f2 526 DMAC4_CHCFG_n_LOEN);
Helmut64 0:a3ea811f80f2 527
Helmut64 0:a3ea811f80f2 528 /* ---- Set factor by specified on-chip peripheral module request ---- */
Helmut64 0:a3ea811f80f2 529 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 530 usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
Helmut64 0:a3ea811f80f2 531 DMAC4_CHCFG_n_AM_SHIFT,
Helmut64 0:a3ea811f80f2 532 DMAC4_CHCFG_n_AM);
Helmut64 0:a3ea811f80f2 533 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 534 usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
Helmut64 0:a3ea811f80f2 535 DMAC4_CHCFG_n_LVL_SHIFT,
Helmut64 0:a3ea811f80f2 536 DMAC4_CHCFG_n_LVL);
Helmut64 0:a3ea811f80f2 537 if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
Helmut64 0:a3ea811f80f2 538 {
Helmut64 0:a3ea811f80f2 539 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 540 usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
Helmut64 0:a3ea811f80f2 541 DMAC4_CHCFG_n_REQD_SHIFT,
Helmut64 0:a3ea811f80f2 542 DMAC4_CHCFG_n_REQD);
Helmut64 0:a3ea811f80f2 543 }
Helmut64 0:a3ea811f80f2 544 else
Helmut64 0:a3ea811f80f2 545 {
Helmut64 0:a3ea811f80f2 546 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
Helmut64 0:a3ea811f80f2 547 req_direction,
Helmut64 0:a3ea811f80f2 548 DMAC4_CHCFG_n_REQD_SHIFT,
Helmut64 0:a3ea811f80f2 549 DMAC4_CHCFG_n_REQD);
Helmut64 0:a3ea811f80f2 550 }
Helmut64 0:a3ea811f80f2 551 RZA_IO_RegWrite_32(&DMAC45.DMARS,
Helmut64 0:a3ea811f80f2 552 usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
Helmut64 0:a3ea811f80f2 553 DMAC45_DMARS_CH4_RID_SHIFT,
Helmut64 0:a3ea811f80f2 554 DMAC45_DMARS_CH4_RID);
Helmut64 0:a3ea811f80f2 555 RZA_IO_RegWrite_32(&DMAC45.DMARS,
Helmut64 0:a3ea811f80f2 556 usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
Helmut64 0:a3ea811f80f2 557 DMAC45_DMARS_CH4_MID_SHIFT,
Helmut64 0:a3ea811f80f2 558 DMAC45_DMARS_CH4_MID);
Helmut64 0:a3ea811f80f2 559
Helmut64 0:a3ea811f80f2 560 /* PR : Round robin mode */
Helmut64 0:a3ea811f80f2 561 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
Helmut64 0:a3ea811f80f2 562 1,
Helmut64 0:a3ea811f80f2 563 DMAC07_DCTRL_0_7_PR_SHIFT,
Helmut64 0:a3ea811f80f2 564 DMAC07_DCTRL_0_7_PR);
Helmut64 0:a3ea811f80f2 565 }
Helmut64 0:a3ea811f80f2 566 }
Helmut64 0:a3ea811f80f2 567
Helmut64 0:a3ea811f80f2 568 /*******************************************************************************
Helmut64 0:a3ea811f80f2 569 * Function Name: usb1_function_DMAC4_Open
Helmut64 0:a3ea811f80f2 570 * Description : Enables DMAC channel 4 transfer.
Helmut64 0:a3ea811f80f2 571 * Arguments : uint32_t req : DMAC request mode
Helmut64 0:a3ea811f80f2 572 * Return Value : 0 : Succeeded in enabling DMA transfer
Helmut64 0:a3ea811f80f2 573 * : -1 : Failed to enable DMA transfer (due to DMA operation)
Helmut64 0:a3ea811f80f2 574 *******************************************************************************/
Helmut64 0:a3ea811f80f2 575 int32_t usb1_function_DMAC4_Open (uint32_t req)
Helmut64 0:a3ea811f80f2 576 {
Helmut64 0:a3ea811f80f2 577 int32_t ret;
Helmut64 0:a3ea811f80f2 578 volatile uint8_t dummy;
Helmut64 0:a3ea811f80f2 579
Helmut64 0:a3ea811f80f2 580 /* Transferable? */
Helmut64 0:a3ea811f80f2 581 if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
Helmut64 0:a3ea811f80f2 582 DMAC4_CHSTAT_n_EN_SHIFT,
Helmut64 0:a3ea811f80f2 583 DMAC4_CHSTAT_n_EN)) &&
Helmut64 0:a3ea811f80f2 584 (0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
Helmut64 0:a3ea811f80f2 585 DMAC4_CHSTAT_n_TACT_SHIFT,
Helmut64 0:a3ea811f80f2 586 DMAC4_CHSTAT_n_TACT)))
Helmut64 0:a3ea811f80f2 587 {
Helmut64 0:a3ea811f80f2 588 /* Clear Channel Status Register */
Helmut64 0:a3ea811f80f2 589 RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
Helmut64 0:a3ea811f80f2 590 1,
Helmut64 0:a3ea811f80f2 591 DMAC4_CHCTRL_n_SWRST_SHIFT,
Helmut64 0:a3ea811f80f2 592 DMAC4_CHCTRL_n_SWRST);
Helmut64 0:a3ea811f80f2 593 dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n,
Helmut64 0:a3ea811f80f2 594 DMAC4_CHCTRL_n_SWRST_SHIFT,
Helmut64 0:a3ea811f80f2 595 DMAC4_CHCTRL_n_SWRST);
Helmut64 0:a3ea811f80f2 596 /* Enable DMA transfer */
Helmut64 0:a3ea811f80f2 597 RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
Helmut64 0:a3ea811f80f2 598 1,
Helmut64 0:a3ea811f80f2 599 DMAC4_CHCTRL_n_SETEN_SHIFT,
Helmut64 0:a3ea811f80f2 600 DMAC4_CHCTRL_n_SETEN);
Helmut64 0:a3ea811f80f2 601
Helmut64 0:a3ea811f80f2 602 /* ---- Request by software ---- */
Helmut64 0:a3ea811f80f2 603 if (DMAC_REQ_MODE_SOFT == req)
Helmut64 0:a3ea811f80f2 604 {
Helmut64 0:a3ea811f80f2 605 /* DMA transfer Request by software */
Helmut64 0:a3ea811f80f2 606 RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
Helmut64 0:a3ea811f80f2 607 1,
Helmut64 0:a3ea811f80f2 608 DMAC4_CHCTRL_n_STG_SHIFT,
Helmut64 0:a3ea811f80f2 609 DMAC4_CHCTRL_n_STG);
Helmut64 0:a3ea811f80f2 610 }
Helmut64 0:a3ea811f80f2 611
Helmut64 0:a3ea811f80f2 612 ret = 0;
Helmut64 0:a3ea811f80f2 613 }
Helmut64 0:a3ea811f80f2 614 else
Helmut64 0:a3ea811f80f2 615 {
Helmut64 0:a3ea811f80f2 616 ret = -1;
Helmut64 0:a3ea811f80f2 617 }
Helmut64 0:a3ea811f80f2 618
Helmut64 0:a3ea811f80f2 619 return ret;
Helmut64 0:a3ea811f80f2 620 }
Helmut64 0:a3ea811f80f2 621
Helmut64 0:a3ea811f80f2 622 /*******************************************************************************
Helmut64 0:a3ea811f80f2 623 * Function Name: usb1_function_DMAC4_Close
Helmut64 0:a3ea811f80f2 624 * Description : Aborts DMAC channel 4 transfer. Returns the remaining transfer
Helmut64 0:a3ea811f80f2 625 * : byte count at the time of DMA transfer abort to the argument
Helmut64 0:a3ea811f80f2 626 * : *remain.
Helmut64 0:a3ea811f80f2 627 * Arguments : uint32_t * remain : Remaining transfer byte count when
Helmut64 0:a3ea811f80f2 628 * : : DMA transfer is aborted
Helmut64 0:a3ea811f80f2 629 * Return Value : none
Helmut64 0:a3ea811f80f2 630 *******************************************************************************/
Helmut64 0:a3ea811f80f2 631 void usb1_function_DMAC4_Close (uint32_t * remain)
Helmut64 0:a3ea811f80f2 632 {
Helmut64 0:a3ea811f80f2 633
Helmut64 0:a3ea811f80f2 634 /* ==== Abort transfer ==== */
Helmut64 0:a3ea811f80f2 635 RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
Helmut64 0:a3ea811f80f2 636 1,
Helmut64 0:a3ea811f80f2 637 DMAC4_CHCTRL_n_CLREN_SHIFT,
Helmut64 0:a3ea811f80f2 638 DMAC4_CHCTRL_n_CLREN);
Helmut64 0:a3ea811f80f2 639
Helmut64 0:a3ea811f80f2 640 while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
Helmut64 0:a3ea811f80f2 641 DMAC4_CHSTAT_n_TACT_SHIFT,
Helmut64 0:a3ea811f80f2 642 DMAC4_CHSTAT_n_TACT))
Helmut64 0:a3ea811f80f2 643 {
Helmut64 0:a3ea811f80f2 644 /* Loop until transfer is aborted */
Helmut64 0:a3ea811f80f2 645 }
Helmut64 0:a3ea811f80f2 646
Helmut64 0:a3ea811f80f2 647 while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
Helmut64 0:a3ea811f80f2 648 DMAC4_CHSTAT_n_EN_SHIFT,
Helmut64 0:a3ea811f80f2 649 DMAC4_CHSTAT_n_EN))
Helmut64 0:a3ea811f80f2 650 {
Helmut64 0:a3ea811f80f2 651 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
Helmut64 0:a3ea811f80f2 652 }
Helmut64 0:a3ea811f80f2 653 /* ==== Obtain remaining transfer byte count ==== */
Helmut64 0:a3ea811f80f2 654 *remain = DMAC4.CRTB_n;
Helmut64 0:a3ea811f80f2 655 }
Helmut64 0:a3ea811f80f2 656
Helmut64 0:a3ea811f80f2 657 /*******************************************************************************
Helmut64 0:a3ea811f80f2 658 * Function Name: usb1_function_DMAC4_Load_Set
Helmut64 0:a3ea811f80f2 659 * Description : Sets the transfer source address, transfer destination
Helmut64 0:a3ea811f80f2 660 * : address, and total transfer byte count respectively
Helmut64 0:a3ea811f80f2 661 * : specified by the argument src_addr, dst_addr, and count to
Helmut64 0:a3ea811f80f2 662 * : DMAC channel 4 as DMA transfer information.
Helmut64 0:a3ea811f80f2 663 * : Sets the register set selected by the CHCFG_n register
Helmut64 0:a3ea811f80f2 664 * : RSEL bit from the Next0 or Next1 register set.
Helmut64 0:a3ea811f80f2 665 * : This function should be called when DMA transfer of DMAC
Helmut64 0:a3ea811f80f2 666 * : channel 4 is aboted.
Helmut64 0:a3ea811f80f2 667 * Arguments : uint32_t src_addr : Transfer source address
Helmut64 0:a3ea811f80f2 668 * : uint32_t dst_addr : Transfer destination address
Helmut64 0:a3ea811f80f2 669 * : uint32_t count : Total transfer byte count
Helmut64 0:a3ea811f80f2 670 * Return Value : none
Helmut64 0:a3ea811f80f2 671 *******************************************************************************/
Helmut64 0:a3ea811f80f2 672 void usb1_function_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
Helmut64 0:a3ea811f80f2 673 {
Helmut64 0:a3ea811f80f2 674 uint8_t reg_set;
Helmut64 0:a3ea811f80f2 675
Helmut64 0:a3ea811f80f2 676 /* Obtain register set in use */
Helmut64 0:a3ea811f80f2 677 reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
Helmut64 0:a3ea811f80f2 678 DMAC4_CHSTAT_n_SR_SHIFT,
Helmut64 0:a3ea811f80f2 679 DMAC4_CHSTAT_n_SR);
Helmut64 0:a3ea811f80f2 680
Helmut64 0:a3ea811f80f2 681 /* ==== Load ==== */
Helmut64 0:a3ea811f80f2 682 if (0 == reg_set)
Helmut64 0:a3ea811f80f2 683 {
Helmut64 0:a3ea811f80f2 684 /* ---- Next0 Register Set ---- */
Helmut64 0:a3ea811f80f2 685 DMAC4.N0SA_n = src_addr; /* Start address of transfer source */
Helmut64 0:a3ea811f80f2 686 DMAC4.N0DA_n = dst_addr; /* Start address of transfer destination */
Helmut64 0:a3ea811f80f2 687 DMAC4.N0TB_n = count; /* Total transfer byte count */
Helmut64 0:a3ea811f80f2 688 }
Helmut64 0:a3ea811f80f2 689 else
Helmut64 0:a3ea811f80f2 690 {
Helmut64 0:a3ea811f80f2 691 /* ---- Next1 Register Set ---- */
Helmut64 0:a3ea811f80f2 692 DMAC4.N1SA_n = src_addr; /* Start address of transfer source */
Helmut64 0:a3ea811f80f2 693 DMAC4.N1DA_n = dst_addr; /* Start address of transfer destination */
Helmut64 0:a3ea811f80f2 694 DMAC4.N1TB_n = count; /* Total transfer byte count */
Helmut64 0:a3ea811f80f2 695 }
Helmut64 0:a3ea811f80f2 696 }
Helmut64 0:a3ea811f80f2 697
Helmut64 0:a3ea811f80f2 698 /* End of File */