Devin Alexander / SX1276GenericLib

I made a fork of a generic library that was developed with support for RFM95 LoRa module that I found online. I Made a few changes and made it compatible with hardware limitations of the MAX32620FTHR and MAX32630FTHR module.

Dependents:   MAX326xxFTHR_LoRa_RFM95 MAX326xxFTHR_LoRa_PingPong MAX326xxFTHR_RFM95_LoRa_PingPong MAX326xxFTHR_LoRa_RFM95_PingPong_Example ... more

Fork of SX1276GenericLib by Helmut Tschemernjak

sx1276/sx1276-hal.cpp@26:87796ee62589, 2017-03-24 (annotated)

Committer:
Helmut64
Date:
Fri Mar 24 15:06:46 2017 +0000
Revision:
26:87796ee62589
Parent:
25:3778e6204cc1
Child:
28:6d83af9f8563
Added support to work with the Murata Lora Modul, in addition to the mbed SX1276 board.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: -
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276-hal.h"
GregCr 0:e6ceb13d2d05 16
mluis 22:7f3aab69cca9 17 const RadioRegisters_t SX1276MB1xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
GregCr 0:e6ceb13d2d05 18
mluis 21:2e496deb7858 19 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events,
GregCr 0:e6ceb13d2d05 20 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 21 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
Helmut64 26:87796ee62589 22 #ifdef MURTA_ANT_SWITCH
Helmut64 26:87796ee62589 23 PinName antSwitch, PinName antSwitchTX, PinName antSwitchTXBoost )
Helmut64 26:87796ee62589 24 #else
GregCr 0:e6ceb13d2d05 25 PinName antSwitch )
Helmut64 26:87796ee62589 26 #endif
mluis 21:2e496deb7858 27 : SX1276( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
Helmut64 26:87796ee62589 28 #ifdef MURTA_ANT_SWITCH
Helmut64 26:87796ee62589 29 antSwitch(antSwitch), antSwitchTX(antSwitchTX), antSwitchTXBoost(antSwitchTXBoost),
Helmut64 26:87796ee62589 30 #else
GregCr 0:e6ceb13d2d05 31 antSwitch( antSwitch ),
Helmut64 26:87796ee62589 32 #endif
Helmut64 26:87796ee62589 33 #if( defined ( TARGET_NUCLEO_L152RE ) )
mluis 25:3778e6204cc1 34 fake( D8 )
Helmut64 26:87796ee62589 35 #else
GregCr 0:e6ceb13d2d05 36 fake( A3 )
Helmut64 26:87796ee62589 37 #endif
GregCr 0:e6ceb13d2d05 38 {
mluis 21:2e496deb7858 39 this->RadioEvents = events;
mluis 21:2e496deb7858 40
GregCr 0:e6ceb13d2d05 41 Reset( );
mluis 25:3778e6204cc1 42
GregCr 0:e6ceb13d2d05 43 RxChainCalibration( );
mluis 25:3778e6204cc1 44
GregCr 0:e6ceb13d2d05 45 IoInit( );
mluis 25:3778e6204cc1 46
GregCr 0:e6ceb13d2d05 47 SetOpMode( RF_OPMODE_SLEEP );
mluis 25:3778e6204cc1 48
GregCr 0:e6ceb13d2d05 49 IoIrqInit( dioIrq );
mluis 25:3778e6204cc1 50
GregCr 0:e6ceb13d2d05 51 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 52
GregCr 0:e6ceb13d2d05 53 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 54
mluis 21:2e496deb7858 55 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 56 }
GregCr 0:e6ceb13d2d05 57
mluis 25:3778e6204cc1 58 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events )
GregCr 12:aa5b3bf7fdf4 59 #if defined ( TARGET_NUCLEO_L152RE )
mluis 21:2e496deb7858 60 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
GregCr 0:e6ceb13d2d05 61 antSwitch( A4 ),
GregCr 0:e6ceb13d2d05 62 fake( D8 )
mluis 20:e05596ba4166 63 #elif defined( TARGET_LPC11U6X )
mluis 21:2e496deb7858 64 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
mluis 20:e05596ba4166 65 antSwitch( P0_23 ),
mluis 20:e05596ba4166 66 fake( A3 )
GregCr 0:e6ceb13d2d05 67 #else
mluis 21:2e496deb7858 68 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
Helmut64 26:87796ee62589 69 #ifdef MURTA_ANT_SWITCH
Helmut64 26:87796ee62589 70 antSwitch(A4), antSwitchTX(NC), antSwitchTXBoost(NC),
Helmut64 26:87796ee62589 71 #else
GregCr 12:aa5b3bf7fdf4 72 antSwitch( A4 ),
Helmut64 26:87796ee62589 73 #endif
GregCr 12:aa5b3bf7fdf4 74 fake( A3 )
GregCr 0:e6ceb13d2d05 75 #endif
GregCr 0:e6ceb13d2d05 76 {
mluis 21:2e496deb7858 77 this->RadioEvents = events;
mluis 21:2e496deb7858 78
GregCr 0:e6ceb13d2d05 79 Reset( );
mluis 25:3778e6204cc1 80
GregCr 5:11ec8a6ba4f0 81 boardConnected = UNKNOWN;
mluis 25:3778e6204cc1 82
GregCr 1:f979673946c0 83 DetectBoardType( );
mluis 25:3778e6204cc1 84
GregCr 0:e6ceb13d2d05 85 RxChainCalibration( );
mluis 25:3778e6204cc1 86
GregCr 0:e6ceb13d2d05 87 IoInit( );
mluis 25:3778e6204cc1 88
GregCr 0:e6ceb13d2d05 89 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 90 IoIrqInit( dioIrq );
mluis 25:3778e6204cc1 91
GregCr 0:e6ceb13d2d05 92 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 93
GregCr 0:e6ceb13d2d05 94 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 95
mluis 21:2e496deb7858 96 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 97 }
GregCr 0:e6ceb13d2d05 98
GregCr 0:e6ceb13d2d05 99 //-------------------------------------------------------------------------
GregCr 0:e6ceb13d2d05 100 // Board relative functions
GregCr 0:e6ceb13d2d05 101 //-------------------------------------------------------------------------
GregCr 2:5eb3066446dd 102 uint8_t SX1276MB1xAS::DetectBoardType( void )
GregCr 1:f979673946c0 103 {
GregCr 5:11ec8a6ba4f0 104 if( boardConnected == UNKNOWN )
GregCr 1:f979673946c0 105 {
GregCr 5:11ec8a6ba4f0 106 antSwitch.input( );
GregCr 5:11ec8a6ba4f0 107 wait_ms( 1 );
GregCr 5:11ec8a6ba4f0 108 if( antSwitch == 1 )
GregCr 5:11ec8a6ba4f0 109 {
GregCr 5:11ec8a6ba4f0 110 boardConnected = SX1276MB1LAS;
GregCr 5:11ec8a6ba4f0 111 }
GregCr 5:11ec8a6ba4f0 112 else
GregCr 5:11ec8a6ba4f0 113 {
GregCr 5:11ec8a6ba4f0 114 boardConnected = SX1276MB1MAS;
GregCr 5:11ec8a6ba4f0 115 }
GregCr 5:11ec8a6ba4f0 116 antSwitch.output( );
GregCr 5:11ec8a6ba4f0 117 wait_ms( 1 );
GregCr 1:f979673946c0 118 }
GregCr 2:5eb3066446dd 119 return ( boardConnected );
GregCr 1:f979673946c0 120 }
GregCr 0:e6ceb13d2d05 121
GregCr 0:e6ceb13d2d05 122 void SX1276MB1xAS::IoInit( void )
GregCr 0:e6ceb13d2d05 123 {
GregCr 0:e6ceb13d2d05 124 AntSwInit( );
GregCr 0:e6ceb13d2d05 125 SpiInit( );
GregCr 0:e6ceb13d2d05 126 }
GregCr 0:e6ceb13d2d05 127
mluis 22:7f3aab69cca9 128 void SX1276MB1xAS::RadioRegistersInit( )
mluis 22:7f3aab69cca9 129 {
GregCr 0:e6ceb13d2d05 130 uint8_t i = 0;
GregCr 0:e6ceb13d2d05 131 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
GregCr 0:e6ceb13d2d05 132 {
GregCr 0:e6ceb13d2d05 133 SetModem( RadioRegsInit[i].Modem );
GregCr 0:e6ceb13d2d05 134 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
GregCr 0:e6ceb13d2d05 135 }
GregCr 0:e6ceb13d2d05 136 }
GregCr 0:e6ceb13d2d05 137
GregCr 0:e6ceb13d2d05 138 void SX1276MB1xAS::SpiInit( void )
GregCr 0:e6ceb13d2d05 139 {
GregCr 0:e6ceb13d2d05 140 nss = 1;
GregCr 0:e6ceb13d2d05 141 spi.format( 8,0 );
GregCr 0:e6ceb13d2d05 142 uint32_t frequencyToSet = 8000000;
Helmut64 26:87796ee62589 143 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) || defined(TARGET_STM) )
GregCr 0:e6ceb13d2d05 144 spi.frequency( frequencyToSet );
GregCr 0:e6ceb13d2d05 145 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
GregCr 0:e6ceb13d2d05 146 spi.frequency( frequencyToSet * 2 );
GregCr 0:e6ceb13d2d05 147 #else
GregCr 0:e6ceb13d2d05 148 #warning "Check the board's SPI frequency"
GregCr 0:e6ceb13d2d05 149 #endif
GregCr 0:e6ceb13d2d05 150 wait(0.1);
GregCr 0:e6ceb13d2d05 151 }
GregCr 0:e6ceb13d2d05 152
GregCr 0:e6ceb13d2d05 153 void SX1276MB1xAS::IoIrqInit( DioIrqHandler *irqHandlers )
GregCr 0:e6ceb13d2d05 154 {
mluis 25:3778e6204cc1 155 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
mluis 25:3778e6204cc1 156 dio0.mode( PullDown );
mluis 25:3778e6204cc1 157 dio1.mode( PullDown );
mluis 25:3778e6204cc1 158 dio2.mode( PullDown );
mluis 25:3778e6204cc1 159 dio3.mode( PullDown );
mluis 25:3778e6204cc1 160 dio4.mode( PullDown );
mluis 22:7f3aab69cca9 161 #endif
GregCr 0:e6ceb13d2d05 162 dio0.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[0] ) );
GregCr 0:e6ceb13d2d05 163 dio1.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[1] ) );
GregCr 0:e6ceb13d2d05 164 dio2.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[2] ) );
GregCr 0:e6ceb13d2d05 165 dio3.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[3] ) );
GregCr 0:e6ceb13d2d05 166 dio4.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[4] ) );
GregCr 0:e6ceb13d2d05 167 }
GregCr 0:e6ceb13d2d05 168
GregCr 0:e6ceb13d2d05 169 void SX1276MB1xAS::IoDeInit( void )
GregCr 0:e6ceb13d2d05 170 {
GregCr 0:e6ceb13d2d05 171 //nothing
GregCr 0:e6ceb13d2d05 172 }
GregCr 0:e6ceb13d2d05 173
GregCr 0:e6ceb13d2d05 174 uint8_t SX1276MB1xAS::GetPaSelect( uint32_t channel )
GregCr 0:e6ceb13d2d05 175 {
GregCr 0:e6ceb13d2d05 176 if( channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 177 {
GregCr 3:ca84be1f3fac 178 if( boardConnected == SX1276MB1LAS )
GregCr 1:f979673946c0 179 {
GregCr 1:f979673946c0 180 return RF_PACONFIG_PASELECT_PABOOST;
GregCr 1:f979673946c0 181 }
GregCr 1:f979673946c0 182 else
GregCr 1:f979673946c0 183 {
GregCr 1:f979673946c0 184 return RF_PACONFIG_PASELECT_RFO;
GregCr 1:f979673946c0 185 }
GregCr 0:e6ceb13d2d05 186 }
GregCr 0:e6ceb13d2d05 187 else
GregCr 0:e6ceb13d2d05 188 {
GregCr 0:e6ceb13d2d05 189 return RF_PACONFIG_PASELECT_RFO;
GregCr 0:e6ceb13d2d05 190 }
GregCr 0:e6ceb13d2d05 191 }
GregCr 0:e6ceb13d2d05 192
GregCr 0:e6ceb13d2d05 193 void SX1276MB1xAS::SetAntSwLowPower( bool status )
GregCr 0:e6ceb13d2d05 194 {
GregCr 0:e6ceb13d2d05 195 if( isRadioActive != status )
GregCr 0:e6ceb13d2d05 196 {
GregCr 0:e6ceb13d2d05 197 isRadioActive = status;
GregCr 0:e6ceb13d2d05 198
GregCr 0:e6ceb13d2d05 199 if( status == false )
GregCr 0:e6ceb13d2d05 200 {
GregCr 0:e6ceb13d2d05 201 AntSwInit( );
GregCr 0:e6ceb13d2d05 202 }
GregCr 0:e6ceb13d2d05 203 else
GregCr 0:e6ceb13d2d05 204 {
GregCr 0:e6ceb13d2d05 205 AntSwDeInit( );
GregCr 0:e6ceb13d2d05 206 }
GregCr 0:e6ceb13d2d05 207 }
GregCr 0:e6ceb13d2d05 208 }
GregCr 0:e6ceb13d2d05 209
GregCr 0:e6ceb13d2d05 210 void SX1276MB1xAS::AntSwInit( void )
GregCr 0:e6ceb13d2d05 211 {
GregCr 0:e6ceb13d2d05 212 antSwitch = 0;
Helmut64 26:87796ee62589 213 #ifdef MURTA_ANT_SWITCH
Helmut64 26:87796ee62589 214 antSwitchTX = 0;
Helmut64 26:87796ee62589 215 antSwitchTXBoost = 0;
Helmut64 26:87796ee62589 216 #endif
GregCr 0:e6ceb13d2d05 217 }
GregCr 0:e6ceb13d2d05 218
GregCr 0:e6ceb13d2d05 219 void SX1276MB1xAS::AntSwDeInit( void )
GregCr 0:e6ceb13d2d05 220 {
GregCr 0:e6ceb13d2d05 221 antSwitch = 0;
Helmut64 26:87796ee62589 222 #ifdef MURTA_ANT_SWITCH
Helmut64 26:87796ee62589 223 antSwitchTX = 0;
Helmut64 26:87796ee62589 224 antSwitchTXBoost = 0;
Helmut64 26:87796ee62589 225 #endif
GregCr 0:e6ceb13d2d05 226 }
GregCr 0:e6ceb13d2d05 227
GregCr 0:e6ceb13d2d05 228 void SX1276MB1xAS::SetAntSw( uint8_t rxTx )
GregCr 0:e6ceb13d2d05 229 {
GregCr 0:e6ceb13d2d05 230
GregCr 0:e6ceb13d2d05 231 this->rxTx = rxTx;
GregCr 0:e6ceb13d2d05 232
mluis 25:3778e6204cc1 233 // 1: Tx, 0: Rx
GregCr 0:e6ceb13d2d05 234 if( rxTx != 0 )
GregCr 0:e6ceb13d2d05 235 {
Helmut64 26:87796ee62589 236 #ifdef MURTA_ANT_SWITCH
Helmut64 26:87796ee62589 237 antSwitch = 0; // RX
Helmut64 26:87796ee62589 238 antSwitchTX = 1; // alternate: antSwitchTXBoost = 1
Helmut64 26:87796ee62589 239 #else
GregCr 0:e6ceb13d2d05 240 antSwitch = 1;
Helmut64 26:87796ee62589 241 #endif
Helmut64 26:87796ee62589 242 } else {
Helmut64 26:87796ee62589 243 #ifdef MURTA_ANT_SWITCH
Helmut64 26:87796ee62589 244 antSwitch = 1; // RX
Helmut64 26:87796ee62589 245 antSwitchTX = 0;
Helmut64 26:87796ee62589 246 antSwitchTXBoost = 0;
Helmut64 26:87796ee62589 247 #else
GregCr 0:e6ceb13d2d05 248 antSwitch = 0;
Helmut64 26:87796ee62589 249 #endif
GregCr 0:e6ceb13d2d05 250 }
GregCr 0:e6ceb13d2d05 251 }
GregCr 0:e6ceb13d2d05 252
GregCr 0:e6ceb13d2d05 253 bool SX1276MB1xAS::CheckRfFrequency( uint32_t frequency )
GregCr 0:e6ceb13d2d05 254 {
GregCr 0:e6ceb13d2d05 255 //TODO: Implement check, currently all frequencies are supported
GregCr 0:e6ceb13d2d05 256 return true;
GregCr 0:e6ceb13d2d05 257 }
GregCr 0:e6ceb13d2d05 258
GregCr 0:e6ceb13d2d05 259
GregCr 0:e6ceb13d2d05 260 void SX1276MB1xAS::Reset( void )
GregCr 0:e6ceb13d2d05 261 {
GregCr 4:f0ce52e94d3f 262 reset.output();
GregCr 0:e6ceb13d2d05 263 reset = 0;
GregCr 0:e6ceb13d2d05 264 wait_ms( 1 );
GregCr 4:f0ce52e94d3f 265 reset.input();
GregCr 0:e6ceb13d2d05 266 wait_ms( 6 );
GregCr 0:e6ceb13d2d05 267 }
GregCr 0:e6ceb13d2d05 268
GregCr 0:e6ceb13d2d05 269 void SX1276MB1xAS::Write( uint8_t addr, uint8_t data )
GregCr 0:e6ceb13d2d05 270 {
GregCr 0:e6ceb13d2d05 271 Write( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 272 }
GregCr 0:e6ceb13d2d05 273
GregCr 0:e6ceb13d2d05 274 uint8_t SX1276MB1xAS::Read( uint8_t addr )
GregCr 0:e6ceb13d2d05 275 {
GregCr 0:e6ceb13d2d05 276 uint8_t data;
GregCr 0:e6ceb13d2d05 277 Read( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 278 return data;
GregCr 0:e6ceb13d2d05 279 }
GregCr 0:e6ceb13d2d05 280
GregCr 0:e6ceb13d2d05 281 void SX1276MB1xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 282 {
GregCr 0:e6ceb13d2d05 283 uint8_t i;
GregCr 0:e6ceb13d2d05 284
GregCr 0:e6ceb13d2d05 285 nss = 0;
GregCr 0:e6ceb13d2d05 286 spi.write( addr | 0x80 );
GregCr 0:e6ceb13d2d05 287 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 288 {
GregCr 0:e6ceb13d2d05 289 spi.write( buffer[i] );
GregCr 0:e6ceb13d2d05 290 }
GregCr 0:e6ceb13d2d05 291 nss = 1;
GregCr 0:e6ceb13d2d05 292 }
GregCr 0:e6ceb13d2d05 293
GregCr 0:e6ceb13d2d05 294 void SX1276MB1xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 295 {
GregCr 0:e6ceb13d2d05 296 uint8_t i;
GregCr 0:e6ceb13d2d05 297
GregCr 0:e6ceb13d2d05 298 nss = 0;
GregCr 0:e6ceb13d2d05 299 spi.write( addr & 0x7F );
GregCr 0:e6ceb13d2d05 300 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 301 {
GregCr 0:e6ceb13d2d05 302 buffer[i] = spi.write( 0 );
GregCr 0:e6ceb13d2d05 303 }
GregCr 0:e6ceb13d2d05 304 nss = 1;
GregCr 0:e6ceb13d2d05 305 }
GregCr 0:e6ceb13d2d05 306
GregCr 0:e6ceb13d2d05 307 void SX1276MB1xAS::WriteFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 308 {
GregCr 0:e6ceb13d2d05 309 Write( 0, buffer, size );
GregCr 0:e6ceb13d2d05 310 }
GregCr 0:e6ceb13d2d05 311
GregCr 0:e6ceb13d2d05 312 void SX1276MB1xAS::ReadFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 313 {
GregCr 0:e6ceb13d2d05 314 Read( 0, buffer, size );
GregCr 0:e6ceb13d2d05 315 }