Damien Frost / NRF2401P

My fork during debugging.

Fork of NRF2401P by Malcolm McCulloch

NRF2401P.cpp@7:621a5b0cf1aa, 2015-07-05 (annotated)

Committer:
nixonkj
Date:
Sun Jul 05 22:20:40 2015 +0000
Revision:
7:621a5b0cf1aa
Parent:
6:77ead8abdd1c
Child:
8:3e027705ce23
Doxygen example "template" for setRadio.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
epgmdm 0:8fd0531ae0be 1 /**
epgmdm 0:8fd0531ae0be 2 *@section DESCRIPTION
epgmdm 0:8fd0531ae0be 3 * mbed NRF2401+ Library
epgmdm 0:8fd0531ae0be 4 *@section LICENSE
epgmdm 0:8fd0531ae0be 5 * Copyright (c) 2015, Malcolm McCulloch
epgmdm 0:8fd0531ae0be 6 *
epgmdm 0:8fd0531ae0be 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
epgmdm 0:8fd0531ae0be 8 * of this software and associated documentation files (the "Software"), to deal
epgmdm 0:8fd0531ae0be 9 * in the Software without restriction, including without limitation the rights
epgmdm 0:8fd0531ae0be 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
epgmdm 0:8fd0531ae0be 11 * copies of the Software, and to permit persons to whom the Software is
epgmdm 0:8fd0531ae0be 12 * furnished to do so, subject to the following conditions:
epgmdm 0:8fd0531ae0be 13 *
epgmdm 0:8fd0531ae0be 14 * The above copyright notice and this permission notice shall be included in
epgmdm 0:8fd0531ae0be 15 * all copies or substantial portions of the Software.
epgmdm 0:8fd0531ae0be 16 *
epgmdm 0:8fd0531ae0be 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
epgmdm 0:8fd0531ae0be 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
epgmdm 0:8fd0531ae0be 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
epgmdm 0:8fd0531ae0be 20 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
epgmdm 0:8fd0531ae0be 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
epgmdm 0:8fd0531ae0be 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
epgmdm 0:8fd0531ae0be 23 * THE SOFTWARE.
epgmdm 0:8fd0531ae0be 24 * @file "NRF2401P.cpp"
epgmdm 0:8fd0531ae0be 25 */
epgmdm 2:ca0a3c0bba70 26 #include "mbed.h"
epgmdm 2:ca0a3c0bba70 27 #include "NRF2401P.h"
epgmdm 2:ca0a3c0bba70 28 #include "nRF24l01.h"
epgmdm 0:8fd0531ae0be 29
epgmdm 0:8fd0531ae0be 30 NRF2401P::NRF2401P ( PinName mosi, PinName miso, PinName sclk, PinName _csn, PinName _ce ) :
epgmdm 0:8fd0531ae0be 31 csn( DigitalOut( _csn ) ), ce( DigitalOut( _ce ) )
epgmdm 0:8fd0531ae0be 32 {
epgmdm 0:8fd0531ae0be 33 addressWidth = 5;
epgmdm 0:8fd0531ae0be 34 pc = new Serial( USBTX, USBRX ); // tx, rx
nixonkj 6:77ead8abdd1c 35 if (debug) {
nixonkj 6:77ead8abdd1c 36 sprintf(logMsg, "Initialise" );
nixonkj 6:77ead8abdd1c 37 log(logMsg);
nixonkj 6:77ead8abdd1c 38 }
epgmdm 0:8fd0531ae0be 39 spi = new SPI( mosi, miso, sclk, NC ); //SPI (PinName mosi, PinName miso, PinName sclk, PinName _unused=NC)
epgmdm 0:8fd0531ae0be 40 spi->frequency( 10000000 ); // 1MHZ max 10 MHz
epgmdm 0:8fd0531ae0be 41 spi->format( 8, 0 ); // 0: 0e 08; 1: 0e 00; 2:0e 00 ;3:1c 00
epgmdm 0:8fd0531ae0be 42 csn = 1;
epgmdm 0:8fd0531ae0be 43 ce = 0;
epgmdm 0:8fd0531ae0be 44 dynamic = false;
nixonkj 6:77ead8abdd1c 45 debug = false;
nixonkj 6:77ead8abdd1c 46 }
epgmdm 0:8fd0531ae0be 47
epgmdm 0:8fd0531ae0be 48 /**
epgmdm 0:8fd0531ae0be 49 * writes to pc and waits
epgmdm 0:8fd0531ae0be 50 */
nixonkj 6:77ead8abdd1c 51 void NRF2401P::log(char *msg)
epgmdm 0:8fd0531ae0be 52 {
epgmdm 0:8fd0531ae0be 53 if(debug) {
epgmdm 2:ca0a3c0bba70 54 printf("\t <%s \t %s>\n\r",statusString(), msg);
epgmdm 1:ff53b1ac3bad 55 wait(0.01);
nixonkj 6:77ead8abdd1c 56 }
epgmdm 0:8fd0531ae0be 57 }
epgmdm 0:8fd0531ae0be 58
epgmdm 0:8fd0531ae0be 59 void NRF2401P::scratch()
epgmdm 0:8fd0531ae0be 60 {
epgmdm 0:8fd0531ae0be 61 int status = 0;
epgmdm 0:8fd0531ae0be 62 int register1 = 0;
epgmdm 0:8fd0531ae0be 63 ce = 0;
epgmdm 0:8fd0531ae0be 64 for ( char i = 0; i < 24; i++ ) {
epgmdm 0:8fd0531ae0be 65 csn = 0;
epgmdm 0:8fd0531ae0be 66 //wait_us(100);
epgmdm 0:8fd0531ae0be 67 status = spi->write( i );
epgmdm 0:8fd0531ae0be 68 register1 = spi->write( 0x00 );
epgmdm 0:8fd0531ae0be 69 csn = 1;
epgmdm 0:8fd0531ae0be 70 sprintf(logMsg, " register %02x (%02x) = %02x", i, status, register1 );
epgmdm 0:8fd0531ae0be 71 log(logMsg);
epgmdm 0:8fd0531ae0be 72 }
nixonkj 6:77ead8abdd1c 73 }
epgmdm 0:8fd0531ae0be 74
epgmdm 0:8fd0531ae0be 75 /**
epgmdm 2:ca0a3c0bba70 76 * start here to configure the basics of the NRF
epgmdm 2:ca0a3c0bba70 77 */
epgmdm 2:ca0a3c0bba70 78 void NRF2401P::start()
epgmdm 2:ca0a3c0bba70 79 {
epgmdm 2:ca0a3c0bba70 80 writeReg( CONFIG, 0x0c ); // set 16 bit crc
epgmdm 2:ca0a3c0bba70 81 setTxRetry(0x01,0x0f); // 500 uS, 15 retries
epgmdm 2:ca0a3c0bba70 82 setRadio(0,0x03); // 1MB/S 0dB
epgmdm 2:ca0a3c0bba70 83 setDynamicPayload();
epgmdm 2:ca0a3c0bba70 84 setChannel(76); // should be clear?
epgmdm 2:ca0a3c0bba70 85 setAddressWidth(5);
epgmdm 2:ca0a3c0bba70 86 flushRx();
epgmdm 2:ca0a3c0bba70 87 flushTx();
epgmdm 2:ca0a3c0bba70 88 setPwrUp();
epgmdm 2:ca0a3c0bba70 89 setTxMode(); // just make sure no spurious reads....
nixonkj 6:77ead8abdd1c 90 }
epgmdm 2:ca0a3c0bba70 91
epgmdm 2:ca0a3c0bba70 92 /**
epgmdm 0:8fd0531ae0be 93 * Sets up a reciever using shockburst and dynamic payload. Uses pipe 1
epgmdm 0:8fd0531ae0be 94 * defaults to 5 bytes
epgmdm 0:8fd0531ae0be 95 */
epgmdm 2:ca0a3c0bba70 96 void NRF2401P::quickRxSetup(int channel,long long addrRx)
epgmdm 0:8fd0531ae0be 97 {
epgmdm 2:ca0a3c0bba70 98 start();
epgmdm 0:8fd0531ae0be 99 setChannel(channel);
epgmdm 2:ca0a3c0bba70 100 setRxAddress(addrRx,1);
epgmdm 0:8fd0531ae0be 101 setRxMode();
epgmdm 0:8fd0531ae0be 102 ce=1;
nixonkj 6:77ead8abdd1c 103 wait(0.001f);
epgmdm 0:8fd0531ae0be 104 }
nixonkj 6:77ead8abdd1c 105
epgmdm 0:8fd0531ae0be 106 /**
epgmdm 0:8fd0531ae0be 107 * Sets up for receive of a message to address 0XA0A0A0
epgmdm 0:8fd0531ae0be 108 */
epgmdm 0:8fd0531ae0be 109 char NRF2401P::testReceive()
epgmdm 0:8fd0531ae0be 110 {
epgmdm 0:8fd0531ae0be 111 char message[64];
epgmdm 0:8fd0531ae0be 112 char width;
epgmdm 0:8fd0531ae0be 113 int channel = 0x12;
epgmdm 0:8fd0531ae0be 114 long long addr=0xA0B0C0;
epgmdm 0:8fd0531ae0be 115 debug = true;
epgmdm 0:8fd0531ae0be 116 quickRxSetup(channel, addr);
epgmdm 0:8fd0531ae0be 117
epgmdm 0:8fd0531ae0be 118 while (1) {
epgmdm 0:8fd0531ae0be 119 while (!isRxData()) {
epgmdm 0:8fd0531ae0be 120 //wait(0.5);
epgmdm 0:8fd0531ae0be 121 };
epgmdm 0:8fd0531ae0be 122 width=getRxData(message);
epgmdm 0:8fd0531ae0be 123 message[width]='\0';
epgmdm 0:8fd0531ae0be 124 sprintf(logMsg,"Received= [%s]",message);
epgmdm 0:8fd0531ae0be 125 log(logMsg);
nixonkj 6:77ead8abdd1c 126 }
epgmdm 0:8fd0531ae0be 127 }
epgmdm 0:8fd0531ae0be 128
epgmdm 0:8fd0531ae0be 129 /**
epgmdm 2:ca0a3c0bba70 130 * Sets the number and the timimg of TX retries
epgmdm 2:ca0a3c0bba70 131 */
nixonkj 6:77ead8abdd1c 132 char NRF2401P::setTxRetry(char delay, char numTries)
epgmdm 2:ca0a3c0bba70 133 {
epgmdm 2:ca0a3c0bba70 134 char val = (delay&0xf)<<4 | (numTries&0xf);
nixonkj 6:77ead8abdd1c 135 char chk;
epgmdm 2:ca0a3c0bba70 136 writeReg (SETUP_RETR, val);
nixonkj 6:77ead8abdd1c 137 readReg( SETUP_RETR, &chk );
nixonkj 6:77ead8abdd1c 138 if (chk&0xff == val) {
nixonkj 6:77ead8abdd1c 139 return 0;
nixonkj 6:77ead8abdd1c 140 } else {
nixonkj 6:77ead8abdd1c 141 return 1;
nixonkj 6:77ead8abdd1c 142 }
epgmdm 2:ca0a3c0bba70 143 }
epgmdm 2:ca0a3c0bba70 144
epgmdm 2:ca0a3c0bba70 145 /**
epgmdm 0:8fd0531ae0be 146 * Sets up a transmitter using shockburst and dynamic payload. Uses pipe 1
epgmdm 0:8fd0531ae0be 147 * defaults to 5 bytes
epgmdm 0:8fd0531ae0be 148 */
epgmdm 0:8fd0531ae0be 149 void NRF2401P::quickTxSetup(int channel,long long addr)
epgmdm 0:8fd0531ae0be 150 {
epgmdm 2:ca0a3c0bba70 151 start();
epgmdm 0:8fd0531ae0be 152 setChannel(channel);
epgmdm 2:ca0a3c0bba70 153 setTxAddress(addr);
epgmdm 0:8fd0531ae0be 154 setTxMode();
epgmdm 0:8fd0531ae0be 155 ce=1;
epgmdm 0:8fd0531ae0be 156 wait (0.0016f); // wait for pll to settle
epgmdm 0:8fd0531ae0be 157 }
epgmdm 0:8fd0531ae0be 158
epgmdm 0:8fd0531ae0be 159 /**
epgmdm 0:8fd0531ae0be 160 * Sets up for transmit of a message to address 0XA0A0A0
epgmdm 0:8fd0531ae0be 161 */
epgmdm 0:8fd0531ae0be 162 char NRF2401P::testTransmit()
epgmdm 0:8fd0531ae0be 163 {
epgmdm 0:8fd0531ae0be 164 long long addr=0xA0B0C0;
epgmdm 0:8fd0531ae0be 165 int channel = 0x12;
epgmdm 0:8fd0531ae0be 166 char data[32] ;
epgmdm 0:8fd0531ae0be 167 int i=0;
epgmdm 0:8fd0531ae0be 168 quickRxSetup(channel, addr);
epgmdm 0:8fd0531ae0be 169 while (1) {
epgmdm 0:8fd0531ae0be 170 sprintf(data," packet %03d", i++ |100);
epgmdm 0:8fd0531ae0be 171 transmitData(data,18);
epgmdm 0:8fd0531ae0be 172 wait (1.0);
epgmdm 0:8fd0531ae0be 173 }
nixonkj 6:77ead8abdd1c 174 }
epgmdm 0:8fd0531ae0be 175
nixonkj 6:77ead8abdd1c 176 char NRF2401P::setRadio(char speed, char power)
epgmdm 0:8fd0531ae0be 177 {
nixonkj 6:77ead8abdd1c 178 char val=0, chk=0;
epgmdm 0:8fd0531ae0be 179 sprintf(logMsg, "Set radio");
epgmdm 0:8fd0531ae0be 180 log(logMsg);
epgmdm 0:8fd0531ae0be 181 if (speed & 0x02) {
epgmdm 0:8fd0531ae0be 182 val |= (1<<5);
epgmdm 0:8fd0531ae0be 183 }
epgmdm 0:8fd0531ae0be 184 val |= (speed & 0x01)<<3;
epgmdm 0:8fd0531ae0be 185
nixonkj 6:77ead8abdd1c 186 val |= ((power & 0x03)<<1);
nixonkj 6:77ead8abdd1c 187 printf("\n\r");
nixonkj 6:77ead8abdd1c 188
nixonkj 6:77ead8abdd1c 189 writeReg (0x06, val);
epgmdm 0:8fd0531ae0be 190
nixonkj 6:77ead8abdd1c 191 // read register to verify settings
nixonkj 6:77ead8abdd1c 192 readReg( 0x06, &chk );
nixonkj 6:77ead8abdd1c 193 if (chk&0x2E == val) {
nixonkj 6:77ead8abdd1c 194 return 0;
nixonkj 6:77ead8abdd1c 195 } else {
nixonkj 6:77ead8abdd1c 196 return 1;
nixonkj 6:77ead8abdd1c 197 }
epgmdm 0:8fd0531ae0be 198 }
nixonkj 6:77ead8abdd1c 199
epgmdm 0:8fd0531ae0be 200 /**
epgmdm 0:8fd0531ae0be 201 Set RF_CH = chan;
epgmdm 0:8fd0531ae0be 202
epgmdm 0:8fd0531ae0be 203 F0= 2400 + chan [MHz]
epgmdm 0:8fd0531ae0be 204 */
epgmdm 0:8fd0531ae0be 205 char NRF2401P::setChannel(char chan)
epgmdm 0:8fd0531ae0be 206 {
nixonkj 6:77ead8abdd1c 207 char chk=0;
nixonkj 6:77ead8abdd1c 208 if (debug) {
nixonkj 6:77ead8abdd1c 209 sprintf(logMsg, "Set channel");
nixonkj 6:77ead8abdd1c 210 log(logMsg);
nixonkj 6:77ead8abdd1c 211 }
epgmdm 0:8fd0531ae0be 212 writeReg (0x05,(chan&0x7f));
nixonkj 6:77ead8abdd1c 213 readReg(0x05,&chk);
nixonkj 6:77ead8abdd1c 214 if (chk&0x7f == chan&0x7f) {
nixonkj 6:77ead8abdd1c 215 return 0;
nixonkj 6:77ead8abdd1c 216 } else {
nixonkj 6:77ead8abdd1c 217 return 1;
nixonkj 6:77ead8abdd1c 218 }
epgmdm 0:8fd0531ae0be 219 }
nixonkj 6:77ead8abdd1c 220
epgmdm 0:8fd0531ae0be 221 /**
epgmdm 0:8fd0531ae0be 222 * Transmits width bytes of data. width <32
epgmdm 0:8fd0531ae0be 223 */
nixonkj 6:77ead8abdd1c 224 char NRF2401P::transmitData( char *data, char width )
epgmdm 0:8fd0531ae0be 225 {
nixonkj 6:77ead8abdd1c 226 if (width>32)
nixonkj 6:77ead8abdd1c 227 return 0;
nixonkj 6:77ead8abdd1c 228 checkStatus();
nixonkj 6:77ead8abdd1c 229 if ((status>>4)&1) { // Max retries - flush tx
nixonkj 6:77ead8abdd1c 230 flushTx();
nixonkj 6:77ead8abdd1c 231 }
epgmdm 2:ca0a3c0bba70 232 //clearStatus();
epgmdm 2:ca0a3c0bba70 233 //ce = 1;
epgmdm 0:8fd0531ae0be 234 csn = 0;
epgmdm 0:8fd0531ae0be 235 char address = 0XA0;
epgmdm 0:8fd0531ae0be 236 int i;
epgmdm 0:8fd0531ae0be 237 // set up for writing
epgmdm 0:8fd0531ae0be 238 status = spi->write( address );
epgmdm 0:8fd0531ae0be 239 for ( i = 0; i <width; i++ ) {
epgmdm 0:8fd0531ae0be 240 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 241 }
epgmdm 0:8fd0531ae0be 242 csn = 1;
epgmdm 3:afe8d307b5c3 243 wait(0.001);
epgmdm 3:afe8d307b5c3 244 if (debug) {
nixonkj 6:77ead8abdd1c 245 sprintf(logMsg, " Transmit data %d bytes to %02x (%02x) = %10s", width, address, status, data );
epgmdm 3:afe8d307b5c3 246 log(logMsg);
epgmdm 2:ca0a3c0bba70 247 }
epgmdm 0:8fd0531ae0be 248 return status;
epgmdm 0:8fd0531ae0be 249 }
epgmdm 0:8fd0531ae0be 250
epgmdm 0:8fd0531ae0be 251 /**
epgmdm 0:8fd0531ae0be 252 * sets acknowledge data width bytes of data. width <32
epgmdm 0:8fd0531ae0be 253 */
epgmdm 1:ff53b1ac3bad 254 char NRF2401P::acknowledgeData( char *data, char width, char pipe )
epgmdm 0:8fd0531ae0be 255 {
epgmdm 0:8fd0531ae0be 256 ce = 1;
epgmdm 0:8fd0531ae0be 257 csn = 0;
epgmdm 2:ca0a3c0bba70 258 //writeReg(0x1d,0x06); // enable payload with ack
epgmdm 2:ca0a3c0bba70 259 char address = W_ACK_PAYLOAD | (pipe&0x07);
epgmdm 0:8fd0531ae0be 260 int i;
epgmdm 0:8fd0531ae0be 261 // set up for writing
epgmdm 3:afe8d307b5c3 262 csn = 0;
epgmdm 0:8fd0531ae0be 263 status = spi->write( address );
epgmdm 0:8fd0531ae0be 264 for ( i = 0; i <width; i++ ) {
epgmdm 0:8fd0531ae0be 265 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 266 }
epgmdm 0:8fd0531ae0be 267 csn = 1;
epgmdm 3:afe8d307b5c3 268 if (debug) {
epgmdm 3:afe8d307b5c3 269 sprintf(logMsg, " acknowledge data %d bytes to %02x (%02x) = %c", width, address, status, *data );
epgmdm 3:afe8d307b5c3 270 log(logMsg);
epgmdm 2:ca0a3c0bba70 271 }
epgmdm 0:8fd0531ae0be 272 return status;
nixonkj 6:77ead8abdd1c 273 }
epgmdm 0:8fd0531ae0be 274
epgmdm 0:8fd0531ae0be 275 /**
epgmdm 0:8fd0531ae0be 276 * Writes 1 byte data to a register
epgmdm 0:8fd0531ae0be 277 **/
nixonkj 6:77ead8abdd1c 278 void NRF2401P::writeReg( char address, char data )
epgmdm 0:8fd0531ae0be 279 {
epgmdm 0:8fd0531ae0be 280 char status = 0;
epgmdm 0:8fd0531ae0be 281 char reg;
epgmdm 0:8fd0531ae0be 282 csn = 0;
epgmdm 0:8fd0531ae0be 283 address &= 0x1F;
epgmdm 0:8fd0531ae0be 284 reg = address | 0x20;
epgmdm 0:8fd0531ae0be 285 status = spi->write( reg );
epgmdm 0:8fd0531ae0be 286 spi->write( data );
epgmdm 0:8fd0531ae0be 287 csn = 1;
nixonkj 6:77ead8abdd1c 288 if (debug) {
nixonkj 6:77ead8abdd1c 289 sprintf(logMsg, " register write %02x (%02x) = %02x", address, status, data );
nixonkj 6:77ead8abdd1c 290 log(logMsg);
nixonkj 6:77ead8abdd1c 291 }
epgmdm 0:8fd0531ae0be 292 }
nixonkj 6:77ead8abdd1c 293
epgmdm 0:8fd0531ae0be 294 /**
epgmdm 0:8fd0531ae0be 295 * Writes width bytes data to a register, ls byte to ms byte /for adressess
epgmdm 0:8fd0531ae0be 296 **/
nixonkj 6:77ead8abdd1c 297 void NRF2401P::writeReg( char address, char *data, char width )
epgmdm 0:8fd0531ae0be 298 {
epgmdm 0:8fd0531ae0be 299 char reg;
epgmdm 0:8fd0531ae0be 300 csn = 0;
epgmdm 0:8fd0531ae0be 301 int i;
epgmdm 0:8fd0531ae0be 302 // set up for writing
epgmdm 0:8fd0531ae0be 303 address &= 0x1F;
epgmdm 0:8fd0531ae0be 304 reg = address| 0x20;
epgmdm 0:8fd0531ae0be 305 status = spi->write( reg );
epgmdm 0:8fd0531ae0be 306 for ( i = width - 1; i >= 0; i-- ) {
epgmdm 0:8fd0531ae0be 307 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 308 }
epgmdm 0:8fd0531ae0be 309 csn = 1;
epgmdm 2:ca0a3c0bba70 310 if (debug) {
epgmdm 2:ca0a3c0bba70 311 sprintf(logMsg, " register write %d bytes to %02x (%02x) = %02x %02x %02x", width, address, status, data[0], data[1], data[2] );
epgmdm 2:ca0a3c0bba70 312 log(logMsg);
epgmdm 2:ca0a3c0bba70 313 }
epgmdm 0:8fd0531ae0be 314 }
nixonkj 6:77ead8abdd1c 315
epgmdm 0:8fd0531ae0be 316 /**
epgmdm 0:8fd0531ae0be 317 * Reads 1 byte from a register
epgmdm 0:8fd0531ae0be 318 **/
nixonkj 6:77ead8abdd1c 319 void NRF2401P::readReg( char address, char *data )
epgmdm 0:8fd0531ae0be 320 {
epgmdm 0:8fd0531ae0be 321 csn = 0;
epgmdm 0:8fd0531ae0be 322 address &= 0x1F;
epgmdm 0:8fd0531ae0be 323 status = spi->write( address );
epgmdm 0:8fd0531ae0be 324 *data = spi->write( 0x00 );
epgmdm 0:8fd0531ae0be 325 csn = 1;
nixonkj 6:77ead8abdd1c 326 if (debug && address != 0x07) { // In debug mode: print out anything other than a status request
nixonkj 6:77ead8abdd1c 327 sprintf(logMsg, " register read %02x (%02x) = %02x", address, status, *data );
nixonkj 6:77ead8abdd1c 328 log(logMsg);
nixonkj 6:77ead8abdd1c 329 }
epgmdm 0:8fd0531ae0be 330 }
nixonkj 6:77ead8abdd1c 331
epgmdm 0:8fd0531ae0be 332 /**
epgmdm 0:8fd0531ae0be 333 * Clears the status flags RX_DR, TX_DS, MAX_RT
epgmdm 0:8fd0531ae0be 334 */
nixonkj 6:77ead8abdd1c 335 void NRF2401P::clearStatus()
epgmdm 0:8fd0531ae0be 336 {
nixonkj 6:77ead8abdd1c 337 writeReg(STATUS,0x70);
epgmdm 2:ca0a3c0bba70 338 if (debug) {
epgmdm 2:ca0a3c0bba70 339 sprintf(logMsg, "Clear status (%02x)", status );
epgmdm 2:ca0a3c0bba70 340 log(logMsg);
epgmdm 2:ca0a3c0bba70 341 }
epgmdm 0:8fd0531ae0be 342 }
nixonkj 6:77ead8abdd1c 343
epgmdm 0:8fd0531ae0be 344 /**
epgmdm 0:8fd0531ae0be 345 * flushes TX FIFO and resets status flags
epgmdm 0:8fd0531ae0be 346 */
nixonkj 6:77ead8abdd1c 347 void NRF2401P::flushTx()
epgmdm 0:8fd0531ae0be 348 {
epgmdm 0:8fd0531ae0be 349 csn = 0;
epgmdm 2:ca0a3c0bba70 350 status = spi->write( FLUSH_TX );
epgmdm 0:8fd0531ae0be 351 csn = 1;
epgmdm 0:8fd0531ae0be 352 clearStatus();
epgmdm 2:ca0a3c0bba70 353 if (debug) {
epgmdm 2:ca0a3c0bba70 354 sprintf(logMsg, "Flush TX FIFO (%02x)", status );
epgmdm 2:ca0a3c0bba70 355 log(logMsg);
epgmdm 2:ca0a3c0bba70 356 }
epgmdm 0:8fd0531ae0be 357 }
epgmdm 0:8fd0531ae0be 358
epgmdm 0:8fd0531ae0be 359 /**
epgmdm 0:8fd0531ae0be 360 * flushes RX FIFO and resets status flags
epgmdm 0:8fd0531ae0be 361 */
nixonkj 6:77ead8abdd1c 362 void NRF2401P::flushRx()
epgmdm 0:8fd0531ae0be 363 {
epgmdm 0:8fd0531ae0be 364 csn = 0;
epgmdm 2:ca0a3c0bba70 365 status = spi->write( FLUSH_RX );
epgmdm 0:8fd0531ae0be 366 csn = 1;
epgmdm 2:ca0a3c0bba70 367 clearStatus();
epgmdm 2:ca0a3c0bba70 368 if (debug) {
epgmdm 2:ca0a3c0bba70 369 sprintf(logMsg, "Flush RX FIFO (%02x)", status );
epgmdm 2:ca0a3c0bba70 370 log(logMsg);
epgmdm 2:ca0a3c0bba70 371 }
epgmdm 0:8fd0531ae0be 372 }
nixonkj 6:77ead8abdd1c 373
epgmdm 0:8fd0531ae0be 374 /**
epgmdm 0:8fd0531ae0be 375 * Sets PRIM_RX = 0;
epgmdm 0:8fd0531ae0be 376 */
nixonkj 6:77ead8abdd1c 377 char NRF2401P::setTxMode()
epgmdm 0:8fd0531ae0be 378 {
epgmdm 0:8fd0531ae0be 379 char data;
epgmdm 0:8fd0531ae0be 380 char bit;
epgmdm 2:ca0a3c0bba70 381 if (debug) {
epgmdm 2:ca0a3c0bba70 382 sprintf(logMsg, "Set Tx Mode");
epgmdm 2:ca0a3c0bba70 383 log(logMsg);
epgmdm 2:ca0a3c0bba70 384 }
epgmdm 2:ca0a3c0bba70 385 readReg( CONFIG, &data );
epgmdm 0:8fd0531ae0be 386 data &= ~( 1 << 0 );
epgmdm 2:ca0a3c0bba70 387 flushTx();
epgmdm 2:ca0a3c0bba70 388 flushRx();
epgmdm 2:ca0a3c0bba70 389 writeReg( CONFIG, data );
epgmdm 3:afe8d307b5c3 390 writeReg( RX_ADDR_P0, txAdd, addressWidth ); // reset p0
epgmdm 2:ca0a3c0bba70 391 writeReg(EN_RXADDR,0x01); // enable pipe 0 for reading
epgmdm 0:8fd0531ae0be 392 // check
epgmdm 0:8fd0531ae0be 393 readReg( 0x00, &data );
epgmdm 0:8fd0531ae0be 394 bit = ( data >> 0 ) & 1;
epgmdm 2:ca0a3c0bba70 395
epgmdm 0:8fd0531ae0be 396 ce=1;
epgmdm 0:8fd0531ae0be 397 wait(0.003);
nixonkj 6:77ead8abdd1c 398 if (bit == 0) {
nixonkj 6:77ead8abdd1c 399 return 0;
nixonkj 6:77ead8abdd1c 400 } else {
nixonkj 6:77ead8abdd1c 401 return 1;
nixonkj 6:77ead8abdd1c 402 }
epgmdm 0:8fd0531ae0be 403 }
epgmdm 0:8fd0531ae0be 404
epgmdm 0:8fd0531ae0be 405 /**
epgmdm 0:8fd0531ae0be 406 * Sets the number of bytes of the address width = 3,4,5
epgmdm 0:8fd0531ae0be 407 */
nixonkj 6:77ead8abdd1c 408 char NRF2401P::setAddressWidth( char width )
epgmdm 0:8fd0531ae0be 409 {
nixonkj 6:77ead8abdd1c 410 char chk=0;
epgmdm 0:8fd0531ae0be 411 addressWidth = width;
epgmdm 0:8fd0531ae0be 412 if ( ( width > 5 ) || ( width < 3 ) )
epgmdm 0:8fd0531ae0be 413 return false;
epgmdm 0:8fd0531ae0be 414 width -= 2;
nixonkj 6:77ead8abdd1c 415 writeReg( 0x03, width );
nixonkj 6:77ead8abdd1c 416 readReg( 0x03, &chk );
nixonkj 6:77ead8abdd1c 417 if (chk&0x03 == width) {
nixonkj 6:77ead8abdd1c 418 return 0;
nixonkj 6:77ead8abdd1c 419 } else {
nixonkj 6:77ead8abdd1c 420 return 1;
nixonkj 6:77ead8abdd1c 421 }
epgmdm 0:8fd0531ae0be 422 }
nixonkj 6:77ead8abdd1c 423
epgmdm 0:8fd0531ae0be 424 /**
nixonkj 6:77ead8abdd1c 425 * Sets the address, uses address width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 426 */
epgmdm 0:8fd0531ae0be 427 char NRF2401P::setTxAddress( char *address )
epgmdm 0:8fd0531ae0be 428 {
epgmdm 2:ca0a3c0bba70 429 memcpy (txAdd,address, addressWidth);
epgmdm 0:8fd0531ae0be 430 writeReg( 0x0A, address, addressWidth ); //Write to RX_ADDR_P0
nixonkj 6:77ead8abdd1c 431 writeReg( 0x10, address, addressWidth ); //Write to TX_ADDR
nixonkj 6:77ead8abdd1c 432 return 0; // must fix this
epgmdm 0:8fd0531ae0be 433 }
epgmdm 0:8fd0531ae0be 434
epgmdm 0:8fd0531ae0be 435 /**
epgmdm 0:8fd0531ae0be 436 * Sets the address, uses addess width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 437 */
epgmdm 0:8fd0531ae0be 438 char NRF2401P::setTxAddress( long long address )
epgmdm 0:8fd0531ae0be 439 {
epgmdm 0:8fd0531ae0be 440 char buff[ 5 ];
epgmdm 0:8fd0531ae0be 441 buff[ 0 ] = address & 0xff;
epgmdm 0:8fd0531ae0be 442 buff[ 1 ] = ( address >> 8 ) & 0xFF;
epgmdm 0:8fd0531ae0be 443 buff[ 2 ] = ( address >> 16 ) & 0xFF;
epgmdm 0:8fd0531ae0be 444 buff[ 3 ] = ( address >> 24 ) & 0xFF;
epgmdm 0:8fd0531ae0be 445 buff[ 4 ] = ( address >> 32 ) & 0xFF;
epgmdm 0:8fd0531ae0be 446 return setTxAddress( buff );
epgmdm 0:8fd0531ae0be 447 }
epgmdm 0:8fd0531ae0be 448
epgmdm 0:8fd0531ae0be 449 /**
epgmdm 0:8fd0531ae0be 450 * Sets the address, uses addess width set (either 3,4 or 5)
epgmdm 2:ca0a3c0bba70 451 * Enables pipe for receiving;
epgmdm 0:8fd0531ae0be 452 */
epgmdm 0:8fd0531ae0be 453 char NRF2401P::setRxAddress( char *address, char pipe )
epgmdm 0:8fd0531ae0be 454 {
epgmdm 2:ca0a3c0bba70 455 if(debug) {
epgmdm 2:ca0a3c0bba70 456 log ("Set Rx Address");
epgmdm 2:ca0a3c0bba70 457 }
epgmdm 2:ca0a3c0bba70 458 if (pipe>5) return 0xff;
epgmdm 2:ca0a3c0bba70 459 if (pipe ==0) {
epgmdm 2:ca0a3c0bba70 460 memcpy (pipe0Add,address, addressWidth);
epgmdm 2:ca0a3c0bba70 461 }
epgmdm 2:ca0a3c0bba70 462
epgmdm 0:8fd0531ae0be 463 char reg = 0x0A + pipe;
epgmdm 0:8fd0531ae0be 464 switch ( pipe ) {
epgmdm 0:8fd0531ae0be 465 case ( 0 ) :
epgmdm 0:8fd0531ae0be 466 case ( 1 ) : {
nixonkj 6:77ead8abdd1c 467 writeReg( reg, address, addressWidth ); //Write to RX_ADDR_P0 or _P1
epgmdm 0:8fd0531ae0be 468 break;
epgmdm 0:8fd0531ae0be 469 }
epgmdm 0:8fd0531ae0be 470 case ( 2 ) :
epgmdm 0:8fd0531ae0be 471 case ( 3 ) :
epgmdm 0:8fd0531ae0be 472 case ( 4 ) :
epgmdm 0:8fd0531ae0be 473 case ( 5 ) : {
nixonkj 6:77ead8abdd1c 474 writeReg( reg, address, 1 ); //Write to RX_ADDR_P2 ... _P5
epgmdm 0:8fd0531ae0be 475 break;
epgmdm 0:8fd0531ae0be 476 }
epgmdm 0:8fd0531ae0be 477
epgmdm 0:8fd0531ae0be 478 }
epgmdm 2:ca0a3c0bba70 479 readReg(EN_RXADDR,&reg);
epgmdm 2:ca0a3c0bba70 480 reg |= (1<<pipe);
epgmdm 2:ca0a3c0bba70 481 writeReg( EN_RXADDR,reg ); //Enable the pipe
nixonkj 6:77ead8abdd1c 482 return 0; // Must fix this
epgmdm 0:8fd0531ae0be 483 }
epgmdm 0:8fd0531ae0be 484
epgmdm 0:8fd0531ae0be 485 /**
epgmdm 0:8fd0531ae0be 486 * Sets the address of pipe (<=5), uses addess width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 487 */
epgmdm 0:8fd0531ae0be 488 char NRF2401P::setRxAddress( long long address, char pipe )
epgmdm 0:8fd0531ae0be 489 {
epgmdm 0:8fd0531ae0be 490 char buff[ 5 ];
epgmdm 0:8fd0531ae0be 491 buff[ 0 ] = address & 0xff;
epgmdm 0:8fd0531ae0be 492 buff[ 1 ] = ( address >> 8 ) & 0xFF;
epgmdm 0:8fd0531ae0be 493 buff[ 2 ] = ( address >> 16 ) & 0xFF;
epgmdm 0:8fd0531ae0be 494 buff[ 3 ] = ( address >> 24 ) & 0xFF;
epgmdm 0:8fd0531ae0be 495 buff[ 4 ] = ( address >> 32 ) & 0xFF;
epgmdm 0:8fd0531ae0be 496 return setRxAddress( buff, pipe );
epgmdm 0:8fd0531ae0be 497 }
nixonkj 6:77ead8abdd1c 498
epgmdm 1:ff53b1ac3bad 499 /**
epgmdm 1:ff53b1ac3bad 500 *checks the status flag
epgmdm 1:ff53b1ac3bad 501 */
epgmdm 1:ff53b1ac3bad 502 char NRF2401P::checkStatus()
epgmdm 1:ff53b1ac3bad 503 {
epgmdm 1:ff53b1ac3bad 504 readReg(0x07,&status);
epgmdm 1:ff53b1ac3bad 505 return status;
epgmdm 1:ff53b1ac3bad 506 }
nixonkj 6:77ead8abdd1c 507
epgmdm 1:ff53b1ac3bad 508 /**
epgmdm 1:ff53b1ac3bad 509 * checks if Ack data available.
epgmdm 1:ff53b1ac3bad 510 */
epgmdm 1:ff53b1ac3bad 511 bool NRF2401P::isAckData()
epgmdm 1:ff53b1ac3bad 512 {
epgmdm 1:ff53b1ac3bad 513 char fifo;
epgmdm 1:ff53b1ac3bad 514 readReg(0x17,&fifo);
epgmdm 1:ff53b1ac3bad 515 bool isData = !(fifo&0x01);
epgmdm 1:ff53b1ac3bad 516 return isData;
epgmdm 1:ff53b1ac3bad 517 }
epgmdm 0:8fd0531ae0be 518
epgmdm 1:ff53b1ac3bad 519 /**
epgmdm 1:ff53b1ac3bad 520 * checks if RX data available.
epgmdm 1:ff53b1ac3bad 521 */
epgmdm 0:8fd0531ae0be 522 bool NRF2401P::isRxData()
epgmdm 0:8fd0531ae0be 523 {
epgmdm 1:ff53b1ac3bad 524 checkStatus();
epgmdm 0:8fd0531ae0be 525 bool isData = (status>>6)&0x01;
epgmdm 0:8fd0531ae0be 526 return isData;
epgmdm 0:8fd0531ae0be 527 }
nixonkj 6:77ead8abdd1c 528
epgmdm 0:8fd0531ae0be 529 /**
epgmdm 0:8fd0531ae0be 530 * returns the width of the dynamic payload
epgmdm 0:8fd0531ae0be 531 */
epgmdm 0:8fd0531ae0be 532 char NRF2401P::getRxWidth()
epgmdm 0:8fd0531ae0be 533 {
epgmdm 0:8fd0531ae0be 534 char width;
epgmdm 0:8fd0531ae0be 535 if (dynamic) {
epgmdm 0:8fd0531ae0be 536 csn = 0;
epgmdm 0:8fd0531ae0be 537 status = spi->write( 0x60 );
epgmdm 0:8fd0531ae0be 538 width = spi->write(0x00);
epgmdm 0:8fd0531ae0be 539 csn = 1;
epgmdm 0:8fd0531ae0be 540
epgmdm 0:8fd0531ae0be 541 if (width>32) {
epgmdm 0:8fd0531ae0be 542 flushRx();
epgmdm 0:8fd0531ae0be 543 width=0;
epgmdm 0:8fd0531ae0be 544 }
epgmdm 0:8fd0531ae0be 545 } else {
nixonkj 6:77ead8abdd1c 546 readReg(0x12,&width); // width of p1
epgmdm 0:8fd0531ae0be 547 }
epgmdm 1:ff53b1ac3bad 548 // width=18;
epgmdm 0:8fd0531ae0be 549 return width;
epgmdm 0:8fd0531ae0be 550 }
nixonkj 6:77ead8abdd1c 551
epgmdm 0:8fd0531ae0be 552 /**
epgmdm 0:8fd0531ae0be 553 * return message in buffer, mem for buffer must have been allocated.
epgmdm 0:8fd0531ae0be 554 * Return value is number of bytes of buffer
epgmdm 0:8fd0531ae0be 555 */
epgmdm 0:8fd0531ae0be 556 char NRF2401P::getRxData(char * buffer)
epgmdm 0:8fd0531ae0be 557 {
epgmdm 0:8fd0531ae0be 558 char address = 0x61;
epgmdm 0:8fd0531ae0be 559 char width;
epgmdm 0:8fd0531ae0be 560 width = getRxWidth();
epgmdm 0:8fd0531ae0be 561 bool isData = (status>>6)&0x01;
epgmdm 0:8fd0531ae0be 562 if (isData) {
epgmdm 0:8fd0531ae0be 563 csn = 0;
epgmdm 0:8fd0531ae0be 564 int i;
epgmdm 0:8fd0531ae0be 565 // set up for reading
epgmdm 0:8fd0531ae0be 566 status = spi->write( address );
epgmdm 0:8fd0531ae0be 567 for ( i = 0; i <= width; i++ ) {
epgmdm 0:8fd0531ae0be 568 buffer[i]=spi->write(0x00 );
epgmdm 0:8fd0531ae0be 569 }
epgmdm 0:8fd0531ae0be 570 csn = 1;
nixonkj 6:77ead8abdd1c 571 if (debug) {
nixonkj 6:77ead8abdd1c 572 sprintf(logMsg, "Receive data %d bytes", width );
nixonkj 6:77ead8abdd1c 573 log(logMsg);
nixonkj 6:77ead8abdd1c 574 }
epgmdm 0:8fd0531ae0be 575 clearStatus();
epgmdm 0:8fd0531ae0be 576 return width;
epgmdm 0:8fd0531ae0be 577 } else {
nixonkj 6:77ead8abdd1c 578 if (debug) {
nixonkj 6:77ead8abdd1c 579 sprintf(logMsg, "Receive NO data %d bytes", width );
nixonkj 6:77ead8abdd1c 580 log(logMsg);
nixonkj 6:77ead8abdd1c 581 }
epgmdm 0:8fd0531ae0be 582 clearStatus();
epgmdm 0:8fd0531ae0be 583 return 0;
epgmdm 0:8fd0531ae0be 584 }
epgmdm 0:8fd0531ae0be 585 }
epgmdm 0:8fd0531ae0be 586
epgmdm 0:8fd0531ae0be 587 /**
epgmdm 0:8fd0531ae0be 588 * Sets all the receive pipes to dynamic payload length
epgmdm 0:8fd0531ae0be 589 */
epgmdm 2:ca0a3c0bba70 590 void NRF2401P::setDynamicPayload()
epgmdm 0:8fd0531ae0be 591 {
epgmdm 0:8fd0531ae0be 592 dynamic = true;
epgmdm 2:ca0a3c0bba70 593 writeReg(FEATURE,0x07); // Enable Dyn payload, Payload with Ack and w_tx_noack command
epgmdm 2:ca0a3c0bba70 594 writeReg(EN_AA,0x3f); // EN_AA regi for P1 and P0
epgmdm 2:ca0a3c0bba70 595 writeReg(DYNPD, 0x1F);
epgmdm 0:8fd0531ae0be 596 }
epgmdm 2:ca0a3c0bba70 597
epgmdm 0:8fd0531ae0be 598 /**
epgmdm 0:8fd0531ae0be 599 * Sets PWR_UP = 1;
nixonkj 6:77ead8abdd1c 600 * return 0 on success
epgmdm 0:8fd0531ae0be 601 */
nixonkj 6:77ead8abdd1c 602 char NRF2401P::setPwrUp()
epgmdm 0:8fd0531ae0be 603 {
epgmdm 0:8fd0531ae0be 604 char data;
epgmdm 0:8fd0531ae0be 605 char bit;
epgmdm 0:8fd0531ae0be 606 ce=1;
epgmdm 2:ca0a3c0bba70 607 readReg( CONFIG, &data );
epgmdm 2:ca0a3c0bba70 608 if ((data>>1) &0x01) {
epgmdm 2:ca0a3c0bba70 609 return true; // Already powered up
epgmdm 2:ca0a3c0bba70 610 };
epgmdm 0:8fd0531ae0be 611 data |= ( 0x02 );
epgmdm 0:8fd0531ae0be 612 writeReg( 0x00, data );
epgmdm 0:8fd0531ae0be 613 // check
epgmdm 0:8fd0531ae0be 614 readReg( 0x00, &data );
epgmdm 0:8fd0531ae0be 615 bit = ( data >> 1 ) & 1;
epgmdm 2:ca0a3c0bba70 616
epgmdm 0:8fd0531ae0be 617 wait(0.005); // wait 5ms
epgmdm 2:ca0a3c0bba70 618 if(debug) {
epgmdm 2:ca0a3c0bba70 619 sprintf(logMsg, "Set PWR_UP to %x", bit);
epgmdm 2:ca0a3c0bba70 620 log(logMsg);
epgmdm 2:ca0a3c0bba70 621 }
nixonkj 6:77ead8abdd1c 622 if (bit == 1) {
nixonkj 6:77ead8abdd1c 623 return 0;
nixonkj 6:77ead8abdd1c 624 } else {
nixonkj 6:77ead8abdd1c 625 return 1;
nixonkj 6:77ead8abdd1c 626 }
nixonkj 6:77ead8abdd1c 627 }
epgmdm 2:ca0a3c0bba70 628
epgmdm 0:8fd0531ae0be 629 /**
epgmdm 0:8fd0531ae0be 630 * Sets PRIM_RX = 0;
epgmdm 0:8fd0531ae0be 631 */
nixonkj 6:77ead8abdd1c 632 char NRF2401P::setRxMode()
epgmdm 0:8fd0531ae0be 633 {
epgmdm 0:8fd0531ae0be 634 char data;
epgmdm 0:8fd0531ae0be 635 char bit;
epgmdm 0:8fd0531ae0be 636 ce=1;
epgmdm 0:8fd0531ae0be 637 readReg( 0x00, &data );
epgmdm 2:ca0a3c0bba70 638 data |= ( 0x01 );
epgmdm 2:ca0a3c0bba70 639
epgmdm 0:8fd0531ae0be 640 writeReg( 0x00, data );
epgmdm 3:afe8d307b5c3 641 if (pipe0Add[0]|pipe0Add[1]|pipe0Add[2]|pipe0Add[3]|pipe0Add[4] >0) {
epgmdm 3:afe8d307b5c3 642 setRxAddress(pipe0Add,0);
epgmdm 2:ca0a3c0bba70 643 }
epgmdm 0:8fd0531ae0be 644 // check
epgmdm 0:8fd0531ae0be 645 readReg( 0x00, &data );
epgmdm 0:8fd0531ae0be 646 bit = ( data >> 0 ) & 1;
epgmdm 2:ca0a3c0bba70 647
epgmdm 2:ca0a3c0bba70 648 wait (0.001);
epgmdm 0:8fd0531ae0be 649 flushRx();
epgmdm 2:ca0a3c0bba70 650 flushTx();
epgmdm 2:ca0a3c0bba70 651 if (debug) {
epgmdm 2:ca0a3c0bba70 652 sprintf(logMsg, " set PRIM_RX to %x", bit);
epgmdm 2:ca0a3c0bba70 653 log(logMsg);
epgmdm 2:ca0a3c0bba70 654 }
nixonkj 6:77ead8abdd1c 655 if ( bit == 1 ) {
nixonkj 6:77ead8abdd1c 656 return 0;
nixonkj 6:77ead8abdd1c 657 } else {
nixonkj 6:77ead8abdd1c 658 return 1;
nixonkj 6:77ead8abdd1c 659 }
epgmdm 0:8fd0531ae0be 660 }
nixonkj 6:77ead8abdd1c 661
epgmdm 0:8fd0531ae0be 662 /**
epgmdm 0:8fd0531ae0be 663 * Prints status string
epgmdm 0:8fd0531ae0be 664 */
epgmdm 0:8fd0531ae0be 665 char * NRF2401P::statusString()
epgmdm 0:8fd0531ae0be 666 {
epgmdm 0:8fd0531ae0be 667 char *msg;
epgmdm 0:8fd0531ae0be 668 msg = statusS;
epgmdm 0:8fd0531ae0be 669 if (((status>>1) & 0x07)==0x07) {
epgmdm 0:8fd0531ae0be 670 sprintf(msg,"RX empty");
epgmdm 0:8fd0531ae0be 671 } else {
epgmdm 0:8fd0531ae0be 672 sprintf(msg,"pipe %02x",(status>>1) & 0x07);
epgmdm 0:8fd0531ae0be 673 }
epgmdm 0:8fd0531ae0be 674
epgmdm 0:8fd0531ae0be 675 if ((status>>6)&0x01) strcat(msg," RX_DR,");
epgmdm 0:8fd0531ae0be 676 if ((status>>5)&0x01) strcat(msg," TX_DS,");
epgmdm 0:8fd0531ae0be 677 if ((status>>4)&0x01) strcat(msg," MAX_RT,");
epgmdm 0:8fd0531ae0be 678 if ((status>>0)&0x01) strcat(msg," TX_FLL,");
epgmdm 0:8fd0531ae0be 679
epgmdm 0:8fd0531ae0be 680 return msg;
epgmdm 0:8fd0531ae0be 681 }