Deepana Ishtaweera / vl53l0x

tof library

Dependents:   speed_robot

VL53L0X.h@0:1c8c01640f54, 2019-10-01 (annotated)

Committer:
deepanaishtaweera174
Date:
Tue Oct 01 12:33:27 2019 +0000
Revision:
0:1c8c01640f54
hey

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deepanaishtaweera174 0:1c8c01640f54 1 #ifndef VL53L0X_h
deepanaishtaweera174 0:1c8c01640f54 2 #define VL53L0X_h
deepanaishtaweera174 0:1c8c01640f54 3
deepanaishtaweera174 0:1c8c01640f54 4 #include <mbed.h>
deepanaishtaweera174 0:1c8c01640f54 5
deepanaishtaweera174 0:1c8c01640f54 6 class VL53L0X
deepanaishtaweera174 0:1c8c01640f54 7 {
deepanaishtaweera174 0:1c8c01640f54 8 public:
deepanaishtaweera174 0:1c8c01640f54 9 // register addresses from API vl53l0x_device.h (ordered as listed there)
deepanaishtaweera174 0:1c8c01640f54 10 enum regAddr
deepanaishtaweera174 0:1c8c01640f54 11 {
deepanaishtaweera174 0:1c8c01640f54 12 SYSRANGE_START = 0x00,
deepanaishtaweera174 0:1c8c01640f54 13
deepanaishtaweera174 0:1c8c01640f54 14 SYSTEM_THRESH_HIGH = 0x0C,
deepanaishtaweera174 0:1c8c01640f54 15 SYSTEM_THRESH_LOW = 0x0E,
deepanaishtaweera174 0:1c8c01640f54 16
deepanaishtaweera174 0:1c8c01640f54 17 SYSTEM_SEQUENCE_CONFIG = 0x01,
deepanaishtaweera174 0:1c8c01640f54 18 SYSTEM_RANGE_CONFIG = 0x09,
deepanaishtaweera174 0:1c8c01640f54 19 SYSTEM_INTERMEASUREMENT_PERIOD = 0x04,
deepanaishtaweera174 0:1c8c01640f54 20
deepanaishtaweera174 0:1c8c01640f54 21 SYSTEM_INTERRUPT_CONFIG_GPIO = 0x0A,
deepanaishtaweera174 0:1c8c01640f54 22
deepanaishtaweera174 0:1c8c01640f54 23 GPIO_HV_MUX_ACTIVE_HIGH = 0x84,
deepanaishtaweera174 0:1c8c01640f54 24
deepanaishtaweera174 0:1c8c01640f54 25 SYSTEM_INTERRUPT_CLEAR = 0x0B,
deepanaishtaweera174 0:1c8c01640f54 26
deepanaishtaweera174 0:1c8c01640f54 27 RESULT_INTERRUPT_STATUS = 0x13,
deepanaishtaweera174 0:1c8c01640f54 28 RESULT_RANGE_STATUS = 0x14,
deepanaishtaweera174 0:1c8c01640f54 29
deepanaishtaweera174 0:1c8c01640f54 30 RESULT_CORE_AMBIENT_WINDOW_EVENTS_RTN = 0xBC,
deepanaishtaweera174 0:1c8c01640f54 31 RESULT_CORE_RANGING_TOTAL_EVENTS_RTN = 0xC0,
deepanaishtaweera174 0:1c8c01640f54 32 RESULT_CORE_AMBIENT_WINDOW_EVENTS_REF = 0xD0,
deepanaishtaweera174 0:1c8c01640f54 33 RESULT_CORE_RANGING_TOTAL_EVENTS_REF = 0xD4,
deepanaishtaweera174 0:1c8c01640f54 34 RESULT_PEAK_SIGNAL_RATE_REF = 0xB6,
deepanaishtaweera174 0:1c8c01640f54 35
deepanaishtaweera174 0:1c8c01640f54 36 ALGO_PART_TO_PART_RANGE_OFFSET_MM = 0x28,
deepanaishtaweera174 0:1c8c01640f54 37
deepanaishtaweera174 0:1c8c01640f54 38 I2C_SLAVE_DEVICE_ADDRESS = 0x8A,
deepanaishtaweera174 0:1c8c01640f54 39
deepanaishtaweera174 0:1c8c01640f54 40 MSRC_CONFIG_CONTROL = 0x60,
deepanaishtaweera174 0:1c8c01640f54 41
deepanaishtaweera174 0:1c8c01640f54 42 PRE_RANGE_CONFIG_MIN_SNR = 0x27,
deepanaishtaweera174 0:1c8c01640f54 43 PRE_RANGE_CONFIG_VALID_PHASE_LOW = 0x56,
deepanaishtaweera174 0:1c8c01640f54 44 PRE_RANGE_CONFIG_VALID_PHASE_HIGH = 0x57,
deepanaishtaweera174 0:1c8c01640f54 45 PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT = 0x64,
deepanaishtaweera174 0:1c8c01640f54 46
deepanaishtaweera174 0:1c8c01640f54 47 FINAL_RANGE_CONFIG_MIN_SNR = 0x67,
deepanaishtaweera174 0:1c8c01640f54 48 FINAL_RANGE_CONFIG_VALID_PHASE_LOW = 0x47,
deepanaishtaweera174 0:1c8c01640f54 49 FINAL_RANGE_CONFIG_VALID_PHASE_HIGH = 0x48,
deepanaishtaweera174 0:1c8c01640f54 50 FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT = 0x44,
deepanaishtaweera174 0:1c8c01640f54 51
deepanaishtaweera174 0:1c8c01640f54 52 PRE_RANGE_CONFIG_SIGMA_THRESH_HI = 0x61,
deepanaishtaweera174 0:1c8c01640f54 53 PRE_RANGE_CONFIG_SIGMA_THRESH_LO = 0x62,
deepanaishtaweera174 0:1c8c01640f54 54
deepanaishtaweera174 0:1c8c01640f54 55 PRE_RANGE_CONFIG_VCSEL_PERIOD = 0x50,
deepanaishtaweera174 0:1c8c01640f54 56 PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI = 0x51,
deepanaishtaweera174 0:1c8c01640f54 57 PRE_RANGE_CONFIG_TIMEOUT_MACROP_LO = 0x52,
deepanaishtaweera174 0:1c8c01640f54 58
deepanaishtaweera174 0:1c8c01640f54 59 SYSTEM_HISTOGRAM_BIN = 0x81,
deepanaishtaweera174 0:1c8c01640f54 60 HISTOGRAM_CONFIG_INITIAL_PHASE_SELECT = 0x33,
deepanaishtaweera174 0:1c8c01640f54 61 HISTOGRAM_CONFIG_READOUT_CTRL = 0x55,
deepanaishtaweera174 0:1c8c01640f54 62
deepanaishtaweera174 0:1c8c01640f54 63 FINAL_RANGE_CONFIG_VCSEL_PERIOD = 0x70,
deepanaishtaweera174 0:1c8c01640f54 64 FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI = 0x71,
deepanaishtaweera174 0:1c8c01640f54 65 FINAL_RANGE_CONFIG_TIMEOUT_MACROP_LO = 0x72,
deepanaishtaweera174 0:1c8c01640f54 66 CROSSTALK_COMPENSATION_PEAK_RATE_MCPS = 0x20,
deepanaishtaweera174 0:1c8c01640f54 67
deepanaishtaweera174 0:1c8c01640f54 68 MSRC_CONFIG_TIMEOUT_MACROP = 0x46,
deepanaishtaweera174 0:1c8c01640f54 69
deepanaishtaweera174 0:1c8c01640f54 70 SOFT_RESET_GO2_SOFT_RESET_N = 0xBF,
deepanaishtaweera174 0:1c8c01640f54 71 IDENTIFICATION_MODEL_ID = 0xC0,
deepanaishtaweera174 0:1c8c01640f54 72 IDENTIFICATION_REVISION_ID = 0xC2,
deepanaishtaweera174 0:1c8c01640f54 73
deepanaishtaweera174 0:1c8c01640f54 74 OSC_CALIBRATE_VAL = 0xF8,
deepanaishtaweera174 0:1c8c01640f54 75
deepanaishtaweera174 0:1c8c01640f54 76 GLOBAL_CONFIG_VCSEL_WIDTH = 0x32,
deepanaishtaweera174 0:1c8c01640f54 77 GLOBAL_CONFIG_SPAD_ENABLES_REF_0 = 0xB0,
deepanaishtaweera174 0:1c8c01640f54 78 GLOBAL_CONFIG_SPAD_ENABLES_REF_1 = 0xB1,
deepanaishtaweera174 0:1c8c01640f54 79 GLOBAL_CONFIG_SPAD_ENABLES_REF_2 = 0xB2,
deepanaishtaweera174 0:1c8c01640f54 80 GLOBAL_CONFIG_SPAD_ENABLES_REF_3 = 0xB3,
deepanaishtaweera174 0:1c8c01640f54 81 GLOBAL_CONFIG_SPAD_ENABLES_REF_4 = 0xB4,
deepanaishtaweera174 0:1c8c01640f54 82 GLOBAL_CONFIG_SPAD_ENABLES_REF_5 = 0xB5,
deepanaishtaweera174 0:1c8c01640f54 83
deepanaishtaweera174 0:1c8c01640f54 84 GLOBAL_CONFIG_REF_EN_START_SELECT = 0xB6,
deepanaishtaweera174 0:1c8c01640f54 85 DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD = 0x4E,
deepanaishtaweera174 0:1c8c01640f54 86 DYNAMIC_SPAD_REF_EN_START_OFFSET = 0x4F,
deepanaishtaweera174 0:1c8c01640f54 87 POWER_MANAGEMENT_GO1_POWER_FORCE = 0x80,
deepanaishtaweera174 0:1c8c01640f54 88
deepanaishtaweera174 0:1c8c01640f54 89 VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV = 0x89,
deepanaishtaweera174 0:1c8c01640f54 90
deepanaishtaweera174 0:1c8c01640f54 91 ALGO_PHASECAL_LIM = 0x30,
deepanaishtaweera174 0:1c8c01640f54 92 ALGO_PHASECAL_CONFIG_TIMEOUT = 0x30,
deepanaishtaweera174 0:1c8c01640f54 93 };
deepanaishtaweera174 0:1c8c01640f54 94
deepanaishtaweera174 0:1c8c01640f54 95 enum vcselPeriodType { VcselPeriodPreRange, VcselPeriodFinalRange };
deepanaishtaweera174 0:1c8c01640f54 96
deepanaishtaweera174 0:1c8c01640f54 97 uint8_t last_status; // status of last I2C transmission
deepanaishtaweera174 0:1c8c01640f54 98
deepanaishtaweera174 0:1c8c01640f54 99 VL53L0X(I2C*, Timer*);
deepanaishtaweera174 0:1c8c01640f54 100
deepanaishtaweera174 0:1c8c01640f54 101 void setAddress(uint8_t new_addr);
deepanaishtaweera174 0:1c8c01640f54 102 inline uint8_t getAddress(void) { return address; }
deepanaishtaweera174 0:1c8c01640f54 103
deepanaishtaweera174 0:1c8c01640f54 104 bool init(bool io_2v8 = true);
deepanaishtaweera174 0:1c8c01640f54 105
deepanaishtaweera174 0:1c8c01640f54 106 void writeReg(uint8_t reg, uint8_t value);
deepanaishtaweera174 0:1c8c01640f54 107 void writeReg16Bit(uint8_t reg, uint16_t value);
deepanaishtaweera174 0:1c8c01640f54 108 void writeReg32Bit(uint8_t reg, uint32_t value);
deepanaishtaweera174 0:1c8c01640f54 109 uint8_t readReg(uint8_t reg);
deepanaishtaweera174 0:1c8c01640f54 110 uint16_t readReg16Bit(uint8_t reg);
deepanaishtaweera174 0:1c8c01640f54 111 uint32_t readReg32Bit(uint8_t reg);
deepanaishtaweera174 0:1c8c01640f54 112
deepanaishtaweera174 0:1c8c01640f54 113 void writeMulti(uint8_t reg, uint8_t const * src, uint8_t count);
deepanaishtaweera174 0:1c8c01640f54 114 void readMulti(uint8_t reg, uint8_t * dst, uint8_t count);
deepanaishtaweera174 0:1c8c01640f54 115
deepanaishtaweera174 0:1c8c01640f54 116 bool setSignalRateLimit(float limit_Mcps);
deepanaishtaweera174 0:1c8c01640f54 117 float getSignalRateLimit(void);
deepanaishtaweera174 0:1c8c01640f54 118
deepanaishtaweera174 0:1c8c01640f54 119 bool setMeasurementTimingBudget(uint32_t budget_us);
deepanaishtaweera174 0:1c8c01640f54 120 uint32_t getMeasurementTimingBudget(void);
deepanaishtaweera174 0:1c8c01640f54 121
deepanaishtaweera174 0:1c8c01640f54 122 bool setVcselPulsePeriod(vcselPeriodType type, uint8_t period_pclks);
deepanaishtaweera174 0:1c8c01640f54 123 uint8_t getVcselPulsePeriod(vcselPeriodType type);
deepanaishtaweera174 0:1c8c01640f54 124
deepanaishtaweera174 0:1c8c01640f54 125 void startContinuous(uint32_t period_ms = 0);
deepanaishtaweera174 0:1c8c01640f54 126 void stopContinuous(void);
deepanaishtaweera174 0:1c8c01640f54 127 uint16_t readRangeContinuousMillimeters(void);
deepanaishtaweera174 0:1c8c01640f54 128 uint16_t readRangeSingleMillimeters(void);
deepanaishtaweera174 0:1c8c01640f54 129
deepanaishtaweera174 0:1c8c01640f54 130 inline void setTimeout(uint16_t timeout) { io_timeout = timeout; }
deepanaishtaweera174 0:1c8c01640f54 131 inline uint16_t getTimeout(void) { return io_timeout; }
deepanaishtaweera174 0:1c8c01640f54 132 bool timeoutOccurred(void);
deepanaishtaweera174 0:1c8c01640f54 133
deepanaishtaweera174 0:1c8c01640f54 134 private:
deepanaishtaweera174 0:1c8c01640f54 135 // TCC: Target CentreCheck
deepanaishtaweera174 0:1c8c01640f54 136 // MSRC: Minimum Signal Rate Check
deepanaishtaweera174 0:1c8c01640f54 137 // DSS: Dynamic Spad Selection
deepanaishtaweera174 0:1c8c01640f54 138
deepanaishtaweera174 0:1c8c01640f54 139 struct SequenceStepEnables
deepanaishtaweera174 0:1c8c01640f54 140 {
deepanaishtaweera174 0:1c8c01640f54 141 bool tcc, msrc, dss, pre_range, final_range;
deepanaishtaweera174 0:1c8c01640f54 142 };
deepanaishtaweera174 0:1c8c01640f54 143
deepanaishtaweera174 0:1c8c01640f54 144 struct SequenceStepTimeouts
deepanaishtaweera174 0:1c8c01640f54 145 {
deepanaishtaweera174 0:1c8c01640f54 146 uint16_t pre_range_vcsel_period_pclks, final_range_vcsel_period_pclks;
deepanaishtaweera174 0:1c8c01640f54 147
deepanaishtaweera174 0:1c8c01640f54 148 uint16_t msrc_dss_tcc_mclks, pre_range_mclks, final_range_mclks;
deepanaishtaweera174 0:1c8c01640f54 149 uint32_t msrc_dss_tcc_us, pre_range_us, final_range_us;
deepanaishtaweera174 0:1c8c01640f54 150 };
deepanaishtaweera174 0:1c8c01640f54 151
deepanaishtaweera174 0:1c8c01640f54 152 uint8_t address;
deepanaishtaweera174 0:1c8c01640f54 153 uint16_t io_timeout;
deepanaishtaweera174 0:1c8c01640f54 154 bool did_timeout;
deepanaishtaweera174 0:1c8c01640f54 155 uint16_t timeout_start_ms;
deepanaishtaweera174 0:1c8c01640f54 156
deepanaishtaweera174 0:1c8c01640f54 157 uint8_t stop_variable; // read by init and used when starting measurement; is StopVariable field of VL53L0X_DevData_t structure in API
deepanaishtaweera174 0:1c8c01640f54 158 uint32_t measurement_timing_budget_us;
deepanaishtaweera174 0:1c8c01640f54 159
deepanaishtaweera174 0:1c8c01640f54 160 bool getSpadInfo(uint8_t * count, bool * type_is_aperture);
deepanaishtaweera174 0:1c8c01640f54 161
deepanaishtaweera174 0:1c8c01640f54 162 void getSequenceStepEnables(SequenceStepEnables * enables);
deepanaishtaweera174 0:1c8c01640f54 163 void getSequenceStepTimeouts(SequenceStepEnables const * enables, SequenceStepTimeouts * timeouts);
deepanaishtaweera174 0:1c8c01640f54 164
deepanaishtaweera174 0:1c8c01640f54 165 bool performSingleRefCalibration(uint8_t vhv_init_byte);
deepanaishtaweera174 0:1c8c01640f54 166
deepanaishtaweera174 0:1c8c01640f54 167 static uint16_t decodeTimeout(uint16_t value);
deepanaishtaweera174 0:1c8c01640f54 168 static uint16_t encodeTimeout(uint16_t timeout_mclks);
deepanaishtaweera174 0:1c8c01640f54 169 static uint32_t timeoutMclksToMicroseconds(uint16_t timeout_period_mclks, uint8_t vcsel_period_pclks);
deepanaishtaweera174 0:1c8c01640f54 170 static uint32_t timeoutMicrosecondsToMclks(uint32_t timeout_period_us, uint8_t vcsel_period_pclks);
deepanaishtaweera174 0:1c8c01640f54 171
deepanaishtaweera174 0:1c8c01640f54 172 // mbed members
deepanaishtaweera174 0:1c8c01640f54 173 I2C* i2c;
deepanaishtaweera174 0:1c8c01640f54 174 Timer* timer;
deepanaishtaweera174 0:1c8c01640f54 175 };
deepanaishtaweera174 0:1c8c01640f54 176
deepanaishtaweera174 0:1c8c01640f54 177 #endif