David Prentice / Mbed 2 deprecated Nucleo_dir_L152

Please run it on your NUCLEO-L152

Dependencies:   mbed

MCUFRIEND_kbv/utility/mcufriend_special.h@1:d88d2ad55fac, 2019-09-18 (annotated)

Committer:
davidprentice
Date:
Wed Sep 18 10:38:19 2019 +0000
Revision:
1:d88d2ad55fac
Parent:
0:b608c7f02f80 
Added messages to Serial Terminal (9600 baud)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
davidprentice 0:b608c7f02f80 1 // only define one "USE_XXX" macro at any time
davidprentice 0:b608c7f02f80 2
davidprentice 0:b608c7f02f80 3 //#define USE_MEGA_8BIT_PROTOSHIELD
davidprentice 0:b608c7f02f80 4 //#define USE_MEGA_8BIT_SHIELD // 4.7sec Mega2560 Shield
davidprentice 0:b608c7f02f80 5 //#define USE_MEGA_16BIT_SHIELD // 2.14sec Mega2560 Shield
davidprentice 0:b608c7f02f80 6 //#define USE_BLD_BST_MEGA32U4
davidprentice 0:b608c7f02f80 7 //#define USE_BLD_BST_MEGA2560 // 12.23sec Uno Shield (17.38s C)
davidprentice 0:b608c7f02f80 8 //#define USE_BLD_BST_MEGA4809 // 5.43sec XPRO-Adapter (7.09s C)
davidprentice 0:b608c7f02f80 9 //#define USE_DUE_8BIT_PROTOSHIELD
davidprentice 0:b608c7f02f80 10 //#define USE_DUE_16BIT_SHIELD //RD on PA15 (D24)
davidprentice 0:b608c7f02f80 11 //#define USE_BOBCACHELOT_TEENSY
davidprentice 0:b608c7f02f80 12 //#define USE_OPENSMART_SHIELD_PINOUT_UNO
davidprentice 0:b608c7f02f80 13 //#define USE_OPENSMART_SHIELD_PINOUT_MEGA
davidprentice 0:b608c7f02f80 14 //#define USE_OPENSMART_SHIELD_PINOUT_DUE //thanks Michel53
davidprentice 0:b608c7f02f80 15 //#define USE_ELECHOUSE_DUE_16BIT_SHIELD //Untested yet
davidprentice 0:b608c7f02f80 16 //#define USE_MY_BLUEPILL
davidprentice 0:b608c7f02f80 17 //#define USE_ADIGITALEU_TEENSY
davidprentice 0:b608c7f02f80 18 //#define USE_MIKROELEKTRONIKA
davidprentice 0:b608c7f02f80 19 //#define USE_XPRO_MEGA4809
davidprentice 0:b608c7f02f80 20
davidprentice 0:b608c7f02f80 21 /*
davidprentice 0:b608c7f02f80 22 HX8347A tWC =100ns tWRH = 35ns tRCFM = 450ns tRC = ? ns
davidprentice 0:b608c7f02f80 23 HX8347D tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
davidprentice 0:b608c7f02f80 24 HX8347I tWC =100ns tWRH = 15ns tRCFM = 600ns tRC = 160ns
davidprentice 0:b608c7f02f80 25 HX8357C tWC = 50ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
davidprentice 0:b608c7f02f80 26 ILI9320 tWC =100ns tWRH = 50ns tRCFM = 300ns tRC = 300ns
davidprentice 0:b608c7f02f80 27 ILI9341 tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
davidprentice 0:b608c7f02f80 28 ILI9481 tWC =100ns tWRH = 30ns tRCFM = 450ns tRC = 450ns
davidprentice 0:b608c7f02f80 29 ILI9486 tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns (tWCFM= 286ns on mystery 9486_16)
davidprentice 0:b608c7f02f80 30 ILI9486L tWC = 50ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
davidprentice 0:b608c7f02f80 31 ILI9488 tWC = 30ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
davidprentice 0:b608c7f02f80 32 NT35310 tWC = 40ns tWRH = 19ns tRCFM = 400ns tRC = 160ns
davidprentice 0:b608c7f02f80 33 RM68140 tWC = 50ns tWRH = 15ns tRCFM = 450ns tRC = 160ns (tWCFM= 119ns)
davidprentice 0:b608c7f02f80 34 SPFD5408 tWC =125ns tWRH = 70ns tRCFM = 450ns tRC = 450ns
davidprentice 0:b608c7f02f80 35 SSD1289 tWC =100ns tWRH = 50ns tRCFM =1000ns tRC =1000ns (tWCFM= 238ns)
davidprentice 0:b608c7f02f80 36 SSD1963 tWC = 26ns tWRH = 13ns tRCFM = 110ns tRC = 72ns
davidprentice 0:b608c7f02f80 37 ST7789V tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
davidprentice 0:b608c7f02f80 38 */
davidprentice 0:b608c7f02f80 39
davidprentice 0:b608c7f02f80 40 #if 0
davidprentice 0:b608c7f02f80 41
davidprentice 0:b608c7f02f80 42 #elif defined(__AVR_ATxmega128A1__) // Xplained or MIKROE
davidprentice 0:b608c7f02f80 43 #if defined(USE_MIKROELEKTRONIKA) // HX8347-D 16.2ns@62MHz 20.9ns@48MHz
davidprentice 0:b608c7f02f80 44 #if F_CPU > 46000000
davidprentice 0:b608c7f02f80 45 #error MIKROELEKTRONIKA must be less than 48MHz
davidprentice 0:b608c7f02f80 46 #else
davidprentice 0:b608c7f02f80 47 #warning MIKROELEKTRONIKA DEV BOARD (48MHz max)
davidprentice 0:b608c7f02f80 48 #endif
davidprentice 0:b608c7f02f80 49 #define WRITE_DELAY { }
davidprentice 0:b608c7f02f80 50 #define READ_DELAY { RD_ACTIVE4; }
davidprentice 0:b608c7f02f80 51 #define VPMAP10 0x58 // VPORT0=J, 1=F, 2=K, 3=D
davidprentice 0:b608c7f02f80 52 #define VPMAP32 0x39 // VPORT0=J, 1=F, 2=K, 3=D
davidprentice 0:b608c7f02f80 53 #define RD_PORT VPORT0 //PJ2.
davidprentice 0:b608c7f02f80 54 #define RD_PIN 2
davidprentice 0:b608c7f02f80 55 #define WR_PORT VPORT0
davidprentice 0:b608c7f02f80 56 #define WR_PIN 3
davidprentice 0:b608c7f02f80 57 #define CD_PORT VPORT0
davidprentice 0:b608c7f02f80 58 #define CD_PIN 4
davidprentice 0:b608c7f02f80 59 #define CS_PORT VPORT0
davidprentice 0:b608c7f02f80 60 #define CS_PIN 5
davidprentice 0:b608c7f02f80 61 #define RESET_PORT VPORT0 //PJ1
davidprentice 0:b608c7f02f80 62 #define RESET_PIN 1
davidprentice 0:b608c7f02f80 63 #else
davidprentice 0:b608c7f02f80 64 #warning Home made shield with Xplained
davidprentice 0:b608c7f02f80 65 #define WRITE_DELAY { }
davidprentice 0:b608c7f02f80 66 #define READ_DELAY { RD_ACTIVE4; }
davidprentice 0:b608c7f02f80 67 #define VPMAP10 0x15 // VPORT0=F, 1=B, 2=C, 3=D
davidprentice 0:b608c7f02f80 68 #define VPMAP32 0x32 // VPORT0=F, 1=B, 2=C, 3=D
davidprentice 0:b608c7f02f80 69 #define RD_PORT VPORT0 //PF0.
davidprentice 0:b608c7f02f80 70 #define RD_PIN 0
davidprentice 0:b608c7f02f80 71 #define WR_PORT VPORT0
davidprentice 0:b608c7f02f80 72 #define WR_PIN 1
davidprentice 0:b608c7f02f80 73 #define CD_PORT VPORT0
davidprentice 0:b608c7f02f80 74 #define CD_PIN 2
davidprentice 0:b608c7f02f80 75 #define CS_PORT VPORT0
davidprentice 0:b608c7f02f80 76 #define CS_PIN 3
davidprentice 0:b608c7f02f80 77 #define RESET_PORT VPORT0 //PK4
davidprentice 0:b608c7f02f80 78 #define RESET_PIN 4
davidprentice 0:b608c7f02f80 79 #endif
davidprentice 0:b608c7f02f80 80
davidprentice 0:b608c7f02f80 81 // VPORTs are very fast. CBI, SBI are only one cycle. Hence all those RD_ACTIVEs
davidprentice 0:b608c7f02f80 82 // ILI9320 data sheet says tDDR=100ns. We need 218ns to read REGs correctly.
davidprentice 0:b608c7f02f80 83 #define write_8(x) { VPORT2.OUT = x; }
davidprentice 0:b608c7f02f80 84 #define read_8() ( VPORT2.IN )
davidprentice 0:b608c7f02f80 85 #define setWriteDir() { PORTCFG.VPCTRLA=VPMAP10; PORTCFG.VPCTRLB=VPMAP32; VPORT2.DIR = 0xFF; }
davidprentice 0:b608c7f02f80 86 #define setReadDir() { VPORT2.DIR = 0x00; }
davidprentice 0:b608c7f02f80 87 #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
davidprentice 0:b608c7f02f80 88 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 89 //#define READ_8(dst) { RD_STROBE; RD_ACTIVE2; RD_ACTIVE; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 90 #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 91 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
davidprentice 0:b608c7f02f80 92
davidprentice 0:b608c7f02f80 93 #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
davidprentice 0:b608c7f02f80 94 #define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
davidprentice 0:b608c7f02f80 95 #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
davidprentice 0:b608c7f02f80 96 #elif defined(__AVR_ATxmega32A4U__) || defined(__AVR_ATxmega128A4U__) // Home made shield with Batsocks module
davidprentice 0:b608c7f02f80 97 #warning Home made shield with Batsocks module
davidprentice 0:b608c7f02f80 98 #define RD_PORT VPORT1 //PB0. VPORT0=A, 1=B, 2=C, 3=D
davidprentice 0:b608c7f02f80 99 #define RD_PIN 0
davidprentice 0:b608c7f02f80 100 #define WR_PORT VPORT1
davidprentice 0:b608c7f02f80 101 #define WR_PIN 1
davidprentice 0:b608c7f02f80 102 #define CD_PORT VPORT1
davidprentice 0:b608c7f02f80 103 #define CD_PIN 2
davidprentice 0:b608c7f02f80 104 #define CS_PORT VPORT1
davidprentice 0:b608c7f02f80 105 #define CS_PIN 3
davidprentice 0:b608c7f02f80 106 #define RESET_PORT PORTE
davidprentice 0:b608c7f02f80 107 #define RESET_PIN 0
davidprentice 0:b608c7f02f80 108
davidprentice 0:b608c7f02f80 109 // VPORTs are very fast. CBI, SBI are only one cycle. Hence all those RD_ACTIVEs
davidprentice 0:b608c7f02f80 110 // ILI9320 data sheet says tDDR=100ns. We need 218ns to read REGs correctly.
davidprentice 0:b608c7f02f80 111 // S6D0154 data sheet says tDDR=250ns. We need ~500ns to read REGs correctly.
davidprentice 0:b608c7f02f80 112 // ST7789 data sheet says tRC=450ns. We need ~167ns to read REGs correctly. (10 cycles @ 60MHz )
davidprentice 0:b608c7f02f80 113 // ST7789 says tRC=160ns for ID and tRC=450ns for Frame Memory
davidprentice 0:b608c7f02f80 114 // ILI9341 says tRC=160ns for ID and tRC=450ns for Frame Memory. They are FASTER
davidprentice 0:b608c7f02f80 115 #define WRITE_DELAY { }
davidprentice 0:b608c7f02f80 116 #define READ_DELAY { RD_ACTIVE4; }
davidprentice 0:b608c7f02f80 117 #define write_8(x) { VPORT2.OUT = x; }
davidprentice 0:b608c7f02f80 118 #define read_8() ( VPORT2.IN )
davidprentice 0:b608c7f02f80 119 #define setWriteDir() { PORTCFG.VPCTRLA=0x10; PORTCFG.VPCTRLB=0x32; VPORT2.DIR = 0xFF; }
davidprentice 0:b608c7f02f80 120 #define setReadDir() { VPORT2.DIR = 0x00; }
davidprentice 0:b608c7f02f80 121 #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
davidprentice 0:b608c7f02f80 122 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 123 #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 124 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
davidprentice 0:b608c7f02f80 125
davidprentice 0:b608c7f02f80 126 #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
davidprentice 0:b608c7f02f80 127 #define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
davidprentice 0:b608c7f02f80 128 #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
davidprentice 0:b608c7f02f80 129
davidprentice 0:b608c7f02f80 130 //################################# XPRO-4809 with XPRO-Shield_Adapter ############################
davidprentice 0:b608c7f02f80 131 #elif defined(__AVR_ATmega4809__) && !defined(USE_BLD_BST_MEGA4809) && defined(USE_XPRO_MEGA4809) // XPRO-4809 with XPRO-Shield_Adapter
davidprentice 0:b608c7f02f80 132 #warning XPRO-4809 with XPRO-Shield_Adapter using PORT.OUTSET
davidprentice 0:b608c7f02f80 133 #define RD_PORT PORTD //
davidprentice 0:b608c7f02f80 134 #define RD_PIN 2
davidprentice 0:b608c7f02f80 135 #define WR_PORT PORTD
davidprentice 0:b608c7f02f80 136 #define WR_PIN 3
davidprentice 0:b608c7f02f80 137 #define CD_PORT PORTD
davidprentice 0:b608c7f02f80 138 #define CD_PIN 4
davidprentice 0:b608c7f02f80 139 #define CS_PORT PORTD
davidprentice 0:b608c7f02f80 140 #define CS_PIN 5
davidprentice 0:b608c7f02f80 141 #define RESET_PORT PORTC
davidprentice 0:b608c7f02f80 142 #define RESET_PIN 2
davidprentice 0:b608c7f02f80 143
davidprentice 0:b608c7f02f80 144 // PORT.OUTSET is fast but still 2 cycles. Hence all those RD_ACTIVEs
davidprentice 0:b608c7f02f80 145 #define AMASK (3<<2)
davidprentice 0:b608c7f02f80 146 #define BMASK (3<<2)
davidprentice 0:b608c7f02f80 147 #define CMASK (3<<6)
davidprentice 0:b608c7f02f80 148 #define EMASK (1<<1)
davidprentice 0:b608c7f02f80 149 #define FMASK (1<<6)
davidprentice 0:b608c7f02f80 150 #define write_8(x) { \
davidprentice 0:b608c7f02f80 151 PORTA.OUTCLR = AMASK; PORTA.OUTSET = (((x) & (3<<0)) << 2); \
davidprentice 0:b608c7f02f80 152 PORTB.OUTCLR = BMASK; PORTB.OUTSET = (((x) & (1<<2))) | (((x) & (1<<6)) >> 3); \
davidprentice 0:b608c7f02f80 153 PORTC.OUTCLR = CMASK; PORTC.OUTSET = (((x) & (3<<3)) << 3); \
davidprentice 0:b608c7f02f80 154 PORTE.OUTCLR = EMASK; PORTE.OUTSET = (((x) & (1<<7)) >> 6); \
davidprentice 0:b608c7f02f80 155 PORTF.OUTCLR = FMASK; PORTF.OUTSET = (((x) & (1<<5)) << 1); \
davidprentice 0:b608c7f02f80 156 }
davidprentice 0:b608c7f02f80 157 #define read_8() ( ((PORTA.IN & AMASK) >> 2)\
davidprentice 0:b608c7f02f80 158 | ((PORTB.IN & (1<<2)) >> 0)\
davidprentice 0:b608c7f02f80 159 | ((PORTB.IN & (1<<3)) << 3)\
davidprentice 0:b608c7f02f80 160 | ((PORTC.IN & CMASK) >> 3)\
davidprentice 0:b608c7f02f80 161 | ((PORTE.IN & EMASK) << 6)\
davidprentice 0:b608c7f02f80 162 | ((PORTF.IN & FMASK) >> 1)\
davidprentice 0:b608c7f02f80 163 )
davidprentice 0:b608c7f02f80 164 #define setWriteDir() { PORTA.DIRSET = AMASK; PORTB.DIRSET = BMASK; PORTC.DIRSET = CMASK; PORTE.DIRSET = EMASK; PORTF.DIRSET = FMASK; }
davidprentice 0:b608c7f02f80 165 #define setReadDir() { PORTA.DIRCLR = AMASK; PORTB.DIRCLR = BMASK; PORTC.DIRCLR = CMASK; PORTE.DIRCLR = EMASK; PORTF.DIRCLR = FMASK; }
davidprentice 0:b608c7f02f80 166
davidprentice 0:b608c7f02f80 167 #define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=7.09s @20MHz (-O1=8.13s, -O3=6.03s)
davidprentice 0:b608c7f02f80 168 #define READ_DELAY { RD_ACTIVE2; } //ID=0x7789
davidprentice 0:b608c7f02f80 169 #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
davidprentice 0:b608c7f02f80 170 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 171 #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 172 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
davidprentice 0:b608c7f02f80 173
davidprentice 0:b608c7f02f80 174 #define PIN_LOW(p, b) (p).OUTCLR = (1<<(b))
davidprentice 0:b608c7f02f80 175 #define PIN_HIGH(p, b) (p).OUTSET = (1<<(b))
davidprentice 0:b608c7f02f80 176 #define PIN_OUTPUT(p, b) (p).DIRSET = (1<<(b))
davidprentice 0:b608c7f02f80 177
davidprentice 0:b608c7f02f80 178 #elif defined(__AVR_ATmega4809__) && defined(USE_BLD_BST_MEGA4809) && defined(USE_XPRO_MEGA4809) // XPRO-4809 with XPRO-Shield_Adapter
davidprentice 0:b608c7f02f80 179 #warning XPRO-4809 with XPRO-Shield_Adapter using VPORT.OUT and BLD/BST
davidprentice 0:b608c7f02f80 180 #define RD_PORT VPORTD //
davidprentice 0:b608c7f02f80 181 #define RD_PIN 2
davidprentice 0:b608c7f02f80 182 #define WR_PORT VPORTD
davidprentice 0:b608c7f02f80 183 #define WR_PIN 3
davidprentice 0:b608c7f02f80 184 #define CD_PORT VPORTD
davidprentice 0:b608c7f02f80 185 #define CD_PIN 4
davidprentice 0:b608c7f02f80 186 #define CS_PORT VPORTD
davidprentice 0:b608c7f02f80 187 #define CS_PIN 5
davidprentice 0:b608c7f02f80 188 #define RESET_PORT VPORTC
davidprentice 0:b608c7f02f80 189 #define RESET_PIN 2
davidprentice 0:b608c7f02f80 190
davidprentice 0:b608c7f02f80 191 #define AMASK (3<<2)
davidprentice 0:b608c7f02f80 192 #define BMASK (3<<2)
davidprentice 0:b608c7f02f80 193 #define CMASK (3<<6)
davidprentice 0:b608c7f02f80 194 #define EMASK (1<<1)
davidprentice 0:b608c7f02f80 195 #define FMASK (1<<6)
davidprentice 0:b608c7f02f80 196 static __attribute((always_inline))
davidprentice 0:b608c7f02f80 197 void write_8(uint8_t val)
davidprentice 0:b608c7f02f80 198 {
davidprentice 0:b608c7f02f80 199 asm volatile("in __tmp_reg__,0x01" "\n\t" //VPORTA.OUT
davidprentice 0:b608c7f02f80 200 "BST %0,0" "\n\t" "BLD __tmp_reg__,2" "\n\t"
davidprentice 0:b608c7f02f80 201 "BST %0,1" "\n\t" "BLD __tmp_reg__,3" "\n\t"
davidprentice 0:b608c7f02f80 202 "out 0x01,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 203 asm volatile("in __tmp_reg__,0x05" "\n\t" //VPORTB.OUT
davidprentice 0:b608c7f02f80 204 "BST %0,2" "\n\t" "BLD __tmp_reg__,2" "\n\t"
davidprentice 0:b608c7f02f80 205 "BST %0,6" "\n\t" "BLD __tmp_reg__,3" "\n\t"
davidprentice 0:b608c7f02f80 206 "out 0x05,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 207 asm volatile("in __tmp_reg__,0x09" "\n\t" //VPORTC.OUT
davidprentice 0:b608c7f02f80 208 "BST %0,3" "\n\t" "BLD __tmp_reg__,6" "\n\t"
davidprentice 0:b608c7f02f80 209 "BST %0,4" "\n\t" "BLD __tmp_reg__,7" "\n\t"
davidprentice 0:b608c7f02f80 210 "out 0x09,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 211 asm volatile("in __tmp_reg__,0x11" "\n\t" //VPORTE.OUT
davidprentice 0:b608c7f02f80 212 "BST %0,7" "\n\t" "BLD __tmp_reg__,1" "\n\t"
davidprentice 0:b608c7f02f80 213 "out 0x11,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 214 asm volatile("in __tmp_reg__,0x15" "\n\t" //VPORTF.OUT
davidprentice 0:b608c7f02f80 215 "BST %0,5" "\n\t" "BLD __tmp_reg__,6" "\n\t"
davidprentice 0:b608c7f02f80 216 "out 0x15,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 217 }
davidprentice 0:b608c7f02f80 218
davidprentice 0:b608c7f02f80 219 #define read_8() ( ((VPORTA_IN & AMASK) >> 2)\
davidprentice 0:b608c7f02f80 220 | ((VPORTB_IN & (1<<2)) >> 0)\
davidprentice 0:b608c7f02f80 221 | ((VPORTB_IN & (1<<3)) << 3)\
davidprentice 0:b608c7f02f80 222 | ((VPORTC_IN & CMASK) >> 3)\
davidprentice 0:b608c7f02f80 223 | ((VPORTE_IN & EMASK) << 6)\
davidprentice 0:b608c7f02f80 224 | ((VPORTF_IN & FMASK) >> 1)\
davidprentice 0:b608c7f02f80 225 )
davidprentice 0:b608c7f02f80 226 #define setWriteDir() { VPORTA_DIR |= AMASK; VPORTB_DIR |= BMASK; VPORTC_DIR |= CMASK; VPORTE_DIR |= EMASK; VPORTF_DIR |= FMASK; }
davidprentice 0:b608c7f02f80 227 #define setReadDir() { VPORTA_DIR &= ~AMASK; VPORTB_DIR &= ~BMASK; VPORTC_DIR &= ~CMASK; VPORTE_DIR &= ~EMASK; VPORTF_DIR &= ~FMASK; }
davidprentice 0:b608c7f02f80 228
davidprentice 0:b608c7f02f80 229 //#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; } //6.47s no_inline
davidprentice 0:b608c7f02f80 230 #define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=5.43s @20MHz always_inline. (-O1=5.41s, -O3=5.25s)
davidprentice 0:b608c7f02f80 231 #define READ_DELAY { RD_ACTIVE4; } //ID=0x7789
davidprentice 0:b608c7f02f80 232 #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
davidprentice 0:b608c7f02f80 233 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 234 #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 235 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
davidprentice 0:b608c7f02f80 236
davidprentice 0:b608c7f02f80 237 #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
davidprentice 0:b608c7f02f80 238 #define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
davidprentice 0:b608c7f02f80 239 #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
davidprentice 0:b608c7f02f80 240
davidprentice 0:b608c7f02f80 241 #elif defined(__AVR_ATmega328P__) && defined(USE_OPENSMART_SHIELD_PINOUT_UNO)
davidprentice 0:b608c7f02f80 242 #define RD_PORT PORTC
davidprentice 0:b608c7f02f80 243 #define RD_PIN 0
davidprentice 0:b608c7f02f80 244 #define WR_PORT PORTC
davidprentice 0:b608c7f02f80 245 #define WR_PIN 1
davidprentice 0:b608c7f02f80 246 #define CD_PORT PORTC
davidprentice 0:b608c7f02f80 247 #define CD_PIN 2
davidprentice 0:b608c7f02f80 248 #define CS_PORT PORTC
davidprentice 0:b608c7f02f80 249 #define CS_PIN 3
davidprentice 0:b608c7f02f80 250 #define RESET_PORT PORTC
davidprentice 0:b608c7f02f80 251 #define RESET_PIN 1 // n/a. so mimic WR_PIN
davidprentice 0:b608c7f02f80 252
davidprentice 0:b608c7f02f80 253 #define BMASK B00101111
davidprentice 0:b608c7f02f80 254 #define DMASK B11010000
davidprentice 0:b608c7f02f80 255
davidprentice 0:b608c7f02f80 256 #define write_8(x) { \
davidprentice 0:b608c7f02f80 257 PORTD = (PORTD & ~DMASK) | ((x) & DMASK); \
davidprentice 0:b608c7f02f80 258 PORTB = (PORTB & ~BMASK) | ((x) & BMASK);} // STROBEs are defined later
davidprentice 0:b608c7f02f80 259
davidprentice 0:b608c7f02f80 260 #define read_8() ((PIND & DMASK) | (PINB & BMASK))
davidprentice 0:b608c7f02f80 261
davidprentice 0:b608c7f02f80 262 #define setWriteDir() { DDRD |= DMASK; DDRB |= BMASK; }
davidprentice 0:b608c7f02f80 263 #define setReadDir() { DDRD &= ~DMASK; DDRB &= ~BMASK; }
davidprentice 0:b608c7f02f80 264
davidprentice 0:b608c7f02f80 265
davidprentice 0:b608c7f02f80 266 #define write8(x) { write_8(x); WR_STROBE; }
davidprentice 0:b608c7f02f80 267 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 268 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 269 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
davidprentice 0:b608c7f02f80 270
davidprentice 0:b608c7f02f80 271 #define PIN_LOW(p, b) (p) &= ~(1<<(b))
davidprentice 0:b608c7f02f80 272 #define PIN_HIGH(p, b) (p) |= (1<<(b))
davidprentice 0:b608c7f02f80 273 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
davidprentice 0:b608c7f02f80 274
davidprentice 0:b608c7f02f80 275 #elif defined(__AVR_ATmega2560__) && defined(USE_OPENSMART_SHIELD_PINOUT_MEGA)
davidprentice 0:b608c7f02f80 276 #define RD_PORT PORTF
davidprentice 0:b608c7f02f80 277 #define RD_PIN 0
davidprentice 0:b608c7f02f80 278 #define WR_PORT PORTF
davidprentice 0:b608c7f02f80 279 #define WR_PIN 1
davidprentice 0:b608c7f02f80 280 #define CD_PORT PORTF
davidprentice 0:b608c7f02f80 281 #define CD_PIN 2
davidprentice 0:b608c7f02f80 282 #define CS_PORT PORTF
davidprentice 0:b608c7f02f80 283 #define CS_PIN 3
davidprentice 0:b608c7f02f80 284 #define RESET_PORT PORTF
davidprentice 0:b608c7f02f80 285 #define RESET_PIN 1 // n/a. so mimic WR_PIN
davidprentice 0:b608c7f02f80 286
davidprentice 0:b608c7f02f80 287 #define BMASK B10110000 //D13, D11, D10
davidprentice 0:b608c7f02f80 288 #define GMASK 0x20 //D4
davidprentice 0:b608c7f02f80 289 #define HMASK 0x78 //D6, D7, D8, D9
davidprentice 0:b608c7f02f80 290
davidprentice 0:b608c7f02f80 291 #if defined(USE_BLD_BST_MEGA2560)
davidprentice 0:b608c7f02f80 292 static __attribute((always_inline)) void write_8(uint8_t val)
davidprentice 0:b608c7f02f80 293 {
davidprentice 0:b608c7f02f80 294 asm volatile("lds __tmp_reg__,0x0102" "\n\t" //PORTH
davidprentice 0:b608c7f02f80 295 "BST %0,0" "\n\t" "BLD __tmp_reg__,5" "\n\t"
davidprentice 0:b608c7f02f80 296 "BST %0,1" "\n\t" "BLD __tmp_reg__,6" "\n\t"
davidprentice 0:b608c7f02f80 297 "BST %0,6" "\n\t" "BLD __tmp_reg__,3" "\n\t"
davidprentice 0:b608c7f02f80 298 "BST %0,7" "\n\t" "BLD __tmp_reg__,4" "\n\t"
davidprentice 0:b608c7f02f80 299 "sts 0x0102,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 300 asm volatile("in __tmp_reg__,0x05" "\n\t" //PORTB
davidprentice 0:b608c7f02f80 301 "BST %0,2" "\n\t" "BLD __tmp_reg__,4" "\n\t"
davidprentice 0:b608c7f02f80 302 "BST %0,3" "\n\t" "BLD __tmp_reg__,5" "\n\t"
davidprentice 0:b608c7f02f80 303 "BST %0,5" "\n\t" "BLD __tmp_reg__,7" "\n\t"
davidprentice 0:b608c7f02f80 304 "out 0x05,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 305 asm volatile("in __tmp_reg__,0x14" "\n\t" //PORTG
davidprentice 0:b608c7f02f80 306 "BST %0,4" "\n\t" "BLD __tmp_reg__,5" "\n\t"
davidprentice 0:b608c7f02f80 307 "out 0x14,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 308 }
davidprentice 0:b608c7f02f80 309 #else
davidprentice 0:b608c7f02f80 310 #define write_8(x) { \
davidprentice 0:b608c7f02f80 311 PORTH = (PORTH&~HMASK)|(((x)&B11000000)>>3)|(((x)&B00000011)<<5); \
davidprentice 0:b608c7f02f80 312 PORTB = (PORTB&~BMASK)|(((x)&B00101100)<<2); \
davidprentice 0:b608c7f02f80 313 PORTG = (PORTG&~GMASK)|(((x)&B00010000)<<1); \
davidprentice 0:b608c7f02f80 314 }
davidprentice 0:b608c7f02f80 315 #endif
davidprentice 0:b608c7f02f80 316
davidprentice 0:b608c7f02f80 317 #define read_8()(\
davidprentice 0:b608c7f02f80 318 ((PINH & B00011000) << 3) | ((PINB & BMASK) >> 2) | \
davidprentice 0:b608c7f02f80 319 ((PING & GMASK) >> 1) | ((PINH & B01100000) >> 5) )
davidprentice 0:b608c7f02f80 320 #define setWriteDir() { DDRH |= HMASK; DDRB |= BMASK; DDRG |= GMASK; }
davidprentice 0:b608c7f02f80 321 #define setReadDir() { DDRH &= ~HMASK; DDRB &= ~BMASK; DDRG &= ~GMASK; }
davidprentice 0:b608c7f02f80 322
davidprentice 0:b608c7f02f80 323 #define write8(x) { write_8(x); WR_STROBE; }
davidprentice 0:b608c7f02f80 324 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 325 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 326 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
davidprentice 0:b608c7f02f80 327
davidprentice 0:b608c7f02f80 328 #define PIN_LOW(p, b) (p) &= ~(1<<(b))
davidprentice 0:b608c7f02f80 329 #define PIN_HIGH(p, b) (p) |= (1<<(b))
davidprentice 0:b608c7f02f80 330 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
davidprentice 0:b608c7f02f80 331
davidprentice 0:b608c7f02f80 332 #elif defined(__SAM3X8E__) && defined(USE_OPENSMART_SHIELD_PINOUT_DUE) //OPENSMART shield on DUE
davidprentice 0:b608c7f02f80 333 #warning USE_OPENSMART_SHIELD_PINOUT on DUE
davidprentice 0:b608c7f02f80 334 // configure macros for the control pins
davidprentice 0:b608c7f02f80 335 #define RD_PORT PIOA
davidprentice 0:b608c7f02f80 336 #define RD_PIN 16
davidprentice 0:b608c7f02f80 337 #define WR_PORT PIOA
davidprentice 0:b608c7f02f80 338 #define WR_PIN 24
davidprentice 0:b608c7f02f80 339 #define CD_PORT PIOA
davidprentice 0:b608c7f02f80 340 #define CD_PIN 23
davidprentice 0:b608c7f02f80 341 #define CS_PORT PIOA
davidprentice 0:b608c7f02f80 342 #define CS_PIN 22
davidprentice 0:b608c7f02f80 343 #define RESET_PORT PIOA
davidprentice 0:b608c7f02f80 344 #define RESET_PIN 24 // n/a. so mimic WR_PIN
davidprentice 0:b608c7f02f80 345 // configure macros for data bus
davidprentice 0:b608c7f02f80 346 #define BMASK (1<<27)
davidprentice 0:b608c7f02f80 347 #define CMASK (0x12F << 21)
davidprentice 0:b608c7f02f80 348 #define DMASK (1<<7)
davidprentice 0:b608c7f02f80 349 #define write_8(x) { PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; PIOD->PIO_CODR = DMASK; \
davidprentice 0:b608c7f02f80 350 PIOC->PIO_SODR = (((x) & (1<<0)) << 22); \
davidprentice 0:b608c7f02f80 351 PIOC->PIO_SODR = (((x) & (1<<1)) << 20); \
davidprentice 0:b608c7f02f80 352 PIOC->PIO_SODR = (((x) & (1<<2)) << 27); \
davidprentice 0:b608c7f02f80 353 PIOD->PIO_SODR = (((x) & (1<<3)) << 4); \
davidprentice 0:b608c7f02f80 354 PIOC->PIO_SODR = (((x) & (1<<4)) << 22); \
davidprentice 0:b608c7f02f80 355 PIOB->PIO_SODR = (((x) & (1<<5)) << 22); \
davidprentice 0:b608c7f02f80 356 PIOC->PIO_SODR = (((x) & (1<<6)) << 18); \
davidprentice 0:b608c7f02f80 357 PIOC->PIO_SODR = (((x) & (1<<7)) << 16); \
davidprentice 0:b608c7f02f80 358 }
davidprentice 0:b608c7f02f80 359
davidprentice 0:b608c7f02f80 360 #define read_8() ( ((PIOC->PIO_PDSR & (1<<22)) >> 22)\
davidprentice 0:b608c7f02f80 361 | ((PIOC->PIO_PDSR & (1<<21)) >> 20)\
davidprentice 0:b608c7f02f80 362 | ((PIOC->PIO_PDSR & (1<<29)) >> 27)\
davidprentice 0:b608c7f02f80 363 | ((PIOD->PIO_PDSR & (1<<7)) >> 4)\
davidprentice 0:b608c7f02f80 364 | ((PIOC->PIO_PDSR & (1<<26)) >> 22)\
davidprentice 0:b608c7f02f80 365 | ((PIOB->PIO_PDSR & (1<<27)) >> 22)\
davidprentice 0:b608c7f02f80 366 | ((PIOC->PIO_PDSR & (1<<24)) >> 18)\
davidprentice 0:b608c7f02f80 367 | ((PIOC->PIO_PDSR & (1<<23)) >> 16)\
davidprentice 0:b608c7f02f80 368 )
davidprentice 0:b608c7f02f80 369 #define setWriteDir() { PIOB->PIO_OER = BMASK; PIOC->PIO_OER = CMASK; PIOD->PIO_OER = DMASK; }
davidprentice 0:b608c7f02f80 370 #define setReadDir() { \
davidprentice 0:b608c7f02f80 371 PMC->PMC_PCER0 = (1 << ID_PIOB)|(1 << ID_PIOC)|(1 << ID_PIOD);\
davidprentice 0:b608c7f02f80 372 PIOB->PIO_ODR = BMASK; PIOC->PIO_ODR = CMASK; PIOD->PIO_ODR = DMASK;\
davidprentice 0:b608c7f02f80 373 }
davidprentice 0:b608c7f02f80 374 #define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; }
davidprentice 0:b608c7f02f80 375 //#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; WR_IDLE; }
davidprentice 0:b608c7f02f80 376 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 377 #define READ_8(dst) { RD_STROBE; RD_ACTIVE; dst = read_8(); RD_IDLE; RD_IDLE; }
davidprentice 0:b608c7f02f80 378 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
davidprentice 0:b608c7f02f80 379 // Shield Control macros.
davidprentice 0:b608c7f02f80 380 #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
davidprentice 0:b608c7f02f80 381 #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
davidprentice 0:b608c7f02f80 382 #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
davidprentice 0:b608c7f02f80 383
davidprentice 0:b608c7f02f80 384 #elif defined(__AVR_ATmega2560__) && defined(USE_BLD_BST_MEGA2560) //regular UNO shield on MEGA2560 using BLD/BST
davidprentice 0:b608c7f02f80 385 #warning regular UNO shield on MEGA2560 using BLD/BST
davidprentice 0:b608c7f02f80 386 #define RD_PORT PORTF
davidprentice 0:b608c7f02f80 387 #define RD_PIN 0
davidprentice 0:b608c7f02f80 388 #define WR_PORT PORTF
davidprentice 0:b608c7f02f80 389 #define WR_PIN 1
davidprentice 0:b608c7f02f80 390 #define CD_PORT PORTF
davidprentice 0:b608c7f02f80 391 #define CD_PIN 2
davidprentice 0:b608c7f02f80 392 #define CS_PORT PORTF
davidprentice 0:b608c7f02f80 393 #define CS_PIN 3
davidprentice 0:b608c7f02f80 394 #define RESET_PORT PORTF
davidprentice 0:b608c7f02f80 395 #define RESET_PIN 4
davidprentice 0:b608c7f02f80 396
davidprentice 0:b608c7f02f80 397 #define EMASK 0x38
davidprentice 0:b608c7f02f80 398 #define GMASK 0x20
davidprentice 0:b608c7f02f80 399 #define HMASK 0x78
davidprentice 0:b608c7f02f80 400 static __attribute((always_inline)) void write_8(uint8_t val)
davidprentice 0:b608c7f02f80 401 {
davidprentice 0:b608c7f02f80 402 asm volatile("lds __tmp_reg__,0x0102" "\n\t"
davidprentice 0:b608c7f02f80 403 "BST %0,0" "\n\t" "BLD __tmp_reg__,5" "\n\t"
davidprentice 0:b608c7f02f80 404 "BST %0,1" "\n\t" "BLD __tmp_reg__,6" "\n\t"
davidprentice 0:b608c7f02f80 405 "BST %0,6" "\n\t" "BLD __tmp_reg__,3" "\n\t"
davidprentice 0:b608c7f02f80 406 "BST %0,7" "\n\t" "BLD __tmp_reg__,4" "\n\t"
davidprentice 0:b608c7f02f80 407 "sts 0x0102,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 408 asm volatile("in __tmp_reg__,0x0E" "\n\t"
davidprentice 0:b608c7f02f80 409 "BST %0,2" "\n\t" "BLD __tmp_reg__,4" "\n\t"
davidprentice 0:b608c7f02f80 410 "BST %0,3" "\n\t" "BLD __tmp_reg__,5" "\n\t"
davidprentice 0:b608c7f02f80 411 "BST %0,5" "\n\t" "BLD __tmp_reg__,3" "\n\t"
davidprentice 0:b608c7f02f80 412 "out 0x0E,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 413 asm volatile("in __tmp_reg__,0x14" "\n\t"
davidprentice 0:b608c7f02f80 414 "BST %0,4" "\n\t" "BLD __tmp_reg__,5" "\n\t"
davidprentice 0:b608c7f02f80 415 "out 0x14,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 416 }
davidprentice 0:b608c7f02f80 417
davidprentice 0:b608c7f02f80 418 #define read_8() ( ((PINH & (3<<5)) >> 5)\
davidprentice 0:b608c7f02f80 419 | ((PINE & (3<<4)) >> 2)\
davidprentice 0:b608c7f02f80 420 | ((PING & (1<<5)) >> 1)\
davidprentice 0:b608c7f02f80 421 | ((PINE & (1<<3)) << 2)\
davidprentice 0:b608c7f02f80 422 | ((PINH & (3<<3)) << 3)\
davidprentice 0:b608c7f02f80 423 )
davidprentice 0:b608c7f02f80 424 #define setWriteDir() { DDRH |= HMASK; DDRG |= GMASK; DDRE |= EMASK; }
davidprentice 0:b608c7f02f80 425 #define setReadDir() { DDRH &= ~HMASK; DDRG &= ~GMASK; DDRE &= ~EMASK; }
davidprentice 0:b608c7f02f80 426 #define write8(x) { write_8(x); WR_STROBE; }
davidprentice 0:b608c7f02f80 427 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 428 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 429 #define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 430
davidprentice 0:b608c7f02f80 431 #define PIN_LOW(p, b) (p) &= ~(1<<(b))
davidprentice 0:b608c7f02f80 432 #define PIN_HIGH(p, b) (p) |= (1<<(b))
davidprentice 0:b608c7f02f80 433 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
davidprentice 0:b608c7f02f80 434
davidprentice 0:b608c7f02f80 435 #elif defined(__AVR_ATmega2560__) && defined(USE_MEGA_16BIT_SHIELD)
davidprentice 0:b608c7f02f80 436 #warning USE_MEGA_16BIT_SHIELD
davidprentice 0:b608c7f02f80 437 #define USES_16BIT_BUS
davidprentice 0:b608c7f02f80 438 #define RD_PORT PORTL
davidprentice 0:b608c7f02f80 439 #define RD_PIN 6 //PL6 (D43). Graham has PA15 (D24) on Due Shield
davidprentice 0:b608c7f02f80 440 #define WR_PORT PORTG
davidprentice 0:b608c7f02f80 441 #define WR_PIN 2 //D39 CTE
davidprentice 0:b608c7f02f80 442 #define CD_PORT PORTD
davidprentice 0:b608c7f02f80 443 #define CD_PIN 7 //D38 CTE
davidprentice 0:b608c7f02f80 444 #define CS_PORT PORTG
davidprentice 0:b608c7f02f80 445 #define CS_PIN 1 //D40 CTE
davidprentice 0:b608c7f02f80 446 #define RESET_PORT PORTG
davidprentice 0:b608c7f02f80 447 #define RESET_PIN 0 //D41 CTE
davidprentice 0:b608c7f02f80 448
davidprentice 0:b608c7f02f80 449 #define write_8(x) { PORTC = x; }
davidprentice 0:b608c7f02f80 450 #define write_16(x) { PORTA = (x) >> 8; PORTC = x; }
davidprentice 0:b608c7f02f80 451
davidprentice 0:b608c7f02f80 452 #define read_16() ( (PINA<<8) | (PINC) )
davidprentice 0:b608c7f02f80 453 #define setWriteDir() { DDRC = 0xFF; DDRA = 0xff; }
davidprentice 0:b608c7f02f80 454 #define setReadDir() { DDRC = 0x00; DDRA = 0x00; }
davidprentice 0:b608c7f02f80 455 //#define write8(x) { write_8(x); WR_STROBE; }
davidprentice 0:b608c7f02f80 456 #define write8(x) { write16((x) & 0xFF); }
davidprentice 0:b608c7f02f80 457 #define write16(x) { write_16(x); WR_ACTIVE; WR_STROBE; }
davidprentice 0:b608c7f02f80 458 #define READ_16(dst) { RD_STROBE; dst = read_16(); RD_IDLE; }
davidprentice 0:b608c7f02f80 459 #define READ_8(dst) { READ_16(dst); dst &= 0x00FF; }
davidprentice 0:b608c7f02f80 460
davidprentice 0:b608c7f02f80 461 #define PIN_LOW(p, b) (p) &= ~(1<<(b))
davidprentice 0:b608c7f02f80 462 #define PIN_HIGH(p, b) (p) |= (1<<(b))
davidprentice 0:b608c7f02f80 463 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
davidprentice 0:b608c7f02f80 464
davidprentice 0:b608c7f02f80 465 #elif defined(__AVR_ATmega2560__) && defined(USE_MEGA_8BIT_SHIELD)
davidprentice 0:b608c7f02f80 466 #warning USE_MEGA_8BIT_SHIELD for vagos21
davidprentice 0:b608c7f02f80 467 #define RD_PORT PORTL
davidprentice 0:b608c7f02f80 468 #define RD_PIN 6 //PL6 (D43). Graham has PA15 (D24) on Due Shield
davidprentice 0:b608c7f02f80 469 #define WR_PORT PORTG
davidprentice 0:b608c7f02f80 470 #define WR_PIN 2 //D39 CTE
davidprentice 0:b608c7f02f80 471 #define CD_PORT PORTD
davidprentice 0:b608c7f02f80 472 #define CD_PIN 7 //D38 CTE
davidprentice 0:b608c7f02f80 473 #define CS_PORT PORTG
davidprentice 0:b608c7f02f80 474 #define CS_PIN 1 //D40 CTE
davidprentice 0:b608c7f02f80 475 #define RESET_PORT PORTG
davidprentice 0:b608c7f02f80 476 #define RESET_PIN 0 //D41 CTE
davidprentice 0:b608c7f02f80 477
davidprentice 0:b608c7f02f80 478 #define write_8(x) { PORTA = x;}
davidprentice 0:b608c7f02f80 479
davidprentice 0:b608c7f02f80 480 #define read_8() ( PINA )
davidprentice 0:b608c7f02f80 481 #define setWriteDir() { DDRA = 0xFF; }
davidprentice 0:b608c7f02f80 482 #define setReadDir() { DDRA = 0x00; }
davidprentice 0:b608c7f02f80 483 #define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; } // HX8357-D is slower
davidprentice 0:b608c7f02f80 484 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 485 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 486 #define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 487
davidprentice 0:b608c7f02f80 488 #define PIN_LOW(p, b) (p) &= ~(1<<(b))
davidprentice 0:b608c7f02f80 489 #define PIN_HIGH(p, b) (p) |= (1<<(b))
davidprentice 0:b608c7f02f80 490 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
davidprentice 0:b608c7f02f80 491
davidprentice 0:b608c7f02f80 492 #elif defined(__AVR_ATmega2560__) && defined(USE_MEGA_8BIT_PROTOSHIELD)
davidprentice 0:b608c7f02f80 493 #warning USE_MEGA_8BIT_PROTOSHIELD
davidprentice 0:b608c7f02f80 494 #define RD_PORT PORTF
davidprentice 0:b608c7f02f80 495 #define RD_PIN 0
davidprentice 0:b608c7f02f80 496 #define WR_PORT PORTF
davidprentice 0:b608c7f02f80 497 #define WR_PIN 1
davidprentice 0:b608c7f02f80 498 #define CD_PORT PORTF
davidprentice 0:b608c7f02f80 499 #define CD_PIN 2
davidprentice 0:b608c7f02f80 500 #define CS_PORT PORTF
davidprentice 0:b608c7f02f80 501 #define CS_PIN 3
davidprentice 0:b608c7f02f80 502 #define RESET_PORT PORTF
davidprentice 0:b608c7f02f80 503 #define RESET_PIN 4
davidprentice 0:b608c7f02f80 504
davidprentice 0:b608c7f02f80 505 #define write_8(x) { PORTA = x;}
davidprentice 0:b608c7f02f80 506
davidprentice 0:b608c7f02f80 507 #define read_8() ( PINA )
davidprentice 0:b608c7f02f80 508 #define setWriteDir() { DDRA = 0xFF; }
davidprentice 0:b608c7f02f80 509 #define setReadDir() { DDRA = 0x00; }
davidprentice 0:b608c7f02f80 510 #define write8(x) { write_8(x); WR_STROBE; }
davidprentice 0:b608c7f02f80 511 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 512 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 513 #define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 514
davidprentice 0:b608c7f02f80 515 #define PIN_LOW(p, b) (p) &= ~(1<<(b))
davidprentice 0:b608c7f02f80 516 #define PIN_HIGH(p, b) (p) |= (1<<(b))
davidprentice 0:b608c7f02f80 517 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
davidprentice 0:b608c7f02f80 518
davidprentice 0:b608c7f02f80 519 #elif defined(__AVR_ATmega32U4__) && defined(USE_BLD_BST_MEGA32U4) //regular UNO shield on Leonardo using BST/BLD
davidprentice 0:b608c7f02f80 520 #warning regular UNO shield on Leonardo using BST/BLD
davidprentice 0:b608c7f02f80 521 #define RD_PORT PORTF
davidprentice 0:b608c7f02f80 522 #define RD_PIN 7
davidprentice 0:b608c7f02f80 523 #define WR_PORT PORTF
davidprentice 0:b608c7f02f80 524 #define WR_PIN 6
davidprentice 0:b608c7f02f80 525 #define CD_PORT PORTF
davidprentice 0:b608c7f02f80 526 #define CD_PIN 5
davidprentice 0:b608c7f02f80 527 #define CS_PORT PORTF
davidprentice 0:b608c7f02f80 528 #define CS_PIN 4
davidprentice 0:b608c7f02f80 529 #define RESET_PORT PORTF
davidprentice 0:b608c7f02f80 530 #define RESET_PIN 1
davidprentice 0:b608c7f02f80 531
davidprentice 0:b608c7f02f80 532 #define BMASK (3<<4)
davidprentice 0:b608c7f02f80 533 #define CMASK (1<<6)
davidprentice 0:b608c7f02f80 534 #define DMASK ((1<<7)|(1<<4)|(3<<0))
davidprentice 0:b608c7f02f80 535 #define EMASK (1<<6)
davidprentice 0:b608c7f02f80 536 static __attribute((always_inline)) void write_8(uint8_t val)
davidprentice 0:b608c7f02f80 537 {
davidprentice 0:b608c7f02f80 538 asm volatile("in __tmp_reg__,0x05" "\n\t"
davidprentice 0:b608c7f02f80 539 "BST %0,0" "\n\t" "BLD __tmp_reg__,4" "\n\t"
davidprentice 0:b608c7f02f80 540 "BST %0,1" "\n\t" "BLD __tmp_reg__,5" "\n\t"
davidprentice 0:b608c7f02f80 541 "out 0x05,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 542 asm volatile("in __tmp_reg__,0x0B" "\n\t"
davidprentice 0:b608c7f02f80 543 "BST %0,2" "\n\t" "BLD __tmp_reg__,1" "\n\t"
davidprentice 0:b608c7f02f80 544 "BST %0,3" "\n\t" "BLD __tmp_reg__,0" "\n\t"
davidprentice 0:b608c7f02f80 545 "BST %0,4" "\n\t" "BLD __tmp_reg__,4" "\n\t"
davidprentice 0:b608c7f02f80 546 "BST %0,6" "\n\t" "BLD __tmp_reg__,7" "\n\t"
davidprentice 0:b608c7f02f80 547 "out 0x0B,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 548 asm volatile("in __tmp_reg__,0x08" "\n\t"
davidprentice 0:b608c7f02f80 549 "BST %0,5" "\n\t" "BLD __tmp_reg__,6" "\n\t"
davidprentice 0:b608c7f02f80 550 "out 0x08,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 551 asm volatile("in __tmp_reg__,0x0E" "\n\t"
davidprentice 0:b608c7f02f80 552 "BST %0,7" "\n\t" "BLD __tmp_reg__,6" "\n\t"
davidprentice 0:b608c7f02f80 553 "out 0x0E,__tmp_reg__" : : "a" (val));
davidprentice 0:b608c7f02f80 554 }
davidprentice 0:b608c7f02f80 555 #define read_8() ( ((PINB & (3<<4)) >> 4)\
davidprentice 0:b608c7f02f80 556 | ((PIND & (1<<1)) << 1)\
davidprentice 0:b608c7f02f80 557 | ((PIND & (1<<0)) << 3)\
davidprentice 0:b608c7f02f80 558 | ((PIND & (1<<4)) >> 0)\
davidprentice 0:b608c7f02f80 559 | ((PINC & (1<<6)) >> 1)\
davidprentice 0:b608c7f02f80 560 | ((PIND & (1<<7)) >> 1)\
davidprentice 0:b608c7f02f80 561 | ((PINE & (1<<6)) << 1)\
davidprentice 0:b608c7f02f80 562 )
davidprentice 0:b608c7f02f80 563 #define setWriteDir() { DDRB |= BMASK; DDRC |= CMASK; DDRD |= DMASK; DDRE |= EMASK; }
davidprentice 0:b608c7f02f80 564 #define setReadDir() { DDRB &= ~BMASK; DDRC &= ~CMASK; DDRD &= ~DMASK; DDRE &= ~EMASK; }
davidprentice 0:b608c7f02f80 565 #define write8(x) { write_8(x); WR_STROBE; }
davidprentice 0:b608c7f02f80 566 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 567 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 568 #define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 569
davidprentice 0:b608c7f02f80 570 #define PIN_LOW(p, b) (p) &= ~(1<<(b))
davidprentice 0:b608c7f02f80 571 #define PIN_HIGH(p, b) (p) |= (1<<(b))
davidprentice 0:b608c7f02f80 572 #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
davidprentice 0:b608c7f02f80 573
davidprentice 0:b608c7f02f80 574 #elif defined(__SAM3X8E__) && defined(USE_DUE_8BIT_PROTOSHIELD) //regular UNO shield on DUE
davidprentice 0:b608c7f02f80 575 #warning USE_DUE_8BIT_PROTOSHIELD
davidprentice 0:b608c7f02f80 576 // configure macros for the control pins
davidprentice 0:b608c7f02f80 577 #define RD_PORT PIOA
davidprentice 0:b608c7f02f80 578 #define RD_PIN 16 //A0
davidprentice 0:b608c7f02f80 579 #define WR_PORT PIOA
davidprentice 0:b608c7f02f80 580 #define WR_PIN 24 //A1
davidprentice 0:b608c7f02f80 581 #define CD_PORT PIOA
davidprentice 0:b608c7f02f80 582 #define CD_PIN 23 //A2
davidprentice 0:b608c7f02f80 583 #define CS_PORT PIOA
davidprentice 0:b608c7f02f80 584 #define CS_PIN 22 //A3
davidprentice 0:b608c7f02f80 585 #define RESET_PORT PIOA
davidprentice 0:b608c7f02f80 586 #define RESET_PIN 6 //A4
davidprentice 0:b608c7f02f80 587 // configure macros for data bus
davidprentice 0:b608c7f02f80 588 #define DMASK (0xFF<<0)
davidprentice 0:b608c7f02f80 589 #define write_8(x) { PIOD->PIO_CODR = DMASK; PIOD->PIO_SODR = x; }
davidprentice 0:b608c7f02f80 590
davidprentice 0:b608c7f02f80 591 #define read_8() ( PIOD->PIO_PDSR & DMASK)
davidprentice 0:b608c7f02f80 592 #define setWriteDir() { PIOD->PIO_OER = DMASK; PIOD->PIO_PER = DMASK; }
davidprentice 0:b608c7f02f80 593 #define setReadDir() { PMC->PMC_PCER0 = (1 << ID_PIOD); PIOD->PIO_ODR = DMASK;}
davidprentice 0:b608c7f02f80 594 #define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; WR_IDLE; WR_IDLE; }
davidprentice 0:b608c7f02f80 595 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 596 #define READ_8(dst) { RD_STROBE; RD_ACTIVE4; dst = read_8(); RD_IDLE; RD_IDLE; RD_IDLE; }
davidprentice 0:b608c7f02f80 597 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
davidprentice 0:b608c7f02f80 598 // Shield Control macros.
davidprentice 0:b608c7f02f80 599 #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
davidprentice 0:b608c7f02f80 600 #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
davidprentice 0:b608c7f02f80 601 #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
davidprentice 0:b608c7f02f80 602
davidprentice 0:b608c7f02f80 603 #elif defined(__SAM3X8E__) && defined(USE_DUE_16BIT_SHIELD) //regular CTE shield on DUE
davidprentice 0:b608c7f02f80 604 #warning USE_DUE_16BIT_SHIELD
davidprentice 0:b608c7f02f80 605 #define USES_16BIT_BUS
davidprentice 0:b608c7f02f80 606 // configure macros for the control pins
davidprentice 0:b608c7f02f80 607 #define RD_PORT PIOA
davidprentice 0:b608c7f02f80 608 #define RD_PIN 15 //D24 Graham
davidprentice 0:b608c7f02f80 609 #define WR_PORT PIOD
davidprentice 0:b608c7f02f80 610 #define WR_PIN 1 //D26
davidprentice 0:b608c7f02f80 611 #define CD_PORT PIOD
davidprentice 0:b608c7f02f80 612 #define CD_PIN 0 //D25
davidprentice 0:b608c7f02f80 613 #define CS_PORT PIOD
davidprentice 0:b608c7f02f80 614 #define CS_PIN 2 //D27
davidprentice 0:b608c7f02f80 615 #define RESET_PORT PIOD
davidprentice 0:b608c7f02f80 616 #define RESET_PIN 3 //D28
davidprentice 0:b608c7f02f80 617 // configure macros for data bus
davidprentice 0:b608c7f02f80 618 // DB0..DB7 on PIOC1..PIOC8, DB8..DB15 on PIOC12..PIOC19
davidprentice 0:b608c7f02f80 619 //
davidprentice 0:b608c7f02f80 620 #define CMASKH (0xFF00<<4)
davidprentice 0:b608c7f02f80 621 #define CMASKL (0x00FF<<1)
davidprentice 0:b608c7f02f80 622 #define CMASK (CMASKH | CMASKL)
davidprentice 0:b608c7f02f80 623 #define write_8(x) { PIOC->PIO_CODR = CMASKL; PIOC->PIO_SODR = (((x)&0x00FF)<<1); }
davidprentice 0:b608c7f02f80 624 #define write_16(x) { PIOC->PIO_CODR = CMASK; \
davidprentice 0:b608c7f02f80 625 PIOC->PIO_SODR = (((x)&0x00FF)<<1)|(((x)&0xFF00)<<4); }
davidprentice 0:b608c7f02f80 626 #define read_16() (((PIOC->PIO_PDSR & CMASKH)>>4)|((PIOC->PIO_PDSR & CMASKL)>>1) )
davidprentice 0:b608c7f02f80 627 #define read_8() (read_16() & 0xFF)
davidprentice 0:b608c7f02f80 628 #define setWriteDir() { PIOC->PIO_OER = CMASK; PIOC->PIO_PER = CMASK; }
davidprentice 0:b608c7f02f80 629 #define setReadDir() { PMC->PMC_PCER0 = (1 << ID_PIOC); PIOC->PIO_ODR = CMASK; }
davidprentice 0:b608c7f02f80 630 #define write8(x) { write16(x & 0xFF); }
davidprentice 0:b608c7f02f80 631 #define write16(x) { write_16(x); WR_ACTIVE; WR_STROBE; WR_IDLE; WR_IDLE; }
davidprentice 0:b608c7f02f80 632 #define READ_16(dst) { RD_STROBE; RD_ACTIVE4; dst = read_16(); RD_IDLE; RD_IDLE; RD_IDLE; }
davidprentice 0:b608c7f02f80 633 #define READ_8(dst) { READ_16(dst); dst &= 0xFF; }
davidprentice 0:b608c7f02f80 634
davidprentice 0:b608c7f02f80 635 // Shield Control macros.
davidprentice 0:b608c7f02f80 636 #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
davidprentice 0:b608c7f02f80 637 #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
davidprentice 0:b608c7f02f80 638 #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
davidprentice 0:b608c7f02f80 639
davidprentice 0:b608c7f02f80 640 #elif defined(__SAM3X8E__) && defined(USE_ELECHOUSE_DUE_16BIT_SHIELD) //ELECHOUSE_DUE shield on DUE
davidprentice 0:b608c7f02f80 641 #warning USE_ELECHOUSE_DUE_16BIT_SHIELD
davidprentice 0:b608c7f02f80 642 #define USES_16BIT_BUS
davidprentice 0:b608c7f02f80 643 // configure macros for the control pins
davidprentice 0:b608c7f02f80 644 #define RD_PORT PIOA
davidprentice 0:b608c7f02f80 645 #define RD_PIN 15 //D24 Graham
davidprentice 0:b608c7f02f80 646 #define WR_PORT PIOA
davidprentice 0:b608c7f02f80 647 #define WR_PIN 14 //D23
davidprentice 0:b608c7f02f80 648 #define CD_PORT PIOB
davidprentice 0:b608c7f02f80 649 #define CD_PIN 26 //D22
davidprentice 0:b608c7f02f80 650 #define CS_PORT PIOA
davidprentice 0:b608c7f02f80 651 #define CS_PIN 7 //D31
davidprentice 0:b608c7f02f80 652 #define RESET_PORT PIOC
davidprentice 0:b608c7f02f80 653 #define RESET_PIN 1 //D33
davidprentice 0:b608c7f02f80 654 // configure macros for data bus
davidprentice 0:b608c7f02f80 655 // DB0..DB7 on PIOC2..PIOC9, DB8..DB15 on PIOC12..PIOC19
davidprentice 0:b608c7f02f80 656 //
davidprentice 0:b608c7f02f80 657 #define CMASKH (0xFF00<<4)
davidprentice 0:b608c7f02f80 658 #define CMASKL (0x00FF<<2)
davidprentice 0:b608c7f02f80 659 #define CMASK (CMASKH | CMASKL)
davidprentice 0:b608c7f02f80 660 #define write_8(x) { PIOC->PIO_CODR = CMASKL; PIOC->PIO_SODR = (((x)&0x00FF)<<2); }
davidprentice 0:b608c7f02f80 661 #define write_16(x) { PIOC->PIO_CODR = CMASK; \
davidprentice 0:b608c7f02f80 662 PIOC->PIO_SODR = (((x)&0x00FF)<<2)|(((x)&0xFF00)<<4); }
davidprentice 0:b608c7f02f80 663 #define read_16() (((PIOC->PIO_PDSR & CMASKH)>>4)|((PIOC->PIO_PDSR & CMASKL)>>2) )
davidprentice 0:b608c7f02f80 664 #define read_8() (read_16() & 0xFF)
davidprentice 0:b608c7f02f80 665 #define setWriteDir() { PIOC->PIO_OER = CMASK; PIOC->PIO_PER = CMASK; }
davidprentice 0:b608c7f02f80 666 #define setReadDir() { PMC->PMC_PCER0 = (1 << ID_PIOC); PIOC->PIO_ODR = CMASK; }
davidprentice 0:b608c7f02f80 667 #define write8(x) { write16(x & 0xFF); }
davidprentice 0:b608c7f02f80 668 #define write16(x) { write_16(x); WR_ACTIVE; WR_STROBE; WR_IDLE; WR_IDLE; }
davidprentice 0:b608c7f02f80 669 #define READ_16(dst) { RD_STROBE; RD_ACTIVE4; dst = read_16(); RD_IDLE; RD_IDLE; RD_IDLE; }
davidprentice 0:b608c7f02f80 670 #define READ_8(dst) { READ_16(dst); dst &= 0xFF; }
davidprentice 0:b608c7f02f80 671
davidprentice 0:b608c7f02f80 672 // Shield Control macros.
davidprentice 0:b608c7f02f80 673 #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
davidprentice 0:b608c7f02f80 674 #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
davidprentice 0:b608c7f02f80 675 #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
davidprentice 0:b608c7f02f80 676
davidprentice 0:b608c7f02f80 677 #elif defined(__SAM3X8E__) && defined(USE_MEGA_16BIT_SHIELD) //regular MEGA shield on DUE
davidprentice 0:b608c7f02f80 678 #warning USE_MEGA_16BIT_SHIELD
davidprentice 0:b608c7f02f80 679 #define USES_16BIT_BUS
davidprentice 0:b608c7f02f80 680 // configure macros for the control pins
davidprentice 0:b608c7f02f80 681 #define RD_PORT PIOA
davidprentice 0:b608c7f02f80 682 #define RD_PIN 20 //D43
davidprentice 0:b608c7f02f80 683 #define WR_PORT PIOC
davidprentice 0:b608c7f02f80 684 #define WR_PIN 7 //D39
davidprentice 0:b608c7f02f80 685 #define CD_PORT PIOC
davidprentice 0:b608c7f02f80 686 #define CD_PIN 6 //D38
davidprentice 0:b608c7f02f80 687 #define CS_PORT PIOC
davidprentice 0:b608c7f02f80 688 #define CS_PIN 8 //D40
davidprentice 0:b608c7f02f80 689 #define RESET_PORT PIOC
davidprentice 0:b608c7f02f80 690 #define RESET_PIN 9 //D41
davidprentice 0:b608c7f02f80 691 // configure macros for data bus
davidprentice 0:b608c7f02f80 692 //
davidprentice 0:b608c7f02f80 693 #define AMASK ((1<<7)|(3<<14)) //PA7, PA14-PA15
davidprentice 0:b608c7f02f80 694 #define BMASK (1<<26) //PB26
davidprentice 0:b608c7f02f80 695 #define CMASK (31<<1) //PC1-PC5
davidprentice 0:b608c7f02f80 696 #define DMASK ((15<<0)|(1<<6)|(3<<9)) //PD0-PD3, PD6, PD9-PD10
davidprentice 0:b608c7f02f80 697
davidprentice 0:b608c7f02f80 698 #define write_16(x) { PIOA->PIO_CODR = AMASK; PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; PIOD->PIO_CODR = DMASK; \
davidprentice 0:b608c7f02f80 699 PIOA->PIO_SODR = (((x)&(1<<6))<<1)|(((x)&(3<<9))<<5); \
davidprentice 0:b608c7f02f80 700 PIOB->PIO_SODR = (((x)&(1<<8))<<18); \
davidprentice 0:b608c7f02f80 701 PIOC->PIO_SODR = (((x)&(1<<0))<<5); \
davidprentice 0:b608c7f02f80 702 PIOC->PIO_SODR = (((x)&(1<<1))<<3); \
davidprentice 0:b608c7f02f80 703 PIOC->PIO_SODR = (((x)&(1<<2))<<1); \
davidprentice 0:b608c7f02f80 704 PIOC->PIO_SODR = (((x)&(1<<3))>>1); \
davidprentice 0:b608c7f02f80 705 PIOC->PIO_SODR = (((x)&(1<<4))>>3); \
davidprentice 0:b608c7f02f80 706 PIOD->PIO_SODR = (((x)&(1<<7))<<2)|(((x)&(1<<5))<<5)|(((x)&(15<<11))>>11)|(((x)&(1<<15))>>9); \
davidprentice 0:b608c7f02f80 707 }
davidprentice 0:b608c7f02f80 708
davidprentice 0:b608c7f02f80 709 /*
davidprentice 0:b608c7f02f80 710 #define write_16(VL) { PIOA->PIO_CODR = AMASK; PIOC->PIO_CODR = CMASK; PIOD->PIO_CODR = DMASK; \
davidprentice 0:b608c7f02f80 711 REG_PIOA_SODR=((((VL)>>8) & 0x06)<<13) | ((VL & 0x40)<<1);\
davidprentice 0:b608c7f02f80 712 if ((VL)&(1<<8)) REG_PIOB_SODR=(1<<26); else REG_PIOB_CODR=(1<<26);\
davidprentice 0:b608c7f02f80 713 REG_PIOC_SODR=((VL & 0x01)<<5) | ((VL & 0x02)<<3) | ((VL & 0x04)<<1) | ((VL & 0x08)>>1) | ((VL & 0x10)>>3);\
davidprentice 0:b608c7f02f80 714 REG_PIOD_SODR=((((VL)>>8) & 0x78)>>3) | ((((VL)>>8) & 0x80)>>1) | ((VL & 0x20)<<5) | ((VL & 0x80)<<2);\
davidprentice 0:b608c7f02f80 715 }
davidprentice 0:b608c7f02f80 716 */
davidprentice 0:b608c7f02f80 717 #define read_16() ( 0\
davidprentice 0:b608c7f02f80 718 |((PIOC->PIO_PDSR & (1<<5))>>5)\
davidprentice 0:b608c7f02f80 719 |((PIOC->PIO_PDSR & (1<<4))>>3)\
davidprentice 0:b608c7f02f80 720 |((PIOC->PIO_PDSR & (1<<3))>>1)\
davidprentice 0:b608c7f02f80 721 |((PIOC->PIO_PDSR & (1<<2))<<1)\
davidprentice 0:b608c7f02f80 722 |((PIOC->PIO_PDSR & (1<<1))<<3)\
davidprentice 0:b608c7f02f80 723 |((PIOD->PIO_PDSR & (1<<10))>>5)\
davidprentice 0:b608c7f02f80 724 |((PIOA->PIO_PDSR & (1<<7))>>1)\
davidprentice 0:b608c7f02f80 725 |((PIOD->PIO_PDSR & (1<<9))>>2)\
davidprentice 0:b608c7f02f80 726 |((PIOB->PIO_PDSR & (1<<26))>>18)\
davidprentice 0:b608c7f02f80 727 |((PIOA->PIO_PDSR & (3<<14))>>5)\
davidprentice 0:b608c7f02f80 728 |((PIOD->PIO_PDSR & (15<<0))<<11)\
davidprentice 0:b608c7f02f80 729 |((PIOD->PIO_PDSR & (1<<6))<<9)\
davidprentice 0:b608c7f02f80 730 )
davidprentice 0:b608c7f02f80 731 #define read_8() (read_16() & 0xFF)
davidprentice 0:b608c7f02f80 732 #define setWriteDir() {\
davidprentice 0:b608c7f02f80 733 PIOA->PIO_OER = AMASK; PIOA->PIO_PER = AMASK; \
davidprentice 0:b608c7f02f80 734 PIOB->PIO_OER = BMASK; PIOB->PIO_PER = BMASK; \
davidprentice 0:b608c7f02f80 735 PIOC->PIO_OER = CMASK; PIOC->PIO_PER = CMASK; \
davidprentice 0:b608c7f02f80 736 PIOD->PIO_OER = DMASK; PIOD->PIO_PER = DMASK; \
davidprentice 0:b608c7f02f80 737 }
davidprentice 0:b608c7f02f80 738 #define setReadDir() { \
davidprentice 0:b608c7f02f80 739 PMC->PMC_PCER0 = (1 << ID_PIOA)|(1 << ID_PIOB)|(1 << ID_PIOC)|(1 << ID_PIOD); \
davidprentice 0:b608c7f02f80 740 PIOA->PIO_ODR = AMASK; \
davidprentice 0:b608c7f02f80 741 PIOB->PIO_ODR = BMASK; \
davidprentice 0:b608c7f02f80 742 PIOC->PIO_ODR = CMASK; \
davidprentice 0:b608c7f02f80 743 PIOD->PIO_ODR = DMASK; \
davidprentice 0:b608c7f02f80 744 }
davidprentice 0:b608c7f02f80 745 #define write8(x) { write16(x & 0xFF); }
davidprentice 0:b608c7f02f80 746 // ILI9486 is slower than ILI9481
davidprentice 0:b608c7f02f80 747 #define write16(x) { write_16(x); WR_ACTIVE8; WR_STROBE; WR_IDLE4;}
davidprentice 0:b608c7f02f80 748 #define READ_16(dst) { RD_STROBE; RD_ACTIVE4; dst = read_16(); RD_IDLE; RD_IDLE; RD_IDLE; }
davidprentice 0:b608c7f02f80 749 #define READ_8(dst) { READ_16(dst); dst &= 0xFF; }
davidprentice 0:b608c7f02f80 750
davidprentice 0:b608c7f02f80 751 // Shield Control macros.
davidprentice 0:b608c7f02f80 752 #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
davidprentice 0:b608c7f02f80 753 #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
davidprentice 0:b608c7f02f80 754 #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
davidprentice 0:b608c7f02f80 755
davidprentice 0:b608c7f02f80 756 #elif defined(__SAM3X8E__) && defined(USE_MEGA_8BIT_SHIELD) //regular CTE shield on DUE
davidprentice 0:b608c7f02f80 757 #warning USE_MEGA_8BIT_SHIELD for peloxp
davidprentice 0:b608c7f02f80 758 // configure macros for the control pins
davidprentice 0:b608c7f02f80 759 #define RD_PORT PIOA
davidprentice 0:b608c7f02f80 760 #define RD_PIN 20 //D43
davidprentice 0:b608c7f02f80 761 #define WR_PORT PIOC
davidprentice 0:b608c7f02f80 762 #define WR_PIN 7 //D39
davidprentice 0:b608c7f02f80 763 #define CD_PORT PIOC
davidprentice 0:b608c7f02f80 764 #define CD_PIN 6 //D38
davidprentice 0:b608c7f02f80 765 #define CS_PORT PIOC
davidprentice 0:b608c7f02f80 766 #define CS_PIN 8 //D40
davidprentice 0:b608c7f02f80 767 #define RESET_PORT PIOC
davidprentice 0:b608c7f02f80 768 #define RESET_PIN 9 //D41
davidprentice 0:b608c7f02f80 769 // configure macros for data bus
davidprentice 0:b608c7f02f80 770 //
davidprentice 0:b608c7f02f80 771 #define AMASK ((3<<14)) //PA14-PA15 D23-D24
davidprentice 0:b608c7f02f80 772 #define BMASK (1<<26) //PB26 D22
davidprentice 0:b608c7f02f80 773 #define DMASK ((15<<0)|(1<<6)) //PD0-PD3, PD6 D25-D28,D29
davidprentice 0:b608c7f02f80 774
davidprentice 0:b608c7f02f80 775 #define write_8(x) { PIOA->PIO_CODR = AMASK; PIOB->PIO_CODR = BMASK; PIOD->PIO_CODR = DMASK; \
davidprentice 0:b608c7f02f80 776 PIOB->PIO_SODR = (((x)&(1<<0))<<26); \
davidprentice 0:b608c7f02f80 777 PIOA->PIO_SODR = (((x)&(3<<1))<<13); \
davidprentice 0:b608c7f02f80 778 PIOD->PIO_SODR = (((x)&(15<<3))>>3); \
davidprentice 0:b608c7f02f80 779 PIOD->PIO_SODR = (((x)&(1<<7))>>1); \
davidprentice 0:b608c7f02f80 780 }
davidprentice 0:b608c7f02f80 781
davidprentice 0:b608c7f02f80 782 #define read_8() ( 0\
davidprentice 0:b608c7f02f80 783 |((PIOB->PIO_PDSR & (1<<26))>>26)\
davidprentice 0:b608c7f02f80 784 |((PIOA->PIO_PDSR & (3<<14))>>13)\
davidprentice 0:b608c7f02f80 785 |((PIOD->PIO_PDSR & (15<<0))<<3)\
davidprentice 0:b608c7f02f80 786 |((PIOD->PIO_PDSR & (1<<6))<<1)\
davidprentice 0:b608c7f02f80 787 )
davidprentice 0:b608c7f02f80 788
davidprentice 0:b608c7f02f80 789 #define setWriteDir() {\
davidprentice 0:b608c7f02f80 790 PIOA->PIO_OER = AMASK; PIOA->PIO_PER = AMASK; \
davidprentice 0:b608c7f02f80 791 PIOB->PIO_OER = BMASK; PIOB->PIO_PER = BMASK; \
davidprentice 0:b608c7f02f80 792 PIOD->PIO_OER = DMASK; PIOD->PIO_PER = DMASK; \
davidprentice 0:b608c7f02f80 793 }
davidprentice 0:b608c7f02f80 794 #define setReadDir() { \
davidprentice 0:b608c7f02f80 795 PMC->PMC_PCER0 = (1 << ID_PIOA)|(1 << ID_PIOB)|(1 << ID_PIOC)|(1 << ID_PIOD); \
davidprentice 0:b608c7f02f80 796 PIOA->PIO_ODR = AMASK; \
davidprentice 0:b608c7f02f80 797 PIOB->PIO_ODR = BMASK; \
davidprentice 0:b608c7f02f80 798 PIOD->PIO_ODR = DMASK; \
davidprentice 0:b608c7f02f80 799 }
davidprentice 0:b608c7f02f80 800
davidprentice 0:b608c7f02f80 801 // ILI9486 is slower than ILI9481. HX8357-D is slower
davidprentice 0:b608c7f02f80 802 #define write8(x) { write_8(x); WR_ACTIVE4; WR_STROBE; WR_IDLE; WR_IDLE; }
davidprentice 0:b608c7f02f80 803 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 804 #define READ_8(dst) { RD_STROBE; RD_ACTIVE4; dst = read_8(); RD_IDLE; RD_IDLE; RD_IDLE; }
davidprentice 0:b608c7f02f80 805 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
davidprentice 0:b608c7f02f80 806
davidprentice 0:b608c7f02f80 807 // Shield Control macros.
davidprentice 0:b608c7f02f80 808 #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
davidprentice 0:b608c7f02f80 809 #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
davidprentice 0:b608c7f02f80 810 #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
davidprentice 0:b608c7f02f80 811
davidprentice 0:b608c7f02f80 812 #elif defined(__MK20DX256__) && defined(USE_BOBCACHELOT_TEENSY) // special for BOBCACHEALOT_TEENSY
davidprentice 0:b608c7f02f80 813 #warning special for BOBCACHEALOT_TEENSY
davidprentice 0:b608c7f02f80 814 #define RD_PORT GPIOD
davidprentice 0:b608c7f02f80 815 #define RD_PIN 1
davidprentice 0:b608c7f02f80 816 #define WR_PORT GPIOC
davidprentice 0:b608c7f02f80 817 #define WR_PIN 0
davidprentice 0:b608c7f02f80 818 #define CD_PORT GPIOB
davidprentice 0:b608c7f02f80 819 #define CD_PIN 0
davidprentice 0:b608c7f02f80 820 #define CS_PORT GPIOB
davidprentice 0:b608c7f02f80 821 #define CS_PIN 1
davidprentice 0:b608c7f02f80 822 #define RESET_PORT GPIOB
davidprentice 0:b608c7f02f80 823 #define RESET_PIN 3
davidprentice 0:b608c7f02f80 824
davidprentice 0:b608c7f02f80 825 // configure macros for the data pins
davidprentice 0:b608c7f02f80 826 #define CMASK ((1<<3))
davidprentice 0:b608c7f02f80 827 #define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7))
davidprentice 0:b608c7f02f80 828
davidprentice 0:b608c7f02f80 829 #define write_8(d) { \
davidprentice 0:b608c7f02f80 830 GPIOC_PCOR = CMASK; GPIOD_PCOR = DMASK; \
davidprentice 0:b608c7f02f80 831 GPIOC_PSOR = (((d) & (1<<1)) << 2); \
davidprentice 0:b608c7f02f80 832 GPIOD_PSOR = (d) & DMASK; \
davidprentice 0:b608c7f02f80 833 }
davidprentice 0:b608c7f02f80 834 #define read_8() ( (GPIOD_PDIR & DMASK) | (GPIOC_PDIR & (1<<3)) >> 2 )
davidprentice 0:b608c7f02f80 835 #define setWriteDir() {GPIOC_PDDR |= CMASK;GPIOD_PDDR |= DMASK; }
davidprentice 0:b608c7f02f80 836 #define setReadDir() {GPIOC_PDDR &= ~CMASK;GPIOD_PDDR &= ~DMASK; }
davidprentice 0:b608c7f02f80 837
davidprentice 0:b608c7f02f80 838 #define write8(x) { write_8(x); WR_STROBE; }
davidprentice 0:b608c7f02f80 839 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 840 #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 841 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
davidprentice 0:b608c7f02f80 842
davidprentice 0:b608c7f02f80 843 #define PASTE(x, y) x ## y
davidprentice 0:b608c7f02f80 844
davidprentice 0:b608c7f02f80 845 #define PIN_LOW(port, pin) PASTE(port, _PCOR) = (1<<(pin))
davidprentice 0:b608c7f02f80 846 #define PIN_HIGH(port, pin) PASTE(port, _PSOR) = (1<<(pin))
davidprentice 0:b608c7f02f80 847 #define PIN_OUTPUT(port, pin) PASTE(port, _PDDR) |= (1<<(pin))
davidprentice 0:b608c7f02f80 848
davidprentice 0:b608c7f02f80 849 #elif defined(USE_MY_BLUEPILL) && (defined(ARDUINO_GENERIC_STM32F103C) || defined(ARDUINO_BLUEPILL_F103C8))
davidprentice 0:b608c7f02f80 850 #warning Uno Shield on MY BLUEPILL
davidprentice 0:b608c7f02f80 851
davidprentice 0:b608c7f02f80 852 //LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |SD_SS|SD_DI|SD_DO|SD_SCK| |SDA|SCL|
davidprentice 0:b608c7f02f80 853 //STM32 pin |PA3 |PA2 |PA1|PA0|PB7|PB6|PA10|PA9| |PB1|PB0|PA7|PA6|PA5| |PB12 |PB15 |PB14 |PB13 | |PB9|PB8|
davidprentice 0:b608c7f02f80 854
davidprentice 0:b608c7f02f80 855 #if defined(ARDUINO_BLUEPILL_F103C8) //regular CMSIS libraries
davidprentice 0:b608c7f02f80 856 #define REGS(x) x
davidprentice 0:b608c7f02f80 857 #define GPIO_INIT() { RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_AFIOEN; \
davidprentice 0:b608c7f02f80 858 AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;}
davidprentice 0:b608c7f02f80 859 #else //weird Maple libraries
davidprentice 0:b608c7f02f80 860 #define REGS(x) regs->x
davidprentice 0:b608c7f02f80 861 #endif
davidprentice 0:b608c7f02f80 862
davidprentice 0:b608c7f02f80 863 #define WRITE_DELAY { }
davidprentice 0:b608c7f02f80 864 #define READ_DELAY { RD_ACTIVE; }
davidprentice 0:b608c7f02f80 865 #define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); }
davidprentice 0:b608c7f02f80 866 #define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
davidprentice 0:b608c7f02f80 867 #define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
davidprentice 0:b608c7f02f80 868 #define PIN_OUTPUT(port, pin) {\
davidprentice 0:b608c7f02f80 869 if (pin < 8) {GP_OUT(port, CRL, 0xF<<((pin)<<2));} \
davidprentice 0:b608c7f02f80 870 else {GP_OUT(port, CRH, 0xF<<((pin&7)<<2));} \
davidprentice 0:b608c7f02f80 871 }
davidprentice 0:b608c7f02f80 872 #define PIN_INPUT(port, pin) { \
davidprentice 0:b608c7f02f80 873 if (pin < 8) { GP_INP(port, CRL, 0xF<<((pin)<<2)); } \
davidprentice 0:b608c7f02f80 874 else { GP_INP(port, CRH, 0xF<<((pin&7)<<2)); } \
davidprentice 0:b608c7f02f80 875 }
davidprentice 0:b608c7f02f80 876 #define PIN_HIGH(port, pin) (port)-> REGS(BSRR) = (1<<(pin))
davidprentice 0:b608c7f02f80 877 #define PIN_LOW(port, pin) (port)-> REGS(BSRR) = (1<<((pin)+16))
davidprentice 0:b608c7f02f80 878
davidprentice 0:b608c7f02f80 879 #define RD_PORT GPIOB
davidprentice 0:b608c7f02f80 880 #define RD_PIN 1
davidprentice 0:b608c7f02f80 881 #define WR_PORT GPIOB
davidprentice 0:b608c7f02f80 882 #define WR_PIN 0
davidprentice 0:b608c7f02f80 883 #define CD_PORT GPIOA
davidprentice 0:b608c7f02f80 884 #define CD_PIN 7
davidprentice 0:b608c7f02f80 885 #define CS_PORT GPIOA
davidprentice 0:b608c7f02f80 886 #define CS_PIN 6
davidprentice 0:b608c7f02f80 887 #define RESET_PORT GPIOA
davidprentice 0:b608c7f02f80 888 #define RESET_PIN 5
davidprentice 0:b608c7f02f80 889
davidprentice 0:b608c7f02f80 890 // configure macros for the data pins
davidprentice 0:b608c7f02f80 891 #define AMASK 0x060F
davidprentice 0:b608c7f02f80 892 #define BMASK 0x00C0
davidprentice 0:b608c7f02f80 893 #define write_8(d) { GPIOA->REGS(BSRR) = AMASK << 16; GPIOB->REGS(BSRR) = BMASK << 16; \
davidprentice 0:b608c7f02f80 894 GPIOA->REGS(BSRR) = (((d) & 3) << 9) | (((d) & 0xF0) >> 4); \
davidprentice 0:b608c7f02f80 895 GPIOB->REGS(BSRR) = (((d) & 0x0C) << 4); \
davidprentice 0:b608c7f02f80 896 }
davidprentice 0:b608c7f02f80 897 #define read_8() (((GPIOA->REGS(IDR) & (3<<9)) >> 9) | ((GPIOA->REGS(IDR) & (0x0F)) << 4) | ((GPIOB->REGS(IDR) & (3<<6)) >> 4))
davidprentice 0:b608c7f02f80 898 // PA10,PA9 PA3-PA0 PB7,PB6
davidprentice 0:b608c7f02f80 899 #define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFF0); GP_OUT(GPIOA, CRL, 0xFFFF); GP_OUT(GPIOB, CRL, 0xFF000000); }
davidprentice 0:b608c7f02f80 900 #define setReadDir() {GP_INP(GPIOA, CRH, 0xFF0); GP_INP(GPIOA, CRL, 0xFFFF); GP_INP(GPIOB, CRL, 0xFF000000); }
davidprentice 0:b608c7f02f80 901
davidprentice 0:b608c7f02f80 902 #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
davidprentice 0:b608c7f02f80 903 #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
davidprentice 0:b608c7f02f80 904 #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 905 #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
davidprentice 0:b608c7f02f80 906
davidprentice 0:b608c7f02f80 907 //####################################### ADIGITALEU_TEENSY ############################
davidprentice 0:b608c7f02f80 908 //UNTESTED
davidprentice 0:b608c7f02f80 909 #elif defined(__MK66FX1M0__) && defined(USE_ADIGITALEU_TEENSY) // 16bit on a Teensy 3.6
davidprentice 0:b608c7f02f80 910 #warning "Teensy 3.6 16bit port C & D only (for now)"
davidprentice 0:b608c7f02f80 911 // Note: Port usage explained in UTFT Teensy edition ...\libraries\UTFT\hardware\arm\HW_Teensy3.h"
davidprentice 0:b608c7f02f80 912
davidprentice 0:b608c7f02f80 913 #define USES_16BIT_BUS
davidprentice 0:b608c7f02f80 914
davidprentice 0:b608c7f02f80 915 #define WRITE_DELAY { WR_ACTIVE8; }
davidprentice 0:b608c7f02f80 916 #define READ_DELAY { RD_ACTIVE16; }
davidprentice 0:b608c7f02f80 917
davidprentice 0:b608c7f02f80 918 #define RD_PORT GPIOA
davidprentice 0:b608c7f02f80 919 #define RD_PIN 16 //28 RD
davidprentice 0:b608c7f02f80 920 #define WR_PORT GPIOA
davidprentice 0:b608c7f02f80 921 #define WR_PIN 5 //25 WR
davidprentice 0:b608c7f02f80 922 #define CD_PORT GPIOE
davidprentice 0:b608c7f02f80 923 #define CD_PIN 26 //24 RS
davidprentice 0:b608c7f02f80 924 #define CS_PORT GPIOA
davidprentice 0:b608c7f02f80 925 #define CS_PIN 14 //26 CS
davidprentice 0:b608c7f02f80 926 #define RESET_PORT GPIOA
davidprentice 0:b608c7f02f80 927 #define RESET_PIN 15 //27 Reset
davidprentice 0:b608c7f02f80 928
davidprentice 0:b608c7f02f80 929 #define write_8(d) { GPIOC_PDOR = d; }
davidprentice 0:b608c7f02f80 930 #define write_16(d) { GPIOC_PDOR = d; GPIOD_PDOR = (d >> 8);}
davidprentice 0:b608c7f02f80 931
davidprentice 0:b608c7f02f80 932 #define read_8() (GPIOC_PDIR)
davidprentice 0:b608c7f02f80 933 #define read_16() (GPIOC_PDIR | GPIOD_PDIR << 8)
davidprentice 0:b608c7f02f80 934
davidprentice 0:b608c7f02f80 935 #define setWriteDir() {GPIOC_PDDR |= 0xFF; GPIOD_PDDR |= 0xFF; }
davidprentice 0:b608c7f02f80 936 #define setReadDir() {GPIOC_PDDR &= ~0xFF; GPIOD_PDDR &= ~0xFF; }
davidprentice 0:b608c7f02f80 937
davidprentice 0:b608c7f02f80 938 #define write8(x) {write_8(x); WRITE_DELAY; WR_STROBE }
davidprentice 0:b608c7f02f80 939 #define write16(x) {write_16(x); WRITE_DELAY; WR_STROBE }
davidprentice 0:b608c7f02f80 940
davidprentice 0:b608c7f02f80 941 #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
davidprentice 0:b608c7f02f80 942 #define READ_16(dst) { RD_STROBE; READ_DELAY; dst = read_16(); RD_IDLE;}
davidprentice 0:b608c7f02f80 943
davidprentice 0:b608c7f02f80 944 //Data: Teensy pins -> D0-D15 :
davidprentice 0:b608c7f02f80 945 // Teensy probably initialises some pins for Analog, Timer, Alternate, ...
davidprentice 0:b608c7f02f80 946 // so it is probably wise to use pinMode(n, OUTPUT) for all the control and data lines
davidprentice 0:b608c7f02f80 947 #define GPIO_INIT() {pinMode(2, OUTPUT); for (int i = 5; i <= 15; i++) pinMode(i, OUTPUT); for (int i = 20; i <= 28; i++) pinMode(i, OUTPUT);}
davidprentice 0:b608c7f02f80 948
davidprentice 0:b608c7f02f80 949 #define PASTE(x, y) x ## y
davidprentice 0:b608c7f02f80 950
davidprentice 0:b608c7f02f80 951 #define PIN_LOW(port, pin) PASTE(port, _PCOR) = (1<<(pin))
davidprentice 0:b608c7f02f80 952 #define PIN_HIGH(port, pin) PASTE(port, _PSOR) = (1<<(pin))
davidprentice 0:b608c7f02f80 953 #define PIN_OUTPUT(port, pin) PASTE(port, _PDDR) |= (1<<(pin))
davidprentice 0:b608c7f02f80 954
davidprentice 0:b608c7f02f80 955 #else
davidprentice 0:b608c7f02f80 956 #define USE_SPECIAL_FAIL
davidprentice 0:b608c7f02f80 957 #endif